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Generate the Verilog code corresponding to the following Chisel files.
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLWidthWidget8_2( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [6:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [6:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [6:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [31:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [7:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [31:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:32]; // @[Repeater.scala:36:26]
wire [31:0] _cated_bits_data_T_1 = anonIn_a_bits_data[31:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [9:0] _repeat_limit_T = 10'h7 << cated_bits_size; // @[package.scala:243:71]
wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire repeat_limit = _repeat_limit_T_2[2]; // @[package.scala:243:46]
reg repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24]
wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24]
wire repeat_sel = cated_bits_address[2]; // @[WidthWidget.scala:116:39, :161:25]
wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [31:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[31:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [31:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [31:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[63:32]; // @[WidthWidget.scala:128:55, :161:25]
wire [31:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30]
wire [3:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[3:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [3:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [3:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[7:4]; // @[WidthWidget.scala:128:55, :161:25]
wire [3:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [9:0] _limit_T = 10'h7 << anonOut_d_bits_size; // @[package.scala:243:71]
wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire limit = _limit_T_2[2]; // @[package.scala:243:46]
reg count; // @[WidthWidget.scala:40:27]
wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = ~count; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56]
wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24]
wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [31:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
wire [31:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [31:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 1'h0; // @[WidthWidget.scala:105:26]
count <= 1'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
always @(posedge)
Repeater_TLBundleA_a32d64s7k1z3u repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_13( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34]
wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34]
wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34]
wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [16:0] a_set; // @[Monitor.scala:626:34]
wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [135:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [16:0] d_clr; // @[Monitor.scala:664:34]
wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16:0] d_clr_1; // @[Monitor.scala:774:34]
wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_128( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File ProbePicker.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, IdRange}
/* A ProbePicker is used to unify multiple cache banks into one logical cache */
class ProbePicker(implicit p: Parameters) extends LazyModule
{
val node = TLAdapterNode(
clientFn = { p =>
// The ProbePicker assembles multiple clients based on the assumption they are contiguous in the clients list
// This should be true for custers of xbar :=* BankBinder connections
def combine(next: TLMasterParameters, pair: (TLMasterParameters, Seq[TLMasterParameters])) = {
val (head, output) = pair
if (head.visibility.exists(x => next.visibility.exists(_.overlaps(x)))) {
(next, head +: output) // pair is not banked, push head without merging
} else {
def redact(x: TLMasterParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0)))
require (redact(next) == redact(head), s"${redact(next)} != ${redact(head)}")
val merge = head.v1copy(
sourceId = IdRange(
head.sourceId.start min next.sourceId.start,
head.sourceId.end max next.sourceId.end),
visibility = AddressSet.unify(head.visibility ++ next.visibility))
(merge, output)
}
}
val myNil: Seq[TLMasterParameters] = Nil
val (head, output) = p.clients.init.foldRight((p.clients.last, myNil))(combine)
p.v1copy(clients = head +: output)
},
managerFn = { p => p })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out <> in
// Based on address, adjust source to route to the correct bank
if (edgeIn.client.clients.size != edgeOut.client.clients.size) {
in.b.bits.source := Mux1H(
edgeOut.client.clients.map(_.sourceId contains out.b.bits.source),
edgeOut.client.clients.map { c =>
val banks = edgeIn.client.clients.filter(c.sourceId contains _.sourceId)
if (banks.size == 1) {
out.b.bits.source // allow sharing the value between single-bank cases
} else {
Mux1H(
banks.map(_.visibility.map(_ contains out.b.bits.address).reduce(_ || _)),
banks.map(_.sourceId.start.U))
}
}
)
}
}
}
}
object ProbePicker
{
def apply()(implicit p: Parameters): TLNode = {
val picker = LazyModule(new ProbePicker)
picker.node
}
}
| module ProbePicker( // @[ProbePicker.scala:42:9]
input clock, // @[ProbePicker.scala:42:9]
input reset, // @[ProbePicker.scala:42:9]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
TLMonitor_35 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_out_0_a_ready),
.io_in_a_valid (auto_in_0_a_valid),
.io_in_a_bits_opcode (auto_in_0_a_bits_opcode),
.io_in_a_bits_param (auto_in_0_a_bits_param),
.io_in_a_bits_size (auto_in_0_a_bits_size),
.io_in_a_bits_source (auto_in_0_a_bits_source),
.io_in_a_bits_address (auto_in_0_a_bits_address),
.io_in_a_bits_mask (auto_in_0_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt),
.io_in_d_ready (auto_in_0_d_ready),
.io_in_d_valid (auto_out_0_d_valid),
.io_in_d_bits_opcode (auto_out_0_d_bits_opcode),
.io_in_d_bits_size (auto_out_0_d_bits_size),
.io_in_d_bits_source (auto_out_0_d_bits_source),
.io_in_d_bits_denied (auto_out_0_d_bits_denied),
.io_in_d_bits_corrupt (auto_out_0_d_bits_corrupt)
); // @[Nodes.scala:27:25]
TLMonitor_36 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_out_1_a_ready),
.io_in_a_valid (auto_in_1_a_valid),
.io_in_a_bits_opcode (auto_in_1_a_bits_opcode),
.io_in_a_bits_param (auto_in_1_a_bits_param),
.io_in_a_bits_size (auto_in_1_a_bits_size),
.io_in_a_bits_source (auto_in_1_a_bits_source),
.io_in_a_bits_address (auto_in_1_a_bits_address),
.io_in_a_bits_mask (auto_in_1_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt),
.io_in_d_ready (auto_in_1_d_ready),
.io_in_d_valid (auto_out_1_d_valid),
.io_in_d_bits_opcode (auto_out_1_d_bits_opcode),
.io_in_d_bits_param (auto_out_1_d_bits_param),
.io_in_d_bits_size (auto_out_1_d_bits_size),
.io_in_d_bits_source (auto_out_1_d_bits_source),
.io_in_d_bits_sink (auto_out_1_d_bits_sink),
.io_in_d_bits_denied (auto_out_1_d_bits_denied),
.io_in_d_bits_corrupt (auto_out_1_d_bits_corrupt)
); // @[Nodes.scala:27:25]
assign auto_in_1_a_ready = auto_out_1_a_ready; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_valid = auto_out_1_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_param = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_sink = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready = auto_out_0_a_ready; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_valid = auto_out_0_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_valid = auto_in_1_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready = auto_in_1_d_ready; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_valid = auto_in_0_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready = auto_in_0_d_ready; // @[ProbePicker.scala:42:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File NoC.scala:
package constellation.noc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody}
import freechips.rocketchip.util.ElaborationArtefacts
import freechips.rocketchip.prci._
import constellation.router._
import constellation.channel._
import constellation.routing.{RoutingRelation, ChannelRoutingInfo}
import constellation.topology.{PhysicalTopology, UnidirectionalLine}
class NoCTerminalIO(
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle {
val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) })
val egress = MixedVec(egressParams.map { u => new EgressChannel(u) })
}
class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
override def shouldBeInlined = nocParams.inlineNoC
val internalParams = InternalNoCParams(nocParams)
val allChannelParams = internalParams.channelParams
val allIngressParams = internalParams.ingressParams
val allEgressParams = internalParams.egressParams
val allRouterParams = internalParams.routerParams
val iP = p.alterPartial({ case InternalNoCKey => internalParams })
val nNodes = nocParams.topology.nNodes
val nocName = nocParams.nocName
val skipValidationChecks = nocParams.skipValidationChecks
val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) }
val router_sink_domains = Seq.tabulate(nNodes) { i =>
val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters(
name = Some(s"${nocName}_router_$i")
)))
router_sink_domain.clockNode := clockSourceNodes(i)
router_sink_domain
}
val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) {
val inParams = allChannelParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val outParams = allChannelParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val ingressParams = allIngressParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val egressParams = allEgressParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val noIn = inParams.size + ingressParams.size == 0
val noOut = outParams.size + egressParams.size == 0
if (noIn || noOut) {
println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated")
None
} else {
Some(LazyModule(new Router(
routerParams = allRouterParams(i),
preDiplomaticInParams = inParams,
preDiplomaticIngressParams = ingressParams,
outDests = outParams.map(_.destId),
egressIds = egressParams.map(_.egressId)
)(iP)))
}
}}.flatten
val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) }
val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) }
// Generate channels between routers diplomatically
Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) {
val routerI = routers.find(_.nodeId == i)
val routerJ = routers.find(_.nodeId == j)
if (routerI.isDefined && routerJ.isDefined) {
val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
require (sourceNodes.size == destNodes.size)
(sourceNodes zip destNodes).foreach { case (src, dst) =>
val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
router_sink_domains(j) {
implicit val p: Parameters = iP
(dst
:= ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits)
:= channelParam.channelGen(p)(src)
)
}
}
}
}}
// Generate terminal channels diplomatically
routers.foreach { dst => router_sink_domains(dst.nodeId) {
implicit val p: Parameters = iP
dst.ingressNodes.foreach(n => {
val ingressId = n.destParams.ingressId
require(dst.payloadBits <= allIngressParams(ingressId).payloadBits)
(n
:= IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits)
:= ingressNodes(ingressId)
)
})
dst.egressNodes.foreach(n => {
val egressId = n.egressId
require(dst.payloadBits <= allEgressParams(egressId).payloadBits)
(egressNodes(egressId)
:= EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits)
:= n
)
})
}}
val debugNodes = routers.map { r =>
val sink = BundleBridgeSink[DebugBundle]()
sink := r.debugNode
sink
}
val ctrlNodes = if (nocParams.hasCtrl) {
(0 until nNodes).map { i =>
routers.find(_.nodeId == i).map { r =>
val sink = BundleBridgeSink[RouterCtrlBundle]()
sink := r.ctrlNode.get
sink
}
}
} else {
Nil
}
println(s"Constellation: $nocName Finished parameter validation")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
println(s"Constellation: $nocName Starting NoC RTL generation")
val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))
val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil
})
(io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l }
(io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r }
(io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r }
if (nocParams.hasCtrl) {
ctrlNodes.zipWithIndex.map { case (c,i) =>
if (c.isDefined) {
io.router_ctrl(i) <> c.get.in(0)._1
} else {
io.router_ctrl(i) <> DontCare
}
}
}
// TODO: These assume a single clock-domain across the entire noc
val debug_va_stall_ctr = RegInit(0.U(64.W))
val debug_sa_stall_ctr = RegInit(0.U(64.W))
val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr
debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_)
debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_)
dontTouch(debug_va_stall_ctr)
dontTouch(debug_sa_stall_ctr)
dontTouch(debug_any_stall_ctr)
def prepend(s: String) = Seq(nocName, s).mkString(".")
ElaborationArtefacts.add(prepend("noc.graphml"), graphML)
val adjList = routers.map { r =>
val outs = r.outParams.map(o => s"${o.destId}").mkString(" ")
val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ")
val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}")
(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.adjlist"), adjList)
val xys = routers.map(r => {
val n = r.nodeId
val ids = (Seq(r.nodeId.toString)
++ r.egressParams.map(e => s"e${e.egressId}")
++ r.ingressParams.map(i => s"i${i.ingressId}")
)
val plotter = nocParams.topology.plotter
val coords = (Seq(plotter.node(r.nodeId))
++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) }
++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) }
)
(ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n")
}).mkString("\n")
ElaborationArtefacts.add(prepend("noc.xy"), xys)
val edgeProps = routers.map { r =>
val outs = r.outParams.map { o =>
(Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val egresses = r.egressParams.map { e =>
(Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val ingresses = r.ingressParams.map { i =>
(Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
(outs ++ egresses ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps)
println(s"Constellation: $nocName Finished NoC RTL generation")
}
}
| module TLSplitACDxBENoC_acd_router_5ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [1:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_5 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3),
.auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3),
.auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_flit_ready (auto_routers_ingress_nodes_in_flit_ready),
.auto_ingress_nodes_in_flit_valid (auto_routers_ingress_nodes_in_flit_valid),
.auto_ingress_nodes_in_flit_bits_head (auto_routers_ingress_nodes_in_flit_bits_head),
.auto_ingress_nodes_in_flit_bits_tail (auto_routers_ingress_nodes_in_flit_bits_tail),
.auto_ingress_nodes_in_flit_bits_payload (auto_routers_ingress_nodes_in_flit_bits_payload),
.auto_ingress_nodes_in_flit_bits_egress_id (auto_routers_ingress_nodes_in_flit_bits_egress_id),
.auto_source_nodes_out_3_flit_0_valid (auto_routers_source_nodes_out_3_flit_0_valid),
.auto_source_nodes_out_3_flit_0_bits_head (auto_routers_source_nodes_out_3_flit_0_bits_head),
.auto_source_nodes_out_3_flit_0_bits_tail (auto_routers_source_nodes_out_3_flit_0_bits_tail),
.auto_source_nodes_out_3_flit_0_bits_payload (auto_routers_source_nodes_out_3_flit_0_bits_payload),
.auto_source_nodes_out_3_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_3_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_3_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_3_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_3_credit_return (auto_routers_source_nodes_out_3_credit_return),
.auto_source_nodes_out_3_vc_free (auto_routers_source_nodes_out_3_vc_free),
.auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid),
.auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head),
.auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail),
.auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload),
.auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return),
.auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free),
.auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),
.auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),
.auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),
.auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),
.auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),
.auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),
.auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),
.auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),
.auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),
.auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),
.auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),
.auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),
.auto_dest_nodes_in_3_flit_0_valid (auto_routers_dest_nodes_in_3_flit_0_valid),
.auto_dest_nodes_in_3_flit_0_bits_head (auto_routers_dest_nodes_in_3_flit_0_bits_head),
.auto_dest_nodes_in_3_flit_0_bits_tail (auto_routers_dest_nodes_in_3_flit_0_bits_tail),
.auto_dest_nodes_in_3_flit_0_bits_payload (auto_routers_dest_nodes_in_3_flit_0_bits_payload),
.auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_3_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_3_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_3_credit_return (auto_routers_dest_nodes_in_3_credit_return),
.auto_dest_nodes_in_3_vc_free (auto_routers_dest_nodes_in_3_vc_free),
.auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid),
.auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head),
.auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail),
.auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload),
.auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return),
.auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free),
.auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),
.auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),
.auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),
.auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),
.auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),
.auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),
.auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),
.auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),
.auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),
.auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),
.auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),
.auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IDPool.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class IDPool(numIds: Int, lateValid: Boolean = false, revocableSelect: Boolean = false) extends Module {
require (numIds > 0)
val idWidth = log2Up(numIds)
val io = IO(new Bundle {
val free = Flipped(Valid(UInt(idWidth.W)))
val alloc = if (revocableSelect) Decoupled(UInt(idWidth.W)) else Irrevocable(UInt(idWidth.W))
})
// True indicates that the id is available
val bitmap = RegInit(UInt(numIds.W), -1.S(numIds.W).asUInt)
val select = RegInit(0.U(idWidth.W))
val valid = RegInit(true.B)
io.alloc.valid := (if (lateValid) bitmap.orR else valid)
io.alloc.bits := (if (revocableSelect) PriorityEncoder(bitmap) else select)
val taken = Mux(io.alloc.ready, UIntToOH(io.alloc.bits, numIds), 0.U)
val allocated = Mux(io.free .valid, UIntToOH(io.free .bits, numIds), 0.U)
val bitmap1 = (bitmap & ~taken) | allocated
val select1 = PriorityEncoder(bitmap1)
val valid1 = ( (bitmap.orR && !((PopCount(bitmap) === 1.U) && io.alloc.ready)) // bitmap not zero, and not allocating last bit
|| io.free.valid)
// Clock gate the bitmap
when (io.alloc.ready || io.free.valid) {
bitmap := bitmap1
valid := valid1
}
// Make select irrevocable
when (io.alloc.ready || (!io.alloc.valid && io.free.valid)) {
select := select1
}
// No double freeing
assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))
// pre-calculations for timing
if (!lateValid) {
assert (valid === bitmap.orR)
}
if (!revocableSelect) {
when (io.alloc.valid && RegNext(io.alloc.ready || (!io.alloc.valid && io.free.valid))) {
assert (select === PriorityEncoder(bitmap))
}
}
}
| module IDPool( // @[IDPool.scala:8:7]
input clock, // @[IDPool.scala:8:7]
input reset, // @[IDPool.scala:8:7]
input io_free_valid, // @[IDPool.scala:12:14]
input [2:0] io_free_bits, // @[IDPool.scala:12:14]
input io_alloc_ready, // @[IDPool.scala:12:14]
output io_alloc_valid, // @[IDPool.scala:12:14]
output [2:0] io_alloc_bits // @[IDPool.scala:12:14]
);
reg [7:0] bitmap; // @[IDPool.scala:18:23]
reg [2:0] select; // @[IDPool.scala:19:23]
reg valid; // @[IDPool.scala:20:23]
wire [7:0] taken = io_alloc_ready ? 8'h1 << select : 8'h0; // @[OneHot.scala:65:12]
wire [7:0] _GEN = {5'h0, io_free_bits}; // @[OneHot.scala:65:12]
reg REG; // @[IDPool.scala:51:36] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_171( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_307 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_143( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_171( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_307 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File SwitchAllocator.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])
(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val tail = Bool()
}
class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams))))
val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val chosen_oh = Vec(outN, Output(UInt(inN.W)))
})
val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) }
val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_))
val mask = RegInit(0.U(inN.W))
val choices = Wire(Vec(outN, UInt(inN.W)))
var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask))
for (i <- 0 until outN) {
choices(i) := sel | (sel >> inN)
sel = PriorityEncoderOH(unassigned & ~choices(i))
}
io.in.foreach(_.ready := false.B)
var chosens = 0.U(inN.W)
val in_tails = Cat(io.in.map(_.bits.tail).reverse)
for (i <- 0 until outN) {
val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse)
val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i))
io.chosen_oh(i) := chosen
io.out(i).valid := (in_valids & chosen).orR
io.out(i).bits := Mux1H(chosen, io.in.map(_.bits))
for (j <- 0 until inN) {
when (chosen(j) && io.out(i).ready) {
io.in(j).ready := true.B
}
}
chosens = chosens | chosen
when (io.out(i).fire) {
lock(i) := chosen & ~in_tails
}
}
when (io.out(0).fire) {
mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_)
} .otherwise {
mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W))
}
}
class SwitchAllocator(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams {
val io = IO(new Bundle {
val req = MixedVec(allInParams.map(u =>
Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams))))))
val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))})
val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup,
MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) })
})
val nInputChannels = allInParams.map(_.nVirtualChannels).sum
val arbs = allOutParams.map { oP => Module(new SwitchArbiter(
allInParams.map(_.destSpeedup).reduce(_+_),
oP.srcSpeedup,
outParams,
egressParams
))}
arbs.foreach(_.io.out.foreach(_.ready := true.B))
var idx = 0
io.req.foreach(_.foreach { o =>
val fires = Wire(Vec(arbs.size, Bool()))
arbs.zipWithIndex.foreach { case (a,i) =>
a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_)
a.io.in(idx).bits := o.bits
fires(i) := a.io.in(idx).fire
}
o.ready := fires.reduce(_||_)
idx += 1
})
for (i <- 0 until nAllOutputs) {
for (j <- 0 until allOutParams(i).srcSpeedup) {
idx = 0
for (m <- 0 until nAllInputs) {
for (n <- 0 until allInParams(m).destSpeedup) {
io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid
idx += 1
}
}
}
}
io.credit_alloc.foreach(_.foreach(_.alloc := false.B))
io.credit_alloc.foreach(_.foreach(_.tail := false.B))
(arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) =>
for (j <- 0 until i.size) {
for (k <- 0 until a.io.out.size) {
when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) {
i(j).alloc := true.B
i(j).tail := a.io.out(k).bits.tail
}
}
}
}
}
| module SwitchArbiter_70( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [2:0] unassigned = {2'h0, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}, :39:21, :41:24]
reg [2:0] mask; // @[SwitchAllocator.scala:27:21]
wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71]
wire [2:0] chosen = io_in_0_valid & lock_0[0] ? lock_0 : sel[2:0] | sel[5:3]; // @[Mux.scala:50:70]
wire _io_out_0_valid_T = io_in_0_valid & chosen[0]; // @[SwitchAllocator.scala:42:21, :44:35]
wire [1:0] _GEN = chosen[1:0] | chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38]
mask <= 3'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (_io_out_0_valid_T) // @[SwitchAllocator.scala:44:35]
lock_0 <= chosen & {2'h3, ~io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= _io_out_0_valid_T ? {chosen[2], _GEN[1], _GEN[0] | chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:35, :57:25, :58:{10,55,71}, :60:{10,16,23,49}]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_44( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_300 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_355( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_99 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_4( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_EntryData_7( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File FIFOFixer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.util.property
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
{
private def fifoMap(seq: Seq[TLSlaveParameters]) = {
val (flatManagers, keepManagers) = seq.partition(policy)
// We need to be careful if one flatManager and one keepManager share an existing domain
// Erring on the side of caution, we will also flatten the keepManager in this case
val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
// Calculate what the FIFO domains look like after the fixer is applied
val flatMap = flatDomains.map { x => (x, 0) }.toMap
val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
val map = flatMap ++ keepMap
val fixMap = seq.map { m => m.fifoId match {
case None => if (policy(m)) Some(0) else None
case Some(id) => Some(map(id)) // also flattens some who did not ask
} }
// Compress the FIFO domain space of those we are combining
val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
val splatMap = seq.map { m => m.fifoId match {
case None => None
case Some(id) => reMap.lift(id)
} }
(fixMap, splatMap)
}
val node = new AdapterNode(TLImp)(
{ cp => cp },
{ mp =>
val (fixMap, _) = fifoMap(mp.managers)
mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })
}) with TLFormatNode {
override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
// Do we need to serialize the request to this manager?
val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)
// Compact the IDs of the cases we serialize
val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None
}
val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0
val a_id = if (compacted.isEmpty) 0.U else
edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)
val a_noDomain = a_id === 0.U
if (false) {
println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
println("")
}
// Count beats
val a_first = edgeIn.first(in.a)
val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))
when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source)
val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)
val track = flight.slice(c.sourceId.start, c.sourceId.end)
a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
}
val stall = stalls.foldLeft(false.B)(_||_)
out.a <> in.a
in.d <> out.d
out.a.valid := in.a.valid && (a_notFIFO || !stall)
in.a.ready := out.a.ready && (a_notFIFO || !stall)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> out.b
out.c <> in .c
out.e <> in .e
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
//Functional cover properties
property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))
val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))
val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))
when (a_first && in.a.fire && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}
object TLFIFOFixer
{
// Which slaves should have their FIFOness combined?
// NOTE: this transformation is still only applied for masters with requestFifo
type Policy = TLSlaveParameters => Boolean
import RegionType._
val all: Policy = m => true
val allFIFO: Policy = m => m.fifoId.isDefined
val allVolatile: Policy = m => m.regionType <= VOLATILE
def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
{
val fixer = LazyModule(new TLFIFOFixer(policy))
fixer.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File SystemBus.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{
BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams
}
import freechips.rocketchip.tilelink.{
TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper,
TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode,
TLFIFOFixer, TLTempNode
}
import freechips.rocketchip.util.Location
case class SystemBusParams(
beatBytes: Int,
blockBytes: Int,
policy: TLArbiter.Policy = TLArbiter.roundRobin,
dtsFrequency: Option[BigInt] = None,
zeroDevice: Option[BuiltInZeroDeviceParams] = None,
errorDevice: Option[BuiltInErrorDeviceParams] = None,
replication: Option[ReplicatedRegion] = None)
extends HasTLBusParams
with HasBuiltInDeviceParams
with TLBusWrapperInstantiationLike
{
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = {
val sbus = LazyModule(new SystemBus(this, loc.name))
sbus.suggestName(loc.name)
context.tlBusWrapperLocationMap += (loc -> sbus)
sbus
}
}
class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p: Parameters)
extends TLBusWrapper(params, name)
{
private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r)))
val prefixNode = replicator.map { r =>
r.prefix := addressPrefixNexusNode
addressPrefixNexusNode
}
private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name)))
val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode())
val outwardNode: TLOutwardNode = system_bus_xbar.node
def busView: TLEdge = system_bus_xbar.node.edges.in.head
val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
}
File LazyScope.scala:
package org.chipsalliance.diplomacy.lazymodule
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
/** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. */
trait LazyScope {
this: LazyModule =>
override def toString: String = s"LazyScope named $name"
/** Evaluate `body` in the current [[LazyModule.scope]] */
def apply[T](body: => T): T = {
// Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function,
// [[LazyModule.scope]] will be altered.
val saved = LazyModule.scope
// [[LazyModule.scope]] stack push.
LazyModule.scope = Some(this)
// Evaluate [[body]] in the current `scope`, saving the result to [[out]].
val out = body
// Check that the `scope` after evaluating `body` is the same as when we started.
require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!")
require(
LazyModule.scope.get eq this,
s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed"
)
// [[LazyModule.scope]] stack pop.
LazyModule.scope = saved
out
}
}
/** Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can
* be instantiated and connected.
*
* It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this
* scope.
*/
object LazyScope {
/** Create a [[LazyScope]] with an implicit instance name.
*
* @param body
* code executed within the generated [[SimpleLazyModule]].
* @param valName
* instance name of generated [[SimpleLazyModule]].
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
body: => T
)(
implicit valName: ValName,
p: Parameters
): T = {
apply(valName.value, "SimpleLazyModule", None)(body)(p)
}
/** Create a [[LazyScope]] with an explicitly defined instance name.
*
* @param name
* instance name of generated [[SimpleLazyModule]].
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
name: String
)(body: => T
)(
implicit p: Parameters
): T = {
apply(name, "SimpleLazyModule", None)(body)(p)
}
/** Create a [[LazyScope]] with an explicit instance and class name, and control inlining.
*
* @param name
* instance name of generated [[SimpleLazyModule]].
* @param desiredModuleName
* class name of generated [[SimpleLazyModule]].
* @param overrideInlining
* tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined.
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
name: String,
desiredModuleName: String,
overrideInlining: Option[Boolean] = None
)(body: => T
)(
implicit p: Parameters
): T = {
val scope = LazyModule(new SimpleLazyModule with LazyScope {
override lazy val desiredName = desiredModuleName
override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined)
}).suggestName(name)
scope {
body
}
}
/** Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it.
*
* For example, we might want to control a set of children's clocks but then not keep the parent wrapper.
*
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def inline[T](
body: => T
)(
implicit p: Parameters
): T = {
apply("noname", "ShouldBeInlined", Some(false))(body)(p)
}
}
| module SystemBus( // @[ClockDomain.scala:14:9]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire coupler_to_bus_named_coh_auto_widget_anon_in_e_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_c_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_b_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire [4:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
wire _coupler_from_rockettile_auto_tl_out_a_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_from_rockettile_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27]
wire [3:0] _coupler_from_rockettile_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27]
wire [4:0] _coupler_from_rockettile_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27]
wire [31:0] _coupler_from_rockettile_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27]
wire [7:0] _coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_from_rockettile_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_from_rockettile_auto_tl_out_b_ready; // @[LazyScope.scala:98:27]
wire _coupler_from_rockettile_auto_tl_out_c_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_from_rockettile_auto_tl_out_c_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_from_rockettile_auto_tl_out_c_bits_param; // @[LazyScope.scala:98:27]
wire [3:0] _coupler_from_rockettile_auto_tl_out_c_bits_size; // @[LazyScope.scala:98:27]
wire [4:0] _coupler_from_rockettile_auto_tl_out_c_bits_source; // @[LazyScope.scala:98:27]
wire [31:0] _coupler_from_rockettile_auto_tl_out_c_bits_address; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_from_rockettile_auto_tl_out_c_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_from_rockettile_auto_tl_out_c_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_from_rockettile_auto_tl_out_d_ready; // @[LazyScope.scala:98:27]
wire _coupler_from_rockettile_auto_tl_out_e_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_from_rockettile_auto_tl_out_e_bits_sink; // @[LazyScope.scala:98:27]
wire _fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:152:27]
wire [1:0] _fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:152:27]
wire [31:0] _fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:152:27]
wire [1:0] _fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:152:27]
wire [3:0] _fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:152:27]
wire [4:0] _fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:152:27]
wire [63:0] _fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:152:27]
wire [3:0] _fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:152:27]
wire [4:0] _fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:152:27]
wire [31:0] _fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:152:27]
wire [7:0] _fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:152:27]
wire [63:0] _fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_1_b_ready; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_1_c_valid; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_out_1_c_bits_opcode; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_out_1_c_bits_param; // @[FIFOFixer.scala:152:27]
wire [3:0] _fixer_auto_anon_out_1_c_bits_size; // @[FIFOFixer.scala:152:27]
wire [4:0] _fixer_auto_anon_out_1_c_bits_source; // @[FIFOFixer.scala:152:27]
wire [31:0] _fixer_auto_anon_out_1_c_bits_address; // @[FIFOFixer.scala:152:27]
wire [63:0] _fixer_auto_anon_out_1_c_bits_data; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_1_c_bits_corrupt; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_1_e_valid; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_out_1_e_bits_sink; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:152:27]
wire [2:0] _fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:152:27]
wire [3:0] _fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:152:27]
wire [4:0] _fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:152:27]
wire [31:0] _fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:152:27]
wire [7:0] _fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:152:27]
wire [63:0] _fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:152:27]
wire _fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:152:27]
wire _system_bus_xbar_auto_anon_in_1_a_ready; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_1_b_valid; // @[SystemBus.scala:47:43]
wire [1:0] _system_bus_xbar_auto_anon_in_1_b_bits_param; // @[SystemBus.scala:47:43]
wire [31:0] _system_bus_xbar_auto_anon_in_1_b_bits_address; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_1_c_ready; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_1_d_valid; // @[SystemBus.scala:47:43]
wire [2:0] _system_bus_xbar_auto_anon_in_1_d_bits_opcode; // @[SystemBus.scala:47:43]
wire [1:0] _system_bus_xbar_auto_anon_in_1_d_bits_param; // @[SystemBus.scala:47:43]
wire [3:0] _system_bus_xbar_auto_anon_in_1_d_bits_size; // @[SystemBus.scala:47:43]
wire [4:0] _system_bus_xbar_auto_anon_in_1_d_bits_source; // @[SystemBus.scala:47:43]
wire [2:0] _system_bus_xbar_auto_anon_in_1_d_bits_sink; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_1_d_bits_denied; // @[SystemBus.scala:47:43]
wire [63:0] _system_bus_xbar_auto_anon_in_1_d_bits_data; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_1_d_bits_corrupt; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_0_a_ready; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_0_d_valid; // @[SystemBus.scala:47:43]
wire [2:0] _system_bus_xbar_auto_anon_in_0_d_bits_opcode; // @[SystemBus.scala:47:43]
wire [1:0] _system_bus_xbar_auto_anon_in_0_d_bits_param; // @[SystemBus.scala:47:43]
wire [3:0] _system_bus_xbar_auto_anon_in_0_d_bits_size; // @[SystemBus.scala:47:43]
wire [4:0] _system_bus_xbar_auto_anon_in_0_d_bits_source; // @[SystemBus.scala:47:43]
wire [2:0] _system_bus_xbar_auto_anon_in_0_d_bits_sink; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_0_d_bits_denied; // @[SystemBus.scala:47:43]
wire [63:0] _system_bus_xbar_auto_anon_in_0_d_bits_data; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_in_0_d_bits_corrupt; // @[SystemBus.scala:47:43]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_valid; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_1_clock_0 = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_1_reset_0 = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_0_clock_0 = auto_sbus_clock_groups_in_member_sbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_0_reset_0 = auto_sbus_clock_groups_in_member_sbus_0_reset; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_source = 3'h0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_mask = 8'hFF; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_mask = 8'hFF; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_data = 64'h0; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_data = 64'h0; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_data = 64'h0; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_data = 64'h0; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire sbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire sbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire sbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_coh_widget_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_in_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_widget_auto_anon_in_e_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_e_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_coh_widget_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_source = 6'h10; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_source = 6'h10; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_source = 6'h10; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_source = 6'h10; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_source = 6'h10; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_source = 6'h10; // @[MixedNode.scala:542:17]
wire [5:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_source = 6'h10; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_b_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_b_valid_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_c_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_c_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_e_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_address = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_mask = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [4:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire sbus_clock_groups_auto_in_member_sbus_1_clock = auto_sbus_clock_groups_in_member_sbus_1_clock_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_1_reset = auto_sbus_clock_groups_in_member_sbus_1_reset_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_0_clock = auto_sbus_clock_groups_in_member_sbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_0_reset = auto_sbus_clock_groups_in_member_sbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire sbus_clock_groups_nodeIn_member_sbus_1_clock = sbus_clock_groups_auto_in_member_sbus_1_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_1_reset = sbus_clock_groups_auto_in_member_sbus_1_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_0_clock = sbus_clock_groups_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_0_reset = sbus_clock_groups_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17]
assign auto_sbus_clock_groups_out_member_coh_0_clock_0 = sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17]
assign auto_sbus_clock_groups_out_member_coh_0_reset_0 = sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_sbus_0_clock = sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_sbus_0_reset = sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign sbus_clock_groups_x1_nodeOut_member_coh_0_clock = sbus_clock_groups_nodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_x1_nodeOut_member_coh_0_reset = sbus_clock_groups_nodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_nodeOut_member_sbus_0_clock = sbus_clock_groups_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_nodeOut_member_sbus_0_reset = sbus_clock_groups_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_auto_out_0_member_sbus_0_clock = sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_0_member_sbus_0_reset = sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_1_member_coh_0_clock = sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_1_member_coh_0_reset = sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire clockGroup_nodeIn_member_sbus_0_clock = clockGroup_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_sbus_0_reset = clockGroup_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingOut_a_ready = coupler_to_bus_named_cbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [28:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_cbus_bus_xingOut_d_valid = coupler_to_bus_named_cbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_param = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_size = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_source = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_data = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_cbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_a_valid = coupler_to_bus_named_cbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_address = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_ready = coupler_to_bus_named_cbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_a_ready = coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingIn_a_valid = coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [5:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_address = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_cbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_ready = coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_d_valid = coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [5:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_anonIn_a_ready = coupler_to_bus_named_cbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_cbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_cbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_cbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_cbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_cbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_cbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_cbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_anonIn_d_valid = coupler_to_bus_named_cbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_cbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_param = coupler_to_bus_named_cbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_size = coupler_to_bus_named_cbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_source = coupler_to_bus_named_cbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_cbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_cbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_data = coupler_to_bus_named_cbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_cbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_cbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_anonOut_a_valid = coupler_to_bus_named_cbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_cbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_param = coupler_to_bus_named_cbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_size = coupler_to_bus_named_cbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_source = coupler_to_bus_named_cbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_address = coupler_to_bus_named_cbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_cbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_data = coupler_to_bus_named_cbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_cbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_anonOut_d_ready = coupler_to_bus_named_cbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_cbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_cbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_cbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_cbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_cbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_bus_xingIn_a_ready = coupler_to_bus_named_cbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_cbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_cbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_cbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_cbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_cbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_cbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_cbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_valid = coupler_to_bus_named_cbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_cbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_param = coupler_to_bus_named_cbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_size = coupler_to_bus_named_cbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_source = coupler_to_bus_named_cbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_cbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_cbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_data = coupler_to_bus_named_cbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_cbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_cbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_bus_xingOut_a_valid = coupler_to_bus_named_cbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_cbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_param = coupler_to_bus_named_cbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_size = coupler_to_bus_named_cbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_source = coupler_to_bus_named_cbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_address = coupler_to_bus_named_cbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_cbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_data = coupler_to_bus_named_cbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_cbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_bus_xingOut_d_ready = coupler_to_bus_named_cbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_cbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_cbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_cbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_cbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_cbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_ready = coupler_from_bus_named_fbus_auto_widget_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_valid = coupler_from_bus_named_fbus_auto_widget_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_opcode = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_param = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_size = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_source = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_sink = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_denied = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_data = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_corrupt = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_bus_xingIn_a_valid = coupler_from_bus_named_fbus_auto_bus_xing_in_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_opcode = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_param = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_size = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_source = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_address = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_mask = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_data = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingIn_a_bits_corrupt = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingIn_d_ready = coupler_from_bus_named_fbus_auto_bus_xing_in_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [4:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_bus_named_fbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingOut_a_ready = coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire coupler_from_bus_named_fbus_widget_anonIn_a_valid = coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [4:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_address = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_mask = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_bus_named_fbus_widget_anonIn_a_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_bus_named_fbus_widget_anonIn_d_ready = coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingOut_d_valid = coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [4:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_sink = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_bus_named_fbus_bus_xingOut_d_bits_denied = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_bus_xingOut_d_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_a_ready = coupler_from_bus_named_fbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid = coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready = coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_d_valid = coupler_from_bus_named_fbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_sink = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_d_bits_denied = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_from_bus_named_fbus_widget_anonOut_d_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_anonIn_a_ready = coupler_from_bus_named_fbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid = coupler_from_bus_named_fbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode = coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param = coupler_from_bus_named_fbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size = coupler_from_bus_named_fbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source = coupler_from_bus_named_fbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address = coupler_from_bus_named_fbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask = coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data = coupler_from_bus_named_fbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt = coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready = coupler_from_bus_named_fbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_anonIn_d_valid = coupler_from_bus_named_fbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode = coupler_from_bus_named_fbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_param = coupler_from_bus_named_fbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_size = coupler_from_bus_named_fbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_source = coupler_from_bus_named_fbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink = coupler_from_bus_named_fbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied = coupler_from_bus_named_fbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_data = coupler_from_bus_named_fbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt = coupler_from_bus_named_fbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready = coupler_from_bus_named_fbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_anonOut_a_valid = coupler_from_bus_named_fbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode = coupler_from_bus_named_fbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_param = coupler_from_bus_named_fbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_size = coupler_from_bus_named_fbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_source = coupler_from_bus_named_fbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_address = coupler_from_bus_named_fbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask = coupler_from_bus_named_fbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_data = coupler_from_bus_named_fbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt = coupler_from_bus_named_fbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_anonOut_d_ready = coupler_from_bus_named_fbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid = coupler_from_bus_named_fbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode = coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param = coupler_from_bus_named_fbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size = coupler_from_bus_named_fbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source = coupler_from_bus_named_fbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink = coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied = coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data = coupler_from_bus_named_fbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt = coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_bus_xingIn_a_ready = coupler_from_bus_named_fbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid = coupler_from_bus_named_fbus_bus_xingOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode = coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param = coupler_from_bus_named_fbus_bus_xingOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size = coupler_from_bus_named_fbus_bus_xingOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source = coupler_from_bus_named_fbus_bus_xingOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address = coupler_from_bus_named_fbus_bus_xingOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask = coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data = coupler_from_bus_named_fbus_bus_xingOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt = coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready = coupler_from_bus_named_fbus_bus_xingOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_from_bus_named_fbus_bus_xingIn_d_valid = coupler_from_bus_named_fbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode = coupler_from_bus_named_fbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_param = coupler_from_bus_named_fbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_size = coupler_from_bus_named_fbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_source = coupler_from_bus_named_fbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink = coupler_from_bus_named_fbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied = coupler_from_bus_named_fbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_data = coupler_from_bus_named_fbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt = coupler_from_bus_named_fbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready = coupler_from_bus_named_fbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_valid = coupler_from_bus_named_fbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode = coupler_from_bus_named_fbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_param = coupler_from_bus_named_fbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_size = coupler_from_bus_named_fbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_source = coupler_from_bus_named_fbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_address = coupler_from_bus_named_fbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask = coupler_from_bus_named_fbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_data = coupler_from_bus_named_fbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt = coupler_from_bus_named_fbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_bus_xingOut_d_ready = coupler_from_bus_named_fbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid = coupler_from_bus_named_fbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode = coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param = coupler_from_bus_named_fbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size = coupler_from_bus_named_fbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source = coupler_from_bus_named_fbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink = coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied = coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data = coupler_from_bus_named_fbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt = coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_b_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_b_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_c_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_b_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_c_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_a_ready = coupler_to_bus_named_coh_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_valid = coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_b_ready = coupler_to_bus_named_coh_widget_anonOut_b_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_b_valid = coupler_to_bus_named_coh_widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_b_bits_param = coupler_to_bus_named_coh_widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_b_bits_address = coupler_to_bus_named_coh_widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_c_ready = coupler_to_bus_named_coh_widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_valid = coupler_to_bus_named_coh_widget_anonOut_c_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param = coupler_to_bus_named_coh_widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size = coupler_to_bus_named_coh_widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source = coupler_to_bus_named_coh_widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address = coupler_to_bus_named_coh_widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data = coupler_to_bus_named_coh_widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_d_ready = coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_d_valid = coupler_to_bus_named_coh_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_param = coupler_to_bus_named_coh_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_size = coupler_to_bus_named_coh_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_source = coupler_to_bus_named_coh_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_sink = coupler_to_bus_named_coh_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_denied = coupler_to_bus_named_coh_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_data = coupler_to_bus_named_coh_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_out_e_valid = coupler_to_bus_named_coh_widget_anonOut_e_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink = coupler_to_bus_named_coh_widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_a_ready = coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonOut_a_valid = coupler_to_bus_named_coh_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_param = coupler_to_bus_named_coh_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_size = coupler_to_bus_named_coh_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_source = coupler_to_bus_named_coh_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_address = coupler_to_bus_named_coh_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_mask = coupler_to_bus_named_coh_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_data = coupler_to_bus_named_coh_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_b_ready = coupler_to_bus_named_coh_widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_in_b_valid = coupler_to_bus_named_coh_widget_anonIn_b_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param = coupler_to_bus_named_coh_widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address = coupler_to_bus_named_coh_widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_c_ready = coupler_to_bus_named_coh_widget_anonIn_c_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonOut_c_valid = coupler_to_bus_named_coh_widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_param = coupler_to_bus_named_coh_widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_size = coupler_to_bus_named_coh_widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_source = coupler_to_bus_named_coh_widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_address = coupler_to_bus_named_coh_widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_data = coupler_to_bus_named_coh_widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_d_ready = coupler_to_bus_named_coh_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_valid = coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonOut_e_valid = coupler_to_bus_named_coh_widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_e_bits_sink = coupler_to_bus_named_coh_widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
FixedClockBroadcast_4 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0),
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_sbus_i2_o2_a32d64s6k3z4c system_bus_xbar ( // @[SystemBus.scala:47:43]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_1_a_ready (_system_bus_xbar_auto_anon_in_1_a_ready),
.auto_anon_in_1_a_valid (_fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_a_bits_opcode (_fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_a_bits_param (_fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_a_bits_size (_fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_a_bits_source (_fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_a_bits_address (_fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_a_bits_mask (_fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_a_bits_data (_fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_a_bits_corrupt (_fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_b_ready (_fixer_auto_anon_out_1_b_ready), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_b_valid (_system_bus_xbar_auto_anon_in_1_b_valid),
.auto_anon_in_1_b_bits_param (_system_bus_xbar_auto_anon_in_1_b_bits_param),
.auto_anon_in_1_b_bits_address (_system_bus_xbar_auto_anon_in_1_b_bits_address),
.auto_anon_in_1_c_ready (_system_bus_xbar_auto_anon_in_1_c_ready),
.auto_anon_in_1_c_valid (_fixer_auto_anon_out_1_c_valid), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_c_bits_opcode (_fixer_auto_anon_out_1_c_bits_opcode), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_c_bits_param (_fixer_auto_anon_out_1_c_bits_param), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_c_bits_size (_fixer_auto_anon_out_1_c_bits_size), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_c_bits_source (_fixer_auto_anon_out_1_c_bits_source), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_c_bits_address (_fixer_auto_anon_out_1_c_bits_address), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_c_bits_data (_fixer_auto_anon_out_1_c_bits_data), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_c_bits_corrupt (_fixer_auto_anon_out_1_c_bits_corrupt), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_d_ready (_fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_d_valid (_system_bus_xbar_auto_anon_in_1_d_valid),
.auto_anon_in_1_d_bits_opcode (_system_bus_xbar_auto_anon_in_1_d_bits_opcode),
.auto_anon_in_1_d_bits_param (_system_bus_xbar_auto_anon_in_1_d_bits_param),
.auto_anon_in_1_d_bits_size (_system_bus_xbar_auto_anon_in_1_d_bits_size),
.auto_anon_in_1_d_bits_source (_system_bus_xbar_auto_anon_in_1_d_bits_source),
.auto_anon_in_1_d_bits_sink (_system_bus_xbar_auto_anon_in_1_d_bits_sink),
.auto_anon_in_1_d_bits_denied (_system_bus_xbar_auto_anon_in_1_d_bits_denied),
.auto_anon_in_1_d_bits_data (_system_bus_xbar_auto_anon_in_1_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (_system_bus_xbar_auto_anon_in_1_d_bits_corrupt),
.auto_anon_in_1_e_valid (_fixer_auto_anon_out_1_e_valid), // @[FIFOFixer.scala:152:27]
.auto_anon_in_1_e_bits_sink (_fixer_auto_anon_out_1_e_bits_sink), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_ready (_system_bus_xbar_auto_anon_in_0_a_ready),
.auto_anon_in_0_a_valid (_fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_bits_opcode (_fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_bits_param (_fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_bits_size (_fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_bits_source (_fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_bits_address (_fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_bits_mask (_fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_bits_data (_fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_a_bits_corrupt (_fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_d_ready (_fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:152:27]
.auto_anon_in_0_d_valid (_system_bus_xbar_auto_anon_in_0_d_valid),
.auto_anon_in_0_d_bits_opcode (_system_bus_xbar_auto_anon_in_0_d_bits_opcode),
.auto_anon_in_0_d_bits_param (_system_bus_xbar_auto_anon_in_0_d_bits_param),
.auto_anon_in_0_d_bits_size (_system_bus_xbar_auto_anon_in_0_d_bits_size),
.auto_anon_in_0_d_bits_source (_system_bus_xbar_auto_anon_in_0_d_bits_source),
.auto_anon_in_0_d_bits_sink (_system_bus_xbar_auto_anon_in_0_d_bits_sink),
.auto_anon_in_0_d_bits_denied (_system_bus_xbar_auto_anon_in_0_d_bits_denied),
.auto_anon_in_0_d_bits_data (_system_bus_xbar_auto_anon_in_0_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (_system_bus_xbar_auto_anon_in_0_d_bits_corrupt),
.auto_anon_out_1_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_a_valid),
.auto_anon_out_1_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode),
.auto_anon_out_1_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param),
.auto_anon_out_1_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size),
.auto_anon_out_1_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source),
.auto_anon_out_1_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address),
.auto_anon_out_1_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask),
.auto_anon_out_1_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt),
.auto_anon_out_1_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_b_ready),
.auto_anon_out_1_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_b_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_c_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_c_valid),
.auto_anon_out_1_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode),
.auto_anon_out_1_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param),
.auto_anon_out_1_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size),
.auto_anon_out_1_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source),
.auto_anon_out_1_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address),
.auto_anon_out_1_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data),
.auto_anon_out_1_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt),
.auto_anon_out_1_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_d_ready),
.auto_anon_out_1_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_e_valid),
.auto_anon_out_1_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink),
.auto_anon_out_0_a_ready (coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_a_valid (coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid),
.auto_anon_out_0_a_bits_opcode (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode),
.auto_anon_out_0_a_bits_param (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param),
.auto_anon_out_0_a_bits_size (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size),
.auto_anon_out_0_a_bits_source (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source),
.auto_anon_out_0_a_bits_address (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address),
.auto_anon_out_0_a_bits_mask (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask),
.auto_anon_out_0_a_bits_data (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt),
.auto_anon_out_0_d_ready (coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready),
.auto_anon_out_0_d_valid (coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_opcode (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_param (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_size (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_source (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_sink (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_denied (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_data (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_d_bits_corrupt (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7]
); // @[SystemBus.scala:47:43]
TLFIFOFixer fixer ( // @[FIFOFixer.scala:152:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_1_a_ready (_fixer_auto_anon_in_1_a_ready),
.auto_anon_in_1_a_valid (_coupler_from_rockettile_auto_tl_out_a_valid), // @[LazyScope.scala:98:27]
.auto_anon_in_1_a_bits_opcode (_coupler_from_rockettile_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_in_1_a_bits_param (_coupler_from_rockettile_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_in_1_a_bits_size (_coupler_from_rockettile_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_in_1_a_bits_source (_coupler_from_rockettile_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_in_1_a_bits_address (_coupler_from_rockettile_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27]
.auto_anon_in_1_a_bits_mask (_coupler_from_rockettile_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27]
.auto_anon_in_1_a_bits_data (_coupler_from_rockettile_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_in_1_a_bits_corrupt (_coupler_from_rockettile_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27]
.auto_anon_in_1_b_ready (_coupler_from_rockettile_auto_tl_out_b_ready), // @[LazyScope.scala:98:27]
.auto_anon_in_1_b_valid (_fixer_auto_anon_in_1_b_valid),
.auto_anon_in_1_b_bits_param (_fixer_auto_anon_in_1_b_bits_param),
.auto_anon_in_1_b_bits_address (_fixer_auto_anon_in_1_b_bits_address),
.auto_anon_in_1_c_ready (_fixer_auto_anon_in_1_c_ready),
.auto_anon_in_1_c_valid (_coupler_from_rockettile_auto_tl_out_c_valid), // @[LazyScope.scala:98:27]
.auto_anon_in_1_c_bits_opcode (_coupler_from_rockettile_auto_tl_out_c_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_in_1_c_bits_param (_coupler_from_rockettile_auto_tl_out_c_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_in_1_c_bits_size (_coupler_from_rockettile_auto_tl_out_c_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_in_1_c_bits_source (_coupler_from_rockettile_auto_tl_out_c_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_in_1_c_bits_address (_coupler_from_rockettile_auto_tl_out_c_bits_address), // @[LazyScope.scala:98:27]
.auto_anon_in_1_c_bits_data (_coupler_from_rockettile_auto_tl_out_c_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_in_1_c_bits_corrupt (_coupler_from_rockettile_auto_tl_out_c_bits_corrupt), // @[LazyScope.scala:98:27]
.auto_anon_in_1_d_ready (_coupler_from_rockettile_auto_tl_out_d_ready), // @[LazyScope.scala:98:27]
.auto_anon_in_1_d_valid (_fixer_auto_anon_in_1_d_valid),
.auto_anon_in_1_d_bits_opcode (_fixer_auto_anon_in_1_d_bits_opcode),
.auto_anon_in_1_d_bits_param (_fixer_auto_anon_in_1_d_bits_param),
.auto_anon_in_1_d_bits_size (_fixer_auto_anon_in_1_d_bits_size),
.auto_anon_in_1_d_bits_source (_fixer_auto_anon_in_1_d_bits_source),
.auto_anon_in_1_d_bits_sink (_fixer_auto_anon_in_1_d_bits_sink),
.auto_anon_in_1_d_bits_denied (_fixer_auto_anon_in_1_d_bits_denied),
.auto_anon_in_1_d_bits_data (_fixer_auto_anon_in_1_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (_fixer_auto_anon_in_1_d_bits_corrupt),
.auto_anon_in_1_e_valid (_coupler_from_rockettile_auto_tl_out_e_valid), // @[LazyScope.scala:98:27]
.auto_anon_in_1_e_bits_sink (_coupler_from_rockettile_auto_tl_out_e_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_in_0_a_ready (coupler_from_bus_named_fbus_auto_widget_anon_out_a_ready),
.auto_anon_in_0_a_valid (coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_a_bits_opcode (coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_a_bits_param (coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_a_bits_size (coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_a_bits_source (coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_a_bits_address (coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_a_bits_mask (coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_a_bits_data (coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_a_bits_corrupt (coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_d_ready (coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_0_d_valid (coupler_from_bus_named_fbus_auto_widget_anon_out_d_valid),
.auto_anon_in_0_d_bits_opcode (coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_opcode),
.auto_anon_in_0_d_bits_param (coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_param),
.auto_anon_in_0_d_bits_size (coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_size),
.auto_anon_in_0_d_bits_source (coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_source),
.auto_anon_in_0_d_bits_sink (coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_sink),
.auto_anon_in_0_d_bits_denied (coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_denied),
.auto_anon_in_0_d_bits_data (coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_corrupt),
.auto_anon_out_1_a_ready (_system_bus_xbar_auto_anon_in_1_a_ready), // @[SystemBus.scala:47:43]
.auto_anon_out_1_a_valid (_fixer_auto_anon_out_1_a_valid),
.auto_anon_out_1_a_bits_opcode (_fixer_auto_anon_out_1_a_bits_opcode),
.auto_anon_out_1_a_bits_param (_fixer_auto_anon_out_1_a_bits_param),
.auto_anon_out_1_a_bits_size (_fixer_auto_anon_out_1_a_bits_size),
.auto_anon_out_1_a_bits_source (_fixer_auto_anon_out_1_a_bits_source),
.auto_anon_out_1_a_bits_address (_fixer_auto_anon_out_1_a_bits_address),
.auto_anon_out_1_a_bits_mask (_fixer_auto_anon_out_1_a_bits_mask),
.auto_anon_out_1_a_bits_data (_fixer_auto_anon_out_1_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (_fixer_auto_anon_out_1_a_bits_corrupt),
.auto_anon_out_1_b_ready (_fixer_auto_anon_out_1_b_ready),
.auto_anon_out_1_b_valid (_system_bus_xbar_auto_anon_in_1_b_valid), // @[SystemBus.scala:47:43]
.auto_anon_out_1_b_bits_param (_system_bus_xbar_auto_anon_in_1_b_bits_param), // @[SystemBus.scala:47:43]
.auto_anon_out_1_b_bits_address (_system_bus_xbar_auto_anon_in_1_b_bits_address), // @[SystemBus.scala:47:43]
.auto_anon_out_1_c_ready (_system_bus_xbar_auto_anon_in_1_c_ready), // @[SystemBus.scala:47:43]
.auto_anon_out_1_c_valid (_fixer_auto_anon_out_1_c_valid),
.auto_anon_out_1_c_bits_opcode (_fixer_auto_anon_out_1_c_bits_opcode),
.auto_anon_out_1_c_bits_param (_fixer_auto_anon_out_1_c_bits_param),
.auto_anon_out_1_c_bits_size (_fixer_auto_anon_out_1_c_bits_size),
.auto_anon_out_1_c_bits_source (_fixer_auto_anon_out_1_c_bits_source),
.auto_anon_out_1_c_bits_address (_fixer_auto_anon_out_1_c_bits_address),
.auto_anon_out_1_c_bits_data (_fixer_auto_anon_out_1_c_bits_data),
.auto_anon_out_1_c_bits_corrupt (_fixer_auto_anon_out_1_c_bits_corrupt),
.auto_anon_out_1_d_ready (_fixer_auto_anon_out_1_d_ready),
.auto_anon_out_1_d_valid (_system_bus_xbar_auto_anon_in_1_d_valid), // @[SystemBus.scala:47:43]
.auto_anon_out_1_d_bits_opcode (_system_bus_xbar_auto_anon_in_1_d_bits_opcode), // @[SystemBus.scala:47:43]
.auto_anon_out_1_d_bits_param (_system_bus_xbar_auto_anon_in_1_d_bits_param), // @[SystemBus.scala:47:43]
.auto_anon_out_1_d_bits_size (_system_bus_xbar_auto_anon_in_1_d_bits_size), // @[SystemBus.scala:47:43]
.auto_anon_out_1_d_bits_source (_system_bus_xbar_auto_anon_in_1_d_bits_source), // @[SystemBus.scala:47:43]
.auto_anon_out_1_d_bits_sink (_system_bus_xbar_auto_anon_in_1_d_bits_sink), // @[SystemBus.scala:47:43]
.auto_anon_out_1_d_bits_denied (_system_bus_xbar_auto_anon_in_1_d_bits_denied), // @[SystemBus.scala:47:43]
.auto_anon_out_1_d_bits_data (_system_bus_xbar_auto_anon_in_1_d_bits_data), // @[SystemBus.scala:47:43]
.auto_anon_out_1_d_bits_corrupt (_system_bus_xbar_auto_anon_in_1_d_bits_corrupt), // @[SystemBus.scala:47:43]
.auto_anon_out_1_e_valid (_fixer_auto_anon_out_1_e_valid),
.auto_anon_out_1_e_bits_sink (_fixer_auto_anon_out_1_e_bits_sink),
.auto_anon_out_0_a_ready (_system_bus_xbar_auto_anon_in_0_a_ready), // @[SystemBus.scala:47:43]
.auto_anon_out_0_a_valid (_fixer_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_fixer_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_fixer_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_fixer_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_fixer_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_fixer_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_fixer_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_fixer_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_fixer_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_fixer_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_system_bus_xbar_auto_anon_in_0_d_valid), // @[SystemBus.scala:47:43]
.auto_anon_out_0_d_bits_opcode (_system_bus_xbar_auto_anon_in_0_d_bits_opcode), // @[SystemBus.scala:47:43]
.auto_anon_out_0_d_bits_param (_system_bus_xbar_auto_anon_in_0_d_bits_param), // @[SystemBus.scala:47:43]
.auto_anon_out_0_d_bits_size (_system_bus_xbar_auto_anon_in_0_d_bits_size), // @[SystemBus.scala:47:43]
.auto_anon_out_0_d_bits_source (_system_bus_xbar_auto_anon_in_0_d_bits_source), // @[SystemBus.scala:47:43]
.auto_anon_out_0_d_bits_sink (_system_bus_xbar_auto_anon_in_0_d_bits_sink), // @[SystemBus.scala:47:43]
.auto_anon_out_0_d_bits_denied (_system_bus_xbar_auto_anon_in_0_d_bits_denied), // @[SystemBus.scala:47:43]
.auto_anon_out_0_d_bits_data (_system_bus_xbar_auto_anon_in_0_d_bits_data), // @[SystemBus.scala:47:43]
.auto_anon_out_0_d_bits_corrupt (_system_bus_xbar_auto_anon_in_0_d_bits_corrupt) // @[SystemBus.scala:47:43]
); // @[FIFOFixer.scala:152:27]
TLInterconnectCoupler_sbus_from_rockettile coupler_from_rockettile ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_tl_master_clock_xing_in_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready_0),
.auto_tl_master_clock_xing_in_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid_0),
.auto_tl_master_clock_xing_in_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param_0),
.auto_tl_master_clock_xing_in_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address_0),
.auto_tl_master_clock_xing_in_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready_0),
.auto_tl_master_clock_xing_in_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid_0),
.auto_tl_master_clock_xing_in_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode_0),
.auto_tl_master_clock_xing_in_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param_0),
.auto_tl_master_clock_xing_in_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size_0),
.auto_tl_master_clock_xing_in_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source_0),
.auto_tl_master_clock_xing_in_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink_0),
.auto_tl_master_clock_xing_in_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied_0),
.auto_tl_master_clock_xing_in_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data_0),
.auto_tl_master_clock_xing_in_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt_0),
.auto_tl_master_clock_xing_in_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid_0), // @[ClockDomain.scala:14:9]
.auto_tl_master_clock_xing_in_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink_0), // @[ClockDomain.scala:14:9]
.auto_tl_out_a_ready (_fixer_auto_anon_in_1_a_ready), // @[FIFOFixer.scala:152:27]
.auto_tl_out_a_valid (_coupler_from_rockettile_auto_tl_out_a_valid),
.auto_tl_out_a_bits_opcode (_coupler_from_rockettile_auto_tl_out_a_bits_opcode),
.auto_tl_out_a_bits_param (_coupler_from_rockettile_auto_tl_out_a_bits_param),
.auto_tl_out_a_bits_size (_coupler_from_rockettile_auto_tl_out_a_bits_size),
.auto_tl_out_a_bits_source (_coupler_from_rockettile_auto_tl_out_a_bits_source),
.auto_tl_out_a_bits_address (_coupler_from_rockettile_auto_tl_out_a_bits_address),
.auto_tl_out_a_bits_mask (_coupler_from_rockettile_auto_tl_out_a_bits_mask),
.auto_tl_out_a_bits_data (_coupler_from_rockettile_auto_tl_out_a_bits_data),
.auto_tl_out_a_bits_corrupt (_coupler_from_rockettile_auto_tl_out_a_bits_corrupt),
.auto_tl_out_b_ready (_coupler_from_rockettile_auto_tl_out_b_ready),
.auto_tl_out_b_valid (_fixer_auto_anon_in_1_b_valid), // @[FIFOFixer.scala:152:27]
.auto_tl_out_b_bits_param (_fixer_auto_anon_in_1_b_bits_param), // @[FIFOFixer.scala:152:27]
.auto_tl_out_b_bits_address (_fixer_auto_anon_in_1_b_bits_address), // @[FIFOFixer.scala:152:27]
.auto_tl_out_c_ready (_fixer_auto_anon_in_1_c_ready), // @[FIFOFixer.scala:152:27]
.auto_tl_out_c_valid (_coupler_from_rockettile_auto_tl_out_c_valid),
.auto_tl_out_c_bits_opcode (_coupler_from_rockettile_auto_tl_out_c_bits_opcode),
.auto_tl_out_c_bits_param (_coupler_from_rockettile_auto_tl_out_c_bits_param),
.auto_tl_out_c_bits_size (_coupler_from_rockettile_auto_tl_out_c_bits_size),
.auto_tl_out_c_bits_source (_coupler_from_rockettile_auto_tl_out_c_bits_source),
.auto_tl_out_c_bits_address (_coupler_from_rockettile_auto_tl_out_c_bits_address),
.auto_tl_out_c_bits_data (_coupler_from_rockettile_auto_tl_out_c_bits_data),
.auto_tl_out_c_bits_corrupt (_coupler_from_rockettile_auto_tl_out_c_bits_corrupt),
.auto_tl_out_d_ready (_coupler_from_rockettile_auto_tl_out_d_ready),
.auto_tl_out_d_valid (_fixer_auto_anon_in_1_d_valid), // @[FIFOFixer.scala:152:27]
.auto_tl_out_d_bits_opcode (_fixer_auto_anon_in_1_d_bits_opcode), // @[FIFOFixer.scala:152:27]
.auto_tl_out_d_bits_param (_fixer_auto_anon_in_1_d_bits_param), // @[FIFOFixer.scala:152:27]
.auto_tl_out_d_bits_size (_fixer_auto_anon_in_1_d_bits_size), // @[FIFOFixer.scala:152:27]
.auto_tl_out_d_bits_source (_fixer_auto_anon_in_1_d_bits_source), // @[FIFOFixer.scala:152:27]
.auto_tl_out_d_bits_sink (_fixer_auto_anon_in_1_d_bits_sink), // @[FIFOFixer.scala:152:27]
.auto_tl_out_d_bits_denied (_fixer_auto_anon_in_1_d_bits_denied), // @[FIFOFixer.scala:152:27]
.auto_tl_out_d_bits_data (_fixer_auto_anon_in_1_d_bits_data), // @[FIFOFixer.scala:152:27]
.auto_tl_out_d_bits_corrupt (_fixer_auto_anon_in_1_d_bits_corrupt), // @[FIFOFixer.scala:152:27]
.auto_tl_out_e_valid (_coupler_from_rockettile_auto_tl_out_e_valid),
.auto_tl_out_e_bits_sink (_coupler_from_rockettile_auto_tl_out_e_bits_sink)
); // @[LazyScope.scala:98:27]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to
Chisel by Andrew Waterman).
Copyright 2019, 2020 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf)
val notNaN_isInfOut = io.a.isInf || io.b.isInf
val notNaN_isZeroOut = io.a.isZero || io.b.isZero
val notNaN_signOut = io.a.sign ^ io.b.sign
val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S
val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc
io.rawOut.isInf := notNaN_isInfOut
io.rawOut.isZero := notNaN_isZeroOut
io.rawOut.sExp := common_sExpOut
io.rawOut.isNaN := io.a.isNaN || io.b.isNaN
io.rawOut.sign := notNaN_signOut
io.rawOut.sig := common_sigOut
}
class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth))
mulFullRaw.io.a := io.a
mulFullRaw.io.b := io.b
io.invalidExc := mulFullRaw.io.invalidExc
io.rawOut := mulFullRaw.io.rawOut
io.rawOut.sig := {
val sig = mulFullRaw.io.rawOut.sig
Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR)
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulRawFN = Module(new MulRawFN(expWidth, sigWidth))
mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulRawFN.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulFullRawFN_12( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
| module NoCMonitor_92( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h4; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_136( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
class IntXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o := cat }
}
}
class IntSyncXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntSyncNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o.sync := cat }
}
}
object IntXbar {
def apply()(implicit p: Parameters): IntNode = {
val xbar = LazyModule(new IntXbar)
xbar.intnode
}
}
object IntSyncXbar {
def apply()(implicit p: Parameters): IntSyncNode = {
val xbar = LazyModule(new IntSyncXbar)
xbar.intnode
}
}
| module IntXbar_i4_o1_5( // @[Xbar.scala:22:9]
input auto_anon_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_1, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4 // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_3_0_0 = auto_anon_in_3_0; // @[Xbar.scala:22:9]
wire auto_anon_in_2_0_0 = auto_anon_in_2_0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9]
wire auto_anon_in_1_1_0 = auto_anon_in_1_1; // @[Xbar.scala:22:9]
wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_3_0 = auto_anon_in_3_0_0; // @[Xbar.scala:22:9]
wire anonIn_2_0 = auto_anon_in_2_0_0; // @[Xbar.scala:22:9]
wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9]
wire anonIn_1_1 = auto_anon_in_1_1_0; // @[Xbar.scala:22:9]
wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9]
wire anonOut_0; // @[MixedNode.scala:542:17]
wire anonOut_1; // @[MixedNode.scala:542:17]
wire anonOut_2; // @[MixedNode.scala:542:17]
wire anonOut_3; // @[MixedNode.scala:542:17]
wire anonOut_4; // @[MixedNode.scala:542:17]
wire auto_anon_out_0_0; // @[Xbar.scala:22:9]
wire auto_anon_out_1_0; // @[Xbar.scala:22:9]
wire auto_anon_out_2_0; // @[Xbar.scala:22:9]
wire auto_anon_out_3_0; // @[Xbar.scala:22:9]
wire auto_anon_out_4_0; // @[Xbar.scala:22:9]
assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_2 = anonIn_1_1; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_3 = anonIn_2_0; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_4 = anonIn_3_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1_0 = anonOut_1; // @[Xbar.scala:22:9]
assign auto_anon_out_2_0 = anonOut_2; // @[Xbar.scala:22:9]
assign auto_anon_out_3_0 = anonOut_3; // @[Xbar.scala:22:9]
assign auto_anon_out_4_0 = anonOut_4; // @[Xbar.scala:22:9]
assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1 = auto_anon_out_1_0; // @[Xbar.scala:22:9]
assign auto_anon_out_2 = auto_anon_out_2_0; // @[Xbar.scala:22:9]
assign auto_anon_out_3 = auto_anon_out_3_0; // @[Xbar.scala:22:9]
assign auto_anon_out_4 = auto_anon_out_4_0; // @[Xbar.scala:22:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_71( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_71 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File btb.scala:
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomBTBParams(
nSets: Int = 128,
nWays: Int = 2,
offsetSz: Int = 13,
extendedNSets: Int = 128
)
class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
override val nWays = params.nWays
val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1
val offsetSz = params.offsetSz
val extendedNSets = params.extendedNSets
require(isPow2(nSets))
require(isPow2(extendedNSets) || extendedNSets == 0)
require(extendedNSets <= nSets)
require(extendedNSets >= 1)
class BTBEntry extends Bundle {
val offset = SInt(offsetSz.W)
val extended = Bool()
}
val btbEntrySz = offsetSz + 1
class BTBMeta extends Bundle {
val is_br = Bool()
val tag = UInt(tagSz.W)
}
val btbMetaSz = tagSz + 1
class BTBPredictMeta extends Bundle {
val write_way = UInt(log2Ceil(nWays).W)
}
val s1_meta = Wire(new BTBPredictMeta)
val f3_meta = RegNext(RegNext(s1_meta))
io.f3_meta := f3_meta.asUInt
override val metaSz = s1_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }
val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }
val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))
val mems = (((0 until nWays) map ({w:Int => Seq(
(f"btb_meta_way$w", nSets, bankWidth * btbMetaSz),
(f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended)))
val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })
val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })
val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)
val s1_req_tag = s1_idx >> log2Ceil(nSets)
val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))
val s1_is_br = Wire(Vec(bankWidth, Bool()))
val s1_is_jal = Wire(Vec(bankWidth, Bool()))
val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>
VecInit((0 until nWays) map { w =>
s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)
})
})
val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }
val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }
for (w <- 0 until bankWidth) {
val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)
val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)
s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)
s1_resp(w).bits := Mux(
entry_btb.extended,
s1_req_rebtb,
(s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)
s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br
s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br
io.resp.f2(w) := io.resp_in(0).f2(w)
io.resp.f3(w) := io.resp_in(0).f3(w)
when (RegNext(s1_hits(w))) {
io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))
io.resp.f2(w).is_br := RegNext(s1_is_br(w))
io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))
when (RegNext(s1_is_jal(w))) {
io.resp.f2(w).taken := true.B
}
}
when (RegNext(RegNext(s1_hits(w)))) {
io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)
io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)
io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)
when (RegNext(RegNext(s1_is_jal(w)))) {
io.resp.f3(w).taken := true.B
}
}
}
val alloc_way = if (nWays > 1) {
val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))
val l = log2Ceil(nWays)
val nChunks = (r_metas.getWidth + l - 1) / l
val chunks = (0 until nChunks) map { i =>
r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
}
chunks.reduce(_^_)
} else {
0.U
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
alloc_way)
val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)
val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt
val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt
val new_offset_value = (s1_update.bits.target.asSInt -
(s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)
val offset_is_extended = (new_offset_value > max_offset_value ||
new_offset_value < min_offset_value)
val s1_update_wbtb_data = Wire(new BTBEntry)
s1_update_wbtb_data.extended := offset_is_extended
s1_update_wbtb_data.offset := new_offset_value
val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &
Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))
val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &
(Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |
(Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)
)
)
val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))
for (w <- 0 until bankWidth) {
s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))
s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)
}
for (w <- 0 until nWays) {
when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {
btb(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),
VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wbtb_mask).asBools
)
meta(w).write(
Mux(doing_reset,
reset_idx,
s1_update_idx),
Mux(doing_reset,
VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),
VecInit(s1_update_wmeta_data.map(_.asUInt))),
Mux(doing_reset,
(~(0.U(bankWidth.W))),
s1_update_wmeta_mask).asBools
)
}
}
when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {
ebtb.write(s1_update_idx, s1_update.bits.target)
}
}
| module meta_0_1( // @[btb.scala:65:47]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [123:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [123:0] W0_data,
input [3:0] W0_mask
);
meta_0_ext meta_0_ext ( // @[btb.scala:65:47]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[btb.scala:65:47]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
File AccumulatorMem.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
class AccumulatorReadReq[T <: Data: Arithmetic, U <: Data](n: Int, acc_t: T, scale_t: U) extends Bundle {
val addr = UInt(log2Ceil(n).W)
val scale = scale_t
val igelu_qb = acc_t.cloneType
val igelu_qc = acc_t.cloneType
val iexp_qln2 = acc_t.cloneType
val iexp_qln2_inv = acc_t.cloneType
val act = UInt(Activation.bitwidth.W) // TODO magic number
val full = Bool() // Whether or not we return the full bitwidth output
val fromDMA = Bool()
}
class AccumulatorReadResp[T <: Data: Arithmetic, U <: Data](fullDataType: Vec[Vec[T]], scale_t: U) extends Bundle {
val data = fullDataType.cloneType
val fromDMA = Bool()
val scale = scale_t.cloneType
val igelu_qb = fullDataType.head.head.cloneType
val igelu_qc = fullDataType.head.head.cloneType
val iexp_qln2 = fullDataType.head.head.cloneType
val iexp_qln2_inv = fullDataType.head.head.cloneType
val act = UInt(Activation.bitwidth.W) // TODO magic number
val acc_bank_id = UInt(2.W) // TODO magic number
}
class AccumulatorReadIO[T <: Data: Arithmetic, U <: Data](n: Int, fullDataType: Vec[Vec[T]], scale_t: U) extends Bundle {
val req = Decoupled(new AccumulatorReadReq[T, U](n, fullDataType.head.head.cloneType, scale_t))
val resp = Flipped(Decoupled(new AccumulatorReadResp[T, U](fullDataType, scale_t)))
}
class AccumulatorWriteReq[T <: Data: Arithmetic](n: Int, t: Vec[Vec[T]]) extends Bundle {
val addr = UInt(log2Up(n).W)
val data = t.cloneType
val acc = Bool()
val mask = Vec(t.getWidth / 8, Bool()) // TODO Use aligned_to here
}
class AccumulatorMemIO [T <: Data: Arithmetic, U <: Data](n: Int, t: Vec[Vec[T]], scale_t: U,
acc_sub_banks: Int, use_shared_ext_mem: Boolean
) extends Bundle {
val read = Flipped(new AccumulatorReadIO(n, t, scale_t))
val write = Flipped(Decoupled(new AccumulatorWriteReq(n, t)))
val ext_mem = if (use_shared_ext_mem) Some(Vec(acc_sub_banks, new ExtMemIO)) else None
val adder = new Bundle {
val valid = Output(Bool())
val op1 = Output(t.cloneType)
val op2 = Output(t.cloneType)
val sum = Input(t.cloneType)
}
}
class AccPipe[T <: Data : Arithmetic](latency: Int, t: T)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val op1 = Input(t.cloneType)
val op2 = Input(t.cloneType)
val sum = Output(t.cloneType)
})
import ev._
io.sum := ShiftRegister(io.op1 + io.op2, latency)
}
class AccPipeShared[T <: Data : Arithmetic](latency: Int, t: Vec[Vec[T]], banks: Int) extends Module {
val io = IO(new Bundle {
val in_sel = Input(Vec(banks, Bool()))
val ina = Input(Vec(banks, t.cloneType))
val inb = Input(Vec(banks, t.cloneType))
val out = Output(t.cloneType)
})
val ina = Mux1H(io.in_sel, io.ina)
val inb = Mux1H(io.in_sel, io.inb)
io.out := VecInit((ina zip inb).map { case (rv, wv) =>
VecInit((rv zip wv).map { case (re, we) =>
val m = Module(new AccPipe(latency, t.head.head.cloneType))
m.io.op1 := re
m.io.op2 := we
m.io.sum
})
})
}
class AccumulatorMem[T <: Data, U <: Data](
n: Int, t: Vec[Vec[T]], scale_func: (T, U) => T, scale_t: U,
acc_singleported: Boolean, acc_sub_banks: Int,
use_shared_ext_mem: Boolean,
acc_latency: Int, acc_type: T, is_dummy: Boolean
)
(implicit ev: Arithmetic[T]) extends Module {
// TODO Do writes in this module work with matrices of size 2? If we try to read from an address right after writing
// to it, then we might not get the written data. We might need some kind of cooldown counter after addresses in the
// accumulator have been written to for configurations with such small matrices
// TODO make a new aligned_to variable specifically for AccumulatorMem. We should assume that inputs are at least
// accType.getWidth/8 aligned, because it won't make sense to do matrix additions directly in the DMA otherwise.
import ev._
// TODO unify this with TwoPortSyncMemIO
val io = IO(new AccumulatorMemIO(n, t, scale_t, acc_sub_banks, use_shared_ext_mem))
require (acc_latency >= 2)
val pipelined_writes = Reg(Vec(acc_latency, Valid(new AccumulatorWriteReq(n, t))))
val oldest_pipelined_write = pipelined_writes(acc_latency-1)
pipelined_writes(0).valid := io.write.fire
pipelined_writes(0).bits := io.write.bits
for (i <- 1 until acc_latency) {
pipelined_writes(i) := pipelined_writes(i-1)
}
val rdata_for_adder = Wire(t)
rdata_for_adder := DontCare
val rdata_for_read_resp = Wire(t)
rdata_for_read_resp := DontCare
val adder_sum = io.adder.sum
io.adder.valid := pipelined_writes(0).valid && pipelined_writes(0).bits.acc
io.adder.op1 := rdata_for_adder
io.adder.op2 := pipelined_writes(0).bits.data
val block_read_req = WireInit(false.B)
val block_write_req = WireInit(false.B)
val mask_len = t.getWidth / 8
val mask_elem = UInt((t.getWidth / mask_len).W)
if (!acc_singleported && !is_dummy) {
require(!use_shared_ext_mem)
val mem = TwoPortSyncMem(n, t, mask_len) // TODO We assume byte-alignment here. Use aligned_to instead
mem.io.waddr := oldest_pipelined_write.bits.addr
mem.io.wen := oldest_pipelined_write.valid
mem.io.wdata := Mux(oldest_pipelined_write.bits.acc, adder_sum, oldest_pipelined_write.bits.data)
mem.io.mask := oldest_pipelined_write.bits.mask
rdata_for_adder := mem.io.rdata
rdata_for_read_resp := mem.io.rdata
mem.io.raddr := Mux(io.write.fire && io.write.bits.acc, io.write.bits.addr, io.read.req.bits.addr)
mem.io.ren := io.read.req.fire || (io.write.fire && io.write.bits.acc)
} else if (!is_dummy) {
val rmw_req = Wire(Decoupled(UInt()))
rmw_req.valid := io.write.valid && io.write.bits.acc
rmw_req.bits := io.write.bits.addr
rmw_req.ready := true.B
block_write_req := !rmw_req.ready
val only_read_req = Wire(Decoupled(UInt()))
only_read_req.valid := io.read.req.valid
only_read_req.bits := io.read.req.bits.addr
only_read_req.ready := true.B
block_read_req := !only_read_req.ready
for (i <- 0 until acc_sub_banks) {
def isThisBank(addr: UInt) = addr(log2Ceil(acc_sub_banks)-1,0) === i.U
def getBankIdx(addr: UInt) = addr >> log2Ceil(acc_sub_banks)
val (read, write) = if (use_shared_ext_mem) {
def read(addr: UInt, ren: Bool): Data = {
io.ext_mem.get(i).read_en := ren
io.ext_mem.get(i).read_addr := addr
io.ext_mem.get(i).read_data
}
io.ext_mem.get(i).write_en := false.B
io.ext_mem.get(i).write_addr := DontCare
io.ext_mem.get(i).write_data := DontCare
io.ext_mem.get(i).write_mask := DontCare
def write(addr: UInt, wdata: Vec[UInt], wmask: Vec[Bool]) = {
io.ext_mem.get(i).write_en := true.B
io.ext_mem.get(i).write_addr := addr
io.ext_mem.get(i).write_data := wdata.asUInt
io.ext_mem.get(i).write_mask := wmask.asUInt
}
(read _, write _)
} else {
val mem = SyncReadMem(n / acc_sub_banks, Vec(mask_len, mask_elem))
def read(addr: UInt, ren: Bool): Data = mem.read(addr, ren)
def write(addr: UInt, wdata: Vec[UInt], wmask: Vec[Bool]) = mem.write(addr, wdata, wmask)
(read _, write _)
}
val ren = WireInit(false.B)
val raddr = WireInit(getBankIdx(rmw_req.bits))
val nEntries = 3
// Writes coming 2 cycles after read leads to bad bank behavior
// Add another buffer here
class W_Q_Entry[T <: Data](mask_len: Int, mask_elem: T) extends Bundle {
val valid = Bool()
val data = Vec(mask_len, mask_elem)
val mask = Vec(mask_len, Bool())
val addr = UInt(log2Ceil(n/acc_sub_banks).W)
}
val w_q = Reg(Vec(nEntries, new W_Q_Entry(mask_len, mask_elem)))
for (e <- w_q) {
when (e.valid) {
assert(!(
io.write.fire && io.write.bits.acc &&
isThisBank(io.write.bits.addr) && getBankIdx(io.write.bits.addr) === e.addr &&
((io.write.bits.mask.asUInt & e.mask.asUInt) =/= 0.U)
), "you cannot accumulate to an AccumulatorMem address until previous writes to that address have completed")
when (io.write.bits.acc && isThisBank(io.write.bits.addr) && getBankIdx(io.write.bits.addr) === e.addr) {
rmw_req.ready := false.B
}
when (isThisBank(io.read.req.bits.addr) && getBankIdx(io.read.req.bits.addr) === e.addr) {
only_read_req.ready := false.B
}
}
}
val w_q_head = RegInit(1.U(nEntries.W))
val w_q_tail = RegInit(1.U(nEntries.W))
val w_q_full = (w_q_tail.asBools zip w_q.map(_.valid)).map({ case (h,v) => h && v }).reduce(_||_)
val w_q_empty = !(w_q_head.asBools zip w_q.map(_.valid)).map({ case (h,v) => h && v }).reduce(_||_)
val wen = WireInit(false.B)
val wdata = Mux1H(w_q_head.asBools, w_q.map(_.data))
val wmask = Mux1H(w_q_head.asBools, w_q.map(_.mask))
val waddr = Mux1H(w_q_head.asBools, w_q.map(_.addr))
when (wen) {
w_q_head := (w_q_head << 1).asUInt | w_q_head(nEntries-1)
for (i <- 0 until nEntries) {
when (w_q_head(i)) {
w_q(i).valid := false.B
}
}
}
val w_q_push = oldest_pipelined_write.valid && isThisBank(oldest_pipelined_write.bits.addr)
when (w_q_push) {
assert(!w_q_full || wen, "we ran out of acc-sub-bank write q entries")
w_q_tail := (w_q_tail << 1).asUInt | w_q_tail(nEntries-1)
for (i <- 0 until nEntries) {
when (w_q_tail(i)) {
w_q(i).valid := true.B
w_q(i).data := Mux(oldest_pipelined_write.bits.acc, adder_sum, oldest_pipelined_write.bits.data).asTypeOf(Vec(mask_len, mask_elem))
w_q(i).mask := oldest_pipelined_write.bits.mask
w_q(i).addr := getBankIdx(oldest_pipelined_write.bits.addr)
}
}
}
val bank_rdata = read(raddr, ren && !wen).asTypeOf(t)
when (RegNext(ren && rmw_req.valid && isThisBank(rmw_req.bits))) {
rdata_for_adder := bank_rdata
} .elsewhen (RegNext(ren)) {
rdata_for_read_resp := bank_rdata
}
when (wen) {
write(waddr, wdata, wmask)
}
// Three requestors, 1 slot
// Priority is (in descending order):
// 1. incoming reads for RMW
// 2. writes from RMW
// 3. incoming reads
when (rmw_req.fire && isThisBank(rmw_req.bits)) {
ren := true.B
when (isThisBank(only_read_req.bits)) {
only_read_req.ready := false.B
}
} .elsewhen (!w_q_empty) {
wen := true.B
when (isThisBank(only_read_req.bits)) {
only_read_req.ready := false.B
}
} .otherwise {
ren := isThisBank(only_read_req.bits) && only_read_req.fire
raddr := getBankIdx(only_read_req.bits)
}
when (reset.asBool) {
w_q.foreach(_.valid := false.B)
}
}
}
val q = Module(new Queue(new AccumulatorReadResp(t, scale_t), 1, true, true))
q.io.enq.bits.data := rdata_for_read_resp
if (is_dummy) {
rdata_for_read_resp := DontCare
rdata_for_adder := DontCare
}
q.io.enq.bits.scale := RegNext(io.read.req.bits.scale)
q.io.enq.bits.igelu_qb := RegNext(io.read.req.bits.igelu_qb)
q.io.enq.bits.igelu_qc := RegNext(io.read.req.bits.igelu_qc)
q.io.enq.bits.iexp_qln2 := RegNext(io.read.req.bits.iexp_qln2)
q.io.enq.bits.iexp_qln2_inv := RegNext(io.read.req.bits.iexp_qln2_inv)
q.io.enq.bits.act := RegNext(io.read.req.bits.act)
q.io.enq.bits.fromDMA := RegNext(io.read.req.bits.fromDMA)
q.io.enq.bits.acc_bank_id := DontCare
q.io.enq.valid := RegNext(io.read.req.fire)
val p = q.io.deq
io.read.resp.bits.data := p.bits.data
io.read.resp.bits.fromDMA := p.bits.fromDMA
io.read.resp.bits.igelu_qb := p.bits.igelu_qb
io.read.resp.bits.igelu_qc := p.bits.igelu_qc
io.read.resp.bits.iexp_qln2 := p.bits.iexp_qln2
io.read.resp.bits.iexp_qln2_inv := p.bits.iexp_qln2_inv
io.read.resp.bits.act := p.bits.act
io.read.resp.bits.scale := p.bits.scale
io.read.resp.bits.acc_bank_id := DontCare // This is set in Scratchpad
io.read.resp.valid := p.valid
p.ready := io.read.resp.ready
val q_will_be_empty = (q.io.count +& q.io.enq.fire) - q.io.deq.fire === 0.U
io.read.req.ready := q_will_be_empty && (
// Make sure we aren't accumulating, which would take over both ports
!(io.write.valid && io.write.bits.acc) &&
!pipelined_writes.map(r => r.valid && r.bits.addr === io.read.req.bits.addr).reduce(_||_) &&
!block_read_req
)
io.write.ready := !block_write_req &&
!pipelined_writes.map(r => r.valid && r.bits.addr === io.write.bits.addr && io.write.bits.acc).reduce(_||_)
when (reset.asBool) {
pipelined_writes.foreach(_.valid := false.B)
}
// assert(!(io.read.req.valid && io.write.en && io.write.acc), "reading and accumulating simultaneously is not supported")
assert(!(io.read.req.fire && io.write.fire && io.read.req.bits.addr === io.write.bits.addr), "reading from and writing to same address is not supported")
}
| module AccPipe_1( // @[AccumulatorMem.scala:63:7]
input clock, // @[AccumulatorMem.scala:63:7]
input reset, // @[AccumulatorMem.scala:63:7]
input [31:0] io_op1, // @[AccumulatorMem.scala:64:14]
input [31:0] io_op2, // @[AccumulatorMem.scala:64:14]
output [31:0] io_sum // @[AccumulatorMem.scala:64:14]
);
wire [31:0] io_op1_0 = io_op1; // @[AccumulatorMem.scala:63:7]
wire [31:0] io_op2_0 = io_op2; // @[AccumulatorMem.scala:63:7]
wire [31:0] io_sum_0; // @[AccumulatorMem.scala:63:7]
wire [32:0] _io_sum_T = {io_op1_0[31], io_op1_0} + {io_op2_0[31], io_op2_0}; // @[Arithmetic.scala:94:38]
wire [31:0] _io_sum_T_1 = _io_sum_T[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _io_sum_T_2 = _io_sum_T_1; // @[Arithmetic.scala:94:38]
reg [31:0] io_sum_r; // @[AccumulatorMem.scala:70:26]
assign io_sum_0 = io_sum_r; // @[AccumulatorMem.scala:63:7, :70:26]
always @(posedge clock) // @[AccumulatorMem.scala:63:7]
io_sum_r <= _io_sum_T_2; // @[Arithmetic.scala:94:38]
assign io_sum = io_sum_0; // @[AccumulatorMem.scala:63:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_135( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a32d64s4k3z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_23 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s4k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s4k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
| module MSHR_3( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_1 = _req_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire req_clientBit = _req_clientBit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:56:48]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10]
wire _probe_bit_T_1 = _probe_bit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}]
wire probe_bit = _probe_bit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_1 = _new_clientBit_T == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire new_clientBit = _new_clientBit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_36( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [2:0] b_first_counter; // @[Edges.scala:229:27]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [5:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [34:0] inflight; // @[Monitor.scala:614:27]
reg [139:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [139:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [34:0] inflight_1; // @[Monitor.scala:726:35]
reg [139:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [6:0] inflight_2; // @[Monitor.scala:828:27]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35]
wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_344( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_15( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34]
wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34]
wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34]
wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1492 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1492; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1492; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1565 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1565; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1565; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1565; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [16:0] a_set; // @[Monitor.scala:626:34]
wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [135:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1418 = _T_1492 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1418 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1418 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1418 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1418 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1418 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [16:0] d_clr; // @[Monitor.scala:664:34]
wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1464 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1464 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1433 = _T_1565 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1433 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1433 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1433 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16:0] d_clr_1; // @[Monitor.scala:774:34]
wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1536 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1536 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1518 = _T_1565 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1518 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1518 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1518 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module AsyncResetRegVec_w1_i0_5( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
input io_en // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire io_en_0 = io_en; // @[AsyncResetReg.scala:56:7]
wire _reg_T = 1'h1; // @[AsyncResetReg.scala:56:7, :61:29]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
wire reg_0 = 1'h0; // @[AsyncResetReg.scala:61:50]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File SourceE.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
class SourceERequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val sink = UInt(params.outer.bundle.sinkBits.W)
}
class SourceE(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new SourceERequest(params)))
val e = Decoupled(new TLBundleE(params.outer.bundle))
})
// ready must be a register, because we derive valid from ready
require (!params.micro.outerBuf.e.pipe && params.micro.outerBuf.e.isDefined)
val e = Wire(chiselTypeOf(io.e))
io.e <> params.micro.outerBuf.e(e)
io.req.ready := e.ready
e.valid := io.req.valid
e.bits.sink := io.req.bits.sink
// we can't cover valid+!ready, because no backpressure on E is common
}
| module SourceE( // @[SourceE.scala:29:7]
input clock, // @[SourceE.scala:29:7]
input reset, // @[SourceE.scala:29:7]
output io_req_ready, // @[SourceE.scala:31:14]
input io_req_valid, // @[SourceE.scala:31:14]
input [2:0] io_req_bits_sink, // @[SourceE.scala:31:14]
output io_e_valid, // @[SourceE.scala:31:14]
output [2:0] io_e_bits_sink // @[SourceE.scala:31:14]
);
Queue2_TLBundleE_a32d64s4k3z3c io_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (io_req_ready),
.io_enq_valid (io_req_valid),
.io_enq_bits_sink (io_req_bits_sink),
.io_deq_valid (io_e_valid),
.io_deq_bits_sink (io_e_bits_sink)
); // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File DMA.scala:
package gemmini
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp}
import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket.MStatus
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import Util._
import midas.targetutils.PerfCounter
import midas.targetutils.SynthesizePrintf
class StreamReadRequest[U <: Data](spad_rows: Int, acc_rows: Int, mvin_scale_t_bits: Int)(implicit p: Parameters) extends CoreBundle {
val vaddr = UInt(coreMaxAddrBits.W)
val spaddr = UInt(log2Up(spad_rows max acc_rows).W) // TODO use LocalAddr in DMA
val is_acc = Bool()
val accumulate = Bool()
val has_acc_bitwidth = Bool()
val scale = UInt(mvin_scale_t_bits.W)
val status = new MStatus
val len = UInt(16.W) // TODO magic number
val repeats = UInt(16.W) // TODO magic number
val pixel_repeats = UInt(8.W) // TODO magic number
val block_stride = UInt(16.W) // TODO magic number
val cmd_id = UInt(8.W) // TODO magic number
}
class StreamReadResponse[U <: Data](spadWidth: Int, accWidth: Int, spad_rows: Int, acc_rows: Int, aligned_to: Int, mvin_scale_t_bits: Int)
(implicit p: Parameters) extends CoreBundle {
val data = UInt((spadWidth max accWidth).W)
val addr = UInt(log2Up(spad_rows max acc_rows).W)
val mask = Vec((spadWidth max accWidth) / (aligned_to * 8) max 1, Bool())
val is_acc = Bool()
val accumulate = Bool()
val has_acc_bitwidth = Bool()
val scale = UInt(mvin_scale_t_bits.W)
val repeats = UInt(16.W) // TODO magic number
val pixel_repeats = UInt(16.W) // TODO magic number
val len = UInt(16.W) // TODO magic number
val last = Bool()
val bytes_read = UInt(8.W) // TODO magic number
val cmd_id = UInt(8.W) // TODO magic number
}
class StreamReader[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T, U, V], nXacts: Int, beatBits: Int, maxBytes: Int, spadWidth: Int, accWidth: Int, aligned_to: Int,
spad_rows: Int, acc_rows: Int, meshRows: Int, use_tlb_register_filter: Boolean, use_firesim_simulation_counters: Boolean)
(implicit p: Parameters) extends LazyModule {
val core = LazyModule(new StreamReaderCore(config, nXacts, beatBits, maxBytes, spadWidth, accWidth, aligned_to, spad_rows, acc_rows, meshRows, use_tlb_register_filter, use_firesim_simulation_counters))
val node = core.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new StreamReadRequest(spad_rows, acc_rows, config.mvin_scale_t_bits)))
val resp = Decoupled(new StreamReadResponse(spadWidth, accWidth, spad_rows, acc_rows, aligned_to, config.mvin_scale_t_bits))
val tlb = new FrontendTLBIO
val busy = Output(Bool())
val flush = Input(Bool())
val counter = new CounterEventIO()
})
val nCmds = (nXacts / meshRows) + 1
val xactTracker = Module(new XactTracker(nXacts, maxBytes, spadWidth, accWidth, spad_rows, acc_rows, maxBytes, config.mvin_scale_t_bits, nCmds, use_firesim_simulation_counters))
val beatPacker = Module(new BeatMerger(beatBits, maxBytes, spadWidth, accWidth, spad_rows, acc_rows, maxBytes, aligned_to, meshRows, config.mvin_scale_t_bits, nCmds))
core.module.io.req <> io.req
io.tlb <> core.module.io.tlb
io.busy := xactTracker.io.busy
core.module.io.flush := io.flush
xactTracker.io.alloc <> core.module.io.reserve
xactTracker.io.peek.xactid := RegEnableThru(core.module.io.beatData.bits.xactid, beatPacker.io.req.fire)
xactTracker.io.peek.pop := beatPacker.io.in.fire && core.module.io.beatData.bits.last
core.module.io.beatData.ready := beatPacker.io.in.ready
beatPacker.io.req.valid := core.module.io.beatData.valid
beatPacker.io.req.bits := xactTracker.io.peek.entry
beatPacker.io.req.bits.lg_len_req := core.module.io.beatData.bits.lg_len_req
beatPacker.io.in.valid := core.module.io.beatData.valid
beatPacker.io.in.bits := core.module.io.beatData.bits.data
beatPacker.io.out.ready := io.resp.ready
io.resp.valid := beatPacker.io.out.valid
io.resp.bits.data := beatPacker.io.out.bits.data
io.resp.bits.addr := beatPacker.io.out.bits.addr
io.resp.bits.mask := beatPacker.io.out.bits.mask
io.resp.bits.is_acc := beatPacker.io.out.bits.is_acc
io.resp.bits.accumulate := beatPacker.io.out.bits.accumulate
io.resp.bits.has_acc_bitwidth := beatPacker.io.out.bits.has_acc_bitwidth
io.resp.bits.scale := RegEnable(xactTracker.io.peek.entry.scale, beatPacker.io.req.fire)
io.resp.bits.repeats := RegEnable(xactTracker.io.peek.entry.repeats, beatPacker.io.req.fire)
io.resp.bits.pixel_repeats := RegEnable(xactTracker.io.peek.entry.pixel_repeats, beatPacker.io.req.fire)
io.resp.bits.len := RegEnable(xactTracker.io.peek.entry.len, beatPacker.io.req.fire)
io.resp.bits.cmd_id := RegEnable(xactTracker.io.peek.entry.cmd_id, beatPacker.io.req.fire)
io.resp.bits.bytes_read := RegEnable(xactTracker.io.peek.entry.bytes_to_read, beatPacker.io.req.fire)
io.resp.bits.last := beatPacker.io.out.bits.last
io.counter := DontCare
io.counter.collect(core.module.io.counter)
io.counter.collect(xactTracker.io.counter)
}
}
class StreamReadBeat (val nXacts: Int, val beatBits: Int, val maxReqBytes: Int) extends Bundle {
val xactid = UInt(log2Up(nXacts).W)
val data = UInt(beatBits.W)
val lg_len_req = UInt(log2Up(log2Up(maxReqBytes+1)+1).W)
val last = Bool()
}
// TODO StreamReaderCore and StreamWriter are actually very alike. Is there some parent class they could both inherit from?
class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T, U, V], nXacts: Int, beatBits: Int,
maxBytes: Int, spadWidth: Int, accWidth: Int, aligned_to: Int,
spad_rows: Int, acc_rows: Int, meshRows: Int,
use_tlb_register_filter: Boolean,
use_firesim_simulation_counters: Boolean)
(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
name = "stream-reader", sourceId = IdRange(0, nXacts))))))
require(isPow2(aligned_to))
// TODO when we request data from multiple rows which are actually contiguous in main memory, we should merge them into fewer requests
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants {
val (tl, edge) = node.out(0)
val spadWidthBytes = spadWidth / 8
val accWidthBytes = accWidth / 8
val beatBytes = beatBits / 8
val nCmds = (nXacts / meshRows) + 1
val io = IO(new Bundle {
val req = Flipped(Decoupled(new StreamReadRequest(spad_rows, acc_rows, config.mvin_scale_t_bits)))
val reserve = new XactTrackerAllocIO(nXacts, maxBytes, spadWidth, accWidth, spad_rows, acc_rows, maxBytes, config.mvin_scale_t_bits, nCmds)
val beatData = Decoupled(new StreamReadBeat(nXacts, beatBits, maxBytes))
val tlb = new FrontendTLBIO
val flush = Input(Bool())
val counter = new CounterEventIO()
})
val s_idle :: s_req_new_block :: Nil = Enum(2)
val state = RegInit(s_idle)
val req = Reg(new StreamReadRequest(spad_rows, acc_rows, config.mvin_scale_t_bits))
val vaddr = req.vaddr
val bytesRequested = Reg(UInt(log2Ceil(spadWidthBytes max accWidthBytes max maxBytes).W)) // TODO this only needs to count up to (dataBytes/aligned_to), right?
val bytesLeft = Mux(req.has_acc_bitwidth, req.len * (config.accType.getWidth / 8).U, req.len * (config.inputType.getWidth / 8).U) - bytesRequested
val state_machine_ready_for_req = WireInit(state === s_idle)
io.req.ready := state_machine_ready_for_req
// Select the size and mask of the TileLink request
class Packet extends Bundle {
val size = UInt(log2Up(maxBytes+1).W)
val lg_size = UInt(log2Ceil(log2Ceil(maxBytes+1)).W)
val bytes_read = UInt(log2Up(maxBytes+1).W)
val shift = UInt(log2Up(maxBytes).W)
//val paddr = UInt(paddrBits.W)
val vaddr = UInt(vaddrBits.W)
}
// TODO Can we filter out the larger read_sizes here if the systolic array is small, in the same way that we do so
// for the write_sizes down below?
val read_sizes = ((aligned_to max beatBytes) to maxBytes by aligned_to).
filter(s => isPow2(s)).
filter(s => s % beatBytes == 0)
val read_packets = read_sizes.map { s =>
val lg_s = log2Ceil(s)
val vaddr_aligned_to_size = if (s == 1) vaddr else Cat(vaddr(vaddrBits-1, lg_s), 0.U(lg_s.W))
val vaddr_offset = if (s > 1) vaddr(lg_s-1, 0) else 0.U
val packet = Wire(new Packet())
packet.size := s.U
packet.lg_size := lg_s.U
packet.bytes_read := minOf(s.U - vaddr_offset, bytesLeft)
packet.shift := vaddr_offset
packet.vaddr := vaddr_aligned_to_size
packet
}
val read_packet = read_packets.reduce { (acc, p) =>
Mux(p.bytes_read > acc.bytes_read, p, acc)
}
val read_vaddr = read_packet.vaddr
val read_lg_size = read_packet.lg_size
val read_bytes_read = read_packet.bytes_read
val read_shift = read_packet.shift
// Firing off TileLink read requests and allocating space inside the reservation buffer for them
val get = edge.Get(
fromSource = io.reserve.xactid,
toAddress = 0.U, //read_paddr,
lgSize = read_lg_size
)._2
class TLBundleAWithInfo extends Bundle {
val tl_a = tl.a.bits.cloneType
val vaddr = Output(UInt(vaddrBits.W))
val status = Output(new MStatus)
}
val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo))
untranslated_a.valid := state === s_req_new_block && io.reserve.ready
untranslated_a.bits.tl_a := get
untranslated_a.bits.vaddr := read_vaddr
untranslated_a.bits.status := req.status
// 0 goes to retries, 1 goes to state machine
val retry_a = Wire(Decoupled(new TLBundleAWithInfo))
val tlb_arb = Module(new Arbiter(new TLBundleAWithInfo, 2))
tlb_arb.io.in(0) <> retry_a
tlb_arb.io.in(1) <> untranslated_a
val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true))
tlb_q.io.enq <> tlb_arb.io.out
io.tlb.req.valid := tlb_q.io.deq.valid
io.tlb.req.bits := DontCare
io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
io.tlb.req.bits.tlb_req.passthrough := false.B
io.tlb.req.bits.tlb_req.size := 0.U // send_size
io.tlb.req.bits.tlb_req.cmd := M_XRD
io.tlb.req.bits.status := tlb_q.io.deq.bits.status
val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true))
translate_q.io.enq <> tlb_q.io.deq
translate_q.io.deq.ready := true.B
retry_a.valid := translate_q.io.deq.valid && (io.tlb.resp.miss || !tl.a.ready)
retry_a.bits := translate_q.io.deq.bits
assert(retry_a.ready)
tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.miss
tl.a.bits := translate_q.io.deq.bits.tl_a
tl.a.bits.address := io.tlb.resp.paddr
io.reserve.valid := state === s_req_new_block && untranslated_a.ready // TODO decouple "reserve.valid" from "tl.a.ready"
io.reserve.entry.shift := read_shift
io.reserve.entry.is_acc := req.is_acc
io.reserve.entry.accumulate := req.accumulate
io.reserve.entry.has_acc_bitwidth := req.has_acc_bitwidth
io.reserve.entry.scale := req.scale
io.reserve.entry.repeats := req.repeats
io.reserve.entry.pixel_repeats := req.pixel_repeats
io.reserve.entry.len := req.len
io.reserve.entry.block_stride := req.block_stride
io.reserve.entry.lg_len_req := DontCare // TODO just remove this from the IO completely
io.reserve.entry.bytes_to_read := read_bytes_read
io.reserve.entry.cmd_id := req.cmd_id
io.reserve.entry.addr := req.spaddr + req.block_stride *
Mux(req.has_acc_bitwidth,
// We only add "if" statements here to satisfy the Verilator linter. The code would be cleaner without the
// "if" condition and the "else" clause. Similarly, the width expansions are also there to satisfy the Verilator
// linter, despite making the code uglier.
if (bytesRequested.getWidth >= log2Up(accWidthBytes+1)) bytesRequested / accWidthBytes.U(bytesRequested.getWidth.W) else 0.U,
if (bytesRequested.getWidth >= log2Up(spadWidthBytes+1)) bytesRequested / spadWidthBytes.U(bytesRequested.getWidth.W) else 0.U)
io.reserve.entry.spad_row_offset := Mux(req.has_acc_bitwidth, bytesRequested % accWidthBytes.U, bytesRequested % spadWidthBytes.U)
when (untranslated_a.fire) {
val next_vaddr = req.vaddr + read_bytes_read // send_size
val new_page = next_vaddr(pgIdxBits-1, 0) === 0.U
req.vaddr := next_vaddr
bytesRequested := bytesRequested + read_bytes_read // send_size
// when (send_size >= bytesLeft) {
when (read_bytes_read >= bytesLeft) {
// We're done with this request at this point
state_machine_ready_for_req := true.B
state := s_idle
}
}
// Forward TileLink read responses to the reservation buffer
tl.d.ready := io.beatData.ready
io.beatData.valid := tl.d.valid
io.beatData.bits.xactid := tl.d.bits.source
io.beatData.bits.data := tl.d.bits.data
io.beatData.bits.lg_len_req := tl.d.bits.size
io.beatData.bits.last := edge.last(tl.d)
// TODO the size data is already returned from TileLink, so there's no need for us to store it in the XactTracker ourselves
// Accepting requests to kick-start the state machine
when (io.req.fire) {
req := io.req.bits
bytesRequested := 0.U
state := s_req_new_block
}
// Performance counter
io.counter := DontCare
CounterEventIO.init(io.counter)
io.counter.connectEventSignal(CounterEvent.RDMA_ACTIVE_CYCLE, state =/= s_idle)
io.counter.connectEventSignal(CounterEvent.RDMA_TLB_WAIT_CYCLES, io.tlb.resp.miss)
io.counter.connectEventSignal(CounterEvent.RDMA_TL_WAIT_CYCLES, tl.a.valid && !tl.a.ready)
// External counters
val total_bytes_read = RegInit(0.U(CounterExternal.EXTERNAL_WIDTH.W))
when (io.counter.external_reset) {
total_bytes_read := 0.U
}.elsewhen (tl.d.fire) {
total_bytes_read := total_bytes_read + (1.U << tl.d.bits.size)
}
io.counter.connectExternalCounter(CounterExternal.RDMA_BYTES_REC, total_bytes_read)
if (use_firesim_simulation_counters) {
PerfCounter(state =/= s_idle, "rdma_active_cycles", "cycles during which the read dma is active")
PerfCounter(tl.a.ready && translate_q.io.deq.valid && io.tlb.resp.miss, "rdma_tlb_wait_cycles", "cycles during which the read dma is stalling as it waits for a TLB response")
PerfCounter(tl.a.valid && !tl.a.ready, "rdma_tl_wait_cycles", "cycles during which the read dma is stalling as it waits for the TileLink port to be available")
val cntr = Counter(500000)
when (cntr.inc()) {
printf(SynthesizePrintf("RDMA bytes rec: %d\n", total_bytes_read))
}
}
}
}
class StreamWriteRequest(val dataWidth: Int, val maxBytes: Int)(implicit p: Parameters) extends CoreBundle {
val vaddr = UInt(coreMaxAddrBits.W)
val data = UInt(dataWidth.W)
val len = UInt(log2Up((dataWidth/8 max maxBytes)+1).W) // The number of bytes to write
val block = UInt(8.W) // TODO magic number
val status = new MStatus
// Pooling variables
val pool_en = Bool()
val store_en = Bool()
}
class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes: Int, dataWidth: Int, aligned_to: Int,
inputType: T, block_cols: Int, use_tlb_register_filter: Boolean,
use_firesim_simulation_counters: Boolean)
(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
name = "stream-writer", sourceId = IdRange(0, nXacts))))))
require(isPow2(aligned_to))
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants {
val (tl, edge) = node.out(0)
val dataBytes = dataWidth / 8
val beatBytes = beatBits / 8
val lgBeatBytes = log2Ceil(beatBytes)
val maxBeatsPerReq = maxBytes / beatBytes
val inputTypeRowBytes = block_cols * inputType.getWidth / 8
val maxBlocks = maxBytes / inputTypeRowBytes
require(beatBytes > 0)
val io = IO(new Bundle {
val req = Flipped(Decoupled(new StreamWriteRequest(dataWidth, maxBytes)))
val tlb = new FrontendTLBIO
val busy = Output(Bool())
val flush = Input(Bool())
val counter = new CounterEventIO()
})
val (s_idle :: s_writing_new_block :: s_writing_beats :: Nil) = Enum(3)
val state = RegInit(s_idle)
val req = Reg(new StreamWriteRequest(dataWidth, maxBytes))
// TODO use the same register to hold data_blocks and data_single_block, so that this Mux here is not necessary
val data_blocks = Reg(Vec(maxBlocks, UInt((inputTypeRowBytes * 8).W)))
val data_single_block = Reg(UInt(dataWidth.W)) // For data that's just one-block-wide
val data = Mux(req.block === 0.U, data_single_block, data_blocks.asUInt)
val bytesSent = Reg(UInt(log2Ceil((dataBytes max maxBytes)+1).W)) // TODO this only needs to count up to (dataBytes/aligned_to), right?
val bytesLeft = req.len - bytesSent
val xactBusy = RegInit(0.U(nXacts.W))
val xactOnehot = PriorityEncoderOH(~xactBusy)
val xactId = OHToUInt(xactOnehot)
val xactBusy_fire = WireInit(false.B)
val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U)
val xactBusy_remove = ~Mux(tl.d.fire, (1.U << tl.d.bits.source).asUInt, 0.U)
xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt
val state_machine_ready_for_req = WireInit(state === s_idle)
io.req.ready := state_machine_ready_for_req
io.busy := xactBusy.orR || (state =/= s_idle)
val vaddr = req.vaddr
// Select the size and mask of the TileLink request
class Packet extends Bundle {
val size = UInt(log2Ceil(maxBytes+1).W)
val lg_size = UInt(log2Ceil(log2Ceil(maxBytes+1)+1).W)
val mask = Vec(maxBeatsPerReq, Vec(beatBytes, Bool()))
val vaddr = UInt(vaddrBits.W)
val is_full = Bool()
val bytes_written = UInt(log2Up(maxBytes+1).W)
val bytes_written_per_beat = Vec(maxBeatsPerReq, UInt(log2Up(beatBytes+1).W))
def total_beats(dummy: Int = 0) = Mux(size < beatBytes.U, 1.U, size / beatBytes.U(size.getWidth.W)) // The width expansion is added here solely to satsify Verilator's linter
}
val smallest_write_size = aligned_to max beatBytes
val write_sizes = (smallest_write_size to maxBytes by aligned_to).
filter(s => isPow2(s)).
filter(s => s % beatBytes == 0) /*.
filter(s => s <= dataBytes*2 || s == smallest_write_size)*/
val write_packets = write_sizes.map { s =>
val lg_s = log2Ceil(s)
val vaddr_aligned_to_size = if (s == 1) vaddr else Cat(vaddr(vaddrBits-1, lg_s), 0.U(lg_s.W))
val vaddr_offset = if (s > 1) vaddr(lg_s - 1, 0) else 0.U
val mask = (0 until maxBytes).map { i => i.U >= vaddr_offset && i.U < vaddr_offset +& bytesLeft && (i < s).B }
val bytes_written = {
Mux(vaddr_offset +& bytesLeft > s.U, s.U - vaddr_offset, bytesLeft)
}
val packet = Wire(new Packet())
packet.size := s.U
packet.lg_size := lg_s.U
packet.mask := VecInit(mask.grouped(beatBytes).map(v => VecInit(v)).toSeq)
packet.vaddr := vaddr_aligned_to_size
packet.is_full := mask.take(s).reduce(_ && _)
packet.bytes_written := bytes_written
packet.bytes_written_per_beat.zipWithIndex.foreach { case (b, i) =>
val start_of_beat = i * beatBytes
val end_of_beat = (i+1) * beatBytes
val left_shift = Mux(vaddr_offset >= start_of_beat.U && vaddr_offset < end_of_beat.U,
vaddr_offset - start_of_beat.U,
0.U)
val right_shift = Mux(vaddr_offset +& bytesLeft >= start_of_beat.U && vaddr_offset +& bytesLeft < end_of_beat.U,
end_of_beat.U - (vaddr_offset +& bytesLeft),
0.U)
val too_early = vaddr_offset >= end_of_beat.U
val too_late = vaddr_offset +& bytesLeft <= start_of_beat.U
b := Mux(too_early || too_late, 0.U, beatBytes.U - (left_shift +& right_shift))
}
packet
}
val best_write_packet = write_packets.reduce { (acc, p) =>
Mux(p.bytes_written > acc.bytes_written, p, acc)
}
val write_packet = RegEnableThru(best_write_packet, state === s_writing_new_block)
val write_size = write_packet.size
val lg_write_size = write_packet.lg_size
val write_beats = write_packet.total_beats()
val write_vaddr = write_packet.vaddr
val write_full = write_packet.is_full
val beatsLeft = Reg(UInt(log2Up(maxBytes/aligned_to).W))
val beatsSent = Mux(state === s_writing_new_block, 0.U, write_beats - beatsLeft)
val write_mask = write_packet.mask(beatsSent)
val write_shift = PriorityEncoder(write_mask)
val bytes_written_this_beat = write_packet.bytes_written_per_beat(beatsSent)
// Firing off TileLink write requests
val putFull = edge.Put(
fromSource = RegEnableThru(xactId, state === s_writing_new_block),
toAddress = 0.U,
lgSize = lg_write_size,
data = (data >> (bytesSent * 8.U)).asUInt
)._2
val putPartial = edge.Put(
fromSource = RegEnableThru(xactId, state === s_writing_new_block),
toAddress = 0.U,
lgSize = lg_write_size,
data = ((data >> (bytesSent * 8.U)) << (write_shift * 8.U)).asUInt,
mask = write_mask.asUInt
)._2
class TLBundleAWithInfo extends Bundle {
val tl_a = tl.a.bits.cloneType
val vaddr = Output(UInt(vaddrBits.W))
val status = Output(new MStatus)
}
val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo))
xactBusy_fire := untranslated_a.fire && state === s_writing_new_block
untranslated_a.valid := (state === s_writing_new_block || state === s_writing_beats) && !xactBusy.andR
untranslated_a.bits.tl_a := Mux(write_full, putFull, putPartial)
untranslated_a.bits.vaddr := write_vaddr
untranslated_a.bits.status := req.status
// 0 goes to retries, 1 goes to state machine
val retry_a = Wire(Decoupled(new TLBundleAWithInfo))
val shadow_retry_a = Module(new Queue(new TLBundleAWithInfo, 1))
shadow_retry_a.io.enq.valid := false.B
shadow_retry_a.io.enq.bits := DontCare
val tlb_arb = Module(new Arbiter(new TLBundleAWithInfo, 3))
tlb_arb.io.in(0) <> retry_a
tlb_arb.io.in(1) <> shadow_retry_a.io.deq
tlb_arb.io.in(2) <> untranslated_a
val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true))
tlb_q.io.enq <> tlb_arb.io.out
io.tlb.req.valid := tlb_q.io.deq.fire
io.tlb.req.bits := DontCare
io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
io.tlb.req.bits.tlb_req.passthrough := false.B
io.tlb.req.bits.tlb_req.size := 0.U // send_size
io.tlb.req.bits.tlb_req.cmd := M_XWR
io.tlb.req.bits.status := tlb_q.io.deq.bits.status
val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true))
translate_q.io.enq <> tlb_q.io.deq
when (retry_a.valid) {
translate_q.io.enq.valid := false.B
shadow_retry_a.io.enq.valid := tlb_q.io.deq.valid
shadow_retry_a.io.enq.bits := tlb_q.io.deq.bits
}
translate_q.io.deq.ready := tl.a.ready || io.tlb.resp.miss
retry_a.valid := translate_q.io.deq.valid && io.tlb.resp.miss
retry_a.bits := translate_q.io.deq.bits
assert(!(retry_a.valid && !retry_a.ready))
tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.miss
tl.a.bits := translate_q.io.deq.bits.tl_a
tl.a.bits.address := RegEnableThru(io.tlb.resp.paddr, RegNext(io.tlb.req.fire))
tl.d.ready := xactBusy.orR
when (untranslated_a.fire) {
when (state === s_writing_new_block) {
beatsLeft := write_beats - 1.U
val next_vaddr = req.vaddr + write_packet.bytes_written
req.vaddr := next_vaddr
bytesSent := bytesSent + bytes_written_this_beat
when (write_beats === 1.U) {
when (bytes_written_this_beat >= bytesLeft) {
// We're done with this request at this point
state_machine_ready_for_req := true.B
state := s_idle
}
}.otherwise {
state := s_writing_beats
}
}.elsewhen(state === s_writing_beats) {
beatsLeft := beatsLeft - 1.U
bytesSent := bytesSent + bytes_written_this_beat
assert(beatsLeft > 0.U)
when (beatsLeft === 1.U) {
when (bytes_written_this_beat >= bytesLeft) {
// We're done with this request at this point
state_machine_ready_for_req := true.B
state := s_idle
}.otherwise {
state := s_writing_new_block
}
}
}
}
// Accepting requests to kick-start the state machine
when (io.req.fire) {
val pooled = {
val cols = dataWidth / inputType.getWidth
val v1 = io.req.bits.data.asTypeOf(Vec(cols, inputType))
val v2 = data_single_block.asTypeOf(Vec(cols, inputType))
val m = v1.zip(v2)
VecInit(m.zipWithIndex.map{case ((x, y), i) => if (i < block_cols) maxOf(x, y) else y}).asUInt
}
req := io.req.bits
req.len := io.req.bits.block * inputTypeRowBytes.U + io.req.bits.len
data_single_block := Mux(io.req.bits.pool_en, pooled, io.req.bits.data)
data_blocks(io.req.bits.block) := io.req.bits.data
bytesSent := 0.U
state := Mux(io.req.bits.store_en, s_writing_new_block, s_idle)
assert(io.req.bits.len <= (block_cols * inputType.getWidth / 8).U || io.req.bits.block === 0.U, "DMA can't write multiple blocks to main memory when writing full accumulator output")
assert(!io.req.bits.pool_en || io.req.bits.block === 0.U, "Can't pool with block-mvout")
}
// Performance counter
CounterEventIO.init(io.counter)
io.counter.connectEventSignal(CounterEvent.WDMA_ACTIVE_CYCLE, state =/= s_idle)
io.counter.connectEventSignal(CounterEvent.WDMA_TLB_WAIT_CYCLES, io.tlb.resp.miss)
io.counter.connectEventSignal(CounterEvent.WDMA_TL_WAIT_CYCLES, tl.a.valid && !tl.a.ready)
// External counters
val total_bytes_sent = RegInit(0.U(CounterExternal.EXTERNAL_WIDTH.W))
when (tl.d.fire) {
total_bytes_sent := total_bytes_sent + (1.U << tl.d.bits.size)
}
val total_latency = RegInit(0.U(CounterExternal.EXTERNAL_WIDTH.W))
total_latency := total_latency + PopCount(xactBusy)
when (io.counter.external_reset) {
total_bytes_sent := 0.U
total_latency := 0.U
}
io.counter.connectExternalCounter(CounterExternal.WDMA_BYTES_SENT, total_bytes_sent)
io.counter.connectExternalCounter(CounterExternal.WDMA_TOTAL_LATENCY, total_latency)
if (use_firesim_simulation_counters) {
PerfCounter(state =/= s_idle, "wdma_active_cycles", "cycles during which write read dma is active")
PerfCounter(tl.a.ready && translate_q.io.deq.valid && io.tlb.resp.miss, "wdma_tlb_wait_cycles", "cycles during which the write dma is stalling as it waits for a TLB response")
PerfCounter(tl.a.valid && !tl.a.ready, "wdma_tl_wait_cycles", "cycles during which the write dma is stalling as it waits for the TileLink port to be available")
val cntr = Counter(500000)
when(cntr.inc()) {
printf(SynthesizePrintf("WDMA bytes sent: %d\n", total_bytes_sent))
printf(SynthesizePrintf("WDMA total latency: %d\n", total_latency))
}
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module StreamReaderCore( // @[DMA.scala:138:9]
input clock, // @[DMA.scala:138:9]
input reset, // @[DMA.scala:138:9]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_req_ready, // @[DMA.scala:147:16]
input io_req_valid, // @[DMA.scala:147:16]
input [39:0] io_req_bits_vaddr, // @[DMA.scala:147:16]
input [13:0] io_req_bits_spaddr, // @[DMA.scala:147:16]
input io_req_bits_is_acc, // @[DMA.scala:147:16]
input io_req_bits_accumulate, // @[DMA.scala:147:16]
input io_req_bits_has_acc_bitwidth, // @[DMA.scala:147:16]
input [31:0] io_req_bits_scale, // @[DMA.scala:147:16]
input io_req_bits_status_debug, // @[DMA.scala:147:16]
input io_req_bits_status_cease, // @[DMA.scala:147:16]
input io_req_bits_status_wfi, // @[DMA.scala:147:16]
input [31:0] io_req_bits_status_isa, // @[DMA.scala:147:16]
input [1:0] io_req_bits_status_dprv, // @[DMA.scala:147:16]
input io_req_bits_status_dv, // @[DMA.scala:147:16]
input [1:0] io_req_bits_status_prv, // @[DMA.scala:147:16]
input io_req_bits_status_v, // @[DMA.scala:147:16]
input io_req_bits_status_sd, // @[DMA.scala:147:16]
input [22:0] io_req_bits_status_zero2, // @[DMA.scala:147:16]
input io_req_bits_status_mpv, // @[DMA.scala:147:16]
input io_req_bits_status_gva, // @[DMA.scala:147:16]
input io_req_bits_status_mbe, // @[DMA.scala:147:16]
input io_req_bits_status_sbe, // @[DMA.scala:147:16]
input [1:0] io_req_bits_status_sxl, // @[DMA.scala:147:16]
input [1:0] io_req_bits_status_uxl, // @[DMA.scala:147:16]
input io_req_bits_status_sd_rv32, // @[DMA.scala:147:16]
input [7:0] io_req_bits_status_zero1, // @[DMA.scala:147:16]
input io_req_bits_status_tsr, // @[DMA.scala:147:16]
input io_req_bits_status_tw, // @[DMA.scala:147:16]
input io_req_bits_status_tvm, // @[DMA.scala:147:16]
input io_req_bits_status_mxr, // @[DMA.scala:147:16]
input io_req_bits_status_sum, // @[DMA.scala:147:16]
input io_req_bits_status_mprv, // @[DMA.scala:147:16]
input [1:0] io_req_bits_status_xs, // @[DMA.scala:147:16]
input [1:0] io_req_bits_status_fs, // @[DMA.scala:147:16]
input [1:0] io_req_bits_status_mpp, // @[DMA.scala:147:16]
input [1:0] io_req_bits_status_vs, // @[DMA.scala:147:16]
input io_req_bits_status_spp, // @[DMA.scala:147:16]
input io_req_bits_status_mpie, // @[DMA.scala:147:16]
input io_req_bits_status_ube, // @[DMA.scala:147:16]
input io_req_bits_status_spie, // @[DMA.scala:147:16]
input io_req_bits_status_upie, // @[DMA.scala:147:16]
input io_req_bits_status_mie, // @[DMA.scala:147:16]
input io_req_bits_status_hie, // @[DMA.scala:147:16]
input io_req_bits_status_sie, // @[DMA.scala:147:16]
input io_req_bits_status_uie, // @[DMA.scala:147:16]
input [15:0] io_req_bits_len, // @[DMA.scala:147:16]
input [15:0] io_req_bits_repeats, // @[DMA.scala:147:16]
input [7:0] io_req_bits_pixel_repeats, // @[DMA.scala:147:16]
input [15:0] io_req_bits_block_stride, // @[DMA.scala:147:16]
input [7:0] io_req_bits_cmd_id, // @[DMA.scala:147:16]
output io_reserve_valid, // @[DMA.scala:147:16]
input io_reserve_ready, // @[DMA.scala:147:16]
input [3:0] io_reserve_xactid, // @[DMA.scala:147:16]
output [5:0] io_reserve_entry_shift, // @[DMA.scala:147:16]
output [13:0] io_reserve_entry_addr, // @[DMA.scala:147:16]
output io_reserve_entry_is_acc, // @[DMA.scala:147:16]
output io_reserve_entry_accumulate, // @[DMA.scala:147:16]
output io_reserve_entry_has_acc_bitwidth, // @[DMA.scala:147:16]
output [31:0] io_reserve_entry_scale, // @[DMA.scala:147:16]
output [15:0] io_reserve_entry_repeats, // @[DMA.scala:147:16]
output [7:0] io_reserve_entry_pixel_repeats, // @[DMA.scala:147:16]
output [15:0] io_reserve_entry_len, // @[DMA.scala:147:16]
output [15:0] io_reserve_entry_block_stride, // @[DMA.scala:147:16]
output [6:0] io_reserve_entry_spad_row_offset, // @[DMA.scala:147:16]
output [6:0] io_reserve_entry_bytes_to_read, // @[DMA.scala:147:16]
output [2:0] io_reserve_entry_cmd_id, // @[DMA.scala:147:16]
input io_beatData_ready, // @[DMA.scala:147:16]
output io_beatData_valid, // @[DMA.scala:147:16]
output [3:0] io_beatData_bits_xactid, // @[DMA.scala:147:16]
output [127:0] io_beatData_bits_data, // @[DMA.scala:147:16]
output [2:0] io_beatData_bits_lg_len_req, // @[DMA.scala:147:16]
output io_beatData_bits_last, // @[DMA.scala:147:16]
output io_tlb_req_valid, // @[DMA.scala:147:16]
output [39:0] io_tlb_req_bits_tlb_req_vaddr, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_debug, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_cease, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_wfi, // @[DMA.scala:147:16]
output [31:0] io_tlb_req_bits_status_isa, // @[DMA.scala:147:16]
output [1:0] io_tlb_req_bits_status_dprv, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_dv, // @[DMA.scala:147:16]
output [1:0] io_tlb_req_bits_status_prv, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_v, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_sd, // @[DMA.scala:147:16]
output [22:0] io_tlb_req_bits_status_zero2, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_mpv, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_gva, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_mbe, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_sbe, // @[DMA.scala:147:16]
output [1:0] io_tlb_req_bits_status_sxl, // @[DMA.scala:147:16]
output [1:0] io_tlb_req_bits_status_uxl, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_sd_rv32, // @[DMA.scala:147:16]
output [7:0] io_tlb_req_bits_status_zero1, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_tsr, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_tw, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_tvm, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_mxr, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_sum, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_mprv, // @[DMA.scala:147:16]
output [1:0] io_tlb_req_bits_status_xs, // @[DMA.scala:147:16]
output [1:0] io_tlb_req_bits_status_fs, // @[DMA.scala:147:16]
output [1:0] io_tlb_req_bits_status_mpp, // @[DMA.scala:147:16]
output [1:0] io_tlb_req_bits_status_vs, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_spp, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_mpie, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_ube, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_spie, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_upie, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_mie, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_hie, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_sie, // @[DMA.scala:147:16]
output io_tlb_req_bits_status_uie, // @[DMA.scala:147:16]
input io_tlb_resp_miss, // @[DMA.scala:147:16]
input [31:0] io_tlb_resp_paddr, // @[DMA.scala:147:16]
input [39:0] io_tlb_resp_gpa, // @[DMA.scala:147:16]
input io_tlb_resp_pf_ld, // @[DMA.scala:147:16]
input io_tlb_resp_pf_st, // @[DMA.scala:147:16]
input io_tlb_resp_pf_inst, // @[DMA.scala:147:16]
input io_tlb_resp_ae_ld, // @[DMA.scala:147:16]
input io_tlb_resp_ae_st, // @[DMA.scala:147:16]
input io_tlb_resp_ae_inst, // @[DMA.scala:147:16]
input io_tlb_resp_cacheable, // @[DMA.scala:147:16]
input io_tlb_resp_must_alloc, // @[DMA.scala:147:16]
input io_tlb_resp_prefetchable, // @[DMA.scala:147:16]
input [4:0] io_tlb_resp_cmd, // @[DMA.scala:147:16]
input io_flush, // @[DMA.scala:147:16]
output io_counter_event_signal_18, // @[DMA.scala:147:16]
output io_counter_event_signal_19, // @[DMA.scala:147:16]
output io_counter_event_signal_20, // @[DMA.scala:147:16]
output [31:0] io_counter_external_values_4, // @[DMA.scala:147:16]
input io_counter_external_reset // @[DMA.scala:147:16]
);
wire [15:0] get_mask; // @[Edges.scala:460:17]
wire [3:0] get_size; // @[Edges.scala:460:17]
wire _translate_q_io_deq_valid; // @[DMA.scala:241:29]
wire [2:0] _translate_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:241:29]
wire [2:0] _translate_q_io_deq_bits_tl_a_param; // @[DMA.scala:241:29]
wire [3:0] _translate_q_io_deq_bits_tl_a_size; // @[DMA.scala:241:29]
wire [3:0] _translate_q_io_deq_bits_tl_a_source; // @[DMA.scala:241:29]
wire [15:0] _translate_q_io_deq_bits_tl_a_mask; // @[DMA.scala:241:29]
wire [127:0] _translate_q_io_deq_bits_tl_a_data; // @[DMA.scala:241:29]
wire _translate_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:241:29]
wire _tlb_q_io_deq_valid; // @[DMA.scala:230:23]
wire [2:0] _tlb_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:230:23]
wire [2:0] _tlb_q_io_deq_bits_tl_a_param; // @[DMA.scala:230:23]
wire [3:0] _tlb_q_io_deq_bits_tl_a_size; // @[DMA.scala:230:23]
wire [3:0] _tlb_q_io_deq_bits_tl_a_source; // @[DMA.scala:230:23]
wire [31:0] _tlb_q_io_deq_bits_tl_a_address; // @[DMA.scala:230:23]
wire [15:0] _tlb_q_io_deq_bits_tl_a_mask; // @[DMA.scala:230:23]
wire [127:0] _tlb_q_io_deq_bits_tl_a_data; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:230:23]
wire [38:0] _tlb_q_io_deq_bits_vaddr; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_debug; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_cease; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_wfi; // @[DMA.scala:230:23]
wire [31:0] _tlb_q_io_deq_bits_status_isa; // @[DMA.scala:230:23]
wire [1:0] _tlb_q_io_deq_bits_status_dprv; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_dv; // @[DMA.scala:230:23]
wire [1:0] _tlb_q_io_deq_bits_status_prv; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_v; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_sd; // @[DMA.scala:230:23]
wire [22:0] _tlb_q_io_deq_bits_status_zero2; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_mpv; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_gva; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_mbe; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_sbe; // @[DMA.scala:230:23]
wire [1:0] _tlb_q_io_deq_bits_status_sxl; // @[DMA.scala:230:23]
wire [1:0] _tlb_q_io_deq_bits_status_uxl; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_sd_rv32; // @[DMA.scala:230:23]
wire [7:0] _tlb_q_io_deq_bits_status_zero1; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_tsr; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_tw; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_tvm; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_mxr; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_sum; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_mprv; // @[DMA.scala:230:23]
wire [1:0] _tlb_q_io_deq_bits_status_xs; // @[DMA.scala:230:23]
wire [1:0] _tlb_q_io_deq_bits_status_fs; // @[DMA.scala:230:23]
wire [1:0] _tlb_q_io_deq_bits_status_mpp; // @[DMA.scala:230:23]
wire [1:0] _tlb_q_io_deq_bits_status_vs; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_spp; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_mpie; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_ube; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_spie; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_upie; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_mie; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_hie; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_sie; // @[DMA.scala:230:23]
wire _tlb_q_io_deq_bits_status_uie; // @[DMA.scala:230:23]
wire _tlb_arb_io_out_valid; // @[DMA.scala:226:25]
wire [2:0] _tlb_arb_io_out_bits_tl_a_opcode; // @[DMA.scala:226:25]
wire [2:0] _tlb_arb_io_out_bits_tl_a_param; // @[DMA.scala:226:25]
wire [3:0] _tlb_arb_io_out_bits_tl_a_size; // @[DMA.scala:226:25]
wire [3:0] _tlb_arb_io_out_bits_tl_a_source; // @[DMA.scala:226:25]
wire [31:0] _tlb_arb_io_out_bits_tl_a_address; // @[DMA.scala:226:25]
wire [15:0] _tlb_arb_io_out_bits_tl_a_mask; // @[DMA.scala:226:25]
wire [127:0] _tlb_arb_io_out_bits_tl_a_data; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_tl_a_corrupt; // @[DMA.scala:226:25]
wire [38:0] _tlb_arb_io_out_bits_vaddr; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_debug; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_cease; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_wfi; // @[DMA.scala:226:25]
wire [31:0] _tlb_arb_io_out_bits_status_isa; // @[DMA.scala:226:25]
wire [1:0] _tlb_arb_io_out_bits_status_dprv; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_dv; // @[DMA.scala:226:25]
wire [1:0] _tlb_arb_io_out_bits_status_prv; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_v; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_sd; // @[DMA.scala:226:25]
wire [22:0] _tlb_arb_io_out_bits_status_zero2; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_mpv; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_gva; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_mbe; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_sbe; // @[DMA.scala:226:25]
wire [1:0] _tlb_arb_io_out_bits_status_sxl; // @[DMA.scala:226:25]
wire [1:0] _tlb_arb_io_out_bits_status_uxl; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_sd_rv32; // @[DMA.scala:226:25]
wire [7:0] _tlb_arb_io_out_bits_status_zero1; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_tsr; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_tw; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_tvm; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_mxr; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_sum; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_mprv; // @[DMA.scala:226:25]
wire [1:0] _tlb_arb_io_out_bits_status_xs; // @[DMA.scala:226:25]
wire [1:0] _tlb_arb_io_out_bits_status_fs; // @[DMA.scala:226:25]
wire [1:0] _tlb_arb_io_out_bits_status_mpp; // @[DMA.scala:226:25]
wire [1:0] _tlb_arb_io_out_bits_status_vs; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_spp; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_mpie; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_ube; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_spie; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_upie; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_mie; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_hie; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_sie; // @[DMA.scala:226:25]
wire _tlb_arb_io_out_bits_status_uie; // @[DMA.scala:226:25]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[DMA.scala:138:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[DMA.scala:138:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DMA.scala:138:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DMA.scala:138:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DMA.scala:138:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DMA.scala:138:9]
wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DMA.scala:138:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DMA.scala:138:9]
wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DMA.scala:138:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DMA.scala:138:9]
wire io_req_valid_0 = io_req_valid; // @[DMA.scala:138:9]
wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[DMA.scala:138:9]
wire [13:0] io_req_bits_spaddr_0 = io_req_bits_spaddr; // @[DMA.scala:138:9]
wire io_req_bits_is_acc_0 = io_req_bits_is_acc; // @[DMA.scala:138:9]
wire io_req_bits_accumulate_0 = io_req_bits_accumulate; // @[DMA.scala:138:9]
wire io_req_bits_has_acc_bitwidth_0 = io_req_bits_has_acc_bitwidth; // @[DMA.scala:138:9]
wire [31:0] io_req_bits_scale_0 = io_req_bits_scale; // @[DMA.scala:138:9]
wire io_req_bits_status_debug_0 = io_req_bits_status_debug; // @[DMA.scala:138:9]
wire io_req_bits_status_cease_0 = io_req_bits_status_cease; // @[DMA.scala:138:9]
wire io_req_bits_status_wfi_0 = io_req_bits_status_wfi; // @[DMA.scala:138:9]
wire [31:0] io_req_bits_status_isa_0 = io_req_bits_status_isa; // @[DMA.scala:138:9]
wire [1:0] io_req_bits_status_dprv_0 = io_req_bits_status_dprv; // @[DMA.scala:138:9]
wire io_req_bits_status_dv_0 = io_req_bits_status_dv; // @[DMA.scala:138:9]
wire [1:0] io_req_bits_status_prv_0 = io_req_bits_status_prv; // @[DMA.scala:138:9]
wire io_req_bits_status_v_0 = io_req_bits_status_v; // @[DMA.scala:138:9]
wire io_req_bits_status_sd_0 = io_req_bits_status_sd; // @[DMA.scala:138:9]
wire [22:0] io_req_bits_status_zero2_0 = io_req_bits_status_zero2; // @[DMA.scala:138:9]
wire io_req_bits_status_mpv_0 = io_req_bits_status_mpv; // @[DMA.scala:138:9]
wire io_req_bits_status_gva_0 = io_req_bits_status_gva; // @[DMA.scala:138:9]
wire io_req_bits_status_mbe_0 = io_req_bits_status_mbe; // @[DMA.scala:138:9]
wire io_req_bits_status_sbe_0 = io_req_bits_status_sbe; // @[DMA.scala:138:9]
wire [1:0] io_req_bits_status_sxl_0 = io_req_bits_status_sxl; // @[DMA.scala:138:9]
wire [1:0] io_req_bits_status_uxl_0 = io_req_bits_status_uxl; // @[DMA.scala:138:9]
wire io_req_bits_status_sd_rv32_0 = io_req_bits_status_sd_rv32; // @[DMA.scala:138:9]
wire [7:0] io_req_bits_status_zero1_0 = io_req_bits_status_zero1; // @[DMA.scala:138:9]
wire io_req_bits_status_tsr_0 = io_req_bits_status_tsr; // @[DMA.scala:138:9]
wire io_req_bits_status_tw_0 = io_req_bits_status_tw; // @[DMA.scala:138:9]
wire io_req_bits_status_tvm_0 = io_req_bits_status_tvm; // @[DMA.scala:138:9]
wire io_req_bits_status_mxr_0 = io_req_bits_status_mxr; // @[DMA.scala:138:9]
wire io_req_bits_status_sum_0 = io_req_bits_status_sum; // @[DMA.scala:138:9]
wire io_req_bits_status_mprv_0 = io_req_bits_status_mprv; // @[DMA.scala:138:9]
wire [1:0] io_req_bits_status_xs_0 = io_req_bits_status_xs; // @[DMA.scala:138:9]
wire [1:0] io_req_bits_status_fs_0 = io_req_bits_status_fs; // @[DMA.scala:138:9]
wire [1:0] io_req_bits_status_mpp_0 = io_req_bits_status_mpp; // @[DMA.scala:138:9]
wire [1:0] io_req_bits_status_vs_0 = io_req_bits_status_vs; // @[DMA.scala:138:9]
wire io_req_bits_status_spp_0 = io_req_bits_status_spp; // @[DMA.scala:138:9]
wire io_req_bits_status_mpie_0 = io_req_bits_status_mpie; // @[DMA.scala:138:9]
wire io_req_bits_status_ube_0 = io_req_bits_status_ube; // @[DMA.scala:138:9]
wire io_req_bits_status_spie_0 = io_req_bits_status_spie; // @[DMA.scala:138:9]
wire io_req_bits_status_upie_0 = io_req_bits_status_upie; // @[DMA.scala:138:9]
wire io_req_bits_status_mie_0 = io_req_bits_status_mie; // @[DMA.scala:138:9]
wire io_req_bits_status_hie_0 = io_req_bits_status_hie; // @[DMA.scala:138:9]
wire io_req_bits_status_sie_0 = io_req_bits_status_sie; // @[DMA.scala:138:9]
wire io_req_bits_status_uie_0 = io_req_bits_status_uie; // @[DMA.scala:138:9]
wire [15:0] io_req_bits_len_0 = io_req_bits_len; // @[DMA.scala:138:9]
wire [15:0] io_req_bits_repeats_0 = io_req_bits_repeats; // @[DMA.scala:138:9]
wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[DMA.scala:138:9]
wire [15:0] io_req_bits_block_stride_0 = io_req_bits_block_stride; // @[DMA.scala:138:9]
wire [7:0] io_req_bits_cmd_id_0 = io_req_bits_cmd_id; // @[DMA.scala:138:9]
wire io_reserve_ready_0 = io_reserve_ready; // @[DMA.scala:138:9]
wire [3:0] io_reserve_xactid_0 = io_reserve_xactid; // @[DMA.scala:138:9]
wire io_beatData_ready_0 = io_beatData_ready; // @[DMA.scala:138:9]
wire io_tlb_resp_miss_0 = io_tlb_resp_miss; // @[DMA.scala:138:9]
wire [31:0] io_tlb_resp_paddr_0 = io_tlb_resp_paddr; // @[DMA.scala:138:9]
wire [39:0] io_tlb_resp_gpa_0 = io_tlb_resp_gpa; // @[DMA.scala:138:9]
wire io_tlb_resp_pf_ld_0 = io_tlb_resp_pf_ld; // @[DMA.scala:138:9]
wire io_tlb_resp_pf_st_0 = io_tlb_resp_pf_st; // @[DMA.scala:138:9]
wire io_tlb_resp_pf_inst_0 = io_tlb_resp_pf_inst; // @[DMA.scala:138:9]
wire io_tlb_resp_ae_ld_0 = io_tlb_resp_ae_ld; // @[DMA.scala:138:9]
wire io_tlb_resp_ae_st_0 = io_tlb_resp_ae_st; // @[DMA.scala:138:9]
wire io_tlb_resp_ae_inst_0 = io_tlb_resp_ae_inst; // @[DMA.scala:138:9]
wire io_tlb_resp_cacheable_0 = io_tlb_resp_cacheable; // @[DMA.scala:138:9]
wire io_tlb_resp_must_alloc_0 = io_tlb_resp_must_alloc; // @[DMA.scala:138:9]
wire io_tlb_resp_prefetchable_0 = io_tlb_resp_prefetchable; // @[DMA.scala:138:9]
wire [4:0] io_tlb_resp_cmd_0 = io_tlb_resp_cmd; // @[DMA.scala:138:9]
wire io_flush_0 = io_flush; // @[DMA.scala:138:9]
wire io_counter_external_reset_0 = io_counter_external_reset; // @[DMA.scala:138:9]
wire [13:0] _get_legal_T_4 = 14'h3000; // @[Parameters.scala:137:31]
wire [16:0] _get_legal_T_19 = 17'h10000; // @[Parameters.scala:137:31]
wire [16:0] _get_legal_T_24 = 17'h10000; // @[Parameters.scala:137:31]
wire [25:0] _get_legal_T_29 = 26'h2000000; // @[Parameters.scala:137:31]
wire [27:0] _get_legal_T_34 = 28'h8000000; // @[Parameters.scala:137:31]
wire [27:0] _get_legal_T_39 = 28'h8000000; // @[Parameters.scala:137:31]
wire [28:0] _get_legal_T_44 = 29'h10000000; // @[Parameters.scala:137:31]
wire [31:0] _get_legal_T_49 = 32'h80000000; // @[Parameters.scala:137:31]
wire [6:0] read_packets_0_size = 7'h10; // @[DMA.scala:188:24]
wire [6:0] read_packets_1_size = 7'h20; // @[DMA.scala:188:24, :191:38]
wire [2:0] read_packets_1_lg_size = 3'h5; // @[DMA.scala:188:24]
wire [6:0] read_packets_2_size = 7'h40; // @[DMA.scala:188:24]
wire [2:0] read_packets_2_lg_size = 3'h6; // @[DMA.scala:188:24]
wire [14:0] _get_legal_T_5 = 15'h3000; // @[Parameters.scala:137:41]
wire [32:0] _get_legal_T_6 = 33'h3000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_7 = 33'h3000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_16 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_17 = 33'h0; // @[Parameters.scala:137:46]
wire [17:0] _get_legal_T_20 = 18'h10000; // @[Parameters.scala:137:41]
wire [17:0] _get_legal_T_25 = 18'h10000; // @[Parameters.scala:137:41]
wire [32:0] _get_legal_T_21 = 33'h10000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_22 = 33'h10000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_26 = 33'h10000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_27 = 33'h10000; // @[Parameters.scala:137:46]
wire [26:0] _get_legal_T_30 = 27'h2000000; // @[Parameters.scala:137:41]
wire [32:0] _get_legal_T_31 = 33'h2000000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_32 = 33'h2000000; // @[Parameters.scala:137:46]
wire [28:0] _get_legal_T_35 = 29'h8000000; // @[Parameters.scala:137:41]
wire [28:0] _get_legal_T_40 = 29'h8000000; // @[Parameters.scala:137:41]
wire [32:0] _get_legal_T_36 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_37 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_41 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_42 = 33'h8000000; // @[Parameters.scala:137:46]
wire [29:0] _get_legal_T_45 = 30'h10000000; // @[Parameters.scala:137:41]
wire [32:0] _get_legal_T_46 = 33'h10000000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_47 = 33'h10000000; // @[Parameters.scala:137:46]
wire [32:0] _get_legal_T_50 = 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _get_legal_T_51 = 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _get_legal_T_52 = 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [2:0] read_packets_0_lg_size = 3'h4; // @[DMA.scala:188:24]
wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] untranslated_a_bits_tl_a_opcode = 3'h4; // @[DMA.scala:218:30]
wire [127:0] get_data = 128'h0; // @[Edges.scala:460:17]
wire [127:0] untranslated_a_bits_tl_a_data = 128'h0; // @[DMA.scala:218:30]
wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_18 = 1'h1; // @[Parameters.scala:137:59]
wire _get_legal_T_54 = 1'h1; // @[Parameters.scala:685:42]
wire _get_legal_T_55 = 1'h1; // @[Parameters.scala:685:42]
wire _get_legal_T_56 = 1'h1; // @[Parameters.scala:685:42]
wire _get_legal_T_57 = 1'h1; // @[Parameters.scala:685:42]
wire _get_legal_T_58 = 1'h1; // @[Parameters.scala:685:42]
wire _get_legal_T_59 = 1'h1; // @[Parameters.scala:685:42]
wire _get_legal_T_60 = 1'h1; // @[Parameters.scala:685:42]
wire get_a_mask_sub_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20]
wire get_a_mask_sub_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27]
wire get_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20]
wire get_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27]
wire get_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20]
wire get_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27]
wire get_a_mask_nbit = 1'h1; // @[Misc.scala:211:20]
wire get_a_mask_eq = 1'h1; // @[Misc.scala:214:27]
wire retry_a_ready = 1'h1; // @[DMA.scala:225:23]
wire [31:0] io_counter_external_values_0 = 32'h0; // @[DMA.scala:138:9]
wire [31:0] io_counter_external_values_1 = 32'h0; // @[DMA.scala:138:9]
wire [31:0] io_counter_external_values_2 = 32'h0; // @[DMA.scala:138:9]
wire [31:0] io_counter_external_values_3 = 32'h0; // @[DMA.scala:138:9]
wire [31:0] io_counter_external_values_5 = 32'h0; // @[DMA.scala:138:9]
wire [31:0] io_counter_external_values_6 = 32'h0; // @[DMA.scala:138:9]
wire [31:0] io_counter_external_values_7 = 32'h0; // @[DMA.scala:138:9]
wire [31:0] get_address = 32'h0; // @[Edges.scala:460:17]
wire [31:0] untranslated_a_bits_tl_a_address = 32'h0; // @[DMA.scala:218:30]
wire [4:0] io_tlb_req_bits_tlb_req_cmd = 5'h0; // @[DMA.scala:138:9]
wire [2:0] io_reserve_entry_lg_len_req = 3'h0; // @[DMA.scala:138:9]
wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] untranslated_a_bits_tl_a_param = 3'h0; // @[DMA.scala:218:30]
wire [1:0] io_tlb_req_bits_tlb_req_size = 2'h0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_tlb_req_prv = 2'h0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_resp_size = 2'h0; // @[DMA.scala:138:9]
wire [1:0] _get_legal_T_15 = 2'h0; // @[Parameters.scala:137:41]
wire io_tlb_req_bits_tlb_req_passthrough = 1'h0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_tlb_req_v = 1'h0; // @[DMA.scala:138:9]
wire io_tlb_resp_gpa_is_pte = 1'h0; // @[DMA.scala:138:9]
wire io_tlb_resp_gf_ld = 1'h0; // @[DMA.scala:138:9]
wire io_tlb_resp_gf_st = 1'h0; // @[DMA.scala:138:9]
wire io_tlb_resp_gf_inst = 1'h0; // @[DMA.scala:138:9]
wire io_tlb_resp_ma_ld = 1'h0; // @[DMA.scala:138:9]
wire io_tlb_resp_ma_st = 1'h0; // @[DMA.scala:138:9]
wire io_tlb_resp_ma_inst = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_0 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_1 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_2 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_3 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_4 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_5 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_6 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_7 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_8 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_9 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_10 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_11 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_12 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_13 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_14 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_15 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_16 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_17 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_21 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_22 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_23 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_24 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_25 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_26 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_27 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_28 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_29 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_30 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_31 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_32 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_33 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_34 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_35 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_36 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_37 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_38 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_39 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_40 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_41 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_42 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_43 = 1'h0; // @[DMA.scala:138:9]
wire io_counter_event_signal_44 = 1'h0; // @[DMA.scala:138:9]
wire _get_legal_T_8 = 1'h0; // @[Parameters.scala:137:59]
wire _get_legal_T_9 = 1'h0; // @[Parameters.scala:684:54]
wire _get_legal_T_14 = 1'h0; // @[Parameters.scala:137:31]
wire _get_legal_T_23 = 1'h0; // @[Parameters.scala:137:59]
wire _get_legal_T_28 = 1'h0; // @[Parameters.scala:137:59]
wire _get_legal_T_33 = 1'h0; // @[Parameters.scala:137:59]
wire _get_legal_T_38 = 1'h0; // @[Parameters.scala:137:59]
wire _get_legal_T_43 = 1'h0; // @[Parameters.scala:137:59]
wire _get_legal_T_48 = 1'h0; // @[Parameters.scala:137:59]
wire _get_legal_T_53 = 1'h0; // @[Parameters.scala:137:59]
wire _get_legal_T_62 = 1'h0; // @[Parameters.scala:686:26]
wire get_corrupt = 1'h0; // @[Edges.scala:460:17]
wire get_a_mask_sub_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_sub_2_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_sub_3_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_4_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_5_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_6_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_sub_7_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_8 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_8 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire get_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27]
wire _get_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire untranslated_a_bits_tl_a_corrupt = 1'h0; // @[DMA.scala:218:30]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[DMA.scala:138:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[DMA.scala:138:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DMA.scala:138:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DMA.scala:138:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DMA.scala:138:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DMA.scala:138:9]
wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DMA.scala:138:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DMA.scala:138:9]
wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DMA.scala:138:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DMA.scala:138:9]
wire state_machine_ready_for_req; // @[DMA.scala:165:47]
wire _io_reserve_valid_T_1; // @[DMA.scala:253:51]
wire [5:0] read_packet_shift; // @[DMA.scala:198:10]
wire [3:0] get_source = io_reserve_xactid_0; // @[Edges.scala:460:17]
wire [6:0] read_packet_bytes_read; // @[DMA.scala:198:10]
assign nodeOut_d_ready = io_beatData_ready_0; // @[DMA.scala:138:9]
wire io_beatData_bits_last_last; // @[Edges.scala:232:33]
wire io_counter_event_signal_19_0 = io_tlb_resp_miss_0; // @[DMA.scala:138:9]
assign nodeOut_a_bits_address = io_tlb_resp_paddr_0; // @[DMA.scala:138:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[DMA.scala:138:9]
wire [2:0] auto_out_a_bits_param_0; // @[DMA.scala:138:9]
wire [3:0] auto_out_a_bits_size_0; // @[DMA.scala:138:9]
wire [3:0] auto_out_a_bits_source_0; // @[DMA.scala:138:9]
wire [31:0] auto_out_a_bits_address_0; // @[DMA.scala:138:9]
wire [15:0] auto_out_a_bits_mask_0; // @[DMA.scala:138:9]
wire [127:0] auto_out_a_bits_data_0; // @[DMA.scala:138:9]
wire auto_out_a_bits_corrupt_0; // @[DMA.scala:138:9]
wire auto_out_a_valid_0; // @[DMA.scala:138:9]
wire auto_out_d_ready_0; // @[DMA.scala:138:9]
wire io_req_ready_0; // @[DMA.scala:138:9]
wire [5:0] io_reserve_entry_shift_0; // @[DMA.scala:138:9]
wire [13:0] io_reserve_entry_addr_0; // @[DMA.scala:138:9]
wire io_reserve_entry_is_acc_0; // @[DMA.scala:138:9]
wire io_reserve_entry_accumulate_0; // @[DMA.scala:138:9]
wire io_reserve_entry_has_acc_bitwidth_0; // @[DMA.scala:138:9]
wire [31:0] io_reserve_entry_scale_0; // @[DMA.scala:138:9]
wire [15:0] io_reserve_entry_repeats_0; // @[DMA.scala:138:9]
wire [7:0] io_reserve_entry_pixel_repeats_0; // @[DMA.scala:138:9]
wire [15:0] io_reserve_entry_len_0; // @[DMA.scala:138:9]
wire [15:0] io_reserve_entry_block_stride_0; // @[DMA.scala:138:9]
wire [6:0] io_reserve_entry_spad_row_offset_0; // @[DMA.scala:138:9]
wire [6:0] io_reserve_entry_bytes_to_read_0; // @[DMA.scala:138:9]
wire [2:0] io_reserve_entry_cmd_id_0; // @[DMA.scala:138:9]
wire io_reserve_valid_0; // @[DMA.scala:138:9]
wire [3:0] io_beatData_bits_xactid_0; // @[DMA.scala:138:9]
wire [127:0] io_beatData_bits_data_0; // @[DMA.scala:138:9]
wire [2:0] io_beatData_bits_lg_len_req_0; // @[DMA.scala:138:9]
wire io_beatData_bits_last_0; // @[DMA.scala:138:9]
wire io_beatData_valid_0; // @[DMA.scala:138:9]
wire [39:0] io_tlb_req_bits_tlb_req_vaddr_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_debug_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_cease_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_wfi_0; // @[DMA.scala:138:9]
wire [31:0] io_tlb_req_bits_status_isa_0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_status_dprv_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_dv_0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_status_prv_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_v_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_sd_0; // @[DMA.scala:138:9]
wire [22:0] io_tlb_req_bits_status_zero2_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_mpv_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_gva_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_mbe_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_sbe_0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_status_sxl_0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_status_uxl_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_sd_rv32_0; // @[DMA.scala:138:9]
wire [7:0] io_tlb_req_bits_status_zero1_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_tsr_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_tw_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_tvm_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_mxr_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_sum_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_mprv_0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_status_xs_0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_status_fs_0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_status_mpp_0; // @[DMA.scala:138:9]
wire [1:0] io_tlb_req_bits_status_vs_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_spp_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_mpie_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_ube_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_spie_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_upie_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_mie_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_hie_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_sie_0; // @[DMA.scala:138:9]
wire io_tlb_req_bits_status_uie_0; // @[DMA.scala:138:9]
wire io_tlb_req_valid_0; // @[DMA.scala:138:9]
wire io_counter_event_signal_18_0; // @[DMA.scala:138:9]
wire io_counter_event_signal_20_0; // @[DMA.scala:138:9]
wire [31:0] io_counter_external_values_4_0; // @[DMA.scala:138:9]
wire _nodeOut_a_valid_T_1; // @[DMA.scala:249:44]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DMA.scala:138:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DMA.scala:138:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DMA.scala:138:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DMA.scala:138:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DMA.scala:138:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DMA.scala:138:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DMA.scala:138:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DMA.scala:138:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[DMA.scala:138:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DMA.scala:138:9]
assign io_beatData_valid_0 = nodeOut_d_valid; // @[DMA.scala:138:9]
assign io_beatData_bits_xactid_0 = nodeOut_d_bits_source; // @[DMA.scala:138:9]
assign io_beatData_bits_data_0 = nodeOut_d_bits_data; // @[DMA.scala:138:9]
reg state; // @[DMA.scala:157:24]
assign io_counter_event_signal_18_0 = state; // @[DMA.scala:138:9, :157:24]
wire _untranslated_a_valid_T = state; // @[DMA.scala:157:24, :219:35]
wire _io_reserve_valid_T = state; // @[DMA.scala:157:24, :253:31]
reg [39:0] req_vaddr; // @[DMA.scala:159:18]
reg [13:0] req_spaddr; // @[DMA.scala:159:18]
reg req_is_acc; // @[DMA.scala:159:18]
assign io_reserve_entry_is_acc_0 = req_is_acc; // @[DMA.scala:138:9, :159:18]
reg req_accumulate; // @[DMA.scala:159:18]
assign io_reserve_entry_accumulate_0 = req_accumulate; // @[DMA.scala:138:9, :159:18]
reg req_has_acc_bitwidth; // @[DMA.scala:159:18]
assign io_reserve_entry_has_acc_bitwidth_0 = req_has_acc_bitwidth; // @[DMA.scala:138:9, :159:18]
reg [31:0] req_scale; // @[DMA.scala:159:18]
assign io_reserve_entry_scale_0 = req_scale; // @[DMA.scala:138:9, :159:18]
reg req_status_debug; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_debug = req_status_debug; // @[DMA.scala:159:18, :218:30]
reg req_status_cease; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_cease = req_status_cease; // @[DMA.scala:159:18, :218:30]
reg req_status_wfi; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_wfi = req_status_wfi; // @[DMA.scala:159:18, :218:30]
reg [31:0] req_status_isa; // @[DMA.scala:159:18]
wire [31:0] untranslated_a_bits_status_isa = req_status_isa; // @[DMA.scala:159:18, :218:30]
reg [1:0] req_status_dprv; // @[DMA.scala:159:18]
wire [1:0] untranslated_a_bits_status_dprv = req_status_dprv; // @[DMA.scala:159:18, :218:30]
reg req_status_dv; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_dv = req_status_dv; // @[DMA.scala:159:18, :218:30]
reg [1:0] req_status_prv; // @[DMA.scala:159:18]
wire [1:0] untranslated_a_bits_status_prv = req_status_prv; // @[DMA.scala:159:18, :218:30]
reg req_status_v; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_v = req_status_v; // @[DMA.scala:159:18, :218:30]
reg req_status_sd; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_sd = req_status_sd; // @[DMA.scala:159:18, :218:30]
reg [22:0] req_status_zero2; // @[DMA.scala:159:18]
wire [22:0] untranslated_a_bits_status_zero2 = req_status_zero2; // @[DMA.scala:159:18, :218:30]
reg req_status_mpv; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_mpv = req_status_mpv; // @[DMA.scala:159:18, :218:30]
reg req_status_gva; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_gva = req_status_gva; // @[DMA.scala:159:18, :218:30]
reg req_status_mbe; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_mbe = req_status_mbe; // @[DMA.scala:159:18, :218:30]
reg req_status_sbe; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_sbe = req_status_sbe; // @[DMA.scala:159:18, :218:30]
reg [1:0] req_status_sxl; // @[DMA.scala:159:18]
wire [1:0] untranslated_a_bits_status_sxl = req_status_sxl; // @[DMA.scala:159:18, :218:30]
reg [1:0] req_status_uxl; // @[DMA.scala:159:18]
wire [1:0] untranslated_a_bits_status_uxl = req_status_uxl; // @[DMA.scala:159:18, :218:30]
reg req_status_sd_rv32; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_sd_rv32 = req_status_sd_rv32; // @[DMA.scala:159:18, :218:30]
reg [7:0] req_status_zero1; // @[DMA.scala:159:18]
wire [7:0] untranslated_a_bits_status_zero1 = req_status_zero1; // @[DMA.scala:159:18, :218:30]
reg req_status_tsr; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_tsr = req_status_tsr; // @[DMA.scala:159:18, :218:30]
reg req_status_tw; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_tw = req_status_tw; // @[DMA.scala:159:18, :218:30]
reg req_status_tvm; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_tvm = req_status_tvm; // @[DMA.scala:159:18, :218:30]
reg req_status_mxr; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_mxr = req_status_mxr; // @[DMA.scala:159:18, :218:30]
reg req_status_sum; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_sum = req_status_sum; // @[DMA.scala:159:18, :218:30]
reg req_status_mprv; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_mprv = req_status_mprv; // @[DMA.scala:159:18, :218:30]
reg [1:0] req_status_xs; // @[DMA.scala:159:18]
wire [1:0] untranslated_a_bits_status_xs = req_status_xs; // @[DMA.scala:159:18, :218:30]
reg [1:0] req_status_fs; // @[DMA.scala:159:18]
wire [1:0] untranslated_a_bits_status_fs = req_status_fs; // @[DMA.scala:159:18, :218:30]
reg [1:0] req_status_mpp; // @[DMA.scala:159:18]
wire [1:0] untranslated_a_bits_status_mpp = req_status_mpp; // @[DMA.scala:159:18, :218:30]
reg [1:0] req_status_vs; // @[DMA.scala:159:18]
wire [1:0] untranslated_a_bits_status_vs = req_status_vs; // @[DMA.scala:159:18, :218:30]
reg req_status_spp; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_spp = req_status_spp; // @[DMA.scala:159:18, :218:30]
reg req_status_mpie; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_mpie = req_status_mpie; // @[DMA.scala:159:18, :218:30]
reg req_status_ube; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_ube = req_status_ube; // @[DMA.scala:159:18, :218:30]
reg req_status_spie; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_spie = req_status_spie; // @[DMA.scala:159:18, :218:30]
reg req_status_upie; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_upie = req_status_upie; // @[DMA.scala:159:18, :218:30]
reg req_status_mie; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_mie = req_status_mie; // @[DMA.scala:159:18, :218:30]
reg req_status_hie; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_hie = req_status_hie; // @[DMA.scala:159:18, :218:30]
reg req_status_sie; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_sie = req_status_sie; // @[DMA.scala:159:18, :218:30]
reg req_status_uie; // @[DMA.scala:159:18]
wire untranslated_a_bits_status_uie = req_status_uie; // @[DMA.scala:159:18, :218:30]
reg [15:0] req_len; // @[DMA.scala:159:18]
assign io_reserve_entry_len_0 = req_len; // @[DMA.scala:138:9, :159:18]
reg [15:0] req_repeats; // @[DMA.scala:159:18]
assign io_reserve_entry_repeats_0 = req_repeats; // @[DMA.scala:138:9, :159:18]
reg [7:0] req_pixel_repeats; // @[DMA.scala:159:18]
assign io_reserve_entry_pixel_repeats_0 = req_pixel_repeats; // @[DMA.scala:138:9, :159:18]
reg [15:0] req_block_stride; // @[DMA.scala:159:18]
assign io_reserve_entry_block_stride_0 = req_block_stride; // @[DMA.scala:138:9, :159:18]
reg [7:0] req_cmd_id; // @[DMA.scala:159:18]
reg [5:0] bytesRequested; // @[DMA.scala:162:29]
wire [18:0] _GEN = {1'h0, req_len, 2'h0}; // @[DMA.scala:159:18, :163:55]
wire [18:0] _bytesLeft_T; // @[DMA.scala:163:55]
assign _bytesLeft_T = _GEN; // @[DMA.scala:163:55]
wire [18:0] _bytesLeft_T_1; // @[DMA.scala:163:98]
assign _bytesLeft_T_1 = _GEN; // @[DMA.scala:163:{55,98}]
wire [18:0] _bytesLeft_T_2 = req_has_acc_bitwidth ? _bytesLeft_T : _bytesLeft_T_1; // @[DMA.scala:159:18, :163:{24,55,98}]
wire [19:0] _bytesLeft_T_3 = {1'h0, _bytesLeft_T_2} - {14'h0, bytesRequested}; // @[DMA.scala:162:29, :163:{24,135}]
wire [18:0] bytesLeft = _bytesLeft_T_3[18:0]; // @[DMA.scala:163:135]
wire _state_machine_ready_for_req_T = ~state; // @[DMA.scala:157:24, :165:54]
assign io_req_ready_0 = state_machine_ready_for_req; // @[DMA.scala:138:9, :165:47]
wire [34:0] _read_packets_vaddr_aligned_to_size_T = req_vaddr[38:4]; // @[DMA.scala:159:18, :185:67]
wire [38:0] read_packets_vaddr_aligned_to_size = {_read_packets_vaddr_aligned_to_size_T, 4'h0}; // @[DMA.scala:185:{61,67}]
wire [38:0] read_packets_0_vaddr = read_packets_vaddr_aligned_to_size; // @[DMA.scala:185:61, :188:24]
wire [3:0] read_packets_vaddr_offset = req_vaddr[3:0]; // @[DMA.scala:159:18, :186:42]
wire [6:0] read_packets_0_bytes_read; // @[DMA.scala:188:24]
wire [5:0] read_packets_0_shift; // @[DMA.scala:188:24]
assign read_packets_0_shift = {2'h0, read_packets_vaddr_offset}; // @[DMA.scala:186:42, :188:24, :191:38]
wire [5:0] _read_packets_packet_bytes_read_T = 6'h10 - read_packets_0_shift; // @[DMA.scala:188:24, :191:38]
wire [4:0] _read_packets_packet_bytes_read_T_1 = _read_packets_packet_bytes_read_T[4:0]; // @[DMA.scala:191:38]
wire [18:0] _GEN_0 = {14'h0, _read_packets_packet_bytes_read_T_1}; // @[Util.scala:109:12]
wire _read_packets_packet_bytes_read_T_2 = _GEN_0 < bytesLeft; // @[Util.scala:109:12]
wire [18:0] _read_packets_packet_bytes_read_T_3 = _read_packets_packet_bytes_read_T_2 ? _GEN_0 : bytesLeft; // @[Util.scala:109:{8,12}]
assign read_packets_0_bytes_read = _read_packets_packet_bytes_read_T_3[6:0]; // @[Util.scala:109:8]
wire [33:0] _read_packets_vaddr_aligned_to_size_T_1 = req_vaddr[38:5]; // @[DMA.scala:159:18, :185:67]
wire [38:0] read_packets_vaddr_aligned_to_size_1 = {_read_packets_vaddr_aligned_to_size_T_1, 5'h0}; // @[DMA.scala:185:{61,67}]
wire [38:0] read_packets_1_vaddr = read_packets_vaddr_aligned_to_size_1; // @[DMA.scala:185:61, :188:24]
wire [4:0] read_packets_vaddr_offset_1 = req_vaddr[4:0]; // @[DMA.scala:159:18, :186:42]
wire [6:0] read_packets_1_bytes_read; // @[DMA.scala:188:24]
wire [5:0] read_packets_1_shift; // @[DMA.scala:188:24]
wire [6:0] _read_packets_packet_bytes_read_T_4 = 7'h20 - {2'h0, read_packets_vaddr_offset_1}; // @[DMA.scala:186:42, :191:38]
wire [5:0] _read_packets_packet_bytes_read_T_5 = _read_packets_packet_bytes_read_T_4[5:0]; // @[DMA.scala:191:38]
wire [18:0] _GEN_1 = {13'h0, _read_packets_packet_bytes_read_T_5}; // @[Util.scala:109:12]
wire _read_packets_packet_bytes_read_T_6 = _GEN_1 < bytesLeft; // @[Util.scala:109:12]
wire [18:0] _read_packets_packet_bytes_read_T_7 = _read_packets_packet_bytes_read_T_6 ? _GEN_1 : bytesLeft; // @[Util.scala:109:{8,12}]
assign read_packets_1_bytes_read = _read_packets_packet_bytes_read_T_7[6:0]; // @[Util.scala:109:8]
assign read_packets_1_shift = {1'h0, read_packets_vaddr_offset_1}; // @[DMA.scala:186:42, :188:24, :192:20]
wire [32:0] _read_packets_vaddr_aligned_to_size_T_2 = req_vaddr[38:6]; // @[DMA.scala:159:18, :185:67]
wire [38:0] read_packets_vaddr_aligned_to_size_2 = {_read_packets_vaddr_aligned_to_size_T_2, 6'h0}; // @[DMA.scala:185:{61,67}]
wire [38:0] read_packets_2_vaddr = read_packets_vaddr_aligned_to_size_2; // @[DMA.scala:185:61, :188:24]
wire [5:0] read_packets_vaddr_offset_2 = req_vaddr[5:0]; // @[DMA.scala:159:18, :186:42]
wire [5:0] read_packets_2_shift = read_packets_vaddr_offset_2; // @[DMA.scala:186:42, :188:24]
wire [6:0] read_packets_2_bytes_read; // @[DMA.scala:188:24]
wire [7:0] _read_packets_packet_bytes_read_T_8 = 8'h40 - {2'h0, read_packets_vaddr_offset_2}; // @[DMA.scala:186:42, :191:38]
wire [6:0] _read_packets_packet_bytes_read_T_9 = _read_packets_packet_bytes_read_T_8[6:0]; // @[DMA.scala:191:38]
wire [18:0] _GEN_2 = {12'h0, _read_packets_packet_bytes_read_T_9}; // @[Util.scala:109:12]
wire _read_packets_packet_bytes_read_T_10 = _GEN_2 < bytesLeft; // @[Util.scala:109:12]
wire [18:0] _read_packets_packet_bytes_read_T_11 = _read_packets_packet_bytes_read_T_10 ? _GEN_2 : bytesLeft; // @[Util.scala:109:{8,12}]
assign read_packets_2_bytes_read = _read_packets_packet_bytes_read_T_11[6:0]; // @[Util.scala:109:8]
wire _read_packet_T = read_packets_1_bytes_read > read_packets_0_bytes_read; // @[DMA.scala:188:24, :198:24]
wire [6:0] _read_packet_T_1_size = _read_packet_T ? 7'h20 : 7'h10; // @[DMA.scala:191:38, :198:{10,24}]
wire [2:0] _read_packet_T_1_lg_size = {2'h2, _read_packet_T}; // @[DMA.scala:198:{10,24}]
wire [6:0] _read_packet_T_1_bytes_read = _read_packet_T ? read_packets_1_bytes_read : read_packets_0_bytes_read; // @[DMA.scala:188:24, :198:{10,24}]
wire [5:0] _read_packet_T_1_shift = _read_packet_T ? read_packets_1_shift : read_packets_0_shift; // @[DMA.scala:188:24, :198:{10,24}]
wire [38:0] _read_packet_T_1_vaddr = _read_packet_T ? read_packets_1_vaddr : read_packets_0_vaddr; // @[DMA.scala:188:24, :198:{10,24}]
wire _read_packet_T_2 = read_packets_2_bytes_read > _read_packet_T_1_bytes_read; // @[DMA.scala:188:24, :198:{10,24}]
wire [6:0] read_packet_size = _read_packet_T_2 ? 7'h40 : _read_packet_T_1_size; // @[DMA.scala:198:{10,24}]
wire [2:0] read_packet_lg_size = _read_packet_T_2 ? 3'h6 : _read_packet_T_1_lg_size; // @[DMA.scala:198:{10,24}]
assign read_packet_bytes_read = _read_packet_T_2 ? read_packets_2_bytes_read : _read_packet_T_1_bytes_read; // @[DMA.scala:188:24, :198:{10,24}]
assign read_packet_shift = _read_packet_T_2 ? read_packets_2_shift : _read_packet_T_1_shift; // @[DMA.scala:188:24, :198:{10,24}]
wire [38:0] read_packet_vaddr = _read_packet_T_2 ? read_packets_2_vaddr : _read_packet_T_1_vaddr; // @[DMA.scala:188:24, :198:{10,24}]
assign io_reserve_entry_bytes_to_read_0 = read_packet_bytes_read; // @[DMA.scala:138:9, :198:10]
assign io_reserve_entry_shift_0 = read_packet_shift; // @[DMA.scala:138:9, :198:10]
wire [38:0] untranslated_a_bits_vaddr = read_packet_vaddr; // @[DMA.scala:198:10, :218:30]
wire _get_legal_T_11 = read_packet_lg_size != 3'h7; // @[Parameters.scala:92:38]
wire _get_legal_T_12 = _get_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _get_legal_T_13 = _get_legal_T_12; // @[Parameters.scala:684:29]
wire _get_legal_T_61 = _get_legal_T_13; // @[Parameters.scala:684:{29,54}]
wire get_legal = _get_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire [3:0] untranslated_a_bits_tl_a_size = get_size; // @[Edges.scala:460:17]
wire [3:0] untranslated_a_bits_tl_a_source = get_source; // @[Edges.scala:460:17]
wire [15:0] _get_a_mask_T; // @[Misc.scala:222:10]
wire [15:0] untranslated_a_bits_tl_a_mask = get_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_3 = {1'h0, read_packet_lg_size}; // @[Edges.scala:463:15]
assign get_size = _GEN_3; // @[Edges.scala:460:17, :463:15]
wire [3:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _get_a_mask_sizeOH_T = _GEN_3; // @[Misc.scala:202:34]
wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire get_a_mask_sub_sub_sub_sub_0_1 = read_packet_lg_size[2]; // @[Misc.scala:206:21]
wire get_a_mask_sub_sub_sub_1_1 = get_a_mask_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21, :215:29]
wire get_a_mask_sub_sub_sub_size = get_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire _get_a_mask_sub_sub_sub_acc_T = get_a_mask_sub_sub_sub_size; // @[Misc.scala:209:26, :215:38]
wire get_a_mask_sub_sub_sub_0_1 = get_a_mask_sub_sub_sub_sub_0_1 | _get_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_sub_2_1 = get_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_sub_3_1 = get_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size; // @[Misc.scala:209:26, :215:38]
wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_4_1 = get_a_mask_sub_sub_2_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_5_1 = get_a_mask_sub_sub_2_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_6_1 = get_a_mask_sub_sub_3_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_7_1 = get_a_mask_sub_sub_3_1; // @[Misc.scala:215:29]
wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire _get_a_mask_sub_acc_T = get_a_mask_sub_size; // @[Misc.scala:209:26, :215:38]
wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_acc_1 = get_a_mask_sub_0_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_2 = get_a_mask_sub_1_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_3 = get_a_mask_sub_1_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_4 = get_a_mask_sub_2_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_5 = get_a_mask_sub_2_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_6 = get_a_mask_sub_3_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_7 = get_a_mask_sub_3_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_8 = get_a_mask_sub_4_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_9 = get_a_mask_sub_4_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_10 = get_a_mask_sub_5_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_11 = get_a_mask_sub_5_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_12 = get_a_mask_sub_6_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_13 = get_a_mask_sub_6_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_14 = get_a_mask_sub_7_1; // @[Misc.scala:215:29]
wire get_a_mask_acc_15 = get_a_mask_sub_7_1; // @[Misc.scala:215:29]
wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire _get_a_mask_acc_T = get_a_mask_size; // @[Misc.scala:209:26, :215:38]
wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire [1:0] get_a_mask_lo_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_lo_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_lo_lo = {get_a_mask_lo_lo_hi, get_a_mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_lo_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_lo_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_lo_hi = {get_a_mask_lo_hi_hi, get_a_mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_hi_lo_lo = {get_a_mask_acc_9, get_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_hi_lo_hi = {get_a_mask_acc_11, get_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_hi_lo = {get_a_mask_hi_lo_hi, get_a_mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_hi_hi_lo = {get_a_mask_acc_13, get_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_hi_hi_hi = {get_a_mask_acc_15, get_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_hi_hi = {get_a_mask_hi_hi_hi, get_a_mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10]
assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10]
wire _untranslated_a_valid_T_1; // @[DMA.scala:219:55]
wire untranslated_a_ready; // @[DMA.scala:218:30]
wire untranslated_a_valid; // @[DMA.scala:218:30]
assign _untranslated_a_valid_T_1 = _untranslated_a_valid_T & io_reserve_ready_0; // @[DMA.scala:138:9, :219:{35,55}]
assign untranslated_a_valid = _untranslated_a_valid_T_1; // @[DMA.scala:218:30, :219:55]
wire _retry_a_valid_T_2; // @[DMA.scala:245:47]
wire [2:0] retry_a_bits_tl_a_opcode; // @[DMA.scala:225:23]
wire [2:0] retry_a_bits_tl_a_param; // @[DMA.scala:225:23]
wire [3:0] retry_a_bits_tl_a_size; // @[DMA.scala:225:23]
wire [3:0] retry_a_bits_tl_a_source; // @[DMA.scala:225:23]
wire [31:0] retry_a_bits_tl_a_address; // @[DMA.scala:225:23]
wire [15:0] retry_a_bits_tl_a_mask; // @[DMA.scala:225:23]
wire [127:0] retry_a_bits_tl_a_data; // @[DMA.scala:225:23]
wire retry_a_bits_tl_a_corrupt; // @[DMA.scala:225:23]
wire retry_a_bits_status_debug; // @[DMA.scala:225:23]
wire retry_a_bits_status_cease; // @[DMA.scala:225:23]
wire retry_a_bits_status_wfi; // @[DMA.scala:225:23]
wire [31:0] retry_a_bits_status_isa; // @[DMA.scala:225:23]
wire [1:0] retry_a_bits_status_dprv; // @[DMA.scala:225:23]
wire retry_a_bits_status_dv; // @[DMA.scala:225:23]
wire [1:0] retry_a_bits_status_prv; // @[DMA.scala:225:23]
wire retry_a_bits_status_v; // @[DMA.scala:225:23]
wire retry_a_bits_status_sd; // @[DMA.scala:225:23]
wire [22:0] retry_a_bits_status_zero2; // @[DMA.scala:225:23]
wire retry_a_bits_status_mpv; // @[DMA.scala:225:23]
wire retry_a_bits_status_gva; // @[DMA.scala:225:23]
wire retry_a_bits_status_mbe; // @[DMA.scala:225:23]
wire retry_a_bits_status_sbe; // @[DMA.scala:225:23]
wire [1:0] retry_a_bits_status_sxl; // @[DMA.scala:225:23]
wire [1:0] retry_a_bits_status_uxl; // @[DMA.scala:225:23]
wire retry_a_bits_status_sd_rv32; // @[DMA.scala:225:23]
wire [7:0] retry_a_bits_status_zero1; // @[DMA.scala:225:23]
wire retry_a_bits_status_tsr; // @[DMA.scala:225:23]
wire retry_a_bits_status_tw; // @[DMA.scala:225:23]
wire retry_a_bits_status_tvm; // @[DMA.scala:225:23]
wire retry_a_bits_status_mxr; // @[DMA.scala:225:23]
wire retry_a_bits_status_sum; // @[DMA.scala:225:23]
wire retry_a_bits_status_mprv; // @[DMA.scala:225:23]
wire [1:0] retry_a_bits_status_xs; // @[DMA.scala:225:23]
wire [1:0] retry_a_bits_status_fs; // @[DMA.scala:225:23]
wire [1:0] retry_a_bits_status_mpp; // @[DMA.scala:225:23]
wire [1:0] retry_a_bits_status_vs; // @[DMA.scala:225:23]
wire retry_a_bits_status_spp; // @[DMA.scala:225:23]
wire retry_a_bits_status_mpie; // @[DMA.scala:225:23]
wire retry_a_bits_status_ube; // @[DMA.scala:225:23]
wire retry_a_bits_status_spie; // @[DMA.scala:225:23]
wire retry_a_bits_status_upie; // @[DMA.scala:225:23]
wire retry_a_bits_status_mie; // @[DMA.scala:225:23]
wire retry_a_bits_status_hie; // @[DMA.scala:225:23]
wire retry_a_bits_status_sie; // @[DMA.scala:225:23]
wire retry_a_bits_status_uie; // @[DMA.scala:225:23]
wire [38:0] retry_a_bits_vaddr; // @[DMA.scala:225:23]
wire retry_a_valid; // @[DMA.scala:225:23]
assign io_tlb_req_bits_tlb_req_vaddr_0 = {1'h0, _tlb_q_io_deq_bits_vaddr}; // @[DMA.scala:138:9, :230:23, :235:35]
wire _retry_a_valid_T = ~nodeOut_a_ready; // @[DMA.scala:245:71]
wire _retry_a_valid_T_1 = io_tlb_resp_miss_0 | _retry_a_valid_T; // @[DMA.scala:138:9, :245:{68,71}]
assign _retry_a_valid_T_2 = _translate_q_io_deq_valid & _retry_a_valid_T_1; // @[DMA.scala:241:29, :245:{47,68}]
assign retry_a_valid = _retry_a_valid_T_2; // @[DMA.scala:225:23, :245:47]
wire _nodeOut_a_valid_T = ~io_tlb_resp_miss_0; // @[DMA.scala:138:9, :249:47]
assign _nodeOut_a_valid_T_1 = _translate_q_io_deq_valid & _nodeOut_a_valid_T; // @[DMA.scala:241:29, :249:{44,47}]
assign nodeOut_a_valid = _nodeOut_a_valid_T_1; // @[DMA.scala:249:44]
assign _io_reserve_valid_T_1 = _io_reserve_valid_T & untranslated_a_ready; // @[DMA.scala:218:30, :253:{31,51}]
assign io_reserve_valid_0 = _io_reserve_valid_T_1; // @[DMA.scala:138:9, :253:51]
assign io_reserve_entry_cmd_id_0 = req_cmd_id[2:0]; // @[DMA.scala:138:9, :159:18, :265:29]
wire [5:0] _GEN_4 = bytesRequested / 6'h10; // @[DMA.scala:162:29, :191:38, :272:80]
wire [5:0] _io_reserve_entry_addr_T; // @[DMA.scala:272:80]
assign _io_reserve_entry_addr_T = _GEN_4; // @[DMA.scala:272:80]
wire [5:0] _io_reserve_entry_addr_T_1; // @[DMA.scala:273:81]
assign _io_reserve_entry_addr_T_1 = _GEN_4; // @[DMA.scala:272:80, :273:81]
wire [5:0] _io_reserve_entry_addr_T_2 = req_has_acc_bitwidth ? _io_reserve_entry_addr_T : _io_reserve_entry_addr_T_1; // @[DMA.scala:159:18, :268:10, :272:80, :273:81]
wire [21:0] _io_reserve_entry_addr_T_3 = {6'h0, req_block_stride} * {16'h0, _io_reserve_entry_addr_T_2}; // @[DMA.scala:159:18, :163:55, :267:60, :268:10]
wire [22:0] _io_reserve_entry_addr_T_4 = {9'h0, req_spaddr} + {1'h0, _io_reserve_entry_addr_T_3}; // @[DMA.scala:159:18, :267:{41,60}]
wire [21:0] _io_reserve_entry_addr_T_5 = _io_reserve_entry_addr_T_4[21:0]; // @[DMA.scala:267:41]
assign io_reserve_entry_addr_0 = _io_reserve_entry_addr_T_5[13:0]; // @[DMA.scala:138:9, :267:{27,41}]
wire [5:0] _GEN_5 = bytesRequested % 6'h10; // @[DMA.scala:162:29, :191:38, :274:82]
wire [4:0] _io_reserve_entry_spad_row_offset_T = _GEN_5[4:0]; // @[DMA.scala:274:82]
wire [4:0] _io_reserve_entry_spad_row_offset_T_1 = _GEN_5[4:0]; // @[DMA.scala:274:{82,116}]
wire [4:0] _io_reserve_entry_spad_row_offset_T_2 = req_has_acc_bitwidth ? _io_reserve_entry_spad_row_offset_T : _io_reserve_entry_spad_row_offset_T_1; // @[DMA.scala:159:18, :274:{44,82,116}]
assign io_reserve_entry_spad_row_offset_0 = {2'h0, _io_reserve_entry_spad_row_offset_T_2}; // @[DMA.scala:138:9, :274:{38,44}]
wire _T_3 = untranslated_a_ready & untranslated_a_valid; // @[Decoupled.scala:51:35]
wire [40:0] _next_vaddr_T = {1'h0, req_vaddr} + {34'h0, read_packet_bytes_read}; // @[DMA.scala:159:18, :198:10, :277:34]
wire [39:0] next_vaddr = _next_vaddr_T[39:0]; // @[DMA.scala:277:34]
wire [11:0] _new_page_T = next_vaddr[11:0]; // @[DMA.scala:277:34, :278:32]
wire new_page = _new_page_T == 12'h0; // @[Util.scala:109:12]
wire [7:0] _bytesRequested_T = {2'h0, bytesRequested} + {1'h0, read_packet_bytes_read}; // @[DMA.scala:162:29, :198:10, :281:40]
wire [6:0] _bytesRequested_T_1 = _bytesRequested_T[6:0]; // @[DMA.scala:281:40]
wire _GEN_6 = _T_3 & {12'h0, read_packet_bytes_read} >= bytesLeft; // @[Decoupled.scala:51:35]
assign state_machine_ready_for_req = _GEN_6 | _state_machine_ready_for_req_T; // @[DMA.scala:165:{47,54}, :276:32, :284:43, :286:37]
assign io_beatData_bits_lg_len_req_0 = nodeOut_d_bits_size[2:0]; // @[DMA.scala:138:9, :296:33]
wire _io_beatData_bits_last_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] _io_beatData_bits_last_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _io_beatData_bits_last_beats1_decode_T_1 = _io_beatData_bits_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_beatData_bits_last_beats1_decode_T_2 = ~_io_beatData_bits_last_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] io_beatData_bits_last_beats1_decode = _io_beatData_bits_last_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire io_beatData_bits_last_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [7:0] io_beatData_bits_last_beats1 = io_beatData_bits_last_beats1_opdata ? io_beatData_bits_last_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] io_beatData_bits_last_counter; // @[Edges.scala:229:27]
wire [8:0] _io_beatData_bits_last_counter1_T = {1'h0, io_beatData_bits_last_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] io_beatData_bits_last_counter1 = _io_beatData_bits_last_counter1_T[7:0]; // @[Edges.scala:230:28]
wire io_beatData_bits_last_first = io_beatData_bits_last_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _io_beatData_bits_last_last_T = io_beatData_bits_last_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _io_beatData_bits_last_last_T_1 = io_beatData_bits_last_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
assign io_beatData_bits_last_last = _io_beatData_bits_last_last_T | _io_beatData_bits_last_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_beatData_bits_last_0 = io_beatData_bits_last_last; // @[Edges.scala:232:33]
wire io_beatData_bits_last_done = io_beatData_bits_last_last & _io_beatData_bits_last_T; // @[Decoupled.scala:51:35]
wire [7:0] _io_beatData_bits_last_count_T = ~io_beatData_bits_last_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] io_beatData_bits_last_count = io_beatData_bits_last_beats1 & _io_beatData_bits_last_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _io_beatData_bits_last_counter_T = io_beatData_bits_last_first ? io_beatData_bits_last_beats1 : io_beatData_bits_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
assign io_counter_event_signal_20_0 = nodeOut_a_valid & ~nodeOut_a_ready; // @[DMA.scala:138:9, :245:71, :313:80]
reg [31:0] total_bytes_read; // @[DMA.scala:316:35]
assign io_counter_external_values_4_0 = total_bytes_read; // @[DMA.scala:138:9, :316:35]
wire [15:0] _total_bytes_read_T = 16'h1 << nodeOut_d_bits_size; // @[DMA.scala:320:51]
wire [32:0] _total_bytes_read_T_1 = {1'h0, total_bytes_read} + {17'h0, _total_bytes_read_T}; // @[DMA.scala:316:35, :320:{44,51}]
wire [31:0] _total_bytes_read_T_2 = _total_bytes_read_T_1[31:0]; // @[DMA.scala:320:44]
wire _T_5 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[DMA.scala:138:9]
if (reset) begin // @[DMA.scala:138:9]
state <= 1'h0; // @[DMA.scala:157:24]
io_beatData_bits_last_counter <= 8'h0; // @[Edges.scala:229:27]
total_bytes_read <= 32'h0; // @[DMA.scala:316:35]
end
else begin // @[DMA.scala:138:9]
state <= _T_5 | ~_GEN_6 & state; // @[Decoupled.scala:51:35]
if (_io_beatData_bits_last_T) // @[Decoupled.scala:51:35]
io_beatData_bits_last_counter <= _io_beatData_bits_last_counter_T; // @[Edges.scala:229:27, :236:21]
if (io_counter_external_reset_0) // @[DMA.scala:138:9]
total_bytes_read <= 32'h0; // @[DMA.scala:316:35]
else if (_io_beatData_bits_last_T) // @[Decoupled.scala:51:35]
total_bytes_read <= _total_bytes_read_T_2; // @[DMA.scala:316:35, :320:44]
end
if (_T_5) begin // @[Decoupled.scala:51:35]
req_vaddr <= io_req_bits_vaddr_0; // @[DMA.scala:138:9, :159:18]
req_spaddr <= io_req_bits_spaddr_0; // @[DMA.scala:138:9, :159:18]
req_is_acc <= io_req_bits_is_acc_0; // @[DMA.scala:138:9, :159:18]
req_accumulate <= io_req_bits_accumulate_0; // @[DMA.scala:138:9, :159:18]
req_has_acc_bitwidth <= io_req_bits_has_acc_bitwidth_0; // @[DMA.scala:138:9, :159:18]
req_scale <= io_req_bits_scale_0; // @[DMA.scala:138:9, :159:18]
req_status_debug <= io_req_bits_status_debug_0; // @[DMA.scala:138:9, :159:18]
req_status_cease <= io_req_bits_status_cease_0; // @[DMA.scala:138:9, :159:18]
req_status_wfi <= io_req_bits_status_wfi_0; // @[DMA.scala:138:9, :159:18]
req_status_isa <= io_req_bits_status_isa_0; // @[DMA.scala:138:9, :159:18]
req_status_dprv <= io_req_bits_status_dprv_0; // @[DMA.scala:138:9, :159:18]
req_status_dv <= io_req_bits_status_dv_0; // @[DMA.scala:138:9, :159:18]
req_status_prv <= io_req_bits_status_prv_0; // @[DMA.scala:138:9, :159:18]
req_status_v <= io_req_bits_status_v_0; // @[DMA.scala:138:9, :159:18]
req_status_sd <= io_req_bits_status_sd_0; // @[DMA.scala:138:9, :159:18]
req_status_zero2 <= io_req_bits_status_zero2_0; // @[DMA.scala:138:9, :159:18]
req_status_mpv <= io_req_bits_status_mpv_0; // @[DMA.scala:138:9, :159:18]
req_status_gva <= io_req_bits_status_gva_0; // @[DMA.scala:138:9, :159:18]
req_status_mbe <= io_req_bits_status_mbe_0; // @[DMA.scala:138:9, :159:18]
req_status_sbe <= io_req_bits_status_sbe_0; // @[DMA.scala:138:9, :159:18]
req_status_sxl <= io_req_bits_status_sxl_0; // @[DMA.scala:138:9, :159:18]
req_status_uxl <= io_req_bits_status_uxl_0; // @[DMA.scala:138:9, :159:18]
req_status_sd_rv32 <= io_req_bits_status_sd_rv32_0; // @[DMA.scala:138:9, :159:18]
req_status_zero1 <= io_req_bits_status_zero1_0; // @[DMA.scala:138:9, :159:18]
req_status_tsr <= io_req_bits_status_tsr_0; // @[DMA.scala:138:9, :159:18]
req_status_tw <= io_req_bits_status_tw_0; // @[DMA.scala:138:9, :159:18]
req_status_tvm <= io_req_bits_status_tvm_0; // @[DMA.scala:138:9, :159:18]
req_status_mxr <= io_req_bits_status_mxr_0; // @[DMA.scala:138:9, :159:18]
req_status_sum <= io_req_bits_status_sum_0; // @[DMA.scala:138:9, :159:18]
req_status_mprv <= io_req_bits_status_mprv_0; // @[DMA.scala:138:9, :159:18]
req_status_xs <= io_req_bits_status_xs_0; // @[DMA.scala:138:9, :159:18]
req_status_fs <= io_req_bits_status_fs_0; // @[DMA.scala:138:9, :159:18]
req_status_mpp <= io_req_bits_status_mpp_0; // @[DMA.scala:138:9, :159:18]
req_status_vs <= io_req_bits_status_vs_0; // @[DMA.scala:138:9, :159:18]
req_status_spp <= io_req_bits_status_spp_0; // @[DMA.scala:138:9, :159:18]
req_status_mpie <= io_req_bits_status_mpie_0; // @[DMA.scala:138:9, :159:18]
req_status_ube <= io_req_bits_status_ube_0; // @[DMA.scala:138:9, :159:18]
req_status_spie <= io_req_bits_status_spie_0; // @[DMA.scala:138:9, :159:18]
req_status_upie <= io_req_bits_status_upie_0; // @[DMA.scala:138:9, :159:18]
req_status_mie <= io_req_bits_status_mie_0; // @[DMA.scala:138:9, :159:18]
req_status_hie <= io_req_bits_status_hie_0; // @[DMA.scala:138:9, :159:18]
req_status_sie <= io_req_bits_status_sie_0; // @[DMA.scala:138:9, :159:18]
req_status_uie <= io_req_bits_status_uie_0; // @[DMA.scala:138:9, :159:18]
req_len <= io_req_bits_len_0; // @[DMA.scala:138:9, :159:18]
req_repeats <= io_req_bits_repeats_0; // @[DMA.scala:138:9, :159:18]
req_pixel_repeats <= io_req_bits_pixel_repeats_0; // @[DMA.scala:138:9, :159:18]
req_block_stride <= io_req_bits_block_stride_0; // @[DMA.scala:138:9, :159:18]
req_cmd_id <= io_req_bits_cmd_id_0; // @[DMA.scala:138:9, :159:18]
bytesRequested <= 6'h0; // @[DMA.scala:162:29]
end
else if (_T_3) begin // @[Decoupled.scala:51:35]
req_vaddr <= next_vaddr; // @[DMA.scala:159:18, :277:34]
bytesRequested <= _bytesRequested_T_1[5:0]; // @[DMA.scala:162:29, :281:{22,40}]
end
always @(posedge)
Arbiter2_TLBundleAWithInfo tlb_arb ( // @[DMA.scala:226:25]
.clock (clock),
.reset (reset),
.io_in_0_valid (retry_a_valid), // @[DMA.scala:225:23]
.io_in_0_bits_tl_a_opcode (retry_a_bits_tl_a_opcode), // @[DMA.scala:225:23]
.io_in_0_bits_tl_a_param (retry_a_bits_tl_a_param), // @[DMA.scala:225:23]
.io_in_0_bits_tl_a_size (retry_a_bits_tl_a_size), // @[DMA.scala:225:23]
.io_in_0_bits_tl_a_source (retry_a_bits_tl_a_source), // @[DMA.scala:225:23]
.io_in_0_bits_tl_a_address (retry_a_bits_tl_a_address), // @[DMA.scala:225:23]
.io_in_0_bits_tl_a_mask (retry_a_bits_tl_a_mask), // @[DMA.scala:225:23]
.io_in_0_bits_tl_a_data (retry_a_bits_tl_a_data), // @[DMA.scala:225:23]
.io_in_0_bits_tl_a_corrupt (retry_a_bits_tl_a_corrupt), // @[DMA.scala:225:23]
.io_in_0_bits_vaddr (retry_a_bits_vaddr), // @[DMA.scala:225:23]
.io_in_0_bits_status_debug (retry_a_bits_status_debug), // @[DMA.scala:225:23]
.io_in_0_bits_status_cease (retry_a_bits_status_cease), // @[DMA.scala:225:23]
.io_in_0_bits_status_wfi (retry_a_bits_status_wfi), // @[DMA.scala:225:23]
.io_in_0_bits_status_isa (retry_a_bits_status_isa), // @[DMA.scala:225:23]
.io_in_0_bits_status_dprv (retry_a_bits_status_dprv), // @[DMA.scala:225:23]
.io_in_0_bits_status_dv (retry_a_bits_status_dv), // @[DMA.scala:225:23]
.io_in_0_bits_status_prv (retry_a_bits_status_prv), // @[DMA.scala:225:23]
.io_in_0_bits_status_v (retry_a_bits_status_v), // @[DMA.scala:225:23]
.io_in_0_bits_status_sd (retry_a_bits_status_sd), // @[DMA.scala:225:23]
.io_in_0_bits_status_zero2 (retry_a_bits_status_zero2), // @[DMA.scala:225:23]
.io_in_0_bits_status_mpv (retry_a_bits_status_mpv), // @[DMA.scala:225:23]
.io_in_0_bits_status_gva (retry_a_bits_status_gva), // @[DMA.scala:225:23]
.io_in_0_bits_status_mbe (retry_a_bits_status_mbe), // @[DMA.scala:225:23]
.io_in_0_bits_status_sbe (retry_a_bits_status_sbe), // @[DMA.scala:225:23]
.io_in_0_bits_status_sxl (retry_a_bits_status_sxl), // @[DMA.scala:225:23]
.io_in_0_bits_status_uxl (retry_a_bits_status_uxl), // @[DMA.scala:225:23]
.io_in_0_bits_status_sd_rv32 (retry_a_bits_status_sd_rv32), // @[DMA.scala:225:23]
.io_in_0_bits_status_zero1 (retry_a_bits_status_zero1), // @[DMA.scala:225:23]
.io_in_0_bits_status_tsr (retry_a_bits_status_tsr), // @[DMA.scala:225:23]
.io_in_0_bits_status_tw (retry_a_bits_status_tw), // @[DMA.scala:225:23]
.io_in_0_bits_status_tvm (retry_a_bits_status_tvm), // @[DMA.scala:225:23]
.io_in_0_bits_status_mxr (retry_a_bits_status_mxr), // @[DMA.scala:225:23]
.io_in_0_bits_status_sum (retry_a_bits_status_sum), // @[DMA.scala:225:23]
.io_in_0_bits_status_mprv (retry_a_bits_status_mprv), // @[DMA.scala:225:23]
.io_in_0_bits_status_xs (retry_a_bits_status_xs), // @[DMA.scala:225:23]
.io_in_0_bits_status_fs (retry_a_bits_status_fs), // @[DMA.scala:225:23]
.io_in_0_bits_status_mpp (retry_a_bits_status_mpp), // @[DMA.scala:225:23]
.io_in_0_bits_status_vs (retry_a_bits_status_vs), // @[DMA.scala:225:23]
.io_in_0_bits_status_spp (retry_a_bits_status_spp), // @[DMA.scala:225:23]
.io_in_0_bits_status_mpie (retry_a_bits_status_mpie), // @[DMA.scala:225:23]
.io_in_0_bits_status_ube (retry_a_bits_status_ube), // @[DMA.scala:225:23]
.io_in_0_bits_status_spie (retry_a_bits_status_spie), // @[DMA.scala:225:23]
.io_in_0_bits_status_upie (retry_a_bits_status_upie), // @[DMA.scala:225:23]
.io_in_0_bits_status_mie (retry_a_bits_status_mie), // @[DMA.scala:225:23]
.io_in_0_bits_status_hie (retry_a_bits_status_hie), // @[DMA.scala:225:23]
.io_in_0_bits_status_sie (retry_a_bits_status_sie), // @[DMA.scala:225:23]
.io_in_0_bits_status_uie (retry_a_bits_status_uie), // @[DMA.scala:225:23]
.io_in_1_ready (untranslated_a_ready),
.io_in_1_valid (untranslated_a_valid), // @[DMA.scala:218:30]
.io_in_1_bits_tl_a_size (untranslated_a_bits_tl_a_size), // @[DMA.scala:218:30]
.io_in_1_bits_tl_a_source (untranslated_a_bits_tl_a_source), // @[DMA.scala:218:30]
.io_in_1_bits_tl_a_mask (untranslated_a_bits_tl_a_mask), // @[DMA.scala:218:30]
.io_in_1_bits_vaddr (untranslated_a_bits_vaddr), // @[DMA.scala:218:30]
.io_in_1_bits_status_debug (untranslated_a_bits_status_debug), // @[DMA.scala:218:30]
.io_in_1_bits_status_cease (untranslated_a_bits_status_cease), // @[DMA.scala:218:30]
.io_in_1_bits_status_wfi (untranslated_a_bits_status_wfi), // @[DMA.scala:218:30]
.io_in_1_bits_status_isa (untranslated_a_bits_status_isa), // @[DMA.scala:218:30]
.io_in_1_bits_status_dprv (untranslated_a_bits_status_dprv), // @[DMA.scala:218:30]
.io_in_1_bits_status_dv (untranslated_a_bits_status_dv), // @[DMA.scala:218:30]
.io_in_1_bits_status_prv (untranslated_a_bits_status_prv), // @[DMA.scala:218:30]
.io_in_1_bits_status_v (untranslated_a_bits_status_v), // @[DMA.scala:218:30]
.io_in_1_bits_status_sd (untranslated_a_bits_status_sd), // @[DMA.scala:218:30]
.io_in_1_bits_status_zero2 (untranslated_a_bits_status_zero2), // @[DMA.scala:218:30]
.io_in_1_bits_status_mpv (untranslated_a_bits_status_mpv), // @[DMA.scala:218:30]
.io_in_1_bits_status_gva (untranslated_a_bits_status_gva), // @[DMA.scala:218:30]
.io_in_1_bits_status_mbe (untranslated_a_bits_status_mbe), // @[DMA.scala:218:30]
.io_in_1_bits_status_sbe (untranslated_a_bits_status_sbe), // @[DMA.scala:218:30]
.io_in_1_bits_status_sxl (untranslated_a_bits_status_sxl), // @[DMA.scala:218:30]
.io_in_1_bits_status_uxl (untranslated_a_bits_status_uxl), // @[DMA.scala:218:30]
.io_in_1_bits_status_sd_rv32 (untranslated_a_bits_status_sd_rv32), // @[DMA.scala:218:30]
.io_in_1_bits_status_zero1 (untranslated_a_bits_status_zero1), // @[DMA.scala:218:30]
.io_in_1_bits_status_tsr (untranslated_a_bits_status_tsr), // @[DMA.scala:218:30]
.io_in_1_bits_status_tw (untranslated_a_bits_status_tw), // @[DMA.scala:218:30]
.io_in_1_bits_status_tvm (untranslated_a_bits_status_tvm), // @[DMA.scala:218:30]
.io_in_1_bits_status_mxr (untranslated_a_bits_status_mxr), // @[DMA.scala:218:30]
.io_in_1_bits_status_sum (untranslated_a_bits_status_sum), // @[DMA.scala:218:30]
.io_in_1_bits_status_mprv (untranslated_a_bits_status_mprv), // @[DMA.scala:218:30]
.io_in_1_bits_status_xs (untranslated_a_bits_status_xs), // @[DMA.scala:218:30]
.io_in_1_bits_status_fs (untranslated_a_bits_status_fs), // @[DMA.scala:218:30]
.io_in_1_bits_status_mpp (untranslated_a_bits_status_mpp), // @[DMA.scala:218:30]
.io_in_1_bits_status_vs (untranslated_a_bits_status_vs), // @[DMA.scala:218:30]
.io_in_1_bits_status_spp (untranslated_a_bits_status_spp), // @[DMA.scala:218:30]
.io_in_1_bits_status_mpie (untranslated_a_bits_status_mpie), // @[DMA.scala:218:30]
.io_in_1_bits_status_ube (untranslated_a_bits_status_ube), // @[DMA.scala:218:30]
.io_in_1_bits_status_spie (untranslated_a_bits_status_spie), // @[DMA.scala:218:30]
.io_in_1_bits_status_upie (untranslated_a_bits_status_upie), // @[DMA.scala:218:30]
.io_in_1_bits_status_mie (untranslated_a_bits_status_mie), // @[DMA.scala:218:30]
.io_in_1_bits_status_hie (untranslated_a_bits_status_hie), // @[DMA.scala:218:30]
.io_in_1_bits_status_sie (untranslated_a_bits_status_sie), // @[DMA.scala:218:30]
.io_in_1_bits_status_uie (untranslated_a_bits_status_uie), // @[DMA.scala:218:30]
.io_out_valid (_tlb_arb_io_out_valid),
.io_out_bits_tl_a_opcode (_tlb_arb_io_out_bits_tl_a_opcode),
.io_out_bits_tl_a_param (_tlb_arb_io_out_bits_tl_a_param),
.io_out_bits_tl_a_size (_tlb_arb_io_out_bits_tl_a_size),
.io_out_bits_tl_a_source (_tlb_arb_io_out_bits_tl_a_source),
.io_out_bits_tl_a_address (_tlb_arb_io_out_bits_tl_a_address),
.io_out_bits_tl_a_mask (_tlb_arb_io_out_bits_tl_a_mask),
.io_out_bits_tl_a_data (_tlb_arb_io_out_bits_tl_a_data),
.io_out_bits_tl_a_corrupt (_tlb_arb_io_out_bits_tl_a_corrupt),
.io_out_bits_vaddr (_tlb_arb_io_out_bits_vaddr),
.io_out_bits_status_debug (_tlb_arb_io_out_bits_status_debug),
.io_out_bits_status_cease (_tlb_arb_io_out_bits_status_cease),
.io_out_bits_status_wfi (_tlb_arb_io_out_bits_status_wfi),
.io_out_bits_status_isa (_tlb_arb_io_out_bits_status_isa),
.io_out_bits_status_dprv (_tlb_arb_io_out_bits_status_dprv),
.io_out_bits_status_dv (_tlb_arb_io_out_bits_status_dv),
.io_out_bits_status_prv (_tlb_arb_io_out_bits_status_prv),
.io_out_bits_status_v (_tlb_arb_io_out_bits_status_v),
.io_out_bits_status_sd (_tlb_arb_io_out_bits_status_sd),
.io_out_bits_status_zero2 (_tlb_arb_io_out_bits_status_zero2),
.io_out_bits_status_mpv (_tlb_arb_io_out_bits_status_mpv),
.io_out_bits_status_gva (_tlb_arb_io_out_bits_status_gva),
.io_out_bits_status_mbe (_tlb_arb_io_out_bits_status_mbe),
.io_out_bits_status_sbe (_tlb_arb_io_out_bits_status_sbe),
.io_out_bits_status_sxl (_tlb_arb_io_out_bits_status_sxl),
.io_out_bits_status_uxl (_tlb_arb_io_out_bits_status_uxl),
.io_out_bits_status_sd_rv32 (_tlb_arb_io_out_bits_status_sd_rv32),
.io_out_bits_status_zero1 (_tlb_arb_io_out_bits_status_zero1),
.io_out_bits_status_tsr (_tlb_arb_io_out_bits_status_tsr),
.io_out_bits_status_tw (_tlb_arb_io_out_bits_status_tw),
.io_out_bits_status_tvm (_tlb_arb_io_out_bits_status_tvm),
.io_out_bits_status_mxr (_tlb_arb_io_out_bits_status_mxr),
.io_out_bits_status_sum (_tlb_arb_io_out_bits_status_sum),
.io_out_bits_status_mprv (_tlb_arb_io_out_bits_status_mprv),
.io_out_bits_status_xs (_tlb_arb_io_out_bits_status_xs),
.io_out_bits_status_fs (_tlb_arb_io_out_bits_status_fs),
.io_out_bits_status_mpp (_tlb_arb_io_out_bits_status_mpp),
.io_out_bits_status_vs (_tlb_arb_io_out_bits_status_vs),
.io_out_bits_status_spp (_tlb_arb_io_out_bits_status_spp),
.io_out_bits_status_mpie (_tlb_arb_io_out_bits_status_mpie),
.io_out_bits_status_ube (_tlb_arb_io_out_bits_status_ube),
.io_out_bits_status_spie (_tlb_arb_io_out_bits_status_spie),
.io_out_bits_status_upie (_tlb_arb_io_out_bits_status_upie),
.io_out_bits_status_mie (_tlb_arb_io_out_bits_status_mie),
.io_out_bits_status_hie (_tlb_arb_io_out_bits_status_hie),
.io_out_bits_status_sie (_tlb_arb_io_out_bits_status_sie),
.io_out_bits_status_uie (_tlb_arb_io_out_bits_status_uie)
); // @[DMA.scala:226:25]
Queue1_TLBundleAWithInfo tlb_q ( // @[DMA.scala:230:23]
.clock (clock),
.reset (reset),
.io_enq_valid (_tlb_arb_io_out_valid), // @[DMA.scala:226:25]
.io_enq_bits_tl_a_opcode (_tlb_arb_io_out_bits_tl_a_opcode), // @[DMA.scala:226:25]
.io_enq_bits_tl_a_param (_tlb_arb_io_out_bits_tl_a_param), // @[DMA.scala:226:25]
.io_enq_bits_tl_a_size (_tlb_arb_io_out_bits_tl_a_size), // @[DMA.scala:226:25]
.io_enq_bits_tl_a_source (_tlb_arb_io_out_bits_tl_a_source), // @[DMA.scala:226:25]
.io_enq_bits_tl_a_address (_tlb_arb_io_out_bits_tl_a_address), // @[DMA.scala:226:25]
.io_enq_bits_tl_a_mask (_tlb_arb_io_out_bits_tl_a_mask), // @[DMA.scala:226:25]
.io_enq_bits_tl_a_data (_tlb_arb_io_out_bits_tl_a_data), // @[DMA.scala:226:25]
.io_enq_bits_tl_a_corrupt (_tlb_arb_io_out_bits_tl_a_corrupt), // @[DMA.scala:226:25]
.io_enq_bits_vaddr (_tlb_arb_io_out_bits_vaddr), // @[DMA.scala:226:25]
.io_enq_bits_status_debug (_tlb_arb_io_out_bits_status_debug), // @[DMA.scala:226:25]
.io_enq_bits_status_cease (_tlb_arb_io_out_bits_status_cease), // @[DMA.scala:226:25]
.io_enq_bits_status_wfi (_tlb_arb_io_out_bits_status_wfi), // @[DMA.scala:226:25]
.io_enq_bits_status_isa (_tlb_arb_io_out_bits_status_isa), // @[DMA.scala:226:25]
.io_enq_bits_status_dprv (_tlb_arb_io_out_bits_status_dprv), // @[DMA.scala:226:25]
.io_enq_bits_status_dv (_tlb_arb_io_out_bits_status_dv), // @[DMA.scala:226:25]
.io_enq_bits_status_prv (_tlb_arb_io_out_bits_status_prv), // @[DMA.scala:226:25]
.io_enq_bits_status_v (_tlb_arb_io_out_bits_status_v), // @[DMA.scala:226:25]
.io_enq_bits_status_sd (_tlb_arb_io_out_bits_status_sd), // @[DMA.scala:226:25]
.io_enq_bits_status_zero2 (_tlb_arb_io_out_bits_status_zero2), // @[DMA.scala:226:25]
.io_enq_bits_status_mpv (_tlb_arb_io_out_bits_status_mpv), // @[DMA.scala:226:25]
.io_enq_bits_status_gva (_tlb_arb_io_out_bits_status_gva), // @[DMA.scala:226:25]
.io_enq_bits_status_mbe (_tlb_arb_io_out_bits_status_mbe), // @[DMA.scala:226:25]
.io_enq_bits_status_sbe (_tlb_arb_io_out_bits_status_sbe), // @[DMA.scala:226:25]
.io_enq_bits_status_sxl (_tlb_arb_io_out_bits_status_sxl), // @[DMA.scala:226:25]
.io_enq_bits_status_uxl (_tlb_arb_io_out_bits_status_uxl), // @[DMA.scala:226:25]
.io_enq_bits_status_sd_rv32 (_tlb_arb_io_out_bits_status_sd_rv32), // @[DMA.scala:226:25]
.io_enq_bits_status_zero1 (_tlb_arb_io_out_bits_status_zero1), // @[DMA.scala:226:25]
.io_enq_bits_status_tsr (_tlb_arb_io_out_bits_status_tsr), // @[DMA.scala:226:25]
.io_enq_bits_status_tw (_tlb_arb_io_out_bits_status_tw), // @[DMA.scala:226:25]
.io_enq_bits_status_tvm (_tlb_arb_io_out_bits_status_tvm), // @[DMA.scala:226:25]
.io_enq_bits_status_mxr (_tlb_arb_io_out_bits_status_mxr), // @[DMA.scala:226:25]
.io_enq_bits_status_sum (_tlb_arb_io_out_bits_status_sum), // @[DMA.scala:226:25]
.io_enq_bits_status_mprv (_tlb_arb_io_out_bits_status_mprv), // @[DMA.scala:226:25]
.io_enq_bits_status_xs (_tlb_arb_io_out_bits_status_xs), // @[DMA.scala:226:25]
.io_enq_bits_status_fs (_tlb_arb_io_out_bits_status_fs), // @[DMA.scala:226:25]
.io_enq_bits_status_mpp (_tlb_arb_io_out_bits_status_mpp), // @[DMA.scala:226:25]
.io_enq_bits_status_vs (_tlb_arb_io_out_bits_status_vs), // @[DMA.scala:226:25]
.io_enq_bits_status_spp (_tlb_arb_io_out_bits_status_spp), // @[DMA.scala:226:25]
.io_enq_bits_status_mpie (_tlb_arb_io_out_bits_status_mpie), // @[DMA.scala:226:25]
.io_enq_bits_status_ube (_tlb_arb_io_out_bits_status_ube), // @[DMA.scala:226:25]
.io_enq_bits_status_spie (_tlb_arb_io_out_bits_status_spie), // @[DMA.scala:226:25]
.io_enq_bits_status_upie (_tlb_arb_io_out_bits_status_upie), // @[DMA.scala:226:25]
.io_enq_bits_status_mie (_tlb_arb_io_out_bits_status_mie), // @[DMA.scala:226:25]
.io_enq_bits_status_hie (_tlb_arb_io_out_bits_status_hie), // @[DMA.scala:226:25]
.io_enq_bits_status_sie (_tlb_arb_io_out_bits_status_sie), // @[DMA.scala:226:25]
.io_enq_bits_status_uie (_tlb_arb_io_out_bits_status_uie), // @[DMA.scala:226:25]
.io_deq_valid (_tlb_q_io_deq_valid),
.io_deq_bits_tl_a_opcode (_tlb_q_io_deq_bits_tl_a_opcode),
.io_deq_bits_tl_a_param (_tlb_q_io_deq_bits_tl_a_param),
.io_deq_bits_tl_a_size (_tlb_q_io_deq_bits_tl_a_size),
.io_deq_bits_tl_a_source (_tlb_q_io_deq_bits_tl_a_source),
.io_deq_bits_tl_a_address (_tlb_q_io_deq_bits_tl_a_address),
.io_deq_bits_tl_a_mask (_tlb_q_io_deq_bits_tl_a_mask),
.io_deq_bits_tl_a_data (_tlb_q_io_deq_bits_tl_a_data),
.io_deq_bits_tl_a_corrupt (_tlb_q_io_deq_bits_tl_a_corrupt),
.io_deq_bits_vaddr (_tlb_q_io_deq_bits_vaddr),
.io_deq_bits_status_debug (_tlb_q_io_deq_bits_status_debug),
.io_deq_bits_status_cease (_tlb_q_io_deq_bits_status_cease),
.io_deq_bits_status_wfi (_tlb_q_io_deq_bits_status_wfi),
.io_deq_bits_status_isa (_tlb_q_io_deq_bits_status_isa),
.io_deq_bits_status_dprv (_tlb_q_io_deq_bits_status_dprv),
.io_deq_bits_status_dv (_tlb_q_io_deq_bits_status_dv),
.io_deq_bits_status_prv (_tlb_q_io_deq_bits_status_prv),
.io_deq_bits_status_v (_tlb_q_io_deq_bits_status_v),
.io_deq_bits_status_sd (_tlb_q_io_deq_bits_status_sd),
.io_deq_bits_status_zero2 (_tlb_q_io_deq_bits_status_zero2),
.io_deq_bits_status_mpv (_tlb_q_io_deq_bits_status_mpv),
.io_deq_bits_status_gva (_tlb_q_io_deq_bits_status_gva),
.io_deq_bits_status_mbe (_tlb_q_io_deq_bits_status_mbe),
.io_deq_bits_status_sbe (_tlb_q_io_deq_bits_status_sbe),
.io_deq_bits_status_sxl (_tlb_q_io_deq_bits_status_sxl),
.io_deq_bits_status_uxl (_tlb_q_io_deq_bits_status_uxl),
.io_deq_bits_status_sd_rv32 (_tlb_q_io_deq_bits_status_sd_rv32),
.io_deq_bits_status_zero1 (_tlb_q_io_deq_bits_status_zero1),
.io_deq_bits_status_tsr (_tlb_q_io_deq_bits_status_tsr),
.io_deq_bits_status_tw (_tlb_q_io_deq_bits_status_tw),
.io_deq_bits_status_tvm (_tlb_q_io_deq_bits_status_tvm),
.io_deq_bits_status_mxr (_tlb_q_io_deq_bits_status_mxr),
.io_deq_bits_status_sum (_tlb_q_io_deq_bits_status_sum),
.io_deq_bits_status_mprv (_tlb_q_io_deq_bits_status_mprv),
.io_deq_bits_status_xs (_tlb_q_io_deq_bits_status_xs),
.io_deq_bits_status_fs (_tlb_q_io_deq_bits_status_fs),
.io_deq_bits_status_mpp (_tlb_q_io_deq_bits_status_mpp),
.io_deq_bits_status_vs (_tlb_q_io_deq_bits_status_vs),
.io_deq_bits_status_spp (_tlb_q_io_deq_bits_status_spp),
.io_deq_bits_status_mpie (_tlb_q_io_deq_bits_status_mpie),
.io_deq_bits_status_ube (_tlb_q_io_deq_bits_status_ube),
.io_deq_bits_status_spie (_tlb_q_io_deq_bits_status_spie),
.io_deq_bits_status_upie (_tlb_q_io_deq_bits_status_upie),
.io_deq_bits_status_mie (_tlb_q_io_deq_bits_status_mie),
.io_deq_bits_status_hie (_tlb_q_io_deq_bits_status_hie),
.io_deq_bits_status_sie (_tlb_q_io_deq_bits_status_sie),
.io_deq_bits_status_uie (_tlb_q_io_deq_bits_status_uie)
); // @[DMA.scala:230:23]
assign io_tlb_req_valid_0 = _tlb_q_io_deq_valid; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_debug_0 = _tlb_q_io_deq_bits_status_debug; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_cease_0 = _tlb_q_io_deq_bits_status_cease; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_wfi_0 = _tlb_q_io_deq_bits_status_wfi; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_isa_0 = _tlb_q_io_deq_bits_status_isa; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_dprv_0 = _tlb_q_io_deq_bits_status_dprv; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_dv_0 = _tlb_q_io_deq_bits_status_dv; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_prv_0 = _tlb_q_io_deq_bits_status_prv; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_v_0 = _tlb_q_io_deq_bits_status_v; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_sd_0 = _tlb_q_io_deq_bits_status_sd; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_zero2_0 = _tlb_q_io_deq_bits_status_zero2; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_mpv_0 = _tlb_q_io_deq_bits_status_mpv; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_gva_0 = _tlb_q_io_deq_bits_status_gva; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_mbe_0 = _tlb_q_io_deq_bits_status_mbe; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_sbe_0 = _tlb_q_io_deq_bits_status_sbe; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_sxl_0 = _tlb_q_io_deq_bits_status_sxl; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_uxl_0 = _tlb_q_io_deq_bits_status_uxl; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_sd_rv32_0 = _tlb_q_io_deq_bits_status_sd_rv32; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_zero1_0 = _tlb_q_io_deq_bits_status_zero1; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_tsr_0 = _tlb_q_io_deq_bits_status_tsr; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_tw_0 = _tlb_q_io_deq_bits_status_tw; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_tvm_0 = _tlb_q_io_deq_bits_status_tvm; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_mxr_0 = _tlb_q_io_deq_bits_status_mxr; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_sum_0 = _tlb_q_io_deq_bits_status_sum; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_mprv_0 = _tlb_q_io_deq_bits_status_mprv; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_xs_0 = _tlb_q_io_deq_bits_status_xs; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_fs_0 = _tlb_q_io_deq_bits_status_fs; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_mpp_0 = _tlb_q_io_deq_bits_status_mpp; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_vs_0 = _tlb_q_io_deq_bits_status_vs; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_spp_0 = _tlb_q_io_deq_bits_status_spp; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_mpie_0 = _tlb_q_io_deq_bits_status_mpie; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_ube_0 = _tlb_q_io_deq_bits_status_ube; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_spie_0 = _tlb_q_io_deq_bits_status_spie; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_upie_0 = _tlb_q_io_deq_bits_status_upie; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_mie_0 = _tlb_q_io_deq_bits_status_mie; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_hie_0 = _tlb_q_io_deq_bits_status_hie; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_sie_0 = _tlb_q_io_deq_bits_status_sie; // @[DMA.scala:138:9, :230:23]
assign io_tlb_req_bits_status_uie_0 = _tlb_q_io_deq_bits_status_uie; // @[DMA.scala:138:9, :230:23]
Queue1_TLBundleAWithInfo_1 translate_q ( // @[DMA.scala:241:29]
.clock (clock),
.reset (reset),
.io_enq_valid (_tlb_q_io_deq_valid), // @[DMA.scala:230:23]
.io_enq_bits_tl_a_opcode (_tlb_q_io_deq_bits_tl_a_opcode), // @[DMA.scala:230:23]
.io_enq_bits_tl_a_param (_tlb_q_io_deq_bits_tl_a_param), // @[DMA.scala:230:23]
.io_enq_bits_tl_a_size (_tlb_q_io_deq_bits_tl_a_size), // @[DMA.scala:230:23]
.io_enq_bits_tl_a_source (_tlb_q_io_deq_bits_tl_a_source), // @[DMA.scala:230:23]
.io_enq_bits_tl_a_address (_tlb_q_io_deq_bits_tl_a_address), // @[DMA.scala:230:23]
.io_enq_bits_tl_a_mask (_tlb_q_io_deq_bits_tl_a_mask), // @[DMA.scala:230:23]
.io_enq_bits_tl_a_data (_tlb_q_io_deq_bits_tl_a_data), // @[DMA.scala:230:23]
.io_enq_bits_tl_a_corrupt (_tlb_q_io_deq_bits_tl_a_corrupt), // @[DMA.scala:230:23]
.io_enq_bits_vaddr (_tlb_q_io_deq_bits_vaddr), // @[DMA.scala:230:23]
.io_enq_bits_status_debug (_tlb_q_io_deq_bits_status_debug), // @[DMA.scala:230:23]
.io_enq_bits_status_cease (_tlb_q_io_deq_bits_status_cease), // @[DMA.scala:230:23]
.io_enq_bits_status_wfi (_tlb_q_io_deq_bits_status_wfi), // @[DMA.scala:230:23]
.io_enq_bits_status_isa (_tlb_q_io_deq_bits_status_isa), // @[DMA.scala:230:23]
.io_enq_bits_status_dprv (_tlb_q_io_deq_bits_status_dprv), // @[DMA.scala:230:23]
.io_enq_bits_status_dv (_tlb_q_io_deq_bits_status_dv), // @[DMA.scala:230:23]
.io_enq_bits_status_prv (_tlb_q_io_deq_bits_status_prv), // @[DMA.scala:230:23]
.io_enq_bits_status_v (_tlb_q_io_deq_bits_status_v), // @[DMA.scala:230:23]
.io_enq_bits_status_sd (_tlb_q_io_deq_bits_status_sd), // @[DMA.scala:230:23]
.io_enq_bits_status_zero2 (_tlb_q_io_deq_bits_status_zero2), // @[DMA.scala:230:23]
.io_enq_bits_status_mpv (_tlb_q_io_deq_bits_status_mpv), // @[DMA.scala:230:23]
.io_enq_bits_status_gva (_tlb_q_io_deq_bits_status_gva), // @[DMA.scala:230:23]
.io_enq_bits_status_mbe (_tlb_q_io_deq_bits_status_mbe), // @[DMA.scala:230:23]
.io_enq_bits_status_sbe (_tlb_q_io_deq_bits_status_sbe), // @[DMA.scala:230:23]
.io_enq_bits_status_sxl (_tlb_q_io_deq_bits_status_sxl), // @[DMA.scala:230:23]
.io_enq_bits_status_uxl (_tlb_q_io_deq_bits_status_uxl), // @[DMA.scala:230:23]
.io_enq_bits_status_sd_rv32 (_tlb_q_io_deq_bits_status_sd_rv32), // @[DMA.scala:230:23]
.io_enq_bits_status_zero1 (_tlb_q_io_deq_bits_status_zero1), // @[DMA.scala:230:23]
.io_enq_bits_status_tsr (_tlb_q_io_deq_bits_status_tsr), // @[DMA.scala:230:23]
.io_enq_bits_status_tw (_tlb_q_io_deq_bits_status_tw), // @[DMA.scala:230:23]
.io_enq_bits_status_tvm (_tlb_q_io_deq_bits_status_tvm), // @[DMA.scala:230:23]
.io_enq_bits_status_mxr (_tlb_q_io_deq_bits_status_mxr), // @[DMA.scala:230:23]
.io_enq_bits_status_sum (_tlb_q_io_deq_bits_status_sum), // @[DMA.scala:230:23]
.io_enq_bits_status_mprv (_tlb_q_io_deq_bits_status_mprv), // @[DMA.scala:230:23]
.io_enq_bits_status_xs (_tlb_q_io_deq_bits_status_xs), // @[DMA.scala:230:23]
.io_enq_bits_status_fs (_tlb_q_io_deq_bits_status_fs), // @[DMA.scala:230:23]
.io_enq_bits_status_mpp (_tlb_q_io_deq_bits_status_mpp), // @[DMA.scala:230:23]
.io_enq_bits_status_vs (_tlb_q_io_deq_bits_status_vs), // @[DMA.scala:230:23]
.io_enq_bits_status_spp (_tlb_q_io_deq_bits_status_spp), // @[DMA.scala:230:23]
.io_enq_bits_status_mpie (_tlb_q_io_deq_bits_status_mpie), // @[DMA.scala:230:23]
.io_enq_bits_status_ube (_tlb_q_io_deq_bits_status_ube), // @[DMA.scala:230:23]
.io_enq_bits_status_spie (_tlb_q_io_deq_bits_status_spie), // @[DMA.scala:230:23]
.io_enq_bits_status_upie (_tlb_q_io_deq_bits_status_upie), // @[DMA.scala:230:23]
.io_enq_bits_status_mie (_tlb_q_io_deq_bits_status_mie), // @[DMA.scala:230:23]
.io_enq_bits_status_hie (_tlb_q_io_deq_bits_status_hie), // @[DMA.scala:230:23]
.io_enq_bits_status_sie (_tlb_q_io_deq_bits_status_sie), // @[DMA.scala:230:23]
.io_enq_bits_status_uie (_tlb_q_io_deq_bits_status_uie), // @[DMA.scala:230:23]
.io_deq_valid (_translate_q_io_deq_valid),
.io_deq_bits_tl_a_opcode (_translate_q_io_deq_bits_tl_a_opcode),
.io_deq_bits_tl_a_param (_translate_q_io_deq_bits_tl_a_param),
.io_deq_bits_tl_a_size (_translate_q_io_deq_bits_tl_a_size),
.io_deq_bits_tl_a_source (_translate_q_io_deq_bits_tl_a_source),
.io_deq_bits_tl_a_address (retry_a_bits_tl_a_address),
.io_deq_bits_tl_a_mask (_translate_q_io_deq_bits_tl_a_mask),
.io_deq_bits_tl_a_data (_translate_q_io_deq_bits_tl_a_data),
.io_deq_bits_tl_a_corrupt (_translate_q_io_deq_bits_tl_a_corrupt),
.io_deq_bits_vaddr (retry_a_bits_vaddr),
.io_deq_bits_status_debug (retry_a_bits_status_debug),
.io_deq_bits_status_cease (retry_a_bits_status_cease),
.io_deq_bits_status_wfi (retry_a_bits_status_wfi),
.io_deq_bits_status_isa (retry_a_bits_status_isa),
.io_deq_bits_status_dprv (retry_a_bits_status_dprv),
.io_deq_bits_status_dv (retry_a_bits_status_dv),
.io_deq_bits_status_prv (retry_a_bits_status_prv),
.io_deq_bits_status_v (retry_a_bits_status_v),
.io_deq_bits_status_sd (retry_a_bits_status_sd),
.io_deq_bits_status_zero2 (retry_a_bits_status_zero2),
.io_deq_bits_status_mpv (retry_a_bits_status_mpv),
.io_deq_bits_status_gva (retry_a_bits_status_gva),
.io_deq_bits_status_mbe (retry_a_bits_status_mbe),
.io_deq_bits_status_sbe (retry_a_bits_status_sbe),
.io_deq_bits_status_sxl (retry_a_bits_status_sxl),
.io_deq_bits_status_uxl (retry_a_bits_status_uxl),
.io_deq_bits_status_sd_rv32 (retry_a_bits_status_sd_rv32),
.io_deq_bits_status_zero1 (retry_a_bits_status_zero1),
.io_deq_bits_status_tsr (retry_a_bits_status_tsr),
.io_deq_bits_status_tw (retry_a_bits_status_tw),
.io_deq_bits_status_tvm (retry_a_bits_status_tvm),
.io_deq_bits_status_mxr (retry_a_bits_status_mxr),
.io_deq_bits_status_sum (retry_a_bits_status_sum),
.io_deq_bits_status_mprv (retry_a_bits_status_mprv),
.io_deq_bits_status_xs (retry_a_bits_status_xs),
.io_deq_bits_status_fs (retry_a_bits_status_fs),
.io_deq_bits_status_mpp (retry_a_bits_status_mpp),
.io_deq_bits_status_vs (retry_a_bits_status_vs),
.io_deq_bits_status_spp (retry_a_bits_status_spp),
.io_deq_bits_status_mpie (retry_a_bits_status_mpie),
.io_deq_bits_status_ube (retry_a_bits_status_ube),
.io_deq_bits_status_spie (retry_a_bits_status_spie),
.io_deq_bits_status_upie (retry_a_bits_status_upie),
.io_deq_bits_status_mie (retry_a_bits_status_mie),
.io_deq_bits_status_hie (retry_a_bits_status_hie),
.io_deq_bits_status_sie (retry_a_bits_status_sie),
.io_deq_bits_status_uie (retry_a_bits_status_uie)
); // @[DMA.scala:241:29]
assign nodeOut_a_bits_opcode = _translate_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:241:29]
assign nodeOut_a_bits_param = _translate_q_io_deq_bits_tl_a_param; // @[DMA.scala:241:29]
assign nodeOut_a_bits_size = _translate_q_io_deq_bits_tl_a_size; // @[DMA.scala:241:29]
assign nodeOut_a_bits_source = _translate_q_io_deq_bits_tl_a_source; // @[DMA.scala:241:29]
assign nodeOut_a_bits_mask = _translate_q_io_deq_bits_tl_a_mask; // @[DMA.scala:241:29]
assign nodeOut_a_bits_data = _translate_q_io_deq_bits_tl_a_data; // @[DMA.scala:241:29]
assign nodeOut_a_bits_corrupt = _translate_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:241:29]
assign retry_a_bits_tl_a_opcode = _translate_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:225:23, :241:29]
assign retry_a_bits_tl_a_param = _translate_q_io_deq_bits_tl_a_param; // @[DMA.scala:225:23, :241:29]
assign retry_a_bits_tl_a_size = _translate_q_io_deq_bits_tl_a_size; // @[DMA.scala:225:23, :241:29]
assign retry_a_bits_tl_a_source = _translate_q_io_deq_bits_tl_a_source; // @[DMA.scala:225:23, :241:29]
assign retry_a_bits_tl_a_mask = _translate_q_io_deq_bits_tl_a_mask; // @[DMA.scala:225:23, :241:29]
assign retry_a_bits_tl_a_data = _translate_q_io_deq_bits_tl_a_data; // @[DMA.scala:225:23, :241:29]
assign retry_a_bits_tl_a_corrupt = _translate_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:225:23, :241:29]
assign auto_out_a_valid = auto_out_a_valid_0; // @[DMA.scala:138:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[DMA.scala:138:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[DMA.scala:138:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[DMA.scala:138:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[DMA.scala:138:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[DMA.scala:138:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[DMA.scala:138:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[DMA.scala:138:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[DMA.scala:138:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[DMA.scala:138:9]
assign io_req_ready = io_req_ready_0; // @[DMA.scala:138:9]
assign io_reserve_valid = io_reserve_valid_0; // @[DMA.scala:138:9]
assign io_reserve_entry_shift = io_reserve_entry_shift_0; // @[DMA.scala:138:9]
assign io_reserve_entry_addr = io_reserve_entry_addr_0; // @[DMA.scala:138:9]
assign io_reserve_entry_is_acc = io_reserve_entry_is_acc_0; // @[DMA.scala:138:9]
assign io_reserve_entry_accumulate = io_reserve_entry_accumulate_0; // @[DMA.scala:138:9]
assign io_reserve_entry_has_acc_bitwidth = io_reserve_entry_has_acc_bitwidth_0; // @[DMA.scala:138:9]
assign io_reserve_entry_scale = io_reserve_entry_scale_0; // @[DMA.scala:138:9]
assign io_reserve_entry_repeats = io_reserve_entry_repeats_0; // @[DMA.scala:138:9]
assign io_reserve_entry_pixel_repeats = io_reserve_entry_pixel_repeats_0; // @[DMA.scala:138:9]
assign io_reserve_entry_len = io_reserve_entry_len_0; // @[DMA.scala:138:9]
assign io_reserve_entry_block_stride = io_reserve_entry_block_stride_0; // @[DMA.scala:138:9]
assign io_reserve_entry_spad_row_offset = io_reserve_entry_spad_row_offset_0; // @[DMA.scala:138:9]
assign io_reserve_entry_bytes_to_read = io_reserve_entry_bytes_to_read_0; // @[DMA.scala:138:9]
assign io_reserve_entry_cmd_id = io_reserve_entry_cmd_id_0; // @[DMA.scala:138:9]
assign io_beatData_valid = io_beatData_valid_0; // @[DMA.scala:138:9]
assign io_beatData_bits_xactid = io_beatData_bits_xactid_0; // @[DMA.scala:138:9]
assign io_beatData_bits_data = io_beatData_bits_data_0; // @[DMA.scala:138:9]
assign io_beatData_bits_lg_len_req = io_beatData_bits_lg_len_req_0; // @[DMA.scala:138:9]
assign io_beatData_bits_last = io_beatData_bits_last_0; // @[DMA.scala:138:9]
assign io_tlb_req_valid = io_tlb_req_valid_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_tlb_req_vaddr = io_tlb_req_bits_tlb_req_vaddr_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_debug = io_tlb_req_bits_status_debug_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_cease = io_tlb_req_bits_status_cease_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_wfi = io_tlb_req_bits_status_wfi_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_isa = io_tlb_req_bits_status_isa_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_dprv = io_tlb_req_bits_status_dprv_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_dv = io_tlb_req_bits_status_dv_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_prv = io_tlb_req_bits_status_prv_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_v = io_tlb_req_bits_status_v_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_sd = io_tlb_req_bits_status_sd_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_zero2 = io_tlb_req_bits_status_zero2_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_mpv = io_tlb_req_bits_status_mpv_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_gva = io_tlb_req_bits_status_gva_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_mbe = io_tlb_req_bits_status_mbe_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_sbe = io_tlb_req_bits_status_sbe_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_sxl = io_tlb_req_bits_status_sxl_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_uxl = io_tlb_req_bits_status_uxl_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_sd_rv32 = io_tlb_req_bits_status_sd_rv32_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_zero1 = io_tlb_req_bits_status_zero1_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_tsr = io_tlb_req_bits_status_tsr_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_tw = io_tlb_req_bits_status_tw_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_tvm = io_tlb_req_bits_status_tvm_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_mxr = io_tlb_req_bits_status_mxr_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_sum = io_tlb_req_bits_status_sum_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_mprv = io_tlb_req_bits_status_mprv_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_xs = io_tlb_req_bits_status_xs_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_fs = io_tlb_req_bits_status_fs_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_mpp = io_tlb_req_bits_status_mpp_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_vs = io_tlb_req_bits_status_vs_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_spp = io_tlb_req_bits_status_spp_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_mpie = io_tlb_req_bits_status_mpie_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_ube = io_tlb_req_bits_status_ube_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_spie = io_tlb_req_bits_status_spie_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_upie = io_tlb_req_bits_status_upie_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_mie = io_tlb_req_bits_status_mie_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_hie = io_tlb_req_bits_status_hie_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_sie = io_tlb_req_bits_status_sie_0; // @[DMA.scala:138:9]
assign io_tlb_req_bits_status_uie = io_tlb_req_bits_status_uie_0; // @[DMA.scala:138:9]
assign io_counter_event_signal_18 = io_counter_event_signal_18_0; // @[DMA.scala:138:9]
assign io_counter_event_signal_19 = io_counter_event_signal_19_0; // @[DMA.scala:138:9]
assign io_counter_event_signal_20 = io_counter_event_signal_20_0; // @[DMA.scala:138:9]
assign io_counter_external_values_4 = io_counter_external_values_4_0; // @[DMA.scala:138:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File BootROM.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketchip.resources.{Resource, SimpleDevice}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
import java.nio.ByteBuffer
import java.nio.file.{Files, Paths}
/** Size, location and contents of the boot rom. */
case class BootROMParams(
address: BigInt = 0x10000,
size: Int = 0x10000,
hang: BigInt = 0x10040, // The hang parameter is used as the power-on reset vector
contentFileName: String)
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
{
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = List(AddressSet(base, size-1)),
resources = resources,
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0))),
beatBytes = beatBytes)))
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val contents = contentsDelayed
val wrapSize = 1 << log2Ceil(contents.size)
require (wrapSize <= size)
val (in, edge) = node.in(0)
val words = (contents ++ Seq.fill(wrapSize-contents.size)(0.toByte)).grouped(beatBytes).toSeq
val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8})
val rom = VecInit(bigs.map(_.U((8*beatBytes).W)))
in.d.valid := in.a.valid
in.a.ready := in.d.ready
val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
val high = if (wrapSize == size) 0.U else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
in.d.bits := edge.AccessAck(in.a.bits, Mux(high.orR, 0.U, rom(index)))
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}
case class BootROMLocated(loc: HierarchicalLocation) extends Field[Option[BootROMParams]](None)
object BootROM {
/** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect
* at a configurable location, but also drives the tiles' reset vectors to point
* at its 'hang' address parameter value.
*/
def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
(implicit p: Parameters): TLROM = {
val tlbus = subsystem.locateTLBusWrapper(where)
val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")
val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
lazy val contents = {
val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
val rom = ByteBuffer.wrap(romdata)
rom.array() ++ subsystem.dtb.contents
}
val bootrom = bootROMDomainWrapper {
LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
}
bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus, Some("BootROM")) := _ }
// Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
InModuleBody {
val reset_vector_source = bootROMResetVectorSourceNode.bundle
require(reset_vector_source.getWidth >= params.hang.bitLength,
s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
bootROMResetVectorSourceNode.bundle := params.hang.U
}
bootrom
}
}
| module TLROM( // @[BootROM.scala:41:9]
input clock, // @[BootROM.scala:41:9]
input reset, // @[BootROM.scala:41:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9]
wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9]
wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9]
wire [511:0][63:0] _GEN =
'{64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h7374,
64'h7075727265746E69,
64'h746E657261702D,
64'h747075727265746E,
64'h6900736B636F6C63,
64'h7665646E2C7663,
64'h7369720079746972,
64'h6F6972702D78616D,
64'h2C76637369720068,
64'h63617474612D6775,
64'h626564006465646E,
64'h657478652D737470,
64'h75727265746E6900,
64'h73656D616E2D7475,
64'h7074756F2D6B636F,
64'h6C6300736C6C6563,
64'h2D6B636F6C632300,
64'h73656D616E2D6765,
64'h72007365676E6172,
64'h656C646E616870,
64'h72656C6C6F7274,
64'h6E6F632D74707572,
64'h7265746E6900736C,
64'h6C65632D74707572,
64'h7265746E69230073,
64'h7574617473006D69,
64'h74642C6576696669,
64'h7300736E6F696765,
64'h72706D702C766373,
64'h6972007974697261,
64'h6C756E617267706D,
64'h702C766373697200,
64'h6173692C76637369,
64'h720067657200657A,
64'h69732D6568636163,
64'h2D6900737465732D,
64'h65686361632D6900,
64'h657A69732D6B636F,
64'h6C622D6568636163,
64'h2D6900746E756F63,
64'h2D746E696F706B61,
64'h6572622D63657865,
64'h2D65726177647261,
64'h6800657079745F65,
64'h6369766564007963,
64'h6E6575716572662D,
64'h6B636F6C63007963,
64'h6E6575716572662D,
64'h65736162656D6974,
64'h687461702D7475,
64'h6F64747300306C61,
64'h69726573006C6564,
64'h6F6D00656C626974,
64'h61706D6F6300736C,
64'h6C65632D657A6973,
64'h2300736C6C65632D,
64'h7373657264646123,
64'h900000002000000,
64'h200000002000000,
64'h6C6F72746E6F63,
64'h3701000008000000,
64'h300000000100000,
64'h1100BB000000,
64'h800000003000000,
64'h30303030,
64'h3131407265747465,
64'h732D74657365722D,
64'h656C697401000000,
64'h2000000006C6F72,
64'h746E6F6337010000,
64'h800000003000000,
64'h10000000000210,
64'hBB00000008000000,
64'h300000001000000,
64'hB801000004000000,
64'h300000004000000,
64'hA701000004000000,
64'h300000000000000,
64'h30747261752C6576,
64'h696669731B000000,
64'hD00000003000000,
64'h3000000A0010000,
64'h400000003000000,
64'h30303030323030,
64'h31406C6169726573,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h737562734E010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'h41010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375627301000000,
64'h2000000006D656D,
64'h3701000004000000,
64'h300000000000100,
64'h100BB000000,
64'h800000003000000,
64'h306D6F722C6576,
64'h696669731B000000,
64'hC00000003000000,
64'h3030303031,
64'h406D6F7201000000,
64'h200000003000000,
64'h2801000004000000,
64'h3000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'h4E0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'h4101000004000000,
64'h300000000006B63,
64'h6F6C635F73756270,
64'h100000002000000,
64'h2000000060,
64'h6030010000,
64'hC00000003000000,
64'h7375622D656C,
64'h706D69731B000000,
64'hB00000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h30303030303030,
64'h3640346978612D74,
64'h726F702D6F696D6D,
64'h100000002000000,
64'h400000028010000,
64'h400000003000000,
64'h100000095010000,
64'h400000003000000,
64'h100000082010000,
64'h400000003000000,
64'h6C6F72746E6F63,
64'h3701000008000000,
64'h300000000000004,
64'hCBB000000,
64'h800000003000000,
64'hB00000002000000,
64'h6101000008000000,
64'h300000013010000,
64'h3000000,
64'h3063696C702C76,
64'h637369721B000000,
64'hC00000003000000,
64'h100000002010000,
64'h400000003000000,
64'h30303030,
64'h3030634072656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h737562664E010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'h41010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375626601000000,
64'h200000000100000,
64'h300000BB000000,
64'h800000003000000,
64'h30726F7272,
64'h652C657669666973,
64'h1B0000000E000000,
64'h300000000000030,
64'h3030334065636976,
64'h65642D726F727265,
64'h100000002000000,
64'h100000028010000,
64'h400000003000000,
64'h6D656D37010000,
64'h400000003000000,
64'h40000000000080,
64'hBB00000008000000,
64'h300000000000000,
64'h306D6974642C6576,
64'h696669731B000000,
64'hD00000003000000,
64'h3030303030,
64'h303038406D697464,
64'h100000002000000,
64'h6C6F72746E6F63,
64'h3701000008000000,
64'h300000000100000,
64'hBB000000,
64'h800000003000000,
64'hFFFF000002000000,
64'h6101000008000000,
64'h300000000000000,
64'h6761746A75010000,
64'h500000003000000,
64'h3331302D,
64'h67756265642C7663,
64'h736972003331302D,
64'h67756265642C6576,
64'h696669731B000000,
64'h2100000003000000,
64'h304072656C6C,
64'h6F72746E6F632D67,
64'h7562656401000000,
64'h2000000006C6F72,
64'h746E6F6337010000,
64'h800000003000000,
64'h10000000001000,
64'hBB00000008000000,
64'h300000000003030,
64'h3030303140726574,
64'h61672D6B636F6C63,
64'h100000002000000,
64'h6C6F72746E6F63,
64'h3701000008000000,
64'h300000000000100,
64'h2BB000000,
64'h800000003000000,
64'h700000002000000,
64'h300000002000000,
64'h6101000010000000,
64'h300000000000000,
64'h30746E696C632C76,
64'h637369721B000000,
64'hD00000003000000,
64'h3030303030,
64'h303240746E696C63,
64'h100000002000000,
64'h6B636F6C632D64,
64'h657869661B000000,
64'hC00000003000000,
64'h6B636F6C635F,
64'h737562634E010000,
64'hB00000003000000,
64'h65CD1D53000000,
64'h400000003000000,
64'h41010000,
64'h400000003000000,
64'h6B636F6C635F,
64'h7375626301000000,
64'h2000000006C6F72,
64'h746E6F6337010000,
64'h800000003000000,
64'h10000000100000,
64'hBB00000008000000,
64'h300000000000030,
64'h303031406765722D,
64'h737365726464612D,
64'h746F6F6201000000,
64'h3001000000000000,
64'h300000000737562,
64'h2D656C706D697300,
64'h636F732D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h2000000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h636F7301000000,
64'h200000000000030,
64'h666974682C626375,
64'h1B0000000A000000,
64'h300000000000000,
64'h6669746801000000,
64'h200000002000000,
64'h200000002000000,
64'h2801000004000000,
64'h300000013010000,
64'h3000000,
64'h63746E692D75,
64'h70632C7663736972,
64'h1B0000000F000000,
64'h300000001000000,
64'h201000004000000,
64'h300000000000000,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6901000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'hFB00000005000000,
64'h300000001000000,
64'hEF00000004000000,
64'h300000008000000,
64'hDE00000004000000,
64'h300000004000000,
64'hC900000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h34367672BF000000,
64'h3800000003000000,
64'hBB000000,
64'h400000003000000,
64'h800000AE000000,
64'h400000003000000,
64'h40000000A1000000,
64'h400000003000000,
64'h400000008E000000,
64'h400000003000000,
64'h10000006F000000,
64'h400000003000000,
64'h75706363000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000030,
64'h4075706301000000,
64'h20A1070040000000,
64'h400000003000000,
64'hF000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h73757063,
64'h100000002000000,
64'h30303030,
64'h32303031406C6169,
64'h7265732F636F732F,
64'h3400000015000000,
64'h300000000006E65,
64'h736F686301000000,
64'h200000000000000,
64'h3030303032303031,
64'h406C61697265732F,
64'h636F732F2C000000,
64'h1500000003000000,
64'h73657361696C61,
64'h100000000000000,
64'h6472617970696863,
64'h2C7261622D626375,
64'h2600000011000000,
64'h300000000000000,
64'h7665642D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h1500000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h1000000,
64'h0,
64'h0,
64'hA0090000C3010000,
64'h10000000,
64'h1100000028000000,
64'hD809000038000000,
64'h9B0B0000EDFE0DD0,
64'h1330200073,
64'h3006307308000613,
64'h185859300000597,
64'hF140257334151073,
64'h5350300001537,
64'h5A02300B505B3,
64'h251513FE029EE3,
64'h5A283F81FF06F,
64'h0,
64'h0,
64'h2C0006F,
64'hFE069AE3FFC62683,
64'h46061300D62023,
64'h10069300458613,
64'h380006F00050463,
64'hF1402573020005B7,
64'hFFDFF06F,
64'h1050007330052073,
64'h3045107300800513,
64'h3445307322200513,
64'h3030107300028863,
64'h12F2934122D293,
64'h301022F330551073,
64'h405051300000517};
wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22]
wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22]
wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22]
wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22]
wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22]
wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22]
wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22]
wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22]
wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22]
wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22]
wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22]
wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22]
wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22]
wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22]
wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22]
wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22]
wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22]
wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22]
wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22]
wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22]
wire [63:0] rom_24 = 64'h9B0B0000EDFE0DD0; // @[BootROM.scala:50:22]
wire [63:0] rom_25 = 64'hD809000038000000; // @[BootROM.scala:50:22]
wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22]
wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22]
wire [63:0] rom_28 = 64'hA0090000C3010000; // @[BootROM.scala:50:22]
wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22]
wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22]
wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22]
wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22]
wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22]
wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22]
wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22]
wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22]
wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22]
wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_69 = 64'h1B00000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_70 = 64'h722C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_71 = 64'h72003074656B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_72 = 64'h76637369; // @[BootROM.scala:50:22]
wire [63:0] rom_74 = 64'h75706363000000; // @[BootROM.scala:50:22]
wire [63:0] rom_76 = 64'h10000006F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_78 = 64'h400000008E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_80 = 64'h40000000A1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_82 = 64'h800000AE000000; // @[BootROM.scala:50:22]
wire [63:0] rom_85 = 64'h3800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_86 = 64'h34367672BF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_87 = 64'h7A62636466616D69; // @[BootROM.scala:50:22]
wire [63:0] rom_88 = 64'h66697A5F72736369; // @[BootROM.scala:50:22]
wire [63:0] rom_89 = 64'h697A5F6965636E65; // @[BootROM.scala:50:22]
wire [63:0] rom_90 = 64'h5F68667A5F6D7068; // @[BootROM.scala:50:22]
wire [63:0] rom_91 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22]
wire [63:0] rom_92 = 64'h636F72785F73627A; // @[BootROM.scala:50:22]
wire [63:0] rom_93 = 64'h30000000074656B; // @[BootROM.scala:50:22]
wire [63:0] rom_94 = 64'hC900000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_96 = 64'hDE00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_97 = 64'h300000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_98 = 64'hEF00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_100 = 64'hFB00000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_101 = 64'h79616B6F; // @[BootROM.scala:50:22]
wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_103 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_104 = 64'h65746E6901000000; // @[BootROM.scala:50:22]
wire [63:0] rom_105 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_106 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_108 = 64'h201000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_110 = 64'h1B0000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_111 = 64'h70632C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_112 = 64'h63746E692D75; // @[BootROM.scala:50:22]
wire [63:0] rom_118 = 64'h6669746801000000; // @[BootROM.scala:50:22]
wire [63:0] rom_120 = 64'h1B0000000A000000; // @[BootROM.scala:50:22]
wire [63:0] rom_121 = 64'h666974682C626375; // @[BootROM.scala:50:22]
wire [63:0] rom_122 = 64'h200000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_123 = 64'h636F7301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_128 = 64'h2000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_129 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_130 = 64'h706968632C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_131 = 64'h636F732D64726179; // @[BootROM.scala:50:22]
wire [63:0] rom_132 = 64'h2D656C706D697300; // @[BootROM.scala:50:22]
wire [63:0] rom_133 = 64'h300000000737562; // @[BootROM.scala:50:22]
wire [63:0] rom_134 = 64'h3001000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_135 = 64'h746F6F6201000000; // @[BootROM.scala:50:22]
wire [63:0] rom_136 = 64'h737365726464612D; // @[BootROM.scala:50:22]
wire [63:0] rom_137 = 64'h303031406765722D; // @[BootROM.scala:50:22]
wire [63:0] rom_140 = 64'h10000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_144 = 64'h7375626301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_151 = 64'h737562634E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_157 = 64'h303240746E696C63; // @[BootROM.scala:50:22]
wire [63:0] rom_161 = 64'h30746E696C632C76; // @[BootROM.scala:50:22]
wire [63:0] rom_163 = 64'h6101000010000000; // @[BootROM.scala:50:22]
wire [63:0] rom_164 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_165 = 64'h700000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_167 = 64'h2BB000000; // @[BootROM.scala:50:22]
wire [63:0] rom_172 = 64'h61672D6B636F6C63; // @[BootROM.scala:50:22]
wire [63:0] rom_173 = 64'h3030303140726574; // @[BootROM.scala:50:22]
wire [63:0] rom_174 = 64'h300000000003030; // @[BootROM.scala:50:22]
wire [63:0] rom_176 = 64'h10000000001000; // @[BootROM.scala:50:22]
wire [63:0] rom_180 = 64'h7562656401000000; // @[BootROM.scala:50:22]
wire [63:0] rom_181 = 64'h6F72746E6F632D67; // @[BootROM.scala:50:22]
wire [63:0] rom_182 = 64'h304072656C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_183 = 64'h2100000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_185 = 64'h67756265642C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_186 = 64'h736972003331302D; // @[BootROM.scala:50:22]
wire [63:0] rom_187 = 64'h67756265642C7663; // @[BootROM.scala:50:22]
wire [63:0] rom_188 = 64'h3331302D; // @[BootROM.scala:50:22]
wire [63:0] rom_189 = 64'h500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_190 = 64'h6761746A75010000; // @[BootROM.scala:50:22]
wire [63:0] rom_193 = 64'hFFFF000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_84 = 64'hBB000000; // @[BootROM.scala:50:22]
wire [63:0] rom_195 = 64'hBB000000; // @[BootROM.scala:50:22]
wire [63:0] rom_200 = 64'h303038406D697464; // @[BootROM.scala:50:22]
wire [63:0] rom_158 = 64'h3030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_201 = 64'h3030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_204 = 64'h306D6974642C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_207 = 64'h40000000000080; // @[BootROM.scala:50:22]
wire [63:0] rom_209 = 64'h6D656D37010000; // @[BootROM.scala:50:22]
wire [63:0] rom_211 = 64'h100000028010000; // @[BootROM.scala:50:22]
wire [63:0] rom_213 = 64'h65642D726F727265; // @[BootROM.scala:50:22]
wire [63:0] rom_214 = 64'h3030334065636976; // @[BootROM.scala:50:22]
wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_138 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_215 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_216 = 64'h1B0000000E000000; // @[BootROM.scala:50:22]
wire [63:0] rom_217 = 64'h652C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_218 = 64'h30726F7272; // @[BootROM.scala:50:22]
wire [63:0] rom_220 = 64'h300000BB000000; // @[BootROM.scala:50:22]
wire [63:0] rom_221 = 64'h200000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_222 = 64'h7375626601000000; // @[BootROM.scala:50:22]
wire [63:0] rom_229 = 64'h737562664E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_236 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22]
wire [63:0] rom_237 = 64'h3030634072656C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_240 = 64'h100000002010000; // @[BootROM.scala:50:22]
wire [63:0] rom_160 = 64'h637369721B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_242 = 64'h637369721B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_243 = 64'h3063696C702C76; // @[BootROM.scala:50:22]
wire [63:0] rom_113 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_244 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_114 = 64'h300000013010000; // @[BootROM.scala:50:22]
wire [63:0] rom_245 = 64'h300000013010000; // @[BootROM.scala:50:22]
wire [63:0] rom_192 = 64'h6101000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_246 = 64'h6101000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_247 = 64'hB00000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_249 = 64'hCBB000000; // @[BootROM.scala:50:22]
wire [63:0] rom_250 = 64'h300000000000004; // @[BootROM.scala:50:22]
wire [63:0] rom_254 = 64'h100000082010000; // @[BootROM.scala:50:22]
wire [63:0] rom_256 = 64'h100000095010000; // @[BootROM.scala:50:22]
wire [63:0] rom_258 = 64'h400000028010000; // @[BootROM.scala:50:22]
wire [63:0] rom_260 = 64'h726F702D6F696D6D; // @[BootROM.scala:50:22]
wire [63:0] rom_261 = 64'h3640346978612D74; // @[BootROM.scala:50:22]
wire [63:0] rom_262 = 64'h30303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_125 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_264 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_127 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_266 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_268 = 64'h706D69731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_269 = 64'h7375622D656C; // @[BootROM.scala:50:22]
wire [63:0] rom_271 = 64'h6030010000; // @[BootROM.scala:50:22]
wire [63:0] rom_272 = 64'h2000000060; // @[BootROM.scala:50:22]
wire [63:0] rom_276 = 64'h4101000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_278 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_279 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_280 = 64'h4E0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_274 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_281 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_275 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_282 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_283 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_284 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_285 = 64'h3000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_115 = 64'h2801000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_286 = 64'h2801000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_287 = 64'h200000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_288 = 64'h406D6F7201000000; // @[BootROM.scala:50:22]
wire [63:0] rom_289 = 64'h3030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_292 = 64'h306D6F722C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_294 = 64'h100BB000000; // @[BootROM.scala:50:22]
wire [63:0] rom_168 = 64'h300000000000100; // @[BootROM.scala:50:22]
wire [63:0] rom_295 = 64'h300000000000100; // @[BootROM.scala:50:22]
wire [63:0] rom_296 = 64'h3701000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_297 = 64'h2000000006D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_298 = 64'h7375627301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_147 = 64'h41010000; // @[BootROM.scala:50:22]
wire [63:0] rom_225 = 64'h41010000; // @[BootROM.scala:50:22]
wire [63:0] rom_301 = 64'h41010000; // @[BootROM.scala:50:22]
wire [63:0] rom_149 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_227 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_303 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_150 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_228 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_267 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_304 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_305 = 64'h737562734E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_145 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_152 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_223 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_230 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_299 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_306 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_153 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_231 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_241 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_270 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_290 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_307 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_154 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_232 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_308 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_155 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_233 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_309 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_156 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_171 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_199 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_212 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_234 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_259 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_273 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_310 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_311 = 64'h31406C6169726573; // @[BootROM.scala:50:22]
wire [63:0] rom_312 = 64'h30303030323030; // @[BootROM.scala:50:22]
wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_73 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_75 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_77 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_79 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_81 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_83 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_102 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_124 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_126 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_146 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_148 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_208 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_210 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_224 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_226 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_239 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_253 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_255 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_257 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_263 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_265 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_300 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_302 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_313 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_314 = 64'h3000000A0010000; // @[BootROM.scala:50:22]
wire [63:0] rom_159 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_202 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_315 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_184 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_203 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_291 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_316 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_317 = 64'h30747261752C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_107 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_119 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_162 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_191 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_205 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_277 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_318 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_319 = 64'hA701000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_95 = 64'h300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_320 = 64'h300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_321 = 64'hB801000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_99 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_109 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_322 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_139 = 64'hBB00000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_175 = 64'hBB00000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_206 = 64'hBB00000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_323 = 64'hBB00000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_324 = 64'h10000000000210; // @[BootROM.scala:50:22]
wire [63:0] rom_142 = 64'h746E6F6337010000; // @[BootROM.scala:50:22]
wire [63:0] rom_178 = 64'h746E6F6337010000; // @[BootROM.scala:50:22]
wire [63:0] rom_326 = 64'h746E6F6337010000; // @[BootROM.scala:50:22]
wire [63:0] rom_143 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_179 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_327 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_328 = 64'h656C697401000000; // @[BootROM.scala:50:22]
wire [63:0] rom_329 = 64'h732D74657365722D; // @[BootROM.scala:50:22]
wire [63:0] rom_330 = 64'h3131407265747465; // @[BootROM.scala:50:22]
wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_238 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_331 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_141 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_166 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_177 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_194 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_219 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_248 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_293 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_325 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_332 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_333 = 64'h1100BB000000; // @[BootROM.scala:50:22]
wire [63:0] rom_196 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_334 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_169 = 64'h3701000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_197 = 64'h3701000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_251 = 64'h3701000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_335 = 64'h3701000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_170 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_198 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_252 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_336 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_116 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_117 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_337 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_338 = 64'h900000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_339 = 64'h7373657264646123; // @[BootROM.scala:50:22]
wire [63:0] rom_340 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22]
wire [63:0] rom_341 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22]
wire [63:0] rom_342 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_343 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22]
wire [63:0] rom_344 = 64'h69726573006C6564; // @[BootROM.scala:50:22]
wire [63:0] rom_345 = 64'h6F64747300306C61; // @[BootROM.scala:50:22]
wire [63:0] rom_346 = 64'h687461702D7475; // @[BootROM.scala:50:22]
wire [63:0] rom_347 = 64'h65736162656D6974; // @[BootROM.scala:50:22]
wire [63:0] rom_349 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22]
wire [63:0] rom_348 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_350 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_351 = 64'h6369766564007963; // @[BootROM.scala:50:22]
wire [63:0] rom_352 = 64'h6800657079745F65; // @[BootROM.scala:50:22]
wire [63:0] rom_353 = 64'h2D65726177647261; // @[BootROM.scala:50:22]
wire [63:0] rom_354 = 64'h6572622D63657865; // @[BootROM.scala:50:22]
wire [63:0] rom_355 = 64'h2D746E696F706B61; // @[BootROM.scala:50:22]
wire [63:0] rom_356 = 64'h2D6900746E756F63; // @[BootROM.scala:50:22]
wire [63:0] rom_357 = 64'h6C622D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_358 = 64'h657A69732D6B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_359 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_360 = 64'h2D6900737465732D; // @[BootROM.scala:50:22]
wire [63:0] rom_361 = 64'h69732D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_362 = 64'h720067657200657A; // @[BootROM.scala:50:22]
wire [63:0] rom_363 = 64'h6173692C76637369; // @[BootROM.scala:50:22]
wire [63:0] rom_364 = 64'h702C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_365 = 64'h6C756E617267706D; // @[BootROM.scala:50:22]
wire [63:0] rom_366 = 64'h6972007974697261; // @[BootROM.scala:50:22]
wire [63:0] rom_367 = 64'h72706D702C766373; // @[BootROM.scala:50:22]
wire [63:0] rom_368 = 64'h7300736E6F696765; // @[BootROM.scala:50:22]
wire [63:0] rom_369 = 64'h74642C6576696669; // @[BootROM.scala:50:22]
wire [63:0] rom_370 = 64'h7574617473006D69; // @[BootROM.scala:50:22]
wire [63:0] rom_371 = 64'h7265746E69230073; // @[BootROM.scala:50:22]
wire [63:0] rom_372 = 64'h6C65632D74707572; // @[BootROM.scala:50:22]
wire [63:0] rom_373 = 64'h7265746E6900736C; // @[BootROM.scala:50:22]
wire [63:0] rom_374 = 64'h6E6F632D74707572; // @[BootROM.scala:50:22]
wire [63:0] rom_375 = 64'h72656C6C6F7274; // @[BootROM.scala:50:22]
wire [63:0] rom_376 = 64'h656C646E616870; // @[BootROM.scala:50:22]
wire [63:0] rom_377 = 64'h72007365676E6172; // @[BootROM.scala:50:22]
wire [63:0] rom_378 = 64'h73656D616E2D6765; // @[BootROM.scala:50:22]
wire [63:0] rom_379 = 64'h2D6B636F6C632300; // @[BootROM.scala:50:22]
wire [63:0] rom_380 = 64'h6C6300736C6C6563; // @[BootROM.scala:50:22]
wire [63:0] rom_381 = 64'h7074756F2D6B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_382 = 64'h73656D616E2D7475; // @[BootROM.scala:50:22]
wire [63:0] rom_383 = 64'h75727265746E6900; // @[BootROM.scala:50:22]
wire [63:0] rom_384 = 64'h657478652D737470; // @[BootROM.scala:50:22]
wire [63:0] rom_385 = 64'h626564006465646E; // @[BootROM.scala:50:22]
wire [63:0] rom_386 = 64'h63617474612D6775; // @[BootROM.scala:50:22]
wire [63:0] rom_387 = 64'h2C76637369720068; // @[BootROM.scala:50:22]
wire [63:0] rom_388 = 64'h6F6972702D78616D; // @[BootROM.scala:50:22]
wire [63:0] rom_389 = 64'h7369720079746972; // @[BootROM.scala:50:22]
wire [63:0] rom_390 = 64'h7665646E2C7663; // @[BootROM.scala:50:22]
wire [63:0] rom_391 = 64'h6900736B636F6C63; // @[BootROM.scala:50:22]
wire [63:0] rom_392 = 64'h747075727265746E; // @[BootROM.scala:50:22]
wire [63:0] rom_393 = 64'h746E657261702D; // @[BootROM.scala:50:22]
wire [63:0] rom_235 = 64'h7075727265746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_394 = 64'h7075727265746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_395 = 64'h7374; // @[BootROM.scala:50:22]
wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_396 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_397 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_398 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_399 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_400 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_401 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_402 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_403 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_404 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_405 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_406 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_407 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_408 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_409 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_410 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_411 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_412 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_413 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_414 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_415 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_416 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_417 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_418 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_419 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_420 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_421 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_422 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_423 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_424 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_425 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_426 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_427 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_428 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_429 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_430 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_431 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_432 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_433 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_434 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_435 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_436 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_437 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_438 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_439 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_440 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_441 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_442 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_443 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_444 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_445 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_446 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_447 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_448 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_449 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_450 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_451 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_452 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_453 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_454 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_455 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_456 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_457 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_458 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_459 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_460 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_461 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_462 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_463 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_464 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_465 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_466 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_467 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_468 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_469 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_470 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_471 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_472 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_473 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22]
wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17]
wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9]
wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9]
wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_in_a_ready_0; // @[BootROM.scala:41:9]
wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
wire [11:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
wire auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9]
assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17]
wire [11:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17]
assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9]
wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34]
wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64]
wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53]
wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}]
assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17]
assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
TLMonitor_47 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module IntSyncCrossingSource_n1x1_35( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_35 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_10( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_22 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PMA.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.{CoreModule, CoreBundle}
import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters}
class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
val paddr = Input(UInt())
val resp = Output(new Bundle {
val cacheable = Bool()
val r = Bool()
val w = Bool()
val pp = Bool()
val al = Bool()
val aa = Bool()
val x = Bool()
val eff = Bool()
})
})
// PMA
// check exist a slave can consume this address.
val legal_address = manager.findSafe(io.paddr).reduce(_||_)
// check utility to help check SoC property.
def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B)
io.resp.cacheable := fastCheck(_.supportsAcquireB)
io.resp.r := fastCheck(_.supportsGet)
io.resp.w := fastCheck(_.supportsPutFull)
io.resp.pp := fastCheck(_.supportsPutPartial)
io.resp.al := fastCheck(_.supportsLogical)
io.resp.aa := fastCheck(_.supportsArithmetic)
io.resp.x := fastCheck(_.executable)
io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
| module PMAChecker( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_71 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_65 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_49; // @[PMA.scala:39:19]
wire _io_resp_pp_T_49; // @[PMA.scala:39:19]
wire _io_resp_al_T_49; // @[PMA.scala:39:19]
wire _io_resp_aa_T_49; // @[PMA.scala:39:19]
wire _io_resp_x_T_73; // @[PMA.scala:39:19]
wire _io_resp_eff_T_67; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_41; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_41 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31]
assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31]
assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_46; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_46 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31]
assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31]
assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_51; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_51 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10016000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_55 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_60; // @[Parameters.scala:137:31]
assign _legal_address_T_60 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_56; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_56 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46]
wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40]
wire _legal_address_T_65 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_70 = _legal_address_T_69 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_71 = _legal_address_T_70 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_72 = _legal_address_T_71 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_73 = _legal_address_T_72 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_74 = _legal_address_T_73 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire _legal_address_T_75 = _legal_address_T_74 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_75 | _legal_address_WIRE_12; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46]
wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73]
assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73]
assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46]
wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73]
assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73]
assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_70 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_9 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10012000}; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T_59; // @[Parameters.scala:137:31]
assign _io_resp_x_T_59 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_30; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [40:0] _io_resp_x_T_60 = {1'h0, _io_resp_x_T_59}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_61 = _io_resp_x_T_60 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_62 = _io_resp_x_T_61; // @[Parameters.scala:137:46]
wire _io_resp_x_T_63 = _io_resp_x_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_64 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_65 = _io_resp_x_T_64 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_66 = _io_resp_x_T_65 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_67 = _io_resp_x_T_66 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_68 = _io_resp_x_T_67 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_69 = _io_resp_x_T_68 | _io_resp_x_T_63; // @[Parameters.scala:629:89]
wire _io_resp_x_T_72 = _io_resp_x_T_70; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_72; // @[Mux.scala:30:73]
assign _io_resp_x_T_73 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_73; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_31 = {1'h0, _io_resp_eff_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_32 = _io_resp_eff_T_31 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_33 = _io_resp_eff_T_32; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_35 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_36 = _io_resp_eff_T_35 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_37 = _io_resp_eff_T_36 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_38 = _io_resp_eff_T_37 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_40 = _io_resp_eff_T_39 | _io_resp_eff_T_34; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_64 = _io_resp_eff_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_42 = {1'h0, _io_resp_eff_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_44 = _io_resp_eff_T_43; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_45 = _io_resp_eff_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_47 = {1'h0, _io_resp_eff_T_46}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_49 = _io_resp_eff_T_48; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_50 = _io_resp_eff_T_49 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_52 = {1'h0, _io_resp_eff_T_51}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_54 = _io_resp_eff_T_53; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_55 = _io_resp_eff_T_54 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_57 = {1'h0, _io_resp_eff_T_56}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_58 = _io_resp_eff_T_57 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_59 = _io_resp_eff_T_58; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_60 = _io_resp_eff_T_59 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_61 = _io_resp_eff_T_45 | _io_resp_eff_T_50; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_62 = _io_resp_eff_T_61 | _io_resp_eff_T_55; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_63 = _io_resp_eff_T_62 | _io_resp_eff_T_60; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_66 = _io_resp_eff_T_64; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_66; // @[Mux.scala:30:73]
assign _io_resp_eff_T_67 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_67; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Plic.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.{Annotated, MuxT, property}
import scala.math.min
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.SeqToAugmentedSeq
class GatewayPLICIO extends Bundle {
val valid = Output(Bool())
val ready = Input(Bool())
val complete = Input(Bool())
}
class LevelGateway extends Module {
val io = IO(new Bundle {
val interrupt = Input(Bool())
val plic = new GatewayPLICIO
})
val inFlight = RegInit(false.B)
when (io.interrupt && io.plic.ready) { inFlight := true.B }
when (io.plic.complete) { inFlight := false.B }
io.plic.valid := io.interrupt && !inFlight
}
object PLICConsts
{
def maxDevices = 1023
def maxMaxHarts = 15872
def priorityBase = 0x0
def pendingBase = 0x1000
def enableBase = 0x2000
def hartBase = 0x200000
def claimOffset = 4
def priorityBytes = 4
def enableOffset(i: Int) = i * ((maxDevices+7)/8)
def hartOffset(i: Int) = i * 0x1000
def enableBase(i: Int):Int = enableOffset(i) + enableBase
def hartBase(i: Int):Int = hartOffset(i) + hartBase
def size(maxHarts: Int): Int = {
require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}")
1 << log2Ceil(hartBase(maxHarts))
}
require(hartBase >= enableBase(maxMaxHarts))
}
case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts)
{
require (maxPriorities >= 0)
def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1)
}
case object PLICKey extends Field[Option[PLICParams]](None)
case class PLICAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object PLICAttachKey extends Field(PLICAttachParams())
/** Platform-Level Interrupt Controller */
class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// plic0 => max devices 1023
val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val extra = Map(
"interrupt-controller" -> Nil,
"riscv,ndev" -> Seq(ResourceInt(nDevices)),
"riscv,max-priority" -> Seq(ResourceInt(nPriorities)),
"#interrupt-cells" -> Seq(ResourceInt(1)))
Description(name, mapping ++ extra)
}
}
val node : TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes,
undefZero = true,
concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
val intnode: IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false)
/* Negotiated sizes */
def nDevices: Int = intnode.edges.in.map(_.source.num).sum
def minPriorities = min(params.maxPriorities, nDevices)
def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1
def nHarts = intnode.edges.out.map(_.source.num).sum
// Assign all the devices unique ranges
lazy val sources = intnode.edges.in.map(_.source)
lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten
ResourceBinding {
flatSources.foreach { s => s.resources.foreach { r =>
// +1 because interrupt 0 is reserved
(s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }
} }
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
val (io_devices, edgesIn) = intnode.in.unzip
val (io_harts, _) = intnode.out.unzip
// Compact the interrupt vector the same way
val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
val harts = io_harts.flatten
def getNInterrupts = interrupts.size
println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
flatSources.foreach { s =>
// +1 because 0 is reserved, +1-1 because the range is half-open
println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
}
println("")
require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}")
require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}")
require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}")
require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}")
// For now, use LevelGateways for all TL2 interrupts
val gateways = interrupts.map { case i =>
val gateway = Module(new LevelGateway)
gateway.io.interrupt := i
gateway.io.plic
}
val prioBits = log2Ceil(nPriorities+1)
val priority =
if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nDevices max 1)(1.U))
val threshold =
if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nHarts)(0.U))
val pending = RegInit(VecInit.fill(nDevices max 1){false.B})
/* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */
val firstEnable = nDevices min 7
val fullEnables = (nDevices - firstEnable) / 8
val tailEnable = nDevices - firstEnable - 8*fullEnables
def enableRegs = (Reg(UInt(firstEnable.W)) +:
Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++
(if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None)
val enables = Seq.fill(nHarts) { enableRegs }
val enableVec = VecInit(enables.map(x => Cat(x.reverse)))
val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W))))
val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))
val pendingUInt = Cat(pending.reverse)
if(nDevices > 0) {
for (hart <- 0 until nHarts) {
val fanin = Module(new PLICFanIn(nDevices, prioBits))
fanin.io.prio := priority
fanin.io.ip := enableVec(hart) & pendingUInt
maxDevs(hart) := fanin.io.dev
harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)
}
}
// Priority registers are 32-bit aligned so treat each as its own group.
// Otherwise, the off-by-one nature of the priority registers gets confusing.
require(PLICConsts.priorityBytes == 4,
s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}")
def priorityRegDesc(i: Int) =
RegFieldDesc(
name = s"priority_$i",
desc = s"Acting priority of interrupt source $i",
group = Some(s"priority_${i}"),
groupDesc = Some(s"Acting priority of interrupt source ${i}"),
reset = if (nPriorities > 0) None else Some(1))
def pendingRegDesc(i: Int) =
RegFieldDesc(
name = s"pending_$i",
desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
group = Some("pending"),
groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."),
volatile = true)
def enableRegDesc(i: Int, j: Int, wide: Int) = {
val low = if (j == 0) 1 else j*8
val high = low + wide - 1
RegFieldDesc(
name = s"enables_${j}",
desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.",
group = Some(s"enables_${i}"),
groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source."))
}
def priorityRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, priorityRegDesc(i))
} else {
RegField.r(prioBits, x, priorityRegDesc(i))
}
val priorityRegFields = priority.zipWithIndex.map { case (p, i) =>
PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) ->
Seq(priorityRegField(p, i+1)) }
val pendingRegFields = Seq(PLICConsts.pendingBase ->
(RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))}))
val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) =>
RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) }
// When a hart reads a claim/complete register, then the
// device which is currently its highest priority is no longer pending.
// This code exploits the fact that, practically, only one claim/complete
// register can be read at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note: PLIC doesn't care which hart reads the register.
val claimer = Wire(Vec(nHarts, Bool()))
assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot
val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_)
val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools)
((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) =>
g.ready := !p
when (c || g.valid) { p := !c }
}
// When a hart writes a claim/complete register, then
// the written device (as long as it is actually enabled for that
// hart) is marked complete.
// This code exploits the fact that, practically, only one claim/complete register
// can be written at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note -- PLIC doesn't care which hart writes the register.
val completer = Wire(Vec(nHarts, Bool()))
assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot
val completerDev = Wire(UInt(log2Up(nDevices + 1).W))
val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U)
(gateways zip completedDevs.asBools.tail) foreach { case (g, c) =>
g.complete := c
}
def thresholdRegDesc(i: Int) =
RegFieldDesc(
name = s"threshold_$i",
desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.",
reset = if (nPriorities > 0) None else Some(1))
def thresholdRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, thresholdRegDesc(i))
} else {
RegField.r(prioBits, x, thresholdRegDesc(i))
}
val hartRegFields = Seq.tabulate(nHarts) { i =>
PLICConsts.hartBase(i) -> Seq(
thresholdRegField(threshold(i), i),
RegField(32-prioBits),
RegField(32,
RegReadFn { valid =>
claimer(i) := valid
(true.B, maxDevs(i))
},
RegWriteFn { (valid, data) =>
assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),
"completerDev should be consistent for all harts")
completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
completer(i) := valid && enableVec0(i)(completerDev)
true.B
},
Some(RegFieldDesc(s"claim_complete_$i",
s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
s"Writing the interrupt number back completes the interrupt.",
reset = None,
wrType = Some(RegFieldWrType.MODIFY),
rdAction = Some(RegFieldRdAction.MODIFY),
volatile = true))
)
)
}
node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
if (nDevices >= 2) {
val claimed = claimer(0) && maxDevs(0) > 0.U
val completed = completer(0)
property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete")
property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim")
val ep = enables(0).asUInt & pending.asUInt
val ep2 = RegNext(ep)
val diff = ep & ~ep2
property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle")
if (nPriorities > 0)
ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)),
"THRESHOLD", "interrupt pending but less than threshold")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc)
}
}
class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
val io = IO(new Bundle {
val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
val ip = Flipped(UInt(nDevices.W))
val dev = UInt(log2Ceil(nDevices+1).W)
val max = UInt(prioBits.W)
})
def findMax(x: Seq[UInt]): (UInt, UInt) = {
if (x.length > 1) {
val half = 1 << (log2Ceil(x.length) - 1)
val left = findMax(x take half)
val right = findMax(x drop half)
MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
} else (x.head, 0.U)
}
val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }
val (maxPri, maxDev) = findMax(effectivePriority)
io.max := maxPri // strips the always-constant high '1' bit
io.dev := maxDev
}
/** Trait that will connect a PLIC to a subsystem */
trait CanHavePeripheryPLIC { this: BaseSubsystem =>
val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>
val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)
val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain")
val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } }
plicDomainWrapper { plic.intnode :=* ibus.toPLIC }
(plic, plicDomainWrapper)
}.unzip
}
| module PLICClockSinkDomain( // @[ClockDomain.scala:14:9]
input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25]
output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_23_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_22_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_21_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_20_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_19_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_18_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_17_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_16_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_15_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_14_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_13_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_12_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_11_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_10_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_9_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_8_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_7_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_6_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_5_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_4_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_3_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_2_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _plic_auto_int_out_23_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_22_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_21_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_20_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_19_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_18_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_17_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_16_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_15_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_14_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_13_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_12_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_11_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_10_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_9_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_8_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_7_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_6_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_5_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_4_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_3_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_2_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_1_0; // @[Plic.scala:367:46]
wire _plic_auto_int_out_0_0; // @[Plic.scala:367:46]
TLPLIC plic ( // @[Plic.scala:367:46]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_int_in_0 (auto_plic_int_in_0),
.auto_int_out_23_0 (_plic_auto_int_out_23_0),
.auto_int_out_22_0 (_plic_auto_int_out_22_0),
.auto_int_out_21_0 (_plic_auto_int_out_21_0),
.auto_int_out_20_0 (_plic_auto_int_out_20_0),
.auto_int_out_19_0 (_plic_auto_int_out_19_0),
.auto_int_out_18_0 (_plic_auto_int_out_18_0),
.auto_int_out_17_0 (_plic_auto_int_out_17_0),
.auto_int_out_16_0 (_plic_auto_int_out_16_0),
.auto_int_out_15_0 (_plic_auto_int_out_15_0),
.auto_int_out_14_0 (_plic_auto_int_out_14_0),
.auto_int_out_13_0 (_plic_auto_int_out_13_0),
.auto_int_out_12_0 (_plic_auto_int_out_12_0),
.auto_int_out_11_0 (_plic_auto_int_out_11_0),
.auto_int_out_10_0 (_plic_auto_int_out_10_0),
.auto_int_out_9_0 (_plic_auto_int_out_9_0),
.auto_int_out_8_0 (_plic_auto_int_out_8_0),
.auto_int_out_7_0 (_plic_auto_int_out_7_0),
.auto_int_out_6_0 (_plic_auto_int_out_6_0),
.auto_int_out_5_0 (_plic_auto_int_out_5_0),
.auto_int_out_4_0 (_plic_auto_int_out_4_0),
.auto_int_out_3_0 (_plic_auto_int_out_3_0),
.auto_int_out_2_0 (_plic_auto_int_out_2_0),
.auto_int_out_1_0 (_plic_auto_int_out_1_0),
.auto_int_out_0_0 (_plic_auto_int_out_0_0),
.auto_in_a_ready (auto_plic_in_a_ready),
.auto_in_a_valid (auto_plic_in_a_valid),
.auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode),
.auto_in_a_bits_param (auto_plic_in_a_bits_param),
.auto_in_a_bits_size (auto_plic_in_a_bits_size),
.auto_in_a_bits_source (auto_plic_in_a_bits_source),
.auto_in_a_bits_address (auto_plic_in_a_bits_address),
.auto_in_a_bits_mask (auto_plic_in_a_bits_mask),
.auto_in_a_bits_data (auto_plic_in_a_bits_data),
.auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt),
.auto_in_d_ready (auto_plic_in_d_ready),
.auto_in_d_valid (auto_plic_in_d_valid),
.auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode),
.auto_in_d_bits_size (auto_plic_in_d_bits_size),
.auto_in_d_bits_source (auto_plic_in_d_bits_source),
.auto_in_d_bits_data (auto_plic_in_d_bits_data)
); // @[Plic.scala:367:46]
IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_0_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_0_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_1 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_1_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_1_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_2 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_2_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_2_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_3 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_3_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_3_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_4 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_4_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_4_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_5 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_5_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_5_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_6 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_6_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_6_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_7 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_7_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_7_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_8 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_8_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_8_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_9 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_9_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_9_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_10 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_10_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_10_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_11 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_11_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_11_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_12 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_12_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_12_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_13 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_13_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_13_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_14 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_14_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_14_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_15 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_15_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_15_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_16 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_16_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_16_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_17 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_17_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_17_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_18 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_18_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_18_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_19 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_19_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_19_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_20 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_20_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_20_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_21 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_21_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_21_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_22 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_22_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_22_sync_0)
); // @[Crossing.scala:29:31]
IntSyncCrossingSource_n1x1 intsource_23 ( // @[Crossing.scala:29:31]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_in_0 (_plic_auto_int_out_23_0), // @[Plic.scala:367:46]
.auto_out_sync_0 (auto_int_in_clock_xing_out_23_sync_0)
); // @[Crossing.scala:29:31]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_27( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_2( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1154 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1154; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1154; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1222 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1222; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1222; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1222; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1087 = _T_1154 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1087 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1087 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1087 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1087 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1087 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1133 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1133 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1102 = _T_1222 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1102 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1102 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1102 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1198 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1198 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1180 = _T_1222 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1180 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1180 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1180 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_47( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_58 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_6( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Control.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
class InclusiveCacheControl(outer: InclusiveCache, control: InclusiveCacheControlParameters)(implicit p: Parameters) extends LazyModule()(p) {
val ctrlnode = TLRegisterNode(
address = Seq(AddressSet(control.address, InclusiveCacheParameters.L2ControlSize-1)),
device = outer.device,
concurrency = 1, // Only one flush at a time (else need to track who answers)
beatBytes = control.beatBytes)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val flush_match = Input(Bool())
val flush_req = Decoupled(UInt(64.W))
val flush_resp = Input(Bool())
})
// Flush directive
val flushInValid = RegInit(false.B)
val flushInAddress = Reg(UInt(64.W))
val flushOutValid = RegInit(false.B)
val flushOutReady = WireInit(init = false.B)
when (flushOutReady) { flushOutValid := false.B }
when (io.flush_resp) { flushOutValid := true.B }
when (io.flush_req.ready) { flushInValid := false.B }
io.flush_req.valid := flushInValid
io.flush_req.bits := flushInAddress
when (!io.flush_match && flushInValid) {
flushInValid := false.B
flushOutValid := true.B
}
val flush32 = RegField.w(32, RegWriteFn((ivalid, oready, data) => {
when (oready) { flushOutReady := true.B }
when (ivalid) { flushInValid := true.B }
when (ivalid && !flushInValid) { flushInAddress := data << 4 }
(!flushInValid, flushOutValid)
}), RegFieldDesc("Flush32", "Flush the physical address equal to the 32-bit written data << 4 from the cache"))
val flush64 = RegField.w(64, RegWriteFn((ivalid, oready, data) => {
when (oready) { flushOutReady := true.B }
when (ivalid) { flushInValid := true.B }
when (ivalid && !flushInValid) { flushInAddress := data }
(!flushInValid, flushOutValid)
}), RegFieldDesc("Flush64", "Flush the phsyical address equal to the 64-bit written data from the cache"))
// Information about the cache configuration
val banksR = RegField.r(8, outer.node.edges.in.size.U, RegFieldDesc("Banks",
"Number of banks in the cache", reset=Some(outer.node.edges.in.size)))
val waysR = RegField.r(8, outer.cache.ways.U, RegFieldDesc("Ways",
"Number of ways per bank", reset=Some(outer.cache.ways)))
val lgSetsR = RegField.r(8, log2Ceil(outer.cache.sets).U, RegFieldDesc("lgSets",
"Base-2 logarithm of the sets per bank", reset=Some(log2Ceil(outer.cache.sets))))
val lgBlockBytesR = RegField.r(8, log2Ceil(outer.cache.blockBytes).U, RegFieldDesc("lgBlockBytes",
"Base-2 logarithm of the bytes per cache block", reset=Some(log2Ceil(outer.cache.blockBytes))))
val regmap = ctrlnode.regmap(
0x000 -> RegFieldGroup("Config", Some("Information about the Cache Configuration"), Seq(banksR, waysR, lgSetsR, lgBlockBytesR)),
0x200 -> (if (control.beatBytes >= 8) Seq(flush64) else Nil),
0x240 -> Seq(flush32)
)
}
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module InclusiveCacheControl( // @[Control.scala:38:9]
input clock, // @[Control.scala:38:9]
input reset, // @[Control.scala:38:9]
output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_flush_match, // @[Control.scala:39:16]
input io_flush_req_ready, // @[Control.scala:39:16]
output io_flush_req_valid, // @[Control.scala:39:16]
output [63:0] io_flush_req_bits, // @[Control.scala:39:16]
input io_flush_resp // @[Control.scala:39:16]
);
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24]
wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24]
wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9]
wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9]
wire [10:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9]
wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9]
wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9]
wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9]
wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9]
wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9]
wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9]
wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9]
wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9]
wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801};
wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48]
wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9]
wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9]
wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9]
wire [10:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9]
wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9]
wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9]
wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9]
wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9]
wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9]
wire [10:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9]
wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9]
wire io_flush_req_valid_0; // @[Control.scala:38:9]
wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9]
wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9]
wire [10:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9]
reg flushInValid; // @[Control.scala:45:33]
assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33]
reg [63:0] flushInAddress; // @[Control.scala:46:29]
assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29]
reg flushOutValid; // @[Control.scala:47:33]
wire flushOutReady; // @[Control.scala:48:34]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_front_valid_T; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23]
wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24]
wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8]
wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = out_f_wiready | _out_T_48; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = flushOutValid | _out_T_51; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24]
assign flushOutReady = out_f_woready_5 | out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23]
wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24]
wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24]
wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23]
wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_f_wiready_1 | _out_T_61; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = flushOutValid | _out_T_64; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21]
wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = out_wifireMux_out_2 | _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21]
wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = out_wifireMux_out_3 | _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48]
wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}]
wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10]
wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21]
wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = out_wofireMux_out_2 | _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21]
wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = out_wofireMux_out_3 | _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48]
wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}]
wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
wire out_iready = out_front_bits_read | out_wifireMux; // @[MuxLiteral.scala:49:10]
wire out_oready = _out_back_front_q_io_deq_bits_read | out_wofireMux; // @[MuxLiteral.scala:49:10]
assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}]
always @(posedge clock) begin // @[Control.scala:38:9]
if (reset) begin // @[Control.scala:38:9]
flushInValid <= 1'h0; // @[Control.scala:45:33]
flushOutValid <= 1'h0; // @[Control.scala:47:33]
end
else begin // @[Control.scala:38:9]
flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_T_1 | io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24]
flushOutValid <= _T_1 | io_flush_resp_0 | ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21]
end
if (_out_T_57) // @[Control.scala:64:20]
flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}]
else if (_out_T_44) // @[Control.scala:71:20]
flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24]
always @(posedge)
TLMonitor_39 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24]
.clock (clock),
.reset (reset),
.io_enq_ready (out_front_ready),
.io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24]
.io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24]
.io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24]
.io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24]
.io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24]
.io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24]
.io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24]
.io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24]
.io_deq_valid (_out_back_front_q_io_deq_valid),
.io_deq_bits_read (_out_back_front_q_io_deq_bits_read),
.io_deq_bits_index (_out_back_front_q_io_deq_bits_index),
.io_deq_bits_data (_out_back_front_q_io_deq_bits_data),
.io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask),
.io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source),
.io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size)
); // @[RegisterRouter.scala:87:24]
assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9]
assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9]
assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_435( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_18( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h8; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h8; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_478( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TLBuffer_a14d64s8k1z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [7:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_22 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a14d64s8k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a14d64s8k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File FIFOFixer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.util.property
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
{
private def fifoMap(seq: Seq[TLSlaveParameters]) = {
val (flatManagers, keepManagers) = seq.partition(policy)
// We need to be careful if one flatManager and one keepManager share an existing domain
// Erring on the side of caution, we will also flatten the keepManager in this case
val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
// Calculate what the FIFO domains look like after the fixer is applied
val flatMap = flatDomains.map { x => (x, 0) }.toMap
val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
val map = flatMap ++ keepMap
val fixMap = seq.map { m => m.fifoId match {
case None => if (policy(m)) Some(0) else None
case Some(id) => Some(map(id)) // also flattens some who did not ask
} }
// Compress the FIFO domain space of those we are combining
val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
val splatMap = seq.map { m => m.fifoId match {
case None => None
case Some(id) => reMap.lift(id)
} }
(fixMap, splatMap)
}
val node = new AdapterNode(TLImp)(
{ cp => cp },
{ mp =>
val (fixMap, _) = fifoMap(mp.managers)
mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })
}) with TLFormatNode {
override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
// Do we need to serialize the request to this manager?
val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)
// Compact the IDs of the cases we serialize
val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None
}
val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0
val a_id = if (compacted.isEmpty) 0.U else
edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)
val a_noDomain = a_id === 0.U
if (false) {
println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
println("")
}
// Count beats
val a_first = edgeIn.first(in.a)
val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))
when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source)
val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)
val track = flight.slice(c.sourceId.start, c.sourceId.end)
a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
}
val stall = stalls.foldLeft(false.B)(_||_)
out.a <> in.a
in.d <> out.d
out.a.valid := in.a.valid && (a_notFIFO || !stall)
in.a.ready := out.a.ready && (a_notFIFO || !stall)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> out.b
out.c <> in .c
out.e <> in .e
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
//Functional cover properties
property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))
val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))
val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))
when (a_first && in.a.fire && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}
object TLFIFOFixer
{
// Which slaves should have their FIFOness combined?
// NOTE: this transformation is still only applied for masters with requestFifo
type Policy = TLSlaveParameters => Boolean
import RegionType._
val all: Policy = m => true
val allFIFO: Policy = m => m.fifoId.isDefined
val allVolatile: Policy = m => m.regionType <= VOLATILE
def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
{
val fixer = LazyModule(new TLFIFOFixer(policy))
fixer.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File SystemBus.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{
BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams
}
import freechips.rocketchip.tilelink.{
TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper,
TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode,
TLFIFOFixer, TLTempNode
}
import freechips.rocketchip.util.Location
case class SystemBusParams(
beatBytes: Int,
blockBytes: Int,
policy: TLArbiter.Policy = TLArbiter.roundRobin,
dtsFrequency: Option[BigInt] = None,
zeroDevice: Option[BuiltInZeroDeviceParams] = None,
errorDevice: Option[BuiltInErrorDeviceParams] = None,
replication: Option[ReplicatedRegion] = None)
extends HasTLBusParams
with HasBuiltInDeviceParams
with TLBusWrapperInstantiationLike
{
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = {
val sbus = LazyModule(new SystemBus(this, loc.name))
sbus.suggestName(loc.name)
context.tlBusWrapperLocationMap += (loc -> sbus)
sbus
}
}
class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p: Parameters)
extends TLBusWrapper(params, name)
{
private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r)))
val prefixNode = replicator.map { r =>
r.prefix := addressPrefixNexusNode
addressPrefixNexusNode
}
private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name)))
val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode())
val outwardNode: TLOutwardNode = system_bus_xbar.node
def busView: TLEdge = system_bus_xbar.node.edges.in.head
val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File LazyScope.scala:
package org.chipsalliance.diplomacy.lazymodule
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
/** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. */
trait LazyScope {
this: LazyModule =>
override def toString: String = s"LazyScope named $name"
/** Evaluate `body` in the current [[LazyModule.scope]] */
def apply[T](body: => T): T = {
// Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function,
// [[LazyModule.scope]] will be altered.
val saved = LazyModule.scope
// [[LazyModule.scope]] stack push.
LazyModule.scope = Some(this)
// Evaluate [[body]] in the current `scope`, saving the result to [[out]].
val out = body
// Check that the `scope` after evaluating `body` is the same as when we started.
require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!")
require(
LazyModule.scope.get eq this,
s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed"
)
// [[LazyModule.scope]] stack pop.
LazyModule.scope = saved
out
}
}
/** Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can
* be instantiated and connected.
*
* It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this
* scope.
*/
object LazyScope {
/** Create a [[LazyScope]] with an implicit instance name.
*
* @param body
* code executed within the generated [[SimpleLazyModule]].
* @param valName
* instance name of generated [[SimpleLazyModule]].
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
body: => T
)(
implicit valName: ValName,
p: Parameters
): T = {
apply(valName.value, "SimpleLazyModule", None)(body)(p)
}
/** Create a [[LazyScope]] with an explicitly defined instance name.
*
* @param name
* instance name of generated [[SimpleLazyModule]].
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
name: String
)(body: => T
)(
implicit p: Parameters
): T = {
apply(name, "SimpleLazyModule", None)(body)(p)
}
/** Create a [[LazyScope]] with an explicit instance and class name, and control inlining.
*
* @param name
* instance name of generated [[SimpleLazyModule]].
* @param desiredModuleName
* class name of generated [[SimpleLazyModule]].
* @param overrideInlining
* tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined.
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
name: String,
desiredModuleName: String,
overrideInlining: Option[Boolean] = None
)(body: => T
)(
implicit p: Parameters
): T = {
val scope = LazyModule(new SimpleLazyModule with LazyScope {
override lazy val desiredName = desiredModuleName
override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined)
}).suggestName(name)
scope {
body
}
}
/** Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it.
*
* For example, we might want to control a set of children's clocks but then not keep the parent wrapper.
*
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def inline[T](
body: => T
)(
implicit p: Parameters
): T = {
apply("noname", "ShouldBeInlined", Some(false))(body)(p)
}
}
| module SystemBus( // @[ClockDomain.scala:14:9]
output auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [3:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [5:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [31:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _system_bus_xbar_auto_anon_out_0_a_valid; // @[SystemBus.scala:47:43]
wire [2:0] _system_bus_xbar_auto_anon_out_0_a_bits_opcode; // @[SystemBus.scala:47:43]
wire [2:0] _system_bus_xbar_auto_anon_out_0_a_bits_param; // @[SystemBus.scala:47:43]
wire [3:0] _system_bus_xbar_auto_anon_out_0_a_bits_size; // @[SystemBus.scala:47:43]
wire [5:0] _system_bus_xbar_auto_anon_out_0_a_bits_source; // @[SystemBus.scala:47:43]
wire [28:0] _system_bus_xbar_auto_anon_out_0_a_bits_address; // @[SystemBus.scala:47:43]
wire [3:0] _system_bus_xbar_auto_anon_out_0_a_bits_mask; // @[SystemBus.scala:47:43]
wire [31:0] _system_bus_xbar_auto_anon_out_0_a_bits_data; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_out_0_a_bits_corrupt; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_out_0_d_ready; // @[SystemBus.scala:47:43]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_valid_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_opcode_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_param_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_size_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_source_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_address_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_mask_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_data_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_corrupt_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_ready_0 = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_1_clock_0 = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_1_reset_0 = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_0_clock_0 = auto_sbus_clock_groups_in_member_sbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_0_reset_0 = auto_sbus_clock_groups_in_member_sbus_0_reset; // @[ClockDomain.scala:14:9]
wire [1:0] fixer__allIDs_FIFOed_T_1 = 2'h3; // @[FIFOFixer.scala:127:48]
wire fixer__a_id_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire fixer__a_id_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire sbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire sbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire sbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixer__a_notFIFO_T_28 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__a_notFIFO_T_59 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire [16:0] fixer__allIDs_FIFOed_T = 17'h1FFFF; // @[FIFOFixer.scala:127:48]
wire [32:0] fixer__a_id_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire sbus_clock_groups_auto_in_member_sbus_1_clock = auto_sbus_clock_groups_in_member_sbus_1_clock_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_1_reset = auto_sbus_clock_groups_in_member_sbus_1_reset_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_0_clock = auto_sbus_clock_groups_in_member_sbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_0_reset = auto_sbus_clock_groups_in_member_sbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire sbus_clock_groups_nodeIn_member_sbus_1_clock = sbus_clock_groups_auto_in_member_sbus_1_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_1_reset = sbus_clock_groups_auto_in_member_sbus_1_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_0_clock = sbus_clock_groups_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_0_reset = sbus_clock_groups_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17]
assign auto_sbus_clock_groups_out_member_coh_0_clock_0 = sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17]
assign auto_sbus_clock_groups_out_member_coh_0_reset_0 = sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_sbus_0_clock = sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_sbus_0_reset = sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign sbus_clock_groups_x1_nodeOut_member_coh_0_clock = sbus_clock_groups_nodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_x1_nodeOut_member_coh_0_reset = sbus_clock_groups_nodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_nodeOut_member_sbus_0_clock = sbus_clock_groups_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_nodeOut_member_sbus_0_reset = sbus_clock_groups_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_auto_out_0_member_sbus_0_clock = sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_0_member_sbus_0_reset = sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_1_member_coh_0_clock = sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_1_member_coh_0_reset = sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire clockGroup_nodeIn_member_sbus_0_clock = clockGroup_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_sbus_0_reset = clockGroup_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixer_x1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_auto_tl_out_a_ready = fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_ibex_tile_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_valid = fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_ibex_tile_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_a_bits_opcode = fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_ibex_tile_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_a_bits_param = fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_ibex_tile_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_a_bits_size = fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire coupler_from_ibex_tile_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_bits_source = fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_ibex_tile_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_a_bits_address = fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_ibex_tile_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_a_bits_mask = fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_ibex_tile_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_a_bits_data = fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_ibex_tile_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_bits_corrupt = fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_ibex_tile_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_d_ready = fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_auto_tl_out_d_valid = fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_ibex_tile_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_ibex_tile_auto_tl_out_d_bits_param = fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_ibex_tile_auto_tl_out_d_bits_size = fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_auto_tl_out_d_bits_source = fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_ibex_tile_auto_tl_out_d_bits_sink = fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_auto_tl_out_d_bits_denied = fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_ibex_tile_auto_tl_out_d_bits_data = fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire fixer_x1_anonOut_a_ready = fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_d_valid = fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_d_bits_opcode = fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_d_bits_param = fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_d_bits_size = fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_source = fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_d_bits_sink = fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_denied = fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonOut_d_bits_data = fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_corrupt = fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_sink = fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_0_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_5 = fixer_x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_1_a_valid = fixer_x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_opcode = fixer_x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_param = fixer_x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_size = fixer_x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_source = fixer_x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_address = fixer_x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_mask = fixer_x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_data = fixer_x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_corrupt = fixer_x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_d_ready = fixer_x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_d_valid = fixer_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_opcode = fixer_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_param = fixer_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_size = fixer_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_source = fixer_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_sink = fixer_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_denied = fixer_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_data = fixer_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_corrupt = fixer_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_0_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_0_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_a_ready = fixer_x1_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_5 = fixer_x1_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonOut_a_bits_opcode = fixer_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_param = fixer_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_size = fixer_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_source = fixer_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_address = fixer_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T_31 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T_5 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_x1_anonOut_a_bits_mask = fixer_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_data = fixer_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_corrupt = fixer_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_d_ready = fixer_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_1_d_valid = fixer_x1_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_opcode = fixer_x1_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_param = fixer_x1_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_size = fixer_x1_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_source = fixer_x1_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_sink = fixer_x1_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_denied = fixer_x1_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_data = fixer_x1_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_corrupt = fixer_x1_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_2 = fixer__a_notFIFO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_3 = fixer__a_notFIFO_T_2; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_4 = fixer__a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_5 = {fixer_anonIn_a_bits_address[31:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_6 = {1'h0, fixer__a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_7 = fixer__a_notFIFO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_8 = fixer__a_notFIFO_T_7; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_9 = fixer__a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_10 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_11 = {1'h0, fixer__a_notFIFO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_12 = fixer__a_notFIFO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_13 = fixer__a_notFIFO_T_12; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_14 = fixer__a_notFIFO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_15 = fixer__a_notFIFO_T_4 | fixer__a_notFIFO_T_9; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_16 = fixer__a_notFIFO_T_15 | fixer__a_notFIFO_T_14; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_17 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_18 = {1'h0, fixer__a_notFIFO_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_19 = fixer__a_notFIFO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_20 = fixer__a_notFIFO_T_19; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_21 = fixer__a_notFIFO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_22 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_23 = {1'h0, fixer__a_notFIFO_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_24 = fixer__a_notFIFO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_25 = fixer__a_notFIFO_T_24; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_26 = fixer__a_notFIFO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_27 = fixer__a_notFIFO_T_21 | fixer__a_notFIFO_T_26; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_29 = fixer__a_notFIFO_T_27; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_30 = fixer__a_notFIFO_T_29; // @[Mux.scala:30:73]
wire fixer_a_notFIFO = fixer__a_notFIFO_T_30; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [9:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [9:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [10:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[9:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [9:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [9:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [9:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [10:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[9:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [9:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [9:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_16; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T = ~fixer_a_notFIFO; // @[Mux.scala:30:73]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [16:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [16:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [16:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [31:0] fixer__SourceIdSet_T = 32'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T & ~fixer_a_notFIFO ? fixer__SourceIdSet_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [31:0] fixer__SourceIdClear_T = 32'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [16:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire [32:0] fixer__a_notFIFO_T_32 = {1'h0, fixer__a_notFIFO_T_31}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_33 = fixer__a_notFIFO_T_32 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_34 = fixer__a_notFIFO_T_33; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_35 = fixer__a_notFIFO_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_36 = {fixer_x1_anonIn_a_bits_address[31:17], fixer_x1_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_37 = {1'h0, fixer__a_notFIFO_T_36}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_38 = fixer__a_notFIFO_T_37 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_39 = fixer__a_notFIFO_T_38; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_40 = fixer__a_notFIFO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_41 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_42 = {1'h0, fixer__a_notFIFO_T_41}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_43 = fixer__a_notFIFO_T_42 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_44 = fixer__a_notFIFO_T_43; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_45 = fixer__a_notFIFO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_46 = fixer__a_notFIFO_T_35 | fixer__a_notFIFO_T_40; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_47 = fixer__a_notFIFO_T_46 | fixer__a_notFIFO_T_45; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_48 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_49 = {1'h0, fixer__a_notFIFO_T_48}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_50 = fixer__a_notFIFO_T_49 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_51 = fixer__a_notFIFO_T_50; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_52 = fixer__a_notFIFO_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_53 = fixer_x1_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_54 = {1'h0, fixer__a_notFIFO_T_53}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_55 = fixer__a_notFIFO_T_54 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_56 = fixer__a_notFIFO_T_55; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_57 = fixer__a_notFIFO_T_56 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_58 = fixer__a_notFIFO_T_52 | fixer__a_notFIFO_T_57; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_60 = fixer__a_notFIFO_T_58; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_61 = fixer__a_notFIFO_T_60; // @[Mux.scala:30:73]
wire fixer_a_notFIFO_1 = fixer__a_notFIFO_T_61; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T_1 = fixer_x1_anonIn_a_ready & fixer_x1_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_4 = fixer__a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_5 = ~fixer__a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] fixer_a_first_beats1_decode_1 = fixer__a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T_1 = fixer_x1_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata_1 = ~fixer__a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [9:0] fixer_a_first_beats1_1 = fixer_a_first_beats1_opdata_1 ? fixer_a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [9:0] fixer_a_first_counter_1; // @[Edges.scala:229:27]
wire [10:0] fixer__a_first_counter1_T_1 = {1'h0, fixer_a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] fixer_a_first_counter1_1 = fixer__a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28]
wire fixer_a_first_1 = fixer_a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T_2 = fixer_a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_3 = fixer_a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last_1 = fixer__a_first_last_T_2 | fixer__a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done_1 = fixer_a_first_last_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35]
wire [9:0] fixer__a_first_count_T_1 = ~fixer_a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [9:0] fixer_a_first_count_1 = fixer_a_first_beats1_1 & fixer__a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] fixer__a_first_counter_T_1 = fixer_a_first_1 ? fixer_a_first_beats1_1 : fixer_a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_2 = fixer_x1_anonOut_d_ready & fixer_x1_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_4 = fixer__d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_5 = ~fixer__d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] fixer_d_first_beats1_decode_1 = fixer__d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata_1 = fixer_x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [9:0] fixer_d_first_beats1_1 = fixer_d_first_beats1_opdata_1 ? fixer_d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] fixer_d_first_counter_1; // @[Edges.scala:229:27]
wire [10:0] fixer__d_first_counter1_T_1 = {1'h0, fixer_d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] fixer_d_first_counter1_1 = fixer__d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first_1 = fixer_d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T_2 = fixer_d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_3 = fixer_d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last_1 = fixer__d_first_last_T_2 | fixer__d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done_1 = fixer_d_first_last_1 & fixer__d_first_T_2; // @[Decoupled.scala:51:35]
wire [9:0] fixer__d_first_count_T_1 = ~fixer_d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [9:0] fixer_d_first_count_1 = fixer_d_first_beats1_1 & fixer__d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] fixer__d_first_counter_T_1 = fixer_d_first_first_1 ? fixer_d_first_beats1_1 : fixer_d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_3 = fixer_x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first_1 = fixer_d_first_first_1 & fixer__d_first_T_3; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_1_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_1; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T_1 = ~fixer_a_notFIFO_1; // @[Mux.scala:30:73]
wire fixer__T_32 = fixer_x1_anonIn_d_ready & fixer_x1_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_x1_anonOut_a_valid = fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonIn_a_ready = fixer__anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33]
reg [1:0] fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35]
wire [1:0] fixer_SourceIdSet_1; // @[FIFOFixer.scala:116:36]
wire [1:0] fixer_SourceIdClear_1; // @[FIFOFixer.scala:117:38]
wire [1:0] fixer__SourceIdSet_T_1 = 2'h1 << fixer_x1_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet_1 = fixer_a_first_1 & fixer__a_first_T_1 & ~fixer_a_notFIFO_1 ? fixer__SourceIdSet_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [1:0] fixer__SourceIdClear_T_1 = 2'h1 << fixer_x1_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear_1 = fixer_d_first_1 & fixer__T_32 ? fixer__SourceIdClear_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [1:0] fixer__SourceIdFIFOed_T_1 = fixer_SourceIdFIFOed_1 | fixer_SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed_1 = &fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_a_ready = coupler_to_bus_named_coh_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_valid = coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_d_ready = coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_d_valid = coupler_to_bus_named_coh_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_param = coupler_to_bus_named_coh_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_size = coupler_to_bus_named_coh_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_source = coupler_to_bus_named_coh_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_sink = coupler_to_bus_named_coh_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_denied = coupler_to_bus_named_coh_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_data = coupler_to_bus_named_coh_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_in_a_ready = coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonOut_a_valid = coupler_to_bus_named_coh_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_param = coupler_to_bus_named_coh_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_size = coupler_to_bus_named_coh_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_source = coupler_to_bus_named_coh_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_address = coupler_to_bus_named_coh_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_mask = coupler_to_bus_named_coh_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_data = coupler_to_bus_named_coh_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_d_ready = coupler_to_bus_named_coh_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_valid = coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_ibex_tile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_ready_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_tlMasterClockXingIn_a_valid = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_opcode = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_param = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_size = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_source = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_address = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_mask = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_data = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_corrupt = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_tlMasterClockXingIn_d_ready = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_ibex_tile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_valid_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_opcode_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_param_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_size_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_source_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_sink_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_denied_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_data_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_corrupt_0 = coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_ibex_tile_tlOut_a_ready = coupler_from_ibex_tile_auto_tl_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_valid = coupler_from_ibex_tile_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_ibex_tile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_opcode = coupler_from_ibex_tile_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_ibex_tile_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_param = coupler_from_ibex_tile_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_ibex_tile_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_size = coupler_from_ibex_tile_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire coupler_from_ibex_tile_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_source = coupler_from_ibex_tile_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_ibex_tile_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_address = coupler_from_ibex_tile_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_ibex_tile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_mask = coupler_from_ibex_tile_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_ibex_tile_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_data = coupler_from_ibex_tile_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_ibex_tile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_corrupt = coupler_from_ibex_tile_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_ibex_tile_tlOut_d_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_d_ready = coupler_from_ibex_tile_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_ibex_tile_tlOut_d_valid = coupler_from_ibex_tile_auto_tl_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_ibex_tile_tlOut_d_bits_opcode = coupler_from_ibex_tile_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_ibex_tile_tlOut_d_bits_param = coupler_from_ibex_tile_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_ibex_tile_tlOut_d_bits_size = coupler_from_ibex_tile_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlOut_d_bits_source = coupler_from_ibex_tile_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_ibex_tile_tlOut_d_bits_sink = coupler_from_ibex_tile_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlOut_d_bits_denied = coupler_from_ibex_tile_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_ibex_tile_tlOut_d_bits_data = coupler_from_ibex_tile_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlOut_d_bits_corrupt = coupler_from_ibex_tile_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlIn_a_ready = coupler_from_ibex_tile_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_valid = coupler_from_ibex_tile_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_ibex_tile_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_bits_opcode = coupler_from_ibex_tile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_ibex_tile_tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_bits_param = coupler_from_ibex_tile_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_ibex_tile_tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_bits_size = coupler_from_ibex_tile_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_bits_source = coupler_from_ibex_tile_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_ibex_tile_tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_bits_address = coupler_from_ibex_tile_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_ibex_tile_tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_bits_mask = coupler_from_ibex_tile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_ibex_tile_tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_bits_data = coupler_from_ibex_tile_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_a_bits_corrupt = coupler_from_ibex_tile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_out_d_ready = coupler_from_ibex_tile_tlOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_ibex_tile_tlIn_d_valid = coupler_from_ibex_tile_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_tlIn_d_bits_opcode = coupler_from_ibex_tile_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_ibex_tile_tlIn_d_bits_param = coupler_from_ibex_tile_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_tlIn_d_bits_size = coupler_from_ibex_tile_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlIn_d_bits_source = coupler_from_ibex_tile_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_tlIn_d_bits_sink = coupler_from_ibex_tile_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlIn_d_bits_denied = coupler_from_ibex_tile_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_tlIn_d_bits_data = coupler_from_ibex_tile_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlIn_d_bits_corrupt = coupler_from_ibex_tile_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_a_ready = coupler_from_ibex_tile_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_valid = coupler_from_ibex_tile_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_bits_opcode = coupler_from_ibex_tile_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_bits_param = coupler_from_ibex_tile_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_bits_size = coupler_from_ibex_tile_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_bits_source = coupler_from_ibex_tile_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_bits_address = coupler_from_ibex_tile_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_bits_mask = coupler_from_ibex_tile_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_bits_data = coupler_from_ibex_tile_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_a_bits_corrupt = coupler_from_ibex_tile_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_tlOut_d_ready = coupler_from_ibex_tile_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_d_valid = coupler_from_ibex_tile_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_no_bufferOut_d_bits_opcode = coupler_from_ibex_tile_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_ibex_tile_no_bufferOut_d_bits_param = coupler_from_ibex_tile_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_no_bufferOut_d_bits_size = coupler_from_ibex_tile_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_d_bits_source = coupler_from_ibex_tile_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_no_bufferOut_d_bits_sink = coupler_from_ibex_tile_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_d_bits_denied = coupler_from_ibex_tile_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_no_bufferOut_d_bits_data = coupler_from_ibex_tile_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferOut_d_bits_corrupt = coupler_from_ibex_tile_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_a_ready = coupler_from_ibex_tile_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_valid = coupler_from_ibex_tile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_bits_opcode = coupler_from_ibex_tile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_bits_param = coupler_from_ibex_tile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_bits_size = coupler_from_ibex_tile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_bits_source = coupler_from_ibex_tile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_bits_address = coupler_from_ibex_tile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_bits_mask = coupler_from_ibex_tile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_bits_data = coupler_from_ibex_tile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_a_bits_corrupt = coupler_from_ibex_tile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlIn_d_ready = coupler_from_ibex_tile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_d_valid = coupler_from_ibex_tile_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_no_bufferIn_d_bits_opcode = coupler_from_ibex_tile_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_ibex_tile_no_bufferIn_d_bits_param = coupler_from_ibex_tile_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_no_bufferIn_d_bits_size = coupler_from_ibex_tile_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_d_bits_source = coupler_from_ibex_tile_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_no_bufferIn_d_bits_sink = coupler_from_ibex_tile_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_d_bits_denied = coupler_from_ibex_tile_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_no_bufferIn_d_bits_data = coupler_from_ibex_tile_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_no_bufferIn_d_bits_corrupt = coupler_from_ibex_tile_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_a_ready = coupler_from_ibex_tile_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_valid = coupler_from_ibex_tile_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_bits_opcode = coupler_from_ibex_tile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_bits_param = coupler_from_ibex_tile_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_bits_size = coupler_from_ibex_tile_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_bits_source = coupler_from_ibex_tile_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_bits_address = coupler_from_ibex_tile_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_bits_mask = coupler_from_ibex_tile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_bits_data = coupler_from_ibex_tile_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_a_bits_corrupt = coupler_from_ibex_tile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_ibex_tile_no_bufferOut_d_ready = coupler_from_ibex_tile_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_d_valid = coupler_from_ibex_tile_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_opcode = coupler_from_ibex_tile_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_param = coupler_from_ibex_tile_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_size = coupler_from_ibex_tile_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_source = coupler_from_ibex_tile_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_sink = coupler_from_ibex_tile_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_denied = coupler_from_ibex_tile_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_data = coupler_from_ibex_tile_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_corrupt = coupler_from_ibex_tile_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_a_ready = coupler_from_ibex_tile_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_valid = coupler_from_ibex_tile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_bits_opcode = coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_bits_param = coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_bits_size = coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_bits_source = coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_bits_address = coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_bits_mask = coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_bits_data = coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_a_bits_corrupt = coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_no_bufferIn_d_ready = coupler_from_ibex_tile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_valid = coupler_from_ibex_tile_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_opcode = coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_param = coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_size = coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_source = coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_sink = coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_denied = coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_data = coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_corrupt = coupler_from_ibex_tile_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_a_ready = coupler_from_ibex_tile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_valid = coupler_from_ibex_tile_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_opcode = coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_param = coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_size = coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_source = coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_address = coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_mask = coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_data = coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_a_bits_corrupt = coupler_from_ibex_tile_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_tlMasterClockXingOut_d_ready = coupler_from_ibex_tile_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_valid = coupler_from_ibex_tile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_ibex_tile_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_ibex_tile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
wire fixer__T_31 = fixer_a_first_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35]
wire fixer__T_33 = fixer_d_first_1 & fixer__T_32; // @[Decoupled.scala:51:35]
always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31]
if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31]
fixer_a_first_counter <= 10'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 10'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 17'h0; // @[FIFOFixer.scala:115:35]
fixer_a_first_counter_1 <= 10'h0; // @[Edges.scala:229:27]
fixer_d_first_counter_1 <= 10'h0; // @[Edges.scala:229:27]
fixer_flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed_1 <= 2'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[LazyModuleImp.scala:155:31]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h0 ? fixer__flight_T : fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h1 ? fixer__flight_T : fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h2 ? fixer__flight_T : fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h3 ? fixer__flight_T : fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h4 ? fixer__flight_T : fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h5 ? fixer__flight_T : fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h6 ? fixer__flight_T : fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h7 ? fixer__flight_T : fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h8 ? fixer__flight_T : fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h9 ? fixer__flight_T : fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hA ? fixer__flight_T : fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hB ? fixer__flight_T : fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hC ? fixer__flight_T : fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hD ? fixer__flight_T : fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hE ? fixer__flight_T : fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hF ? fixer__flight_T : fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h10 ? fixer__flight_T : fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
if (fixer__a_first_T_1) // @[Decoupled.scala:51:35]
fixer_a_first_counter_1 <= fixer__a_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T_2) // @[Decoupled.scala:51:35]
fixer_d_first_counter_1 <= fixer__d_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
fixer_flight_1_0 <= ~(fixer__T_33 & ~fixer_x1_anonIn_d_bits_source) & (fixer__T_31 & ~fixer_x1_anonIn_a_bits_source ? fixer__flight_T_1 : fixer_flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_1 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source ? fixer__flight_T_1 : fixer_flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed_1 <= fixer__SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40]
end
always @(posedge)
FixedClockBroadcast_4 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0),
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_sbus_i2_o2_a32d32s6k3z4u system_bus_xbar ( // @[SystemBus.scala:47:43]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_1_a_ready (fixer_auto_anon_out_1_a_ready),
.auto_anon_in_1_a_valid (fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_opcode (fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_param (fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_size (fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_source (fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_address (fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_mask (fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_data (fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_corrupt (fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_d_ready (fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_d_valid (fixer_auto_anon_out_1_d_valid),
.auto_anon_in_1_d_bits_opcode (fixer_auto_anon_out_1_d_bits_opcode),
.auto_anon_in_1_d_bits_param (fixer_auto_anon_out_1_d_bits_param),
.auto_anon_in_1_d_bits_size (fixer_auto_anon_out_1_d_bits_size),
.auto_anon_in_1_d_bits_source (fixer_auto_anon_out_1_d_bits_source),
.auto_anon_in_1_d_bits_sink (fixer_auto_anon_out_1_d_bits_sink),
.auto_anon_in_1_d_bits_denied (fixer_auto_anon_out_1_d_bits_denied),
.auto_anon_in_1_d_bits_data (fixer_auto_anon_out_1_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (fixer_auto_anon_out_1_d_bits_corrupt),
.auto_anon_in_0_a_ready (fixer_auto_anon_out_0_a_ready),
.auto_anon_in_0_a_valid (fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_opcode (fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_param (fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_size (fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_source (fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_address (fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_mask (fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_data (fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_corrupt (fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_d_ready (fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_d_valid (fixer_auto_anon_out_0_d_valid),
.auto_anon_in_0_d_bits_opcode (fixer_auto_anon_out_0_d_bits_opcode),
.auto_anon_in_0_d_bits_param (fixer_auto_anon_out_0_d_bits_param),
.auto_anon_in_0_d_bits_size (fixer_auto_anon_out_0_d_bits_size),
.auto_anon_in_0_d_bits_source (fixer_auto_anon_out_0_d_bits_source),
.auto_anon_in_0_d_bits_sink (fixer_auto_anon_out_0_d_bits_sink),
.auto_anon_in_0_d_bits_denied (fixer_auto_anon_out_0_d_bits_denied),
.auto_anon_in_0_d_bits_data (fixer_auto_anon_out_0_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (fixer_auto_anon_out_0_d_bits_corrupt),
.auto_anon_out_1_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_a_valid),
.auto_anon_out_1_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode),
.auto_anon_out_1_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param),
.auto_anon_out_1_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size),
.auto_anon_out_1_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source),
.auto_anon_out_1_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address),
.auto_anon_out_1_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask),
.auto_anon_out_1_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt),
.auto_anon_out_1_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_d_ready),
.auto_anon_out_1_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_a_ready (_coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_valid (_system_bus_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_system_bus_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_system_bus_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_system_bus_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_system_bus_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_system_bus_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_system_bus_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_system_bus_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_system_bus_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_system_bus_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_opcode (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_param (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_size (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_source (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_sink (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_denied (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_data (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_corrupt (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27]
); // @[SystemBus.scala:47:43]
TLInterconnectCoupler_sbus_to_bus_named_cbus coupler_to_bus_named_cbus ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_widget_anon_in_a_ready (_coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready),
.auto_widget_anon_in_a_valid (_system_bus_xbar_auto_anon_out_0_a_valid), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_opcode (_system_bus_xbar_auto_anon_out_0_a_bits_opcode), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_param (_system_bus_xbar_auto_anon_out_0_a_bits_param), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_size (_system_bus_xbar_auto_anon_out_0_a_bits_size), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_source (_system_bus_xbar_auto_anon_out_0_a_bits_source), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_address (_system_bus_xbar_auto_anon_out_0_a_bits_address), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_mask (_system_bus_xbar_auto_anon_out_0_a_bits_mask), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_data (_system_bus_xbar_auto_anon_out_0_a_bits_data), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_corrupt (_system_bus_xbar_auto_anon_out_0_a_bits_corrupt), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_d_ready (_system_bus_xbar_auto_anon_out_0_d_ready), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_d_valid (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid),
.auto_widget_anon_in_d_bits_opcode (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode),
.auto_widget_anon_in_d_bits_param (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param),
.auto_widget_anon_in_d_bits_size (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size),
.auto_widget_anon_in_d_bits_source (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source),
.auto_widget_anon_in_d_bits_sink (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink),
.auto_widget_anon_in_d_bits_denied (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied),
.auto_widget_anon_in_d_bits_data (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data),
.auto_widget_anon_in_d_bits_corrupt (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt),
.auto_bus_xing_out_a_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_a_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0),
.auto_bus_xing_out_a_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0),
.auto_bus_xing_out_a_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0),
.auto_bus_xing_out_a_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0),
.auto_bus_xing_out_a_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0),
.auto_bus_xing_out_a_bits_address (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0),
.auto_bus_xing_out_a_bits_mask (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0),
.auto_bus_xing_out_a_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0),
.auto_bus_xing_out_a_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0),
.auto_bus_xing_out_d_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0),
.auto_bus_xing_out_d_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_sink (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_denied (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0) // @[ClockDomain.scala:14:9]
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_sbus_from_bus_named_fbus coupler_from_bus_named_fbus ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_widget_anon_out_a_ready (fixer_auto_anon_in_0_a_ready), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_a_valid (fixer_auto_anon_in_0_a_valid),
.auto_widget_anon_out_a_bits_opcode (fixer_auto_anon_in_0_a_bits_opcode),
.auto_widget_anon_out_a_bits_param (fixer_auto_anon_in_0_a_bits_param),
.auto_widget_anon_out_a_bits_size (fixer_auto_anon_in_0_a_bits_size),
.auto_widget_anon_out_a_bits_source (fixer_auto_anon_in_0_a_bits_source),
.auto_widget_anon_out_a_bits_address (fixer_auto_anon_in_0_a_bits_address),
.auto_widget_anon_out_a_bits_mask (fixer_auto_anon_in_0_a_bits_mask),
.auto_widget_anon_out_a_bits_data (fixer_auto_anon_in_0_a_bits_data),
.auto_widget_anon_out_a_bits_corrupt (fixer_auto_anon_in_0_a_bits_corrupt),
.auto_widget_anon_out_d_ready (fixer_auto_anon_in_0_d_ready),
.auto_widget_anon_out_d_valid (fixer_auto_anon_in_0_d_valid), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_opcode (fixer_auto_anon_in_0_d_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_param (fixer_auto_anon_in_0_d_bits_param), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_size (fixer_auto_anon_in_0_d_bits_size), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_source (fixer_auto_anon_in_0_d_bits_source), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_sink (fixer_auto_anon_in_0_d_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_denied (fixer_auto_anon_in_0_d_bits_denied), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_data (fixer_auto_anon_in_0_d_bits_data), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_corrupt (fixer_auto_anon_in_0_d_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_bus_xing_in_a_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0),
.auto_bus_xing_in_a_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_address (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_mask (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_d_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_d_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0),
.auto_bus_xing_in_d_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0),
.auto_bus_xing_in_d_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0),
.auto_bus_xing_in_d_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0),
.auto_bus_xing_in_d_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0),
.auto_bus_xing_in_d_bits_sink (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0),
.auto_bus_xing_in_d_bits_denied (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0),
.auto_bus_xing_in_d_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0),
.auto_bus_xing_in_d_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0)
); // @[LazyScope.scala:98:27]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_ready = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_valid = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_opcode = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_param = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_size = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_source = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_sink = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_denied = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_data = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_corrupt = auto_coupler_from_ibex_tile_tl_master_clock_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_24( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to the following Chisel files.
File RouteComputer.scala:
package constellation.router
import chisel3._
import chisel3.util._
import chisel3.util.experimental.decode.{TruthTable, decoder}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import freechips.rocketchip.rocket.DecodeLogic
import constellation.channel._
import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo}
import constellation.noc.{HasNoCParams}
class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams {
val src_virt_id = UInt(virtualChannelBits.W)
val flow = new FlowRoutingBundle
}
class RouteComputerResp(
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle
with HasRouterOutputParams {
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
}
class RouteComputer(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams
with HasNoCParams {
val io = IO(new Bundle {
val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) })
val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) })
})
(io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) =>
req.ready := true.B
if (outParams.size == 0) {
assert(!req.valid)
resp.vc_sel := DontCare
} else {
def toUInt(t: (Int, FlowRoutingInfo)): UInt = {
val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) | t._2.vNetId
val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) | t._2.ingressNode
val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) | t._2.ingressNodeId
val l5 = ( l4 << req.bits.flow.egress_node .getWidth) | t._2.egressNode
val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) | t._2.egressNodeId
l6.U(req.bits.getWidth.W)
}
val flow = req.bits.flow
val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI =>
allInParams(i).channelRoutingInfos.map { cI =>
var row: String = "b"
(0 until nOutputs).foreach { o =>
(0 until outParams(o).nVirtualChannels).foreach { outVId =>
row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0")
}
}
((cI.vc, pI), row)
}
}.flatten
val addr = req.bits.asUInt
val width = outParams.map(_.nVirtualChannels).reduce(_+_)
val decoded = if (table.size > 0) {
val truthTable = TruthTable(
table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) },
BitPat("b" + "?" * width)
)
Reverse(decoder(addr, truthTable))
} else {
0.U(width.W)
}
var idx = 0
(0 until nAllOutputs).foreach { o =>
if (o < nOutputs) {
(0 until outParams(o).nVirtualChannels).foreach { outVId =>
resp.vc_sel(o)(outVId) := decoded(idx)
idx += 1
}
} else {
resp.vc_sel(o)(0) := false.B
}
}
}
}
}
| module RouteComputer_60( // @[RouteComputer.scala:29:7]
input [3:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [2:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [2:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_8, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_9, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_8, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_9, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_9, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_9 // @[RouteComputer.scala:40:14]
);
wire [18:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[2:0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [18:0] decoded_invInputs_1 = ~{io_req_1_bits_src_virt_id, io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id[2:1]}; // @[pla.scala:78:21]
wire [3:0] _decoded_andMatrixOutputs_T_2 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_src_virt_id[1], decoded_invInputs_1[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [3:0] _decoded_andMatrixOutputs_T_3 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_src_virt_id[2], decoded_invInputs_1[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [3:0] _decoded_andMatrixOutputs_T_4 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[16], decoded_invInputs_1[17], io_req_1_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [18:0] decoded_invInputs_2 = ~{io_req_2_bits_src_virt_id, io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id[2:1]}; // @[pla.scala:78:21]
wire [3:0] _decoded_andMatrixOutputs_T_5 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [3:0] _decoded_andMatrixOutputs_T_6 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [3:0] _decoded_andMatrixOutputs_T_7 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
assign io_resp_2_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_8 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_9 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_8 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_9 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_2_9 = &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[17], decoded_invInputs[18], io_req_0_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_0_vc_sel_1_9 = &{decoded_invInputs[0], decoded_invInputs[17], decoded_invInputs[18], io_req_0_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Switch.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel.{ChannelParams, IngressChannelParams, EgressChannelParams, Flit}
class SwitchBundle(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams{
val flit = new Flit(allOutParams(0).payloadBits)
val out_virt_channel = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
}
class Switch(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams {
val io = IO(new Bundle {
val in = MixedVec(allInParams.map { u => Vec(u.destSpeedup,
Input(Valid(new SwitchBundle(outParams, egressParams)))) })
val out = MixedVec(allOutParams.map { u => Vec(u.srcSpeedup,
Output(Valid(new Flit(u.payloadBits)))) })
val sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup,
MixedVec(allInParams.map { i => Vec(i.destSpeedup, Input(Bool())) })) })
})
val in_flat = Wire(Vec(allInParams.map(_.destSpeedup).reduce(_+_),
Valid(new SwitchBundle(outParams, egressParams))))
var idx = 0
io.in.foreach(_.foreach { i =>
in_flat(idx) := i
idx += 1
})
for (i <- 0 until nAllOutputs) {
for (j <- 0 until allOutParams(i).srcSpeedup) {
val sel_flat = io.sel(i)(j).asUInt
assert(PopCount(sel_flat) <= 1.U)
io.out(i)(j).valid := Mux1H(sel_flat, in_flat.map(_.valid)) && sel_flat =/= 0.U
io.out(i)(j).bits := Mux1H(sel_flat, in_flat.map(_.bits.flit))
io.out(i)(j).bits.virt_channel_id := Mux1H(sel_flat, in_flat.map(_.bits.out_virt_channel))
}
}
}
| module Switch_47( // @[Switch.scala:16:7]
input clock, // @[Switch.scala:16:7]
input reset, // @[Switch.scala:16:7]
input io_in_4_0_valid, // @[Switch.scala:27:14]
input io_in_4_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_4_0_bits_flit_tail, // @[Switch.scala:27:14]
input [72:0] io_in_4_0_bits_flit_payload, // @[Switch.scala:27:14]
input [2:0] io_in_4_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_4_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_4_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_4_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [2:0] io_in_4_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_4_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_2_0_valid, // @[Switch.scala:27:14]
input io_in_2_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_2_0_bits_flit_tail, // @[Switch.scala:27:14]
input [72:0] io_in_2_0_bits_flit_payload, // @[Switch.scala:27:14]
input [2:0] io_in_2_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_2_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_2_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_2_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [2:0] io_in_2_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_2_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_0_0_valid, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14]
input [72:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14]
input [2:0] io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [2:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
output io_out_6_0_valid, // @[Switch.scala:27:14]
output io_out_6_0_bits_head, // @[Switch.scala:27:14]
output io_out_6_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_6_0_bits_payload, // @[Switch.scala:27:14]
output io_out_5_0_valid, // @[Switch.scala:27:14]
output io_out_5_0_bits_head, // @[Switch.scala:27:14]
output io_out_5_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_5_0_bits_payload, // @[Switch.scala:27:14]
output io_out_4_0_valid, // @[Switch.scala:27:14]
output io_out_4_0_bits_head, // @[Switch.scala:27:14]
output io_out_4_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_4_0_bits_payload, // @[Switch.scala:27:14]
output [3:0] io_out_4_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_4_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output io_out_3_0_valid, // @[Switch.scala:27:14]
output io_out_3_0_bits_head, // @[Switch.scala:27:14]
output io_out_3_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_3_0_bits_payload, // @[Switch.scala:27:14]
output io_out_2_0_valid, // @[Switch.scala:27:14]
output io_out_2_0_bits_head, // @[Switch.scala:27:14]
output io_out_2_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_2_0_bits_payload, // @[Switch.scala:27:14]
output io_out_1_0_valid, // @[Switch.scala:27:14]
output io_out_1_0_bits_head, // @[Switch.scala:27:14]
output io_out_1_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14]
output io_out_0_0_valid, // @[Switch.scala:27:14]
output io_out_0_0_bits_head, // @[Switch.scala:27:14]
output io_out_0_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14]
output [2:0] io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output [2:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14]
input io_sel_6_0_4_0, // @[Switch.scala:27:14]
input io_sel_6_0_2_0, // @[Switch.scala:27:14]
input io_sel_6_0_0_0, // @[Switch.scala:27:14]
input io_sel_5_0_4_0, // @[Switch.scala:27:14]
input io_sel_5_0_2_0, // @[Switch.scala:27:14]
input io_sel_5_0_0_0, // @[Switch.scala:27:14]
input io_sel_4_0_4_0, // @[Switch.scala:27:14]
input io_sel_4_0_2_0, // @[Switch.scala:27:14]
input io_sel_4_0_0_0, // @[Switch.scala:27:14]
input io_sel_3_0_4_0, // @[Switch.scala:27:14]
input io_sel_3_0_2_0, // @[Switch.scala:27:14]
input io_sel_3_0_0_0, // @[Switch.scala:27:14]
input io_sel_2_0_4_0, // @[Switch.scala:27:14]
input io_sel_2_0_2_0, // @[Switch.scala:27:14]
input io_sel_2_0_0_0, // @[Switch.scala:27:14]
input io_sel_1_0_4_0, // @[Switch.scala:27:14]
input io_sel_1_0_2_0, // @[Switch.scala:27:14]
input io_sel_1_0_0_0, // @[Switch.scala:27:14]
input io_sel_0_0_4_0, // @[Switch.scala:27:14]
input io_sel_0_0_2_0 // @[Switch.scala:27:14]
); |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_219( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_475 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to
Chisel by Andrew Waterman).
Copyright 2019, 2020 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf)
val notNaN_isInfOut = io.a.isInf || io.b.isInf
val notNaN_isZeroOut = io.a.isZero || io.b.isZero
val notNaN_signOut = io.a.sign ^ io.b.sign
val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S
val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc
io.rawOut.isInf := notNaN_isInfOut
io.rawOut.isZero := notNaN_isZeroOut
io.rawOut.sExp := common_sExpOut
io.rawOut.isNaN := io.a.isNaN || io.b.isNaN
io.rawOut.sign := notNaN_signOut
io.rawOut.sig := common_sigOut
}
class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth))
mulFullRaw.io.a := io.a
mulFullRaw.io.b := io.b
io.invalidExc := mulFullRaw.io.invalidExc
io.rawOut := mulFullRaw.io.rawOut
io.rawOut.sig := {
val sig = mulFullRaw.io.rawOut.sig
Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR)
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulRawFN = Module(new MulRawFN(expWidth, sigWidth))
mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulRawFN.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulFullRawFN_49( // @[MulRecFN.scala:47:7]
input io_a_isNaN, // @[MulRecFN.scala:49:16]
input io_a_isInf, // @[MulRecFN.scala:49:16]
input io_a_isZero, // @[MulRecFN.scala:49:16]
input io_a_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:49:16]
input io_b_isNaN, // @[MulRecFN.scala:49:16]
input io_b_isInf, // @[MulRecFN.scala:49:16]
input io_b_isZero, // @[MulRecFN.scala:49:16]
input io_b_sign, // @[MulRecFN.scala:49:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:49:16]
output io_invalidExc, // @[MulRecFN.scala:49:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:49:16]
output io_rawOut_isInf, // @[MulRecFN.scala:49:16]
output io_rawOut_isZero, // @[MulRecFN.scala:49:16]
output io_rawOut_sign, // @[MulRecFN.scala:49:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16]
output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16]
);
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7]
wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71]
wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35]
wire notNaN_isInfOut; // @[MulRecFN.scala:59:38]
wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40]
wire notNaN_signOut; // @[MulRecFN.scala:61:36]
wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48]
wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
wire io_invalidExc_0; // @[MulRecFN.scala:47:7]
wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44]
wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76]
wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}]
assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38]
assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40]
assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40]
assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36]
assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36]
wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36]
wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36]
wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36]
wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}]
wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48]
assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48]
assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48]
wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35]
assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}]
assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46]
wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56]
wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}]
wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}]
wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46]
assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}]
assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71]
assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TLFragmenter_LLCCtrl( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30]
wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [25:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71]
wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49]
wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18]
wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}]
wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}]
wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}]
reg aToggle_r; // @[Fragmenter.scala:309:54] |
Generate the Verilog code corresponding to the following Chisel files.
File INToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in);
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
intAsRawFloat.expWidth,
intWidth,
expWidth,
sigWidth,
flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows
))
roundAnyRawFNToRecFN.io.invalidExc := false.B
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := intAsRawFloat
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File rawFloatFromIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object rawFloatFromIN
{
def apply(signedIn: Bool, in: Bits): RawFloat =
{
val expWidth = log2Up(in.getWidth) + 1
//*** CHANGE THIS; CAN BE VERY LARGE:
val extIntWidth = 1<<(expWidth - 1)
val sign = signedIn && in(in.getWidth - 1)
val absIn = Mux(sign, -in.asUInt, in.asUInt)
val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)
val adjustedNormDist = countLeadingZeros(extAbsIn)
val sig =
(extAbsIn<<adjustedNormDist)(
extIntWidth - 1, extIntWidth - in.getWidth)
val out = Wire(new RawFloat(expWidth, in.getWidth))
out.isNaN := false.B
out.isInf := false.B
out.isZero := ! sig(in.getWidth - 1)
out.sign := sign
out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext
out.sig := sig
out
}
}
| module INToRecFN_i1_e8_s24_26(); // @[INToRecFN.scala:43:7]
wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31]
wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44]
wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22]
wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33]
wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_in = 1'h1; // @[Mux.scala:50:70]
wire io_detectTininess = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70]
wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29]
wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23]
wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36]
RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_26 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_44( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_83( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_353( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_65( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_76 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_10( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLFragmenter_BootAddrReg( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [12:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9]
wire [12:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9]
wire [11:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36]
wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50]
wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50]
wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84]
wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49]
wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire find_0 = 1'h1; // @[Parameters.scala:616:12]
wire [13:0] _find_T_2 = 14'h0; // @[Parameters.scala:137:46]
wire [13:0] _find_T_3 = 14'h0; // @[Parameters.scala:137:46]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [12:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [11:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [12:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9]
wire [11:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [11:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [12:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9]
wire [7:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9]
wire [11:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9]
wire [12:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9]
wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49]
assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41]
wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30]
wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37]
wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}]
wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71]
wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}]
wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45]
wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27]
wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}]
wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47]
wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46]
wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35]
wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}]
wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53]
wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}]
wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}]
wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18]
wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18]
wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28]
wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}]
wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55]
wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55]
wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}]
wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41]
wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20]
wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}]
wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}]
assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39]
assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}]
assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36]
assign _anonIn_d_bits_source_T = anonOut_d_bits_source[11:4]; // @[Fragmenter.scala:238:47]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47]
assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32]
wire [12:0] _find_T; // @[Parameters.scala:137:31]
wire [13:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}]
wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49]
wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31]
wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}]
wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71]
wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}]
wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30]
wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46]
wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79]
wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79]
wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}]
wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40]
wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28]
wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}]
wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}]
wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}]
wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}]
wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}]
wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30]
reg aToggle_r; // @[Fragmenter.scala:309:54]
wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}]
wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}]
wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31]
wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53]
wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}]
wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65]
wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}]
wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}]
wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}]
assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[12:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}]
assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
wire [8:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33]
assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33]
assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25] |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_101( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [4:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [4:0] mask; // @[InputUnit.scala:250:21]
wire [4:0] _vcalloc_filter_T_3 = {3'h0, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {3'h0, vcalloc_vals_1, 6'h0}; // @[OneHot.scala:85:71]
wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_1; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_165( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_421 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Metadata.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import freechips.rocketchip.util._
object ClientStates {
val width = 2
def Nothing = 0.U(width.W)
def Branch = 1.U(width.W)
def Trunk = 2.U(width.W)
def Dirty = 3.U(width.W)
def hasReadPermission(state: UInt): Bool = state > Nothing
def hasWritePermission(state: UInt): Bool = state > Branch
}
object MemoryOpCategories extends MemoryOpConstants {
def wr = Cat(true.B, true.B) // Op actually writes
def wi = Cat(false.B, true.B) // Future op will write
def rd = Cat(false.B, false.B) // Op only reads
def categorize(cmd: UInt): UInt = {
val cat = Cat(isWrite(cmd), isWriteIntent(cmd))
//assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.")
cat
}
}
/** Stores the client-side coherence information,
* such as permissions on the data and whether the data is dirty.
* Its API can be used to make TileLink messages in response to
* memory operations, cache control oeprations, or Probe messages.
*/
class ClientMetadata extends Bundle {
/** Actual state information stored in this bundle */
val state = UInt(ClientStates.width.W)
/** Metadata equality */
def ===(rhs: UInt): Bool = state === rhs
def ===(rhs: ClientMetadata): Bool = state === rhs.state
def =/=(rhs: ClientMetadata): Bool = !this.===(rhs)
/** Is the block's data present in this cache */
def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing
/** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */
private def growStarter(cmd: UInt): (Bool, UInt) = {
import MemoryOpCategories._
import TLPermissions._
import ClientStates._
val c = categorize(cmd)
MuxTLookup(Cat(c, state), (false.B, 0.U), Seq(
//(effect, am now) -> (was a hit, next)
Cat(rd, Dirty) -> (true.B, Dirty),
Cat(rd, Trunk) -> (true.B, Trunk),
Cat(rd, Branch) -> (true.B, Branch),
Cat(wi, Dirty) -> (true.B, Dirty),
Cat(wi, Trunk) -> (true.B, Trunk),
Cat(wr, Dirty) -> (true.B, Dirty),
Cat(wr, Trunk) -> (true.B, Dirty),
//(effect, am now) -> (was a miss, param)
Cat(rd, Nothing) -> (false.B, NtoB),
Cat(wi, Branch) -> (false.B, BtoT),
Cat(wi, Nothing) -> (false.B, NtoT),
Cat(wr, Branch) -> (false.B, BtoT),
Cat(wr, Nothing) -> (false.B, NtoT)))
}
/** Determine what state to go to after miss based on Grant param
* For now, doesn't depend on state (which may have been Probed).
*/
private def growFinisher(cmd: UInt, param: UInt): UInt = {
import MemoryOpCategories._
import TLPermissions._
import ClientStates._
val c = categorize(cmd)
//assert(c === rd || param === toT, "Client was expecting trunk permissions.")
MuxLookup(Cat(c, param), Nothing)(Seq(
//(effect param) -> (next)
Cat(rd, toB) -> Branch,
Cat(rd, toT) -> Trunk,
Cat(wi, toT) -> Trunk,
Cat(wr, toT) -> Dirty))
}
/** Does this cache have permissions on this block sufficient to perform op,
* and what to do next (Acquire message param or updated metadata). */
def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = {
val r = growStarter(cmd)
(r._1, r._2, ClientMetadata(r._2))
}
/** Does a secondary miss on the block require another Acquire message */
def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = {
import MemoryOpCategories._
val r1 = growStarter(first_cmd)
val r2 = growStarter(second_cmd)
val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd)
val hit_again = r1._1 && r2._1
val dirties = categorize(second_cmd) === wr
val biggest_grow_param = Mux(dirties, r2._2, r1._2)
val dirtiest_state = ClientMetadata(biggest_grow_param)
val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd)
(needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd)
}
/** Metadata change on a returned Grant */
def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param))
/** Determine what state to go to based on Probe param */
private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = {
import ClientStates._
import TLPermissions._
MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq(
//(wanted, am now) -> (hasDirtyData resp, next)
Cat(toT, Dirty) -> (true.B, TtoT, Trunk),
Cat(toT, Trunk) -> (false.B, TtoT, Trunk),
Cat(toT, Branch) -> (false.B, BtoB, Branch),
Cat(toT, Nothing) -> (false.B, NtoN, Nothing),
Cat(toB, Dirty) -> (true.B, TtoB, Branch),
Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade
Cat(toB, Branch) -> (false.B, BtoB, Branch),
Cat(toB, Nothing) -> (false.B, NtoN, Nothing),
Cat(toN, Dirty) -> (true.B, TtoN, Nothing),
Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade
Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade
Cat(toN, Nothing) -> (false.B, NtoN, Nothing)))
}
/** Translate cache control cmds into Probe param */
private def cmdToPermCap(cmd: UInt): UInt = {
import MemoryOpCategories._
import TLPermissions._
MuxLookup(cmd, toN)(Seq(
M_FLUSH -> toN,
M_PRODUCE -> toB,
M_CLEAN -> toT))
}
def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(cmdToPermCap(cmd))
(r._1, r._2, ClientMetadata(r._3))
}
def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(param)
(r._1, r._2, ClientMetadata(r._3))
}
}
/** Factories for ClientMetadata, including on reset */
object ClientMetadata {
def apply(perm: UInt) = {
val meta = Wire(new ClientMetadata)
meta.state := perm
meta
}
def onReset = ClientMetadata(ClientStates.Nothing)
def maximum = ClientMetadata(ClientStates.Dirty)
}
File dcache.scala:
//******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.rocket._
import boom.v3.common._
import boom.v3.exu.BrUpdateInfo
import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose}
class BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new WritebackReq(edge.bundle)))
val meta_read = Decoupled(new L1MetaReadReq)
val resp = Output(Bool())
val idx = Output(Valid(UInt()))
val data_req = Decoupled(new L1DataReadReq)
val data_resp = Input(UInt(encRowBits.W))
val mem_grant = Input(Bool())
val release = Decoupled(new TLBundleC(edge.bundle))
val lsu_release = Decoupled(new TLBundleC(edge.bundle))
})
val req = Reg(new WritebackReq(edge.bundle))
val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5)
val state = RegInit(s_invalid)
val r1_data_req_fired = RegInit(false.B)
val r2_data_req_fired = RegInit(false.B)
val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))
val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))
val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W))
val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release)
val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W)))
val acked = RegInit(false.B)
io.idx.valid := state =/= s_invalid
io.idx.bits := req.idx
io.release.valid := false.B
io.release.bits := DontCare
io.req.ready := false.B
io.meta_read.valid := false.B
io.meta_read.bits := DontCare
io.data_req.valid := false.B
io.data_req.bits := DontCare
io.resp := false.B
io.lsu_release.valid := false.B
io.lsu_release.bits := DontCare
val r_address = Cat(req.tag, req.idx) << blockOffBits
val id = cfg.nMSHRs
val probeResponse = edge.ProbeAck(
fromSource = id.U,
toAddress = r_address,
lgSize = lgCacheBlockBytes.U,
reportPermissions = req.param,
data = wb_buffer(data_req_cnt))
val voluntaryRelease = edge.Release(
fromSource = id.U,
toAddress = r_address,
lgSize = lgCacheBlockBytes.U,
shrinkPermissions = req.param,
data = wb_buffer(data_req_cnt))._2
when (state === s_invalid) {
io.req.ready := true.B
when (io.req.fire) {
state := s_fill_buffer
data_req_cnt := 0.U
req := io.req.bits
acked := false.B
}
} .elsewhen (state === s_fill_buffer) {
io.meta_read.valid := data_req_cnt < refillCycles.U
io.meta_read.bits.idx := req.idx
io.meta_read.bits.tag := req.tag
io.data_req.valid := data_req_cnt < refillCycles.U
io.data_req.bits.way_en := req.way_en
io.data_req.bits.addr := (if(refillCycles > 1)
Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0))
else req.idx) << rowOffBits
r1_data_req_fired := false.B
r1_data_req_cnt := 0.U
r2_data_req_fired := r1_data_req_fired
r2_data_req_cnt := r1_data_req_cnt
when (io.data_req.fire && io.meta_read.fire) {
r1_data_req_fired := true.B
r1_data_req_cnt := data_req_cnt
data_req_cnt := data_req_cnt + 1.U
}
when (r2_data_req_fired) {
wb_buffer(r2_data_req_cnt) := io.data_resp
when (r2_data_req_cnt === (refillCycles-1).U) {
io.resp := true.B
state := s_lsu_release
data_req_cnt := 0.U
}
}
} .elsewhen (state === s_lsu_release) {
io.lsu_release.valid := true.B
io.lsu_release.bits := probeResponse
when (io.lsu_release.fire) {
state := s_active
}
} .elsewhen (state === s_active) {
io.release.valid := data_req_cnt < refillCycles.U
io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse)
when (io.mem_grant) {
acked := true.B
}
when (io.release.fire) {
data_req_cnt := data_req_cnt + 1.U
}
when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) {
state := Mux(req.voluntary, s_grant, s_invalid)
}
} .elsewhen (state === s_grant) {
when (io.mem_grant) {
acked := true.B
}
when (acked) {
state := s_invalid
}
}
}
class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new TLBundleB(edge.bundle)))
val rep = Decoupled(new TLBundleC(edge.bundle))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val way_en = Input(UInt(nWays.W))
val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done
val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed?
val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own?
val block_state = Input(new ClientMetadata())
val lsu_release = Decoupled(new TLBundleC(edge.bundle))
val state = Output(Valid(UInt(coreMaxAddrBits.W)))
})
val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req ::
s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp ::
s_meta_write :: s_meta_write_resp :: Nil) = Enum(11)
val state = RegInit(s_invalid)
val req = Reg(new TLBundleB(edge.bundle))
val req_idx = req.address(idxMSB, idxLSB)
val req_tag = req.address >> untagBits
val way_en = Reg(UInt())
val tag_matches = way_en.orR
val old_coh = Reg(new ClientMetadata)
val miss_coh = ClientMetadata.onReset
val reply_coh = Mux(tag_matches, old_coh, miss_coh)
val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param)
io.state.valid := state =/= s_invalid
io.state.bits := req.address
io.req.ready := state === s_invalid
io.rep.valid := state === s_release
io.rep.bits := edge.ProbeAck(req, report_param)
assert(!io.rep.valid || !edge.hasData(io.rep.bits),
"ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it")
io.meta_read.valid := state === s_meta_read
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req_tag
io.meta_read.bits.way_en := ~(0.U(nWays.W))
io.meta_write.valid := state === s_meta_write
io.meta_write.bits.way_en := way_en
io.meta_write.bits.idx := req_idx
io.meta_write.bits.tag := req_tag
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.data.coh := new_coh
io.wb_req.valid := state === s_writeback_req
io.wb_req.bits.source := req.source
io.wb_req.bits.idx := req_idx
io.wb_req.bits.tag := req_tag
io.wb_req.bits.param := report_param
io.wb_req.bits.way_en := way_en
io.wb_req.bits.voluntary := false.B
io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp)
io.lsu_release.valid := state === s_lsu_release
io.lsu_release.bits := edge.ProbeAck(req, report_param)
// state === s_invalid
when (state === s_invalid) {
when (io.req.fire) {
state := s_meta_read
req := io.req.bits
}
} .elsewhen (state === s_meta_read) {
when (io.meta_read.fire) {
state := s_meta_resp
}
} .elsewhen (state === s_meta_resp) {
// we need to wait one cycle for the metadata to be read from the array
state := s_mshr_req
} .elsewhen (state === s_mshr_req) {
old_coh := io.block_state
way_en := io.way_en
// if the read didn't go through, we need to retry
state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read)
} .elsewhen (state === s_mshr_resp) {
state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release)
} .elsewhen (state === s_lsu_release) {
when (io.lsu_release.fire) {
state := s_release
}
} .elsewhen (state === s_release) {
when (io.rep.ready) {
state := Mux(tag_matches, s_meta_write, s_invalid)
}
} .elsewhen (state === s_writeback_req) {
when (io.wb_req.fire) {
state := s_writeback_resp
}
} .elsewhen (state === s_writeback_resp) {
// wait for the writeback request to finish before updating the metadata
when (io.wb_req.ready) {
state := s_meta_write
}
} .elsewhen (state === s_meta_write) {
when (io.meta_write.fire) {
state := s_meta_write_resp
}
} .elsewhen (state === s_meta_write_resp) {
state := s_invalid
}
}
class BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) {
val req = Vec(memWidth, new L1MetaReadReq)
}
class BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) {
val req = Vec(memWidth, new L1DataReadReq)
val valid = Vec(memWidth, Bool())
}
abstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters {
val io = IO(new BoomBundle {
val read = Input(Vec(memWidth, Valid(new L1DataReadReq)))
val write = Input(Valid(new L1DataWriteReq))
val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W))))
val nacks = Output(Vec(memWidth, Bool()))
})
def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
}
class BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray
{
val waddr = io.write.bits.addr >> rowOffBits
for (j <- 0 until memWidth) {
val raddr = io.read(j).bits.addr >> rowOffBits
for (w <- 0 until nWays) {
val array = DescribedSRAM(
name = s"array_${w}_${j}",
desc = "Non-blocking DCache Data Array",
size = nSets * refillCycles,
data = Vec(rowWords, Bits(encDataBits.W))
)
when (io.write.bits.way_en(w) && io.write.valid) {
val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))
array.write(waddr, data, io.write.bits.wmask.asBools)
}
io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt)
}
io.nacks(j) := false.B
}
}
class BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray {
val nBanks = boomParams.numDCacheBanks
val bankSize = nSets * refillCycles / nBanks
require (nBanks >= memWidth)
require (bankSize > 0)
val bankBits = log2Ceil(nBanks)
val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes)
val bidxBits = log2Ceil(bankSize)
val bidxOffBits = bankOffBits + bankBits
//----------------------------------------------------------------------------------------------------
val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U)
val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U
val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0)))
val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0)
val s0_read_valids = VecInit(io.read.map(_.valid))
val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c || io.read(i).valid && s0_rbanks(i) === s0_rbanks(w)))
val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c}
val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)}))
val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools
//----------------------------------------------------------------------------------------------------
val s1_rbanks = RegNext(s0_rbanks)
val s1_ridxs = RegNext(s0_ridxs)
val s1_read_valids = RegNext(s0_read_valids)
val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j =>
if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i)
else if (j == i) true.B else false.B))))
val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i)
else if (j == i) true.B else false.B))
val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR)
val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks))
//----------------------------------------------------------------------------------------------------
val s2_bank_selection = RegNext(s1_bank_selection)
val s2_nacks = RegNext(s1_nacks)
for (w <- 0 until nWays) {
val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W)))
for (b <- 0 until nBanks) {
val array = DescribedSRAM(
name = s"array_${w}_${b}",
desc = "Non-blocking DCache Data Array",
size = bankSize,
data = Vec(rowWords, Bits(encDataBits.W))
)
val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs)
val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en))
s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_||_)).asUInt
when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) {
val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))
array.write(s0_widx, data, io.write.bits.wmask.asBools)
}
}
for (i <- 0 until memWidth) {
io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i))
}
}
io.nacks := s2_nacks
}
/**
* Top level class wrapping a non-blocking dcache.
*
* @param hartid hardware thread for the cache
*/
class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule
{
private val tileParams = p(TileKey)
protected val cfg = tileParams.dcache.get
protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(
name = s"Core ${staticIdForMetadataUseOnly} DCache",
sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)),
supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))
protected def mmioClientParameters = Seq(TLMasterParameters.v1(
name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO",
sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs),
requestFifo = true))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
cacheClientParameters ++ mmioClientParameters,
minLatency = 1)))
lazy val module = new BoomNonBlockingDCacheModule(this)
def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)
require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$")
}
class BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) {
val lsu = Flipped(new LSUDMemIO)
}
class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters
with HasBoomCoreParameters
{
implicit val edge = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new BoomDCacheBundle)
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)
fifoManagers.foreach { m =>
require (m.fifoId == fifoManagers.head.fifoId,
s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}")
}
def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6)
val wb = Module(new BoomWritebackUnit)
val prober = Module(new BoomProbeUnit)
val mshrs = Module(new BoomMSHRFile)
mshrs.io.clear_all := io.lsu.force_order
mshrs.io.brupdate := io.lsu.brupdate
mshrs.io.exception := io.lsu.exception
mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx
mshrs.io.rob_head_idx := io.lsu.rob_head_idx
// tags
def onReset = L1Metadata(0.U, ClientMetadata.onReset)
val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) }
val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2))
// 0 goes to MSHR refills, 1 goes to prober
val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6))
// 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read,
// 4 goes to pipeline, 5 goes to prefetcher
metaReadArb.io.in := DontCare
for (w <- 0 until memWidth) {
meta(w).io.write.valid := metaWriteArb.io.out.fire
meta(w).io.write.bits := metaWriteArb.io.out.bits
meta(w).io.read.valid := metaReadArb.io.out.valid
meta(w).io.read.bits := metaReadArb.io.out.bits.req(w)
}
metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_||_)
metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_||_)
// data
val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray)
val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2))
// 0 goes to pipeline, 1 goes to MSHR refills
val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3))
// 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline
dataReadArb.io.in := DontCare
for (w <- 0 until memWidth) {
data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid
data.io.read(w).bits := dataReadArb.io.out.bits.req(w)
}
dataReadArb.io.out.ready := true.B
data.io.write.valid := dataWriteArb.io.out.fire
data.io.write.bits := dataWriteArb.io.out.bits
dataWriteArb.io.out.ready := true.B
// ------------
// New requests
io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready
metaReadArb.io.in(4).valid := io.lsu.req.valid
dataReadArb.io.in(2).valid := io.lsu.req.valid
for (w <- 0 until memWidth) {
// Tag read for new requests
metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits
metaReadArb.io.in(4).bits.req(w).way_en := DontCare
metaReadArb.io.in(4).bits.req(w).tag := DontCare
// Data read for new requests
dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid
dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr
dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W)
}
// ------------
// MSHR Replays
val replay_req = Wire(Vec(memWidth, new BoomDCacheReq))
replay_req := DontCare
replay_req(0).uop := mshrs.io.replay.bits.uop
replay_req(0).addr := mshrs.io.replay.bits.addr
replay_req(0).data := mshrs.io.replay.bits.data
replay_req(0).is_hella := mshrs.io.replay.bits.is_hella
mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready
// Tag read for MSHR replays
// We don't actually need to read the metadata, for replays we already know our way
metaReadArb.io.in(0).valid := mshrs.io.replay.valid
metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits
metaReadArb.io.in(0).bits.req(0).way_en := DontCare
metaReadArb.io.in(0).bits.req(0).tag := DontCare
// Data read for MSHR replays
dataReadArb.io.in(0).valid := mshrs.io.replay.valid
dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr
dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en
dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B)
// -----------
// MSHR Meta read
val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq))
mshr_read_req := DontCare
mshr_read_req(0).uop := NullMicroOp
mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits
mshr_read_req(0).data := DontCare
mshr_read_req(0).is_hella := false.B
metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid
metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits
mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready
// -----------
// Write-backs
val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire
val wb_req = Wire(Vec(memWidth, new BoomDCacheReq))
wb_req := DontCare
wb_req(0).uop := NullMicroOp
wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr)
wb_req(0).data := DontCare
wb_req(0).is_hella := false.B
// Couple the two decoupled interfaces of the WBUnit's meta_read and data_read
// Tag read for write-back
metaReadArb.io.in(2).valid := wb.io.meta_read.valid
metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits
wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready
// Data read for write-back
dataReadArb.io.in(1).valid := wb.io.data_req.valid
dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits
dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B)
wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready
assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))
// -------
// Prober
val prober_fire = prober.io.meta_read.fire
val prober_req = Wire(Vec(memWidth, new BoomDCacheReq))
prober_req := DontCare
prober_req(0).uop := NullMicroOp
prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits
prober_req(0).data := DontCare
prober_req(0).is_hella := false.B
// Tag read for prober
metaReadArb.io.in(1).valid := prober.io.meta_read.valid
metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits
prober.io.meta_read.ready := metaReadArb.io.in(1).ready
// Prober does not need to read data array
// -------
// Prefetcher
val prefetch_fire = mshrs.io.prefetch.fire
val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq))
prefetch_req := DontCare
prefetch_req(0) := mshrs.io.prefetch.bits
// Tag read for prefetch
metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid
metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits
metaReadArb.io.in(5).bits.req(0).way_en := DontCare
metaReadArb.io.in(5).bits.req(0).tag := DontCare
mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready
// Prefetch does not need to read data array
val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)),
Mux(mshrs.io.replay.fire || wb_fire || prober_fire || prefetch_fire || mshrs.io.meta_read.fire,
VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools)))
val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)),
Mux(wb_fire , wb_req,
Mux(prober_fire , prober_req,
Mux(prefetch_fire , prefetch_req,
Mux(mshrs.io.meta_read.fire, mshr_read_req
, replay_req)))))
val s0_type = Mux(io.lsu.req.fire , t_lsu,
Mux(wb_fire , t_wb,
Mux(prober_fire , t_probe,
Mux(prefetch_fire , t_prefetch,
Mux(mshrs.io.meta_read.fire, t_mshr_meta_read
, t_replay)))))
// Does this request need to send a response or nack
val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid,
VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools))
val s1_req = RegNext(s0_req)
for (w <- 0 until memWidth)
s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop)
val s2_store_failed = Wire(Bool())
val s1_valid = widthMap(w =>
RegNext(s0_valid(w) &&
!IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) &&
!(io.lsu.exception && s0_req(w).uop.uses_ldq) &&
!(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq),
init=false.B))
for (w <- 0 until memWidth)
assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))
val s1_addr = s1_req.map(_.addr)
val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready)
val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack)
val s1_type = RegNext(s0_type)
val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en)
val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet
val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en)
// tag check
def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f))
val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt)
val s1_tag_match_way = widthMap(i =>
Mux(s1_type === t_replay, s1_replay_way_en,
Mux(s1_type === t_wb, s1_wb_way_en,
Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en,
wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt))))
val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid)
val s2_req = RegNext(s1_req)
val s2_type = RegNext(s1_type)
val s2_valid = widthMap(w =>
RegNext(s1_valid(w) &&
!io.lsu.s1_kill(w) &&
!IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) &&
!(io.lsu.exception && s1_req(w).uop.uses_ldq) &&
!(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq)))
for (w <- 0 until memWidth)
s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop)
val s2_tag_match_way = RegNext(s1_tag_match_way)
val s2_tag_match = s2_tag_match_way.map(_.orR)
val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh))))
val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1)
val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3)
val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) || s2_type.isOneOf(t_replay, t_wb))
val s2_nack = Wire(Vec(memWidth, Bool()))
assert(!(s2_type === t_replay && !s2_hit(0)), "Replays should always hit")
assert(!(s2_type === t_wb && !s2_hit(0)), "Writeback should always see data hit")
val s2_wb_idx_matches = RegNext(s1_wb_idx_matches)
// lr/sc
val debug_sc_fail_addr = RegInit(0.U)
val debug_sc_fail_cnt = RegInit(0.U(8.W))
val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W))
val lrsc_valid = lrsc_count > lrscBackoff.U
val lrsc_addr = Reg(UInt())
val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) || s2_type === t_replay)
val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) || s2_type === t_replay)
val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits))
val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0)
when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U }
when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) ||
(s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) {
when (s2_lr) {
lrsc_count := (lrscCycles - 1).U
lrsc_addr := s2_req(0).addr >> blockOffBits
}
when (lrsc_count > 0.U) {
lrsc_count := 0.U
}
}
for (w <- 0 until memWidth) {
when (s2_valid(w) &&
s2_type === t_lsu &&
!s2_hit(w) &&
!(s2_has_permission(w) && s2_tag_match(w)) &&
s2_lrsc_addr_match(w) &&
!s2_nack(w)) {
lrsc_count := 0.U
}
}
when (s2_valid(0)) {
when (s2_req(0).addr === debug_sc_fail_addr) {
when (s2_sc_fail) {
debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U
} .elsewhen (s2_sc) {
debug_sc_fail_cnt := 0.U
}
} .otherwise {
when (s2_sc_fail) {
debug_sc_fail_addr := s2_req(0).addr
debug_sc_fail_cnt := 1.U
}
}
}
assert(debug_sc_fail_cnt < 100.U, "L1DCache failed too many SCs in a row")
val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W))))
for (i <- 0 until memWidth) {
for (w <- 0 until nWays) {
s2_data(i)(w) := data.io.resp(i)(w)
}
}
val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w)))
val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWords*wordBytes)-1, log2Up(wordBytes)))
// replacement policy
val replacer = cacheParams.replacement
val s1_replaced_way_en = UIntToOH(replacer.way)
val s2_replaced_way_en = UIntToOH(RegNext(replacer.way))
val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq))
// nack because of incoming probe
val s2_nack_hit = RegNext(VecInit(s1_nack))
// Nack when we hit something currently being evicted
val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w))
// MSHRs not ready for request
val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready)
// Bank conflict on data arrays
val s2_nack_data = widthMap(w => data.io.nacks(w))
// Can't allocate MSHR for same set currently being written back
val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w))
s2_nack := widthMap(w => (s2_nack_miss(w) || s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w) || s2_nack_wb(w)) && s2_type =/= t_replay)
val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) &&
(s2_hit(w) || (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd)))))
val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w)))
for (w <- 0 until memWidth)
assert(!(s2_send_resp(w) && s2_send_nack(w)))
// hits always send a response
// If MSHR is not available, LSU has to replay this request later
// If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later
s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq
// Miss handling
for (w <- 0 until memWidth) {
mshrs.io.req(w).valid := s2_valid(w) &&
!s2_hit(w) &&
!s2_nack_hit(w) &&
!s2_nack_victim(w) &&
!s2_nack_data(w) &&
!s2_nack_wb(w) &&
s2_type.isOneOf(t_lsu, t_prefetch) &&
!IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) &&
!(io.lsu.exception && s2_req(w).uop.uses_ldq) &&
(isPrefetch(s2_req(w).uop.mem_cmd) ||
isRead(s2_req(w).uop.mem_cmd) ||
isWrite(s2_req(w).uop.mem_cmd))
assert(!(mshrs.io.req(w).valid && s2_type === t_replay), "Replays should not need to go back into MSHRs")
mshrs.io.req(w).bits := DontCare
mshrs.io.req(w).bits.uop := s2_req(w).uop
mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop)
mshrs.io.req(w).bits.addr := s2_req(w).addr
mshrs.io.req(w).bits.tag_match := s2_tag_match(w)
mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w))
mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en)
mshrs.io.req(w).bits.data := s2_req(w).data
mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella
mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w)
}
mshrs.io.meta_resp.valid := !s2_nack_hit(0) || prober.io.mshr_wb_rdy
mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp))
when (mshrs.io.req.map(_.fire).reduce(_||_)) { replacer.miss }
tl_out.a <> mshrs.io.mem_acquire
// probes and releases
prober.io.req.valid := tl_out.b.valid && !lrsc_valid
tl_out.b.ready := prober.io.req.ready && !lrsc_valid
prober.io.req.bits := tl_out.b.bits
prober.io.way_en := s2_tag_match_way(0)
prober.io.block_state := s2_hit_state(0)
metaWriteArb.io.in(1) <> prober.io.meta_write
prober.io.mshr_rdy := mshrs.io.probe_rdy
prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid
mshrs.io.prober_state := prober.io.state
// refills
when (tl_out.d.bits.source === cfg.nMSHRs.U) {
// This should be ReleaseAck
tl_out.d.ready := true.B
mshrs.io.mem_grant.valid := false.B
mshrs.io.mem_grant.bits := DontCare
} .otherwise {
// This should be GrantData
mshrs.io.mem_grant <> tl_out.d
}
dataWriteArb.io.in(1) <> mshrs.io.refill
metaWriteArb.io.in(0) <> mshrs.io.meta_write
tl_out.e <> mshrs.io.mem_finish
// writebacks
val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2))
// 0 goes to prober, 1 goes to MSHR evictions
wbArb.io.in(0) <> prober.io.wb_req
wbArb.io.in(1) <> mshrs.io.wb_req
wb.io.req <> wbArb.io.out
wb.io.data_resp := s2_data_muxed(0)
mshrs.io.wb_resp := wb.io.resp
wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U
val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2))
io.lsu.release <> lsu_release_arb.io.out
lsu_release_arb.io.in(0) <> wb.io.lsu_release
lsu_release_arb.io.in(1) <> prober.io.lsu_release
TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep)
io.lsu.perf.release := edge.done(tl_out.c)
io.lsu.perf.acquire := edge.done(tl_out.a)
// load data gen
val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W)))
val s2_data_word = Wire(Vec(memWidth, UInt()))
val loadgen = (0 until memWidth).map { w =>
new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr,
s2_data_word(w), s2_sc && (w == 0).B, wordBytes)
}
// Mux between cache responses and uncache responses
val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp)))
for (w <- 0 until memWidth) {
cache_resp(w).valid := s2_valid(w) && s2_send_resp(w)
cache_resp(w).bits.uop := s2_req(w).uop
cache_resp(w).bits.data := loadgen(w).data | s2_sc_fail
cache_resp(w).bits.is_hella := s2_req(w).is_hella
}
val uncache_resp = Wire(Valid(new BoomDCacheResp))
uncache_resp.bits := mshrs.io.resp.bits
uncache_resp.valid := mshrs.io.resp.valid
mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits
val resp = WireInit(cache_resp)
var uncache_responding = false.B
for (w <- 0 until memWidth) {
val uncache_respond = !cache_resp(w).valid && !uncache_responding
when (uncache_respond) {
resp(w) := uncache_resp
}
uncache_responding = uncache_responding || uncache_respond
}
for (w <- 0 until memWidth) {
io.lsu.resp(w).valid := resp(w).valid &&
!(io.lsu.exception && resp(w).bits.uop.uses_ldq) &&
!IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop)
io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits)
io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) &&
!(io.lsu.exception && s2_req(w).uop.uses_ldq) &&
!IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop)
io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w))
assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))
}
// Store/amo hits
val s3_req = RegNext(s2_req(0))
val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) &&
!s2_sc_fail && !(s2_send_nack(0) && s2_nack(0)))
for (w <- 1 until memWidth) {
assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) &&
!s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))),
"Store must go through 0th pipe in L1D")
}
// For bypassing
val s4_req = RegNext(s3_req)
val s4_valid = RegNext(s3_valid)
val s5_req = RegNext(s4_req)
val s5_valid = RegNext(s4_valid)
val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits)))
val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits)))
val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits)))
// Store -> Load bypassing
for (w <- 0 until memWidth) {
s2_data_word(w) := Mux(s3_bypass(w), s3_req.data,
Mux(s4_bypass(w), s4_req.data,
Mux(s5_bypass(w), s5_req.data,
s2_data_word_prebypass(w))))
}
val amoalu = Module(new AMOALU(xLen))
amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask
amoalu.io.cmd := s2_req(0).uop.mem_cmd
amoalu.io.lhs := s2_data_word(0)
amoalu.io.rhs := s2_req(0).data
s3_req.data := amoalu.io.out
val s3_way = RegNext(s2_tag_match_way(0))
dataWriteArb.io.in(0).valid := s3_valid
dataWriteArb.io.in(0).bits.addr := s3_req.addr
dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb))
dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data)
dataWriteArb.io.in(0).bits.way_en := s3_way
io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_||_) && !s2_valid.reduce(_||_)
}
File Replacement.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import freechips.rocketchip.util.property.cover
abstract class ReplacementPolicy {
def nBits: Int
def perSet: Boolean
def way: UInt
def miss: Unit
def hit: Unit
def access(touch_way: UInt): Unit
def access(touch_ways: Seq[Valid[UInt]]): Unit
def state_read: UInt
def get_next_state(state: UInt, touch_way: UInt): UInt
def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = {
touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev))
}
def get_replace_way(state: UInt): UInt
}
object ReplacementPolicy {
def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match {
case "random" => new RandomReplacement(n_ways)
case "lru" => new TrueLRU(n_ways)
case "plru" => new PseudoLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
}
class RandomReplacement(n_ways: Int) extends ReplacementPolicy {
private val replace = Wire(Bool())
replace := false.B
def nBits = 16
def perSet = false
private val lfsr = LFSR(nBits, replace)
def state_read = WireDefault(lfsr)
def way = Random(n_ways, lfsr)
def miss = replace := true.B
def hit = {}
def access(touch_way: UInt) = {}
def access(touch_ways: Seq[Valid[UInt]]) = {}
def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare
def get_replace_way(state: UInt) = way
}
abstract class SeqReplacementPolicy {
def access(set: UInt): Unit
def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
def way: UInt
}
abstract class SetAssocReplacementPolicy {
def access(set: UInt, touch_way: UInt): Unit
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit
def way(set: UInt): UInt
}
class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
val logic = new RandomReplacement(n_ways)
def access(set: UInt) = { }
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
when (valid && !hit) { logic.miss }
}
def way = logic.way
}
class TrueLRU(n_ways: Int) extends ReplacementPolicy {
// True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others.
// The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits):
// [5] - 3 more recent than 2
// [4] - 3 more recent than 1
// [3] - 2 more recent than 1
// [2] - 3 more recent than 0
// [1] - 2 more recent than 0
// [0] - 1 more recent than 0
def nBits = (n_ways * (n_ways-1)) / 2
def perSet = true
private val state_reg = RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
private def extractMRUVec(state: UInt): Seq[UInt] = {
// Extract per-way information about which higher-indexed ways are more recently used
val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W)))
var lsb = 0
for (i <- 0 until n_ways-1) {
moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W))
lsb = lsb + (n_ways - i - 1)
}
moreRecentVec
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W)))
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
val wayDec = UIntToOH(touch_way, n_ways)
// Compute next value of triangular matrix
// set the touched way as more recent than every other way
nextState.zipWithIndex.map { case (e, i) =>
e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec)
}
nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1
}
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous")
}
}
def get_replace_way(state: UInt): UInt = {
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
// For each way, determine if all other ways are more recent
val mruWayDec = (0 until n_ways).map { i =>
val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR)
val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _))
upperMoreRecent && lowerMoreRecent
}
OHToUInt(mruWayDec)
}
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
@deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05")
def replace: UInt = way
}
class PseudoLRU(n_ways: Int) extends ReplacementPolicy {
// Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU
//
//
// - bits storage example for 4-way PLRU binary tree:
// bit[2]: ways 3+2 older than ways 1+0
// / \
// bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0
//
//
// - bits storage example for 3-way PLRU binary tree:
// bit[1]: way 2 older than ways 1+0
// \
// bit[0]: way 1 older than way 0
//
//
// - bits storage example for 8-way PLRU binary tree:
// bit[6]: ways 7-4 older than ways 3-0
// / \
// bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0
// / \ / \
// bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0
def nBits = n_ways - 1
def perSet = true
private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous")
}
}
/** @param state state_reg bits for this sub-tree
* @param touch_way touched way encoded value bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways")
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val set_left_older = !touch_way(log2Ceil(tree_nways)-1)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(set_left_older,
Mux(set_left_older,
left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree
get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(set_left_older,
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value
!touch_way(0)
} else { // tree_nways <= 1
// we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires)
0.U(1.W)
}
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways))
else touch_way.extract(log2Ceil(n_ways)-1,0)
get_next_state(state, touch_way_sized, n_ways)
}
/** @param state state_reg bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_replace_way(state: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
// this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val left_subtree_older = state(tree_nways-2)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right
get_replace_way(left_subtree_state, left_nways), // recurse left
get_replace_way(right_subtree_state, right_nways))) // recurse right
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right
0.U(1.W),
get_replace_way(right_subtree_state, right_nways))) // recurse right
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value
state(0)
} else { // tree_nways <= 1
// we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value
0.U(1.W)
}
}
def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways)
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
}
class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
val logic = new PseudoLRU(n_ways)
val state = SyncReadMem(n_sets, UInt(logic.nBits.W))
val current_state = Wire(UInt(logic.nBits.W))
val next_state = Wire(UInt(logic.nBits.W))
val plru_way = logic.get_replace_way(current_state)
def access(set: UInt) = {
current_state := state.read(set)
}
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
val update_way = Mux(hit, way, plru_way)
next_state := logic.get_next_state(current_state, update_way)
when (valid) { state.write(set, next_state) }
}
def way = plru_way
}
class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy {
val logic = policy.toLowerCase match {
case "plru" => new PseudoLRU(n_ways)
case "lru" => new TrueLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
val state_vec =
if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line
else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W))))
def access(set: UInt, touch_way: UInt) = {
state_vec(set) := logic.get_next_state(state_vec(set), touch_way)
}
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = {
require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways")
for (set <- 0 until n_sets) {
val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) =>
Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)}
when (set_touch_ways.map(_.valid).orR) {
state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways)
}
}
}
def way(set: UInt) = logic.get_replace_way(state_vec(set))
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) {
val plru = new PseudoLRU(n_ways)
// step
io.finished := RegNext(true.B, false.B)
val get_replace_ways = (0 until (1 << (n_ways-1))).map(state =>
plru.get_replace_way(state = state.U((n_ways-1).W)))
val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way =>
plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W))))
n_ways match {
case 2 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1))
assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1))
}
case 3 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3))
assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2))
assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2))
assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2))
assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2))
}
case 4 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3))
assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4))
assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5))
assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6))
assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7))
assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2))
assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3))
assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2))
assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3))
assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2))
assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3))
assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2))
assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3))
assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0))
assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1))
assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2))
assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3))
assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0))
assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1))
assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2))
assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3))
assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0))
assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1))
assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2))
assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3))
assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0))
assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1))
assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2))
assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3))
}
case 5 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15))
assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0))
assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1))
assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2))
assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3))
assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4))
assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0))
assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1))
assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2))
assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3))
assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4))
assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0))
assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1))
assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2))
assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3))
assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4))
assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0))
assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1))
assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2))
assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3))
assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4))
assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0))
assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1))
assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2))
assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3))
assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4))
assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0))
assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1))
assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2))
assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3))
assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4))
assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0))
assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1))
assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2))
assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3))
assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4))
assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0))
assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1))
assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2))
assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3))
assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4))
assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0))
assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1))
assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2))
assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3))
assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4))
assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0))
assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1))
assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2))
assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3))
assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4))
assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0))
assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1))
assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2))
assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3))
assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4))
assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0))
assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1))
assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2))
assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3))
assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4))
assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0))
assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1))
assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2))
assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3))
assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4))
assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0))
assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1))
assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2))
assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3))
assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4))
assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0))
assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1))
assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2))
assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3))
assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4))
assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0))
assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1))
assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2))
assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3))
assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4))
}
case 6 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15))
assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16))
assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17))
assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18))
assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19))
assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20))
assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21))
assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22))
assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23))
assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24))
assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25))
assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26))
assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27))
assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28))
assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29))
assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30))
assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31))
}
case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways")
}
}
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
File AMOALU.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W))
size := typ
val dat_padded = dat.pad(maxSize*8)
def misaligned: Bool =
(addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR
def mask = {
var res = 1.U
for (i <- 0 until log2Up(maxSize)) {
val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U)
val lower = Mux(addr(i), 0.U, res)
res = Cat(upper, lower)
}
res
}
protected def genData(i: Int): UInt =
if (i >= log2Up(maxSize)) dat_padded
else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1))
def data = genData(0)
def wordData = genData(2)
}
class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
private val size = new StoreGen(typ, addr, dat, maxSize).size
private def genData(logMinSize: Int): UInt = {
var res = dat
for (i <- log2Up(maxSize)-1 to logMinSize by -1) {
val pos = 8 << i
val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
val doZero = (i == 0).B && zero
val zeroed = Mux(doZero, 0.U, shifted)
res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
}
res
}
def wordData = genData(2)
def data = genData(0)
}
class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module {
val minXLen = 32
val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _)
val io = IO(new Bundle {
val mask = Input(UInt((operandBits / 8).W))
val cmd = Input(UInt(M_SZ.W))
val lhs = Input(UInt(operandBits.W))
val rhs = Input(UInt(operandBits.W))
val out = Output(UInt(operandBits.W))
val out_unmasked = Output(UInt(operandBits.W))
})
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
val add = io.cmd === M_XA_ADD
val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND
val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR
val adder_out = {
// partition the carry chain to support sub-xLen addition
val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_)
(io.lhs & mask) + (io.rhs & mask)
}
val less = {
// break up the comparator so the lower parts will be CSE'd
def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = {
if (n == minXLen) x(n-1, 0) < y(n-1, 0)
else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2)
}
def isLess(x: UInt, y: UInt, n: Int): Bool = {
val signed = {
val mask = M_XA_MIN ^ M_XA_MINU
(io.cmd & mask) === (M_XA_MIN & mask)
}
Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1)))
}
PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w))))
}
val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs)
val logic =
Mux(logic_and, io.lhs & io.rhs, 0.U) |
Mux(logic_xor, io.lhs ^ io.rhs, 0.U)
val out =
Mux(add, adder_out,
Mux(logic_and || logic_xor, logic,
minmax))
val wmask = FillInterleaved(8, io.mask)
io.out := wmask & out | ~wmask & io.lhs
io.out_unmasked := out
}
| module BoomNonBlockingDCache( // @[dcache.scala:413:7]
input clock, // @[dcache.scala:413:7]
input reset, // @[dcache.scala:413:7]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output io_lsu_req_ready, // @[dcache.scala:419:14]
input io_lsu_req_valid, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_valid, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_uopc, // @[dcache.scala:419:14]
input [31:0] io_lsu_req_bits_0_bits_uop_inst, // @[dcache.scala:419:14]
input [31:0] io_lsu_req_bits_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
input [39:0] io_lsu_req_bits_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_iq_type, // @[dcache.scala:419:14]
input [9:0] io_lsu_req_bits_0_bits_uop_fu_code, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
input [2:0] io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_iw_state, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_br, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_jal, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
input [15:0] io_lsu_req_bits_0_bits_uop_br_mask, // @[dcache.scala:419:14]
input [3:0] io_lsu_req_bits_0_bits_uop_br_tag, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_taken, // @[dcache.scala:419:14]
input [19:0] io_lsu_req_bits_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
input [11:0] io_lsu_req_bits_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_pdst, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs1, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs2, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_prs3, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_ppred, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
input [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_exception, // @[dcache.scala:419:14]
input [63:0] io_lsu_req_bits_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bypassable, // @[dcache.scala:419:14]
input [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_mem_size, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_fence, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_amo, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_is_unique, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_ldst, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs2, // @[dcache.scala:419:14]
input [5:0] io_lsu_req_bits_0_bits_uop_lrs3, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_fp_val, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_fp_single, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
input [1:0] io_lsu_req_bits_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
input [39:0] io_lsu_req_bits_0_bits_addr, // @[dcache.scala:419:14]
input [63:0] io_lsu_req_bits_0_bits_data, // @[dcache.scala:419:14]
input io_lsu_req_bits_0_bits_is_hella, // @[dcache.scala:419:14]
input io_lsu_s1_kill_0, // @[dcache.scala:419:14]
output io_lsu_resp_0_valid, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_uopc, // @[dcache.scala:419:14]
output [31:0] io_lsu_resp_0_bits_uop_inst, // @[dcache.scala:419:14]
output [31:0] io_lsu_resp_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
output [39:0] io_lsu_resp_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_iq_type, // @[dcache.scala:419:14]
output [9:0] io_lsu_resp_0_bits_uop_fu_code, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
output [2:0] io_lsu_resp_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_iw_state, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_br, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_jal, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
output [15:0] io_lsu_resp_0_bits_uop_br_mask, // @[dcache.scala:419:14]
output [3:0] io_lsu_resp_0_bits_uop_br_tag, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_taken, // @[dcache.scala:419:14]
output [19:0] io_lsu_resp_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
output [11:0] io_lsu_resp_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_pdst, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_prs1, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_prs2, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_prs3, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_ppred, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
output [6:0] io_lsu_resp_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_exception, // @[dcache.scala:419:14]
output [63:0] io_lsu_resp_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bypassable, // @[dcache.scala:419:14]
output [4:0] io_lsu_resp_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_mem_size, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_fence, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_amo, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_is_unique, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_ldst, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs2, // @[dcache.scala:419:14]
output [5:0] io_lsu_resp_0_bits_uop_lrs3, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_fp_val, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_fp_single, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
output [1:0] io_lsu_resp_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
output [63:0] io_lsu_resp_0_bits_data, // @[dcache.scala:419:14]
output io_lsu_resp_0_bits_is_hella, // @[dcache.scala:419:14]
output io_lsu_nack_0_valid, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_uopc, // @[dcache.scala:419:14]
output [31:0] io_lsu_nack_0_bits_uop_inst, // @[dcache.scala:419:14]
output [31:0] io_lsu_nack_0_bits_uop_debug_inst, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_rvc, // @[dcache.scala:419:14]
output [39:0] io_lsu_nack_0_bits_uop_debug_pc, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_iq_type, // @[dcache.scala:419:14]
output [9:0] io_lsu_nack_0_bits_uop_fu_code, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_ctrl_br_type, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
output [2:0] io_lsu_nack_0_bits_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_load, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_sta, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ctrl_is_std, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_iw_state, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_br, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_jalr, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_jal, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_sfb, // @[dcache.scala:419:14]
output [15:0] io_lsu_nack_0_bits_uop_br_mask, // @[dcache.scala:419:14]
output [3:0] io_lsu_nack_0_bits_uop_br_tag, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_ftq_idx, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_edge_inst, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_pc_lob, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_taken, // @[dcache.scala:419:14]
output [19:0] io_lsu_nack_0_bits_uop_imm_packed, // @[dcache.scala:419:14]
output [11:0] io_lsu_nack_0_bits_uop_csr_addr, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_rob_idx, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_ldq_idx, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_stq_idx, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_rxq_idx, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_pdst, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_prs1, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_prs2, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_prs3, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_ppred, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs1_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs2_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_prs3_busy, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ppred_busy, // @[dcache.scala:419:14]
output [6:0] io_lsu_nack_0_bits_uop_stale_pdst, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_exception, // @[dcache.scala:419:14]
output [63:0] io_lsu_nack_0_bits_uop_exc_cause, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bypassable, // @[dcache.scala:419:14]
output [4:0] io_lsu_nack_0_bits_uop_mem_cmd, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_mem_size, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_mem_signed, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_fence, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_fencei, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_amo, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_uses_ldq, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_uses_stq, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_is_unique, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_flush_on_commit, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ldst_is_rs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_ldst, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs1, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs2, // @[dcache.scala:419:14]
output [5:0] io_lsu_nack_0_bits_uop_lrs3, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_ldst_val, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_dst_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_frs3_en, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_fp_val, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_fp_single, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_pf_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_ae_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_xcpt_ma_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bp_debug_if, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_uop_bp_xcpt_if, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_debug_fsrc, // @[dcache.scala:419:14]
output [1:0] io_lsu_nack_0_bits_uop_debug_tsrc, // @[dcache.scala:419:14]
output [39:0] io_lsu_nack_0_bits_addr, // @[dcache.scala:419:14]
output [63:0] io_lsu_nack_0_bits_data, // @[dcache.scala:419:14]
output io_lsu_nack_0_bits_is_hella, // @[dcache.scala:419:14]
input [15:0] io_lsu_brupdate_b1_resolve_mask, // @[dcache.scala:419:14]
input [15:0] io_lsu_brupdate_b1_mispredict_mask, // @[dcache.scala:419:14]
input [6:0] io_lsu_brupdate_b2_uop_uopc, // @[dcache.scala:419:14]
input [31:0] io_lsu_brupdate_b2_uop_inst, // @[dcache.scala:419:14]
input [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_rvc, // @[dcache.scala:419:14]
input [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_iq_type, // @[dcache.scala:419:14]
input [9:0] io_lsu_brupdate_b2_uop_fu_code, // @[dcache.scala:419:14]
input [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ctrl_fcn_dw, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ctrl_is_load, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ctrl_is_sta, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ctrl_is_std, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_iw_state, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_iw_p1_poisoned, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_iw_p2_poisoned, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_br, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_jalr, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_jal, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_sfb, // @[dcache.scala:419:14]
input [15:0] io_lsu_brupdate_b2_uop_br_mask, // @[dcache.scala:419:14]
input [3:0] io_lsu_brupdate_b2_uop_br_tag, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_edge_inst, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_taken, // @[dcache.scala:419:14]
input [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[dcache.scala:419:14]
input [11:0] io_lsu_brupdate_b2_uop_csr_addr, // @[dcache.scala:419:14]
input [6:0] io_lsu_brupdate_b2_uop_rob_idx, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_stq_idx, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[dcache.scala:419:14]
input [6:0] io_lsu_brupdate_b2_uop_pdst, // @[dcache.scala:419:14]
input [6:0] io_lsu_brupdate_b2_uop_prs1, // @[dcache.scala:419:14]
input [6:0] io_lsu_brupdate_b2_uop_prs2, // @[dcache.scala:419:14]
input [6:0] io_lsu_brupdate_b2_uop_prs3, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_ppred, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_prs1_busy, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_prs2_busy, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_prs3_busy, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ppred_busy, // @[dcache.scala:419:14]
input [6:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_exception, // @[dcache.scala:419:14]
input [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_bypassable, // @[dcache.scala:419:14]
input [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_mem_signed, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_fence, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_fencei, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_amo, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_uses_ldq, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_uses_stq, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_is_unique, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_flush_on_commit, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_ldst, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[dcache.scala:419:14]
input [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_ldst_val, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_frs3_en, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_fp_val, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_fp_single, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_bp_debug_if, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_valid, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_mispredict, // @[dcache.scala:419:14]
input io_lsu_brupdate_b2_taken, // @[dcache.scala:419:14]
input [2:0] io_lsu_brupdate_b2_cfi_type, // @[dcache.scala:419:14]
input [1:0] io_lsu_brupdate_b2_pc_sel, // @[dcache.scala:419:14]
input [39:0] io_lsu_brupdate_b2_jalr_target, // @[dcache.scala:419:14]
input [20:0] io_lsu_brupdate_b2_target_offset, // @[dcache.scala:419:14]
input io_lsu_exception, // @[dcache.scala:419:14]
input [6:0] io_lsu_rob_pnr_idx, // @[dcache.scala:419:14]
input [6:0] io_lsu_rob_head_idx, // @[dcache.scala:419:14]
input io_lsu_release_ready, // @[dcache.scala:419:14]
output io_lsu_release_valid, // @[dcache.scala:419:14]
output [2:0] io_lsu_release_bits_opcode, // @[dcache.scala:419:14]
output [2:0] io_lsu_release_bits_param, // @[dcache.scala:419:14]
output [3:0] io_lsu_release_bits_size, // @[dcache.scala:419:14]
output [2:0] io_lsu_release_bits_source, // @[dcache.scala:419:14]
output [31:0] io_lsu_release_bits_address, // @[dcache.scala:419:14]
output [127:0] io_lsu_release_bits_data, // @[dcache.scala:419:14]
input io_lsu_force_order, // @[dcache.scala:419:14]
output io_lsu_ordered, // @[dcache.scala:419:14]
output io_lsu_perf_acquire, // @[dcache.scala:419:14]
output io_lsu_perf_release // @[dcache.scala:419:14]
);
wire resp_0_bits_is_hella; // @[dcache.scala:846:22]
wire [63:0] resp_0_bits_data; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_debug_tsrc; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_debug_fsrc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bp_xcpt_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bp_debug_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_ma_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_ae_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_xcpt_pf_if; // @[dcache.scala:846:22]
wire resp_0_bits_uop_fp_single; // @[dcache.scala:846:22]
wire resp_0_bits_uop_fp_val; // @[dcache.scala:846:22]
wire resp_0_bits_uop_frs3_en; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_lrs2_rtype; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_lrs1_rtype; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_dst_rtype; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ldst_val; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs3; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs2; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_lrs1; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_ldst; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ldst_is_rs1; // @[dcache.scala:846:22]
wire resp_0_bits_uop_flush_on_commit; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_unique; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_uses_stq; // @[dcache.scala:846:22]
wire resp_0_bits_uop_uses_ldq; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_amo; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_fencei; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_fence; // @[dcache.scala:846:22]
wire resp_0_bits_uop_mem_signed; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_mem_size; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_mem_cmd; // @[dcache.scala:846:22]
wire resp_0_bits_uop_bypassable; // @[dcache.scala:846:22]
wire [63:0] resp_0_bits_uop_exc_cause; // @[dcache.scala:846:22]
wire resp_0_bits_uop_exception; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_stale_pdst; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ppred_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs3_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs2_busy; // @[dcache.scala:846:22]
wire resp_0_bits_uop_prs1_busy; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_ppred; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_prs3; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_prs2; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_prs1; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_pdst; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_rxq_idx; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_stq_idx; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_ldq_idx; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_rob_idx; // @[dcache.scala:846:22]
wire [11:0] resp_0_bits_uop_csr_addr; // @[dcache.scala:846:22]
wire [19:0] resp_0_bits_uop_imm_packed; // @[dcache.scala:846:22]
wire resp_0_bits_uop_taken; // @[dcache.scala:846:22]
wire [5:0] resp_0_bits_uop_pc_lob; // @[dcache.scala:846:22]
wire resp_0_bits_uop_edge_inst; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_ftq_idx; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_br_tag; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_sfb; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_jal; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_jalr; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_br; // @[dcache.scala:846:22]
wire resp_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:846:22]
wire resp_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_iw_state; // @[dcache.scala:846:22]
wire [9:0] resp_0_bits_uop_fu_code; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_iq_type; // @[dcache.scala:846:22]
wire [39:0] resp_0_bits_uop_debug_pc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_is_rvc; // @[dcache.scala:846:22]
wire [31:0] resp_0_bits_uop_debug_inst; // @[dcache.scala:846:22]
wire [31:0] resp_0_bits_uop_inst; // @[dcache.scala:846:22]
wire [6:0] resp_0_bits_uop_uopc; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_std; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_sta; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_is_load; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:846:22]
wire resp_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:846:22]
wire [4:0] resp_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:846:22]
wire [2:0] resp_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:846:22]
wire [1:0] resp_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:846:22]
wire [3:0] resp_0_bits_uop_ctrl_br_type; // @[dcache.scala:846:22]
wire [1:0] _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73]
wire [63:0] _amoalu_io_out; // @[dcache.scala:896:24]
wire _lsu_release_arb_io_in_0_ready; // @[dcache.scala:814:31]
wire _lsu_release_arb_io_in_1_ready; // @[dcache.scala:814:31]
wire _wbArb_io_in_0_ready; // @[dcache.scala:805:21]
wire _wbArb_io_in_1_ready; // @[dcache.scala:805:21]
wire _wbArb_io_out_valid; // @[dcache.scala:805:21]
wire [19:0] _wbArb_io_out_bits_tag; // @[dcache.scala:805:21]
wire [5:0] _wbArb_io_out_bits_idx; // @[dcache.scala:805:21]
wire [2:0] _wbArb_io_out_bits_source; // @[dcache.scala:805:21]
wire [2:0] _wbArb_io_out_bits_param; // @[dcache.scala:805:21]
wire [7:0] _wbArb_io_out_bits_way_en; // @[dcache.scala:805:21]
wire _wbArb_io_out_bits_voluntary; // @[dcache.scala:805:21]
wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22]
wire _dataReadArb_io_in_1_ready; // @[dcache.scala:463:27]
wire _dataReadArb_io_in_2_ready; // @[dcache.scala:463:27]
wire _dataReadArb_io_out_valid; // @[dcache.scala:463:27]
wire [7:0] _dataReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:463:27]
wire [11:0] _dataReadArb_io_out_bits_req_0_addr; // @[dcache.scala:463:27]
wire _dataReadArb_io_out_bits_valid_0; // @[dcache.scala:463:27]
wire _dataWriteArb_io_in_1_ready; // @[dcache.scala:461:28]
wire [7:0] _dataWriteArb_io_out_bits_way_en; // @[dcache.scala:461:28]
wire [11:0] _dataWriteArb_io_out_bits_addr; // @[dcache.scala:461:28]
wire [1:0] _dataWriteArb_io_out_bits_wmask; // @[dcache.scala:461:28]
wire [127:0] _dataWriteArb_io_out_bits_data; // @[dcache.scala:461:28]
wire _metaReadArb_io_in_1_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_2_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_3_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_4_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_in_5_ready; // @[dcache.scala:445:27]
wire _metaReadArb_io_out_valid; // @[dcache.scala:445:27]
wire [5:0] _metaReadArb_io_out_bits_req_0_idx; // @[dcache.scala:445:27]
wire [7:0] _metaReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:445:27]
wire [19:0] _metaReadArb_io_out_bits_req_0_tag; // @[dcache.scala:445:27]
wire _metaWriteArb_io_in_0_ready; // @[dcache.scala:443:28]
wire _metaWriteArb_io_in_1_ready; // @[dcache.scala:443:28]
wire _metaWriteArb_io_out_valid; // @[dcache.scala:443:28]
wire [5:0] _metaWriteArb_io_out_bits_idx; // @[dcache.scala:443:28]
wire [7:0] _metaWriteArb_io_out_bits_way_en; // @[dcache.scala:443:28]
wire [19:0] _metaWriteArb_io_out_bits_tag; // @[dcache.scala:443:28]
wire [1:0] _metaWriteArb_io_out_bits_data_coh_state; // @[dcache.scala:443:28]
wire [19:0] _metaWriteArb_io_out_bits_data_tag; // @[dcache.scala:443:28]
wire _meta_0_io_read_ready; // @[dcache.scala:442:41]
wire _meta_0_io_write_ready; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_0_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_0_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_1_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_1_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_2_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_2_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_3_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_3_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_4_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_4_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_5_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_5_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_6_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_6_tag; // @[dcache.scala:442:41]
wire [1:0] _meta_0_io_resp_7_coh_state; // @[dcache.scala:442:41]
wire [19:0] _meta_0_io_resp_7_tag; // @[dcache.scala:442:41]
wire _mshrs_io_req_0_ready; // @[dcache.scala:433:21]
wire _mshrs_io_secondary_miss_0; // @[dcache.scala:433:21]
wire _mshrs_io_block_hit_0; // @[dcache.scala:433:21]
wire _mshrs_io_mem_grant_ready; // @[dcache.scala:433:21]
wire _mshrs_io_refill_valid; // @[dcache.scala:433:21]
wire [7:0] _mshrs_io_refill_bits_way_en; // @[dcache.scala:433:21]
wire [11:0] _mshrs_io_refill_bits_addr; // @[dcache.scala:433:21]
wire [127:0] _mshrs_io_refill_bits_data; // @[dcache.scala:433:21]
wire _mshrs_io_meta_write_valid; // @[dcache.scala:433:21]
wire [5:0] _mshrs_io_meta_write_bits_idx; // @[dcache.scala:433:21]
wire [7:0] _mshrs_io_meta_write_bits_way_en; // @[dcache.scala:433:21]
wire [1:0] _mshrs_io_meta_write_bits_data_coh_state; // @[dcache.scala:433:21]
wire [19:0] _mshrs_io_meta_write_bits_data_tag; // @[dcache.scala:433:21]
wire _mshrs_io_meta_read_valid; // @[dcache.scala:433:21]
wire [5:0] _mshrs_io_meta_read_bits_idx; // @[dcache.scala:433:21]
wire [7:0] _mshrs_io_meta_read_bits_way_en; // @[dcache.scala:433:21]
wire [19:0] _mshrs_io_meta_read_bits_tag; // @[dcache.scala:433:21]
wire _mshrs_io_replay_valid; // @[dcache.scala:433:21]
wire [4:0] _mshrs_io_replay_bits_uop_mem_cmd; // @[dcache.scala:433:21]
wire [39:0] _mshrs_io_replay_bits_addr; // @[dcache.scala:433:21]
wire [7:0] _mshrs_io_replay_bits_way_en; // @[dcache.scala:433:21]
wire _mshrs_io_wb_req_valid; // @[dcache.scala:433:21]
wire [19:0] _mshrs_io_wb_req_bits_tag; // @[dcache.scala:433:21]
wire [5:0] _mshrs_io_wb_req_bits_idx; // @[dcache.scala:433:21]
wire [2:0] _mshrs_io_wb_req_bits_source; // @[dcache.scala:433:21]
wire [2:0] _mshrs_io_wb_req_bits_param; // @[dcache.scala:433:21]
wire [7:0] _mshrs_io_wb_req_bits_way_en; // @[dcache.scala:433:21]
wire _mshrs_io_fence_rdy; // @[dcache.scala:433:21]
wire _mshrs_io_probe_rdy; // @[dcache.scala:433:21]
wire _prober_io_req_ready; // @[dcache.scala:432:22]
wire _prober_io_rep_valid; // @[dcache.scala:432:22]
wire [2:0] _prober_io_rep_bits_param; // @[dcache.scala:432:22]
wire [3:0] _prober_io_rep_bits_size; // @[dcache.scala:432:22]
wire [2:0] _prober_io_rep_bits_source; // @[dcache.scala:432:22]
wire [31:0] _prober_io_rep_bits_address; // @[dcache.scala:432:22]
wire _prober_io_meta_read_valid; // @[dcache.scala:432:22]
wire [5:0] _prober_io_meta_read_bits_idx; // @[dcache.scala:432:22]
wire [19:0] _prober_io_meta_read_bits_tag; // @[dcache.scala:432:22]
wire _prober_io_meta_write_valid; // @[dcache.scala:432:22]
wire [5:0] _prober_io_meta_write_bits_idx; // @[dcache.scala:432:22]
wire [7:0] _prober_io_meta_write_bits_way_en; // @[dcache.scala:432:22]
wire [19:0] _prober_io_meta_write_bits_tag; // @[dcache.scala:432:22]
wire [1:0] _prober_io_meta_write_bits_data_coh_state; // @[dcache.scala:432:22]
wire [19:0] _prober_io_meta_write_bits_data_tag; // @[dcache.scala:432:22]
wire _prober_io_wb_req_valid; // @[dcache.scala:432:22]
wire [19:0] _prober_io_wb_req_bits_tag; // @[dcache.scala:432:22]
wire [5:0] _prober_io_wb_req_bits_idx; // @[dcache.scala:432:22]
wire [2:0] _prober_io_wb_req_bits_source; // @[dcache.scala:432:22]
wire [2:0] _prober_io_wb_req_bits_param; // @[dcache.scala:432:22]
wire [7:0] _prober_io_wb_req_bits_way_en; // @[dcache.scala:432:22]
wire _prober_io_mshr_wb_rdy; // @[dcache.scala:432:22]
wire _prober_io_lsu_release_valid; // @[dcache.scala:432:22]
wire [2:0] _prober_io_lsu_release_bits_param; // @[dcache.scala:432:22]
wire [3:0] _prober_io_lsu_release_bits_size; // @[dcache.scala:432:22]
wire [2:0] _prober_io_lsu_release_bits_source; // @[dcache.scala:432:22]
wire [31:0] _prober_io_lsu_release_bits_address; // @[dcache.scala:432:22]
wire _prober_io_state_valid; // @[dcache.scala:432:22]
wire [39:0] _prober_io_state_bits; // @[dcache.scala:432:22]
wire _wb_io_req_ready; // @[dcache.scala:431:18]
wire _wb_io_meta_read_valid; // @[dcache.scala:431:18]
wire [5:0] _wb_io_meta_read_bits_idx; // @[dcache.scala:431:18]
wire [19:0] _wb_io_meta_read_bits_tag; // @[dcache.scala:431:18]
wire _wb_io_resp; // @[dcache.scala:431:18]
wire _wb_io_idx_valid; // @[dcache.scala:431:18]
wire [5:0] _wb_io_idx_bits; // @[dcache.scala:431:18]
wire _wb_io_data_req_valid; // @[dcache.scala:431:18]
wire [7:0] _wb_io_data_req_bits_way_en; // @[dcache.scala:431:18]
wire [11:0] _wb_io_data_req_bits_addr; // @[dcache.scala:431:18]
wire _wb_io_release_valid; // @[dcache.scala:431:18]
wire [2:0] _wb_io_release_bits_opcode; // @[dcache.scala:431:18]
wire [2:0] _wb_io_release_bits_param; // @[dcache.scala:431:18]
wire [31:0] _wb_io_release_bits_address; // @[dcache.scala:431:18]
wire [127:0] _wb_io_release_bits_data; // @[dcache.scala:431:18]
wire _wb_io_lsu_release_valid; // @[dcache.scala:431:18]
wire [2:0] _wb_io_lsu_release_bits_param; // @[dcache.scala:431:18]
wire [31:0] _wb_io_lsu_release_bits_address; // @[dcache.scala:431:18]
wire [127:0] _wb_io_lsu_release_bits_data; // @[dcache.scala:431:18]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[dcache.scala:413:7]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[dcache.scala:413:7]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[dcache.scala:413:7]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[dcache.scala:413:7]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[dcache.scala:413:7]
wire [2:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[dcache.scala:413:7]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[dcache.scala:413:7]
wire [15:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[dcache.scala:413:7]
wire [127:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[dcache.scala:413:7]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[dcache.scala:413:7]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[dcache.scala:413:7]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[dcache.scala:413:7]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[dcache.scala:413:7]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[dcache.scala:413:7]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[dcache.scala:413:7]
wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[dcache.scala:413:7]
wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[dcache.scala:413:7]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[dcache.scala:413:7]
wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[dcache.scala:413:7]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[dcache.scala:413:7]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[dcache.scala:413:7]
wire io_lsu_req_valid_0 = io_lsu_req_valid; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_valid_0 = io_lsu_req_bits_0_valid; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_uopc_0 = io_lsu_req_bits_0_bits_uop_uopc; // @[dcache.scala:413:7]
wire [31:0] io_lsu_req_bits_0_bits_uop_inst_0 = io_lsu_req_bits_0_bits_uop_inst; // @[dcache.scala:413:7]
wire [31:0] io_lsu_req_bits_0_bits_uop_debug_inst_0 = io_lsu_req_bits_0_bits_uop_debug_inst; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_rvc_0 = io_lsu_req_bits_0_bits_uop_is_rvc; // @[dcache.scala:413:7]
wire [39:0] io_lsu_req_bits_0_bits_uop_debug_pc_0 = io_lsu_req_bits_0_bits_uop_debug_pc; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_iq_type_0 = io_lsu_req_bits_0_bits_uop_iq_type; // @[dcache.scala:413:7]
wire [9:0] io_lsu_req_bits_0_bits_uop_fu_code_0 = io_lsu_req_bits_0_bits_uop_fu_code; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_ctrl_br_type_0 = io_lsu_req_bits_0_bits_uop_ctrl_br_type; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_ctrl_op1_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_op2_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_imm_sel_0 = io_lsu_req_bits_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_ctrl_op_fcn_0 = io_lsu_req_bits_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:413:7]
wire [2:0] io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_load_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_load; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_sta_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_sta; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ctrl_is_std_0 = io_lsu_req_bits_0_bits_uop_ctrl_is_std; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_iw_state_0 = io_lsu_req_bits_0_bits_uop_iw_state; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_iw_p1_poisoned_0 = io_lsu_req_bits_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_iw_p2_poisoned_0 = io_lsu_req_bits_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_br_0 = io_lsu_req_bits_0_bits_uop_is_br; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_jalr_0 = io_lsu_req_bits_0_bits_uop_is_jalr; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_jal_0 = io_lsu_req_bits_0_bits_uop_is_jal; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_sfb_0 = io_lsu_req_bits_0_bits_uop_is_sfb; // @[dcache.scala:413:7]
wire [15:0] io_lsu_req_bits_0_bits_uop_br_mask_0 = io_lsu_req_bits_0_bits_uop_br_mask; // @[dcache.scala:413:7]
wire [3:0] io_lsu_req_bits_0_bits_uop_br_tag_0 = io_lsu_req_bits_0_bits_uop_br_tag; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_ftq_idx_0 = io_lsu_req_bits_0_bits_uop_ftq_idx; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_edge_inst_0 = io_lsu_req_bits_0_bits_uop_edge_inst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_pc_lob_0 = io_lsu_req_bits_0_bits_uop_pc_lob; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_taken_0 = io_lsu_req_bits_0_bits_uop_taken; // @[dcache.scala:413:7]
wire [19:0] io_lsu_req_bits_0_bits_uop_imm_packed_0 = io_lsu_req_bits_0_bits_uop_imm_packed; // @[dcache.scala:413:7]
wire [11:0] io_lsu_req_bits_0_bits_uop_csr_addr_0 = io_lsu_req_bits_0_bits_uop_csr_addr; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_rob_idx_0 = io_lsu_req_bits_0_bits_uop_rob_idx; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_ldq_idx_0 = io_lsu_req_bits_0_bits_uop_ldq_idx; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_stq_idx_0 = io_lsu_req_bits_0_bits_uop_stq_idx; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx_0 = io_lsu_req_bits_0_bits_uop_rxq_idx; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_pdst_0 = io_lsu_req_bits_0_bits_uop_pdst; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs1_0 = io_lsu_req_bits_0_bits_uop_prs1; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs2_0 = io_lsu_req_bits_0_bits_uop_prs2; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_prs3_0 = io_lsu_req_bits_0_bits_uop_prs3; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_ppred_0 = io_lsu_req_bits_0_bits_uop_ppred; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs1_busy_0 = io_lsu_req_bits_0_bits_uop_prs1_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs2_busy_0 = io_lsu_req_bits_0_bits_uop_prs2_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_prs3_busy_0 = io_lsu_req_bits_0_bits_uop_prs3_busy; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ppred_busy_0 = io_lsu_req_bits_0_bits_uop_ppred_busy; // @[dcache.scala:413:7]
wire [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst_0 = io_lsu_req_bits_0_bits_uop_stale_pdst; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_exception_0 = io_lsu_req_bits_0_bits_uop_exception; // @[dcache.scala:413:7]
wire [63:0] io_lsu_req_bits_0_bits_uop_exc_cause_0 = io_lsu_req_bits_0_bits_uop_exc_cause; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bypassable_0 = io_lsu_req_bits_0_bits_uop_bypassable; // @[dcache.scala:413:7]
wire [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd_0 = io_lsu_req_bits_0_bits_uop_mem_cmd; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_mem_size_0 = io_lsu_req_bits_0_bits_uop_mem_size; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_mem_signed_0 = io_lsu_req_bits_0_bits_uop_mem_signed; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_fence_0 = io_lsu_req_bits_0_bits_uop_is_fence; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_fencei_0 = io_lsu_req_bits_0_bits_uop_is_fencei; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_amo_0 = io_lsu_req_bits_0_bits_uop_is_amo; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_uses_ldq_0 = io_lsu_req_bits_0_bits_uop_uses_ldq; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_uses_stq_0 = io_lsu_req_bits_0_bits_uop_uses_stq; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0 = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_is_unique_0 = io_lsu_req_bits_0_bits_uop_is_unique; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_flush_on_commit_0 = io_lsu_req_bits_0_bits_uop_flush_on_commit; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_ldst_0 = io_lsu_req_bits_0_bits_uop_ldst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs1_0 = io_lsu_req_bits_0_bits_uop_lrs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs2_0 = io_lsu_req_bits_0_bits_uop_lrs2; // @[dcache.scala:413:7]
wire [5:0] io_lsu_req_bits_0_bits_uop_lrs3_0 = io_lsu_req_bits_0_bits_uop_lrs3; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_ldst_val_0 = io_lsu_req_bits_0_bits_uop_ldst_val; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype_0 = io_lsu_req_bits_0_bits_uop_dst_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs1_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs2_rtype; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_frs3_en_0 = io_lsu_req_bits_0_bits_uop_frs3_en; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_fp_val_0 = io_lsu_req_bits_0_bits_uop_fp_val; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_fp_single_0 = io_lsu_req_bits_0_bits_uop_fp_single; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_pf_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ae_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ma_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bp_debug_if_0 = io_lsu_req_bits_0_bits_uop_bp_debug_if; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0 = io_lsu_req_bits_0_bits_uop_bp_xcpt_if; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_debug_fsrc_0 = io_lsu_req_bits_0_bits_uop_debug_fsrc; // @[dcache.scala:413:7]
wire [1:0] io_lsu_req_bits_0_bits_uop_debug_tsrc_0 = io_lsu_req_bits_0_bits_uop_debug_tsrc; // @[dcache.scala:413:7]
wire [39:0] io_lsu_req_bits_0_bits_addr_0 = io_lsu_req_bits_0_bits_addr; // @[dcache.scala:413:7]
wire [63:0] io_lsu_req_bits_0_bits_data_0 = io_lsu_req_bits_0_bits_data; // @[dcache.scala:413:7]
wire io_lsu_req_bits_0_bits_is_hella_0 = io_lsu_req_bits_0_bits_is_hella; // @[dcache.scala:413:7]
wire io_lsu_s1_kill_0_0 = io_lsu_s1_kill_0; // @[dcache.scala:413:7]
wire [15:0] io_lsu_brupdate_b1_resolve_mask_0 = io_lsu_brupdate_b1_resolve_mask; // @[dcache.scala:413:7]
wire [15:0] io_lsu_brupdate_b1_mispredict_mask_0 = io_lsu_brupdate_b1_mispredict_mask; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_uopc_0 = io_lsu_brupdate_b2_uop_uopc; // @[dcache.scala:413:7]
wire [31:0] io_lsu_brupdate_b2_uop_inst_0 = io_lsu_brupdate_b2_uop_inst; // @[dcache.scala:413:7]
wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0 = io_lsu_brupdate_b2_uop_debug_inst; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_rvc_0 = io_lsu_brupdate_b2_uop_is_rvc; // @[dcache.scala:413:7]
wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0 = io_lsu_brupdate_b2_uop_debug_pc; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_iq_type_0 = io_lsu_brupdate_b2_uop_iq_type; // @[dcache.scala:413:7]
wire [9:0] io_lsu_brupdate_b2_uop_fu_code_0 = io_lsu_brupdate_b2_uop_fu_code; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type_0 = io_lsu_brupdate_b2_uop_ctrl_br_type; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel_0 = io_lsu_brupdate_b2_uop_ctrl_op1_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel_0 = io_lsu_brupdate_b2_uop_ctrl_op2_sel; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel_0 = io_lsu_brupdate_b2_uop_ctrl_imm_sel; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn_0 = io_lsu_brupdate_b2_uop_ctrl_op_fcn; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0 = io_lsu_brupdate_b2_uop_ctrl_fcn_dw; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0 = io_lsu_brupdate_b2_uop_ctrl_csr_cmd; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_load_0 = io_lsu_brupdate_b2_uop_ctrl_is_load; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_sta_0 = io_lsu_brupdate_b2_uop_ctrl_is_sta; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ctrl_is_std_0 = io_lsu_brupdate_b2_uop_ctrl_is_std; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_iw_state_0 = io_lsu_brupdate_b2_uop_iw_state; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_iw_p1_poisoned_0 = io_lsu_brupdate_b2_uop_iw_p1_poisoned; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_iw_p2_poisoned_0 = io_lsu_brupdate_b2_uop_iw_p2_poisoned; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_br_0 = io_lsu_brupdate_b2_uop_is_br; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_jalr_0 = io_lsu_brupdate_b2_uop_is_jalr; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_jal_0 = io_lsu_brupdate_b2_uop_is_jal; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_sfb_0 = io_lsu_brupdate_b2_uop_is_sfb; // @[dcache.scala:413:7]
wire [15:0] io_lsu_brupdate_b2_uop_br_mask_0 = io_lsu_brupdate_b2_uop_br_mask; // @[dcache.scala:413:7]
wire [3:0] io_lsu_brupdate_b2_uop_br_tag_0 = io_lsu_brupdate_b2_uop_br_tag; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_ftq_idx_0 = io_lsu_brupdate_b2_uop_ftq_idx; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_edge_inst_0 = io_lsu_brupdate_b2_uop_edge_inst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0 = io_lsu_brupdate_b2_uop_pc_lob; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_taken_0 = io_lsu_brupdate_b2_uop_taken; // @[dcache.scala:413:7]
wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0 = io_lsu_brupdate_b2_uop_imm_packed; // @[dcache.scala:413:7]
wire [11:0] io_lsu_brupdate_b2_uop_csr_addr_0 = io_lsu_brupdate_b2_uop_csr_addr; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_rob_idx_0 = io_lsu_brupdate_b2_uop_rob_idx; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_ldq_idx_0 = io_lsu_brupdate_b2_uop_ldq_idx; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_stq_idx_0 = io_lsu_brupdate_b2_uop_stq_idx; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0 = io_lsu_brupdate_b2_uop_rxq_idx; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_pdst_0 = io_lsu_brupdate_b2_uop_pdst; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs1_0 = io_lsu_brupdate_b2_uop_prs1; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs2_0 = io_lsu_brupdate_b2_uop_prs2; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_prs3_0 = io_lsu_brupdate_b2_uop_prs3; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_ppred_0 = io_lsu_brupdate_b2_uop_ppred; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs1_busy_0 = io_lsu_brupdate_b2_uop_prs1_busy; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs2_busy_0 = io_lsu_brupdate_b2_uop_prs2_busy; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_prs3_busy_0 = io_lsu_brupdate_b2_uop_prs3_busy; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ppred_busy_0 = io_lsu_brupdate_b2_uop_ppred_busy; // @[dcache.scala:413:7]
wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst_0 = io_lsu_brupdate_b2_uop_stale_pdst; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_exception_0 = io_lsu_brupdate_b2_uop_exception; // @[dcache.scala:413:7]
wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0 = io_lsu_brupdate_b2_uop_exc_cause; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bypassable_0 = io_lsu_brupdate_b2_uop_bypassable; // @[dcache.scala:413:7]
wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0 = io_lsu_brupdate_b2_uop_mem_cmd; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0 = io_lsu_brupdate_b2_uop_mem_size; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_mem_signed_0 = io_lsu_brupdate_b2_uop_mem_signed; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_fence_0 = io_lsu_brupdate_b2_uop_is_fence; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_fencei_0 = io_lsu_brupdate_b2_uop_is_fencei; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_amo_0 = io_lsu_brupdate_b2_uop_is_amo; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_uses_ldq_0 = io_lsu_brupdate_b2_uop_uses_ldq; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_uses_stq_0 = io_lsu_brupdate_b2_uop_uses_stq; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_is_unique_0 = io_lsu_brupdate_b2_uop_is_unique; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_flush_on_commit_0 = io_lsu_brupdate_b2_uop_flush_on_commit; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_ldst_0 = io_lsu_brupdate_b2_uop_ldst; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0 = io_lsu_brupdate_b2_uop_lrs1; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0 = io_lsu_brupdate_b2_uop_lrs2; // @[dcache.scala:413:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0 = io_lsu_brupdate_b2_uop_lrs3; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_ldst_val_0 = io_lsu_brupdate_b2_uop_ldst_val; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0 = io_lsu_brupdate_b2_uop_dst_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0 = io_lsu_brupdate_b2_uop_lrs1_rtype; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0 = io_lsu_brupdate_b2_uop_lrs2_rtype; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_frs3_en_0 = io_lsu_brupdate_b2_uop_frs3_en; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_fp_val_0 = io_lsu_brupdate_b2_uop_fp_val; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_fp_single_0 = io_lsu_brupdate_b2_uop_fp_single; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bp_debug_if_0 = io_lsu_brupdate_b2_uop_bp_debug_if; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc_0 = io_lsu_brupdate_b2_uop_debug_fsrc; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc_0 = io_lsu_brupdate_b2_uop_debug_tsrc; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_valid_0 = io_lsu_brupdate_b2_valid; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_mispredict_0 = io_lsu_brupdate_b2_mispredict; // @[dcache.scala:413:7]
wire io_lsu_brupdate_b2_taken_0 = io_lsu_brupdate_b2_taken; // @[dcache.scala:413:7]
wire [2:0] io_lsu_brupdate_b2_cfi_type_0 = io_lsu_brupdate_b2_cfi_type; // @[dcache.scala:413:7]
wire [1:0] io_lsu_brupdate_b2_pc_sel_0 = io_lsu_brupdate_b2_pc_sel; // @[dcache.scala:413:7]
wire [39:0] io_lsu_brupdate_b2_jalr_target_0 = io_lsu_brupdate_b2_jalr_target; // @[dcache.scala:413:7]
wire [20:0] io_lsu_brupdate_b2_target_offset_0 = io_lsu_brupdate_b2_target_offset; // @[dcache.scala:413:7]
wire io_lsu_exception_0 = io_lsu_exception; // @[dcache.scala:413:7]
wire [6:0] io_lsu_rob_pnr_idx_0 = io_lsu_rob_pnr_idx; // @[dcache.scala:413:7]
wire [6:0] io_lsu_rob_head_idx_0 = io_lsu_rob_head_idx; // @[dcache.scala:413:7]
wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:413:7]
wire io_lsu_force_order_0 = io_lsu_force_order; // @[dcache.scala:413:7]
wire auto_out_a_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire auto_out_c_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:413:7]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire mshr_read_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_br = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_jal = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_taken = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_exception = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bypassable = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_fence = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_amo = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_is_unique = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_fp_val = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_fp_single = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_is_hella = 1'h0; // @[dcache.scala:517:27]
wire mshr_read_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire mshr_read_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire mshr_read_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_br = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_jal = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_taken = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_exception = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bypassable = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_fence = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_amo = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_is_unique = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_fp_val = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_fp_single = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_is_hella = 1'h0; // @[dcache.scala:532:20]
wire wb_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire wb_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire wb_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_br = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_jal = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_taken = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_exception = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bypassable = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_fence = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_amo = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_is_unique = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_fp_val = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_fp_single = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_is_hella = 1'h0; // @[dcache.scala:553:26]
wire prober_req_0_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire prober_req_0_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire prober_req_0_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire prefetch_fire = 1'h0; // @[Decoupled.scala:51:35]
wire prefetch_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_fcn_dw = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_load = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_sta = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ctrl_is_std = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_iw_p1_poisoned = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_iw_p2_poisoned = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_br = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_jalr = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_jal = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_taken = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_exception = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bypassable = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_fence = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_amo = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_is_unique = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_ldst_val = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_fp_val = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_fp_single = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:568:27]
wire prefetch_req_0_is_hella = 1'h0; // @[dcache.scala:568:27]
wire _s0_valid_WIRE_2_0 = 1'h0; // @[dcache.scala:581:82]
wire _s2_has_permission_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _s2_has_permission_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _s2_new_hit_state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire s2_nack_data_0 = 1'h0; // @[dcache.scala:427:49]
wire opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _nodeOut_c_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _nodeOut_c_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73]
wire cache_resp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire cache_resp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire _s0_valid_WIRE_1_0 = 1'h1; // @[dcache.scala:581:48]
wire _mshrs_io_req_0_valid_T_6 = 1'h1; // @[dcache.scala:750:29]
wire _uncache_respond_T_1 = 1'h1; // @[dcache.scala:849:51]
wire [127:0] _nodeOut_c_bits_T_4 = 128'h0; // @[Mux.scala:30:73]
wire [7:0] maskedBeats_1 = 8'h0; // @[Arbiter.scala:82:69]
wire [7:0] decode = 8'h3; // @[Edges.scala:220:59]
wire [11:0] _decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [3:0] _s2_has_permission_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _s2_new_hit_state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _s2_has_permission_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _s2_new_hit_state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _s2_has_permission_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _s2_new_hit_state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _s2_has_permission_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _s2_new_hit_state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _s2_has_permission_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _s2_new_hit_state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] mshr_read_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_br_tag = 4'h0; // @[dcache.scala:517:27]
wire [3:0] mshr_read_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] mshr_read_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] wb_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_br_tag = 4'h0; // @[dcache.scala:532:20]
wire [3:0] wb_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] wb_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] prober_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_br_tag = 4'h0; // @[dcache.scala:553:26]
wire [3:0] prober_req_0_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] prober_req_0_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [3:0] prefetch_req_0_uop_ctrl_br_type = 4'h0; // @[dcache.scala:568:27]
wire [3:0] prefetch_req_0_uop_br_tag = 4'h0; // @[dcache.scala:568:27]
wire [3:0] _s2_has_permission_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _s2_new_hit_state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [1:0] mshr_read_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_iw_state = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_mem_size = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] mshr_read_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] wb_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_iw_state = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_mem_size = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] prober_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_iw_state = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_mem_size = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] prefetch_req_0_uop_ctrl_op1_sel = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_iw_state = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_mem_size = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_debug_fsrc = 2'h0; // @[dcache.scala:568:27]
wire [1:0] prefetch_req_0_uop_debug_tsrc = 2'h0; // @[dcache.scala:568:27]
wire [1:0] _s2_has_permission_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_has_permission_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _s2_new_hit_state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [3:0] _s2_has_permission_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _s2_new_hit_state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _s2_has_permission_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _s2_new_hit_state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _s2_has_permission_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _s2_new_hit_state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _s2_has_permission_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _s2_new_hit_state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _s2_has_permission_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _s2_new_hit_state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _s2_has_permission_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _s2_new_hit_state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [33:0] _metaReadArb_io_in_5_bits_req_0_idx_T = 34'h0; // @[dcache.scala:573:74]
wire [63:0] mshr_read_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:517:27]
wire [63:0] mshr_read_req_0_data = 64'h0; // @[dcache.scala:517:27]
wire [63:0] mshr_read_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] wb_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:532:20]
wire [63:0] wb_req_0_data = 64'h0; // @[dcache.scala:532:20]
wire [63:0] wb_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] prober_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:553:26]
wire [63:0] prober_req_0_data = 64'h0; // @[dcache.scala:553:26]
wire [63:0] prober_req_0_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [63:0] prefetch_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:568:27]
wire [63:0] prefetch_req_0_data = 64'h0; // @[dcache.scala:568:27]
wire [39:0] mshr_read_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:517:27]
wire [39:0] mshr_read_req_0_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] wb_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:532:20]
wire [39:0] wb_req_0_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] prober_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:553:26]
wire [39:0] prober_req_0_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [39:0] prefetch_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:568:27]
wire [39:0] prefetch_req_0_addr = 40'h0; // @[dcache.scala:568:27]
wire [5:0] mshr_read_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_ldst = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:517:27]
wire [5:0] mshr_read_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] mshr_read_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_ldst = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:532:20]
wire [5:0] wb_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] wb_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_ldst = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:553:26]
wire [5:0] prober_req_0_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prober_req_0_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] prefetch_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_ldst = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:568:27]
wire [5:0] prefetch_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:568:27]
wire [4:0] mshr_read_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_ldq_idx = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_stq_idx = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_ppred = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:517:27]
wire [4:0] mshr_read_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] mshr_read_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] wb_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_ldq_idx = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_stq_idx = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_ppred = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:532:20]
wire [4:0] wb_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] wb_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] prober_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_ldq_idx = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_stq_idx = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_ppred = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:553:26]
wire [4:0] prober_req_0_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] prober_req_0_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] prefetch_req_0_uop_ctrl_op_fcn = 5'h0; // @[dcache.scala:568:27]
wire [4:0] prefetch_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:568:27]
wire [4:0] prefetch_req_0_uop_ldq_idx = 5'h0; // @[dcache.scala:568:27]
wire [4:0] prefetch_req_0_uop_stq_idx = 5'h0; // @[dcache.scala:568:27]
wire [4:0] prefetch_req_0_uop_ppred = 5'h0; // @[dcache.scala:568:27]
wire [4:0] prefetch_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:568:27]
wire [6:0] mshr_read_req_0_uop_uopc = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_rob_idx = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_pdst = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_prs1 = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_prs2 = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_prs3 = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:517:27]
wire [6:0] mshr_read_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] mshr_read_req_0_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uopc = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_rob_idx = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_pdst = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_prs1 = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_prs2 = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_prs3 = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:532:20]
wire [6:0] wb_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] wb_req_0_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uopc = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_rob_idx = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_pdst = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_prs1 = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_prs2 = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_prs3 = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:553:26]
wire [6:0] prober_req_0_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] prober_req_0_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] prefetch_req_0_uop_uopc = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_rob_idx = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_pdst = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_prs1 = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_prs2 = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_prs3 = 7'h0; // @[dcache.scala:568:27]
wire [6:0] prefetch_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:568:27]
wire [11:0] mshr_read_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:517:27]
wire [11:0] mshr_read_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] wb_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:532:20]
wire [11:0] wb_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] prober_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:553:26]
wire [11:0] prober_req_0_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [11:0] prefetch_req_0_uop_csr_addr = 12'h0; // @[dcache.scala:568:27]
wire [19:0] mshr_read_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:517:27]
wire [19:0] mshr_read_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] wb_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:532:20]
wire [19:0] wb_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] prober_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:553:26]
wire [19:0] prober_req_0_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [19:0] prefetch_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:568:27]
wire [15:0] mshr_read_req_0_uop_br_mask = 16'h0; // @[dcache.scala:517:27]
wire [15:0] mshr_read_req_0_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] wb_req_0_uop_br_mask = 16'h0; // @[dcache.scala:532:20]
wire [15:0] wb_req_0_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] prober_req_0_uop_br_mask = 16'h0; // @[dcache.scala:553:26]
wire [15:0] prober_req_0_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [15:0] prefetch_req_0_uop_br_mask = 16'h0; // @[dcache.scala:568:27]
wire [2:0] mshr_read_req_0_uop_iq_type = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:517:27]
wire [2:0] mshr_read_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] mshr_read_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] mshr_read_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] mshr_read_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_iq_type = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:532:20]
wire [2:0] wb_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] wb_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] wb_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_iq_type = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:553:26]
wire [2:0] prober_req_0_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] prober_req_0_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] prober_req_0_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [2:0] prefetch_req_0_uop_iq_type = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_op2_sel = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_imm_sel = 3'h0; // @[dcache.scala:568:27]
wire [2:0] prefetch_req_0_uop_ctrl_csr_cmd = 3'h0; // @[dcache.scala:568:27]
wire [9:0] mshr_read_req_0_uop_fu_code = 10'h0; // @[dcache.scala:517:27]
wire [9:0] mshr_read_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] wb_req_0_uop_fu_code = 10'h0; // @[dcache.scala:532:20]
wire [9:0] wb_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] prober_req_0_uop_fu_code = 10'h0; // @[dcache.scala:553:26]
wire [9:0] prober_req_0_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [9:0] prefetch_req_0_uop_fu_code = 10'h0; // @[dcache.scala:568:27]
wire [31:0] mshr_read_req_0_uop_inst = 32'h0; // @[dcache.scala:517:27]
wire [31:0] mshr_read_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:517:27]
wire [31:0] mshr_read_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] mshr_read_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] wb_req_0_uop_inst = 32'h0; // @[dcache.scala:532:20]
wire [31:0] wb_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:532:20]
wire [31:0] wb_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] wb_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prober_req_0_uop_inst = 32'h0; // @[dcache.scala:553:26]
wire [31:0] prober_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:553:26]
wire [31:0] prober_req_0_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prober_req_0_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] prefetch_req_0_uop_inst = 32'h0; // @[dcache.scala:568:27]
wire [31:0] prefetch_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:568:27]
wire [1:0] mshr_read_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:517:27]
wire [1:0] mshr_read_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] wb_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:532:20]
wire [1:0] wb_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [1:0] prober_req_0_uop_dst_rtype = 2'h2; // @[dcache.scala:553:26]
wire [1:0] prober_req_0_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [7:0] _dataReadArb_io_in_2_bits_req_0_way_en_T = 8'hFF; // @[dcache.scala:491:48]
wire [1:0] _s2_has_permission_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_new_hit_state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _s2_has_permission_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_has_permission_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _s2_new_hit_state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[MixedNode.scala:542:17]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[MixedNode.scala:542:17]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire _io_lsu_req_ready_T; // @[dcache.scala:480:50]
wire _s0_valid_WIRE_0 = io_lsu_req_bits_0_valid_0; // @[dcache.scala:413:7, :579:46]
wire [6:0] _s0_req_WIRE_0_uop_uopc = io_lsu_req_bits_0_bits_uop_uopc_0; // @[dcache.scala:413:7, :582:54]
wire [31:0] _s0_req_WIRE_0_uop_inst = io_lsu_req_bits_0_bits_uop_inst_0; // @[dcache.scala:413:7, :582:54]
wire [31:0] _s0_req_WIRE_0_uop_debug_inst = io_lsu_req_bits_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_rvc = io_lsu_req_bits_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7, :582:54]
wire [39:0] _s0_req_WIRE_0_uop_debug_pc = io_lsu_req_bits_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_iq_type = io_lsu_req_bits_0_bits_uop_iq_type_0; // @[dcache.scala:413:7, :582:54]
wire [9:0] _s0_req_WIRE_0_uop_fu_code = io_lsu_req_bits_0_bits_uop_fu_code_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_ctrl_br_type = io_lsu_req_bits_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_ctrl_op1_sel = io_lsu_req_bits_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_op2_sel = io_lsu_req_bits_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_imm_sel = io_lsu_req_bits_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_ctrl_op_fcn = io_lsu_req_bits_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_fcn_dw = io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7, :582:54]
wire [2:0] _s0_req_WIRE_0_uop_ctrl_csr_cmd = io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_load = io_lsu_req_bits_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_sta = io_lsu_req_bits_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ctrl_is_std = io_lsu_req_bits_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_iw_state = io_lsu_req_bits_0_bits_uop_iw_state_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_iw_p1_poisoned = io_lsu_req_bits_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_iw_p2_poisoned = io_lsu_req_bits_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_br = io_lsu_req_bits_0_bits_uop_is_br_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_jalr = io_lsu_req_bits_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_jal = io_lsu_req_bits_0_bits_uop_is_jal_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_sfb = io_lsu_req_bits_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7, :582:54]
wire [15:0] _s0_req_WIRE_0_uop_br_mask = io_lsu_req_bits_0_bits_uop_br_mask_0; // @[dcache.scala:413:7, :582:54]
wire [3:0] _s0_req_WIRE_0_uop_br_tag = io_lsu_req_bits_0_bits_uop_br_tag_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_ftq_idx = io_lsu_req_bits_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_edge_inst = io_lsu_req_bits_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_pc_lob = io_lsu_req_bits_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_taken = io_lsu_req_bits_0_bits_uop_taken_0; // @[dcache.scala:413:7, :582:54]
wire [19:0] _s0_req_WIRE_0_uop_imm_packed = io_lsu_req_bits_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7, :582:54]
wire [11:0] _s0_req_WIRE_0_uop_csr_addr = io_lsu_req_bits_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_rob_idx = io_lsu_req_bits_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_ldq_idx = io_lsu_req_bits_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_stq_idx = io_lsu_req_bits_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_rxq_idx = io_lsu_req_bits_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_pdst = io_lsu_req_bits_0_bits_uop_pdst_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_prs1 = io_lsu_req_bits_0_bits_uop_prs1_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_prs2 = io_lsu_req_bits_0_bits_uop_prs2_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_prs3 = io_lsu_req_bits_0_bits_uop_prs3_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_ppred = io_lsu_req_bits_0_bits_uop_ppred_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs1_busy = io_lsu_req_bits_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs2_busy = io_lsu_req_bits_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_prs3_busy = io_lsu_req_bits_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ppred_busy = io_lsu_req_bits_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7, :582:54]
wire [6:0] _s0_req_WIRE_0_uop_stale_pdst = io_lsu_req_bits_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_exception = io_lsu_req_bits_0_bits_uop_exception_0; // @[dcache.scala:413:7, :582:54]
wire [63:0] _s0_req_WIRE_0_uop_exc_cause = io_lsu_req_bits_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bypassable = io_lsu_req_bits_0_bits_uop_bypassable_0; // @[dcache.scala:413:7, :582:54]
wire [4:0] _s0_req_WIRE_0_uop_mem_cmd = io_lsu_req_bits_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_mem_size = io_lsu_req_bits_0_bits_uop_mem_size_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_mem_signed = io_lsu_req_bits_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_fence = io_lsu_req_bits_0_bits_uop_is_fence_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_fencei = io_lsu_req_bits_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_amo = io_lsu_req_bits_0_bits_uop_is_amo_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_uses_ldq = io_lsu_req_bits_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_uses_stq = io_lsu_req_bits_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_sys_pc2epc = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_is_unique = io_lsu_req_bits_0_bits_uop_is_unique_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_flush_on_commit = io_lsu_req_bits_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ldst_is_rs1 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_ldst = io_lsu_req_bits_0_bits_uop_ldst_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs1 = io_lsu_req_bits_0_bits_uop_lrs1_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs2 = io_lsu_req_bits_0_bits_uop_lrs2_0; // @[dcache.scala:413:7, :582:54]
wire [5:0] _s0_req_WIRE_0_uop_lrs3 = io_lsu_req_bits_0_bits_uop_lrs3_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_ldst_val = io_lsu_req_bits_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_dst_rtype = io_lsu_req_bits_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_lrs1_rtype = io_lsu_req_bits_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_lrs2_rtype = io_lsu_req_bits_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_frs3_en = io_lsu_req_bits_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_fp_val = io_lsu_req_bits_0_bits_uop_fp_val_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_fp_single = io_lsu_req_bits_0_bits_uop_fp_single_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_pf_if = io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_ae_if = io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_xcpt_ma_if = io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bp_debug_if = io_lsu_req_bits_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_uop_bp_xcpt_if = io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_debug_fsrc = io_lsu_req_bits_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7, :582:54]
wire [1:0] _s0_req_WIRE_0_uop_debug_tsrc = io_lsu_req_bits_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7, :582:54]
wire [39:0] _s0_req_WIRE_0_addr = io_lsu_req_bits_0_bits_addr_0; // @[dcache.scala:413:7, :582:54]
wire [63:0] _s0_req_WIRE_0_data = io_lsu_req_bits_0_bits_data_0; // @[dcache.scala:413:7, :582:54]
wire _s0_req_WIRE_0_is_hella = io_lsu_req_bits_0_bits_is_hella_0; // @[dcache.scala:413:7, :582:54]
wire _io_lsu_resp_0_valid_T_6; // @[dcache.scala:858:78]
wire [6:0] io_lsu_resp_0_bits_out_uop_uopc; // @[util.scala:101:23]
wire [31:0] io_lsu_resp_0_bits_out_uop_inst; // @[util.scala:101:23]
wire [31:0] io_lsu_resp_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
wire [39:0] io_lsu_resp_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_iq_type; // @[util.scala:101:23]
wire [9:0] io_lsu_resp_0_bits_out_uop_fu_code; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
wire [2:0] io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_iw_state; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_br; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_jal; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [15:0] io_lsu_resp_0_bits_out_uop_br_mask; // @[util.scala:101:23]
wire [3:0] io_lsu_resp_0_bits_out_uop_br_tag; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_taken; // @[util.scala:101:23]
wire [19:0] io_lsu_resp_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
wire [11:0] io_lsu_resp_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_pdst; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_prs1; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_prs2; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_prs3; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_ppred; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
wire [6:0] io_lsu_resp_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_exception; // @[util.scala:101:23]
wire [63:0] io_lsu_resp_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bypassable; // @[util.scala:101:23]
wire [4:0] io_lsu_resp_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_mem_size; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_fence; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_amo; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_is_unique; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_ldst; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs1; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs2; // @[util.scala:101:23]
wire [5:0] io_lsu_resp_0_bits_out_uop_lrs3; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_fp_val; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_fp_single; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
wire [1:0] io_lsu_resp_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
wire [63:0] io_lsu_resp_0_bits_out_data; // @[util.scala:101:23]
wire io_lsu_resp_0_bits_out_is_hella; // @[util.scala:101:23]
wire _io_lsu_nack_0_valid_T_7; // @[dcache.scala:863:75]
wire [6:0] io_lsu_nack_0_bits_out_uop_uopc; // @[util.scala:101:23]
wire [31:0] io_lsu_nack_0_bits_out_uop_inst; // @[util.scala:101:23]
wire [31:0] io_lsu_nack_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
wire [39:0] io_lsu_nack_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_iq_type; // @[util.scala:101:23]
wire [9:0] io_lsu_nack_0_bits_out_uop_fu_code; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
wire [2:0] io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_iw_state; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_br; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_jal; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [15:0] io_lsu_nack_0_bits_out_uop_br_mask; // @[util.scala:101:23]
wire [3:0] io_lsu_nack_0_bits_out_uop_br_tag; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_taken; // @[util.scala:101:23]
wire [19:0] io_lsu_nack_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
wire [11:0] io_lsu_nack_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_pdst; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_prs1; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_prs2; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_prs3; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_ppred; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
wire [6:0] io_lsu_nack_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_exception; // @[util.scala:101:23]
wire [63:0] io_lsu_nack_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bypassable; // @[util.scala:101:23]
wire [4:0] io_lsu_nack_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_mem_size; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_fence; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_amo; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_is_unique; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_ldst; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs1; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs2; // @[util.scala:101:23]
wire [5:0] io_lsu_nack_0_bits_out_uop_lrs3; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_fp_val; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_fp_single; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
wire [1:0] io_lsu_nack_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
wire [39:0] io_lsu_nack_0_bits_out_addr; // @[util.scala:101:23]
wire [63:0] io_lsu_nack_0_bits_out_data; // @[util.scala:101:23]
wire io_lsu_nack_0_bits_out_is_hella; // @[util.scala:101:23]
wire _io_lsu_ordered_T_3; // @[dcache.scala:913:66]
wire io_lsu_perf_acquire_done; // @[Edges.scala:233:22]
wire io_lsu_perf_release_done; // @[Edges.scala:233:22]
wire [2:0] auto_out_a_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_a_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_a_bits_size_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_a_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] auto_out_a_bits_address_0; // @[dcache.scala:413:7]
wire [15:0] auto_out_a_bits_mask_0; // @[dcache.scala:413:7]
wire [127:0] auto_out_a_bits_data_0; // @[dcache.scala:413:7]
wire auto_out_a_valid_0; // @[dcache.scala:413:7]
wire auto_out_b_ready_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_c_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_c_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_c_bits_size_0; // @[dcache.scala:413:7]
wire [2:0] auto_out_c_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] auto_out_c_bits_address_0; // @[dcache.scala:413:7]
wire [127:0] auto_out_c_bits_data_0; // @[dcache.scala:413:7]
wire auto_out_c_valid_0; // @[dcache.scala:413:7]
wire auto_out_d_ready_0; // @[dcache.scala:413:7]
wire [3:0] auto_out_e_bits_sink_0; // @[dcache.scala:413:7]
wire auto_out_e_valid_0; // @[dcache.scala:413:7]
wire io_lsu_req_ready_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_uopc_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_resp_0_bits_uop_inst_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_resp_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7]
wire [39:0] io_lsu_resp_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_resp_0_bits_uop_iq_type_0; // @[dcache.scala:413:7]
wire [9:0] io_lsu_resp_0_bits_uop_fu_code_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_iw_state_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_br_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_jal_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7]
wire [15:0] io_lsu_resp_0_bits_uop_br_mask_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_resp_0_bits_uop_br_tag_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_taken_0; // @[dcache.scala:413:7]
wire [19:0] io_lsu_resp_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7]
wire [11:0] io_lsu_resp_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_pdst_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs1_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs2_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_prs3_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_ppred_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_resp_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_exception_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_resp_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bypassable_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_resp_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_mem_size_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_fence_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_amo_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_is_unique_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_ldst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs2_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_resp_0_bits_uop_lrs3_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_fp_val_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_fp_single_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_resp_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_resp_0_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_bits_is_hella_0; // @[dcache.scala:413:7]
wire io_lsu_resp_0_valid_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_ctrl_br_type_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_ctrl_op1_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_op2_sel_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_imm_sel_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_ctrl_op_fcn_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_fcn_dw_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_ctrl_csr_cmd_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_load_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_sta_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ctrl_is_std_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_uopc_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_nack_0_bits_uop_inst_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_nack_0_bits_uop_debug_inst_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_rvc_0; // @[dcache.scala:413:7]
wire [39:0] io_lsu_nack_0_bits_uop_debug_pc_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_nack_0_bits_uop_iq_type_0; // @[dcache.scala:413:7]
wire [9:0] io_lsu_nack_0_bits_uop_fu_code_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_iw_state_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_iw_p1_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_iw_p2_poisoned_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_br_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_jalr_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_jal_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_sfb_0; // @[dcache.scala:413:7]
wire [15:0] io_lsu_nack_0_bits_uop_br_mask_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_nack_0_bits_uop_br_tag_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_ftq_idx_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_edge_inst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_pc_lob_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_taken_0; // @[dcache.scala:413:7]
wire [19:0] io_lsu_nack_0_bits_uop_imm_packed_0; // @[dcache.scala:413:7]
wire [11:0] io_lsu_nack_0_bits_uop_csr_addr_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_rob_idx_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_ldq_idx_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_stq_idx_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_rxq_idx_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_pdst_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs1_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs2_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_prs3_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_ppred_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs1_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs2_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_prs3_busy_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ppred_busy_0; // @[dcache.scala:413:7]
wire [6:0] io_lsu_nack_0_bits_uop_stale_pdst_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_exception_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_nack_0_bits_uop_exc_cause_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bypassable_0; // @[dcache.scala:413:7]
wire [4:0] io_lsu_nack_0_bits_uop_mem_cmd_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_mem_size_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_mem_signed_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_fence_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_fencei_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_amo_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_uses_ldq_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_uses_stq_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_is_unique_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_flush_on_commit_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_ldst_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs1_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs2_0; // @[dcache.scala:413:7]
wire [5:0] io_lsu_nack_0_bits_uop_lrs3_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_ldst_val_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_dst_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_frs3_en_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_fp_val_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_fp_single_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bp_debug_if_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_debug_fsrc_0; // @[dcache.scala:413:7]
wire [1:0] io_lsu_nack_0_bits_uop_debug_tsrc_0; // @[dcache.scala:413:7]
wire [39:0] io_lsu_nack_0_bits_addr_0; // @[dcache.scala:413:7]
wire [63:0] io_lsu_nack_0_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_bits_is_hella_0; // @[dcache.scala:413:7]
wire io_lsu_nack_0_valid_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_release_bits_opcode_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:413:7]
wire [3:0] io_lsu_release_bits_size_0; // @[dcache.scala:413:7]
wire [2:0] io_lsu_release_bits_source_0; // @[dcache.scala:413:7]
wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:413:7]
wire [127:0] io_lsu_release_bits_data_0; // @[dcache.scala:413:7]
wire io_lsu_release_valid_0; // @[dcache.scala:413:7]
wire io_lsu_perf_acquire_0; // @[dcache.scala:413:7]
wire io_lsu_perf_release_0; // @[dcache.scala:413:7]
wire io_lsu_ordered_0; // @[dcache.scala:413:7]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire _nodeOut_b_ready_T_1; // @[dcache.scala:779:48]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire _meta_0_io_write_valid_T = _meta_0_io_write_ready & _metaWriteArb_io_out_valid; // @[Decoupled.scala:51:35]
wire _data_io_read_0_valid_T = _dataReadArb_io_out_bits_valid_0 & _dataReadArb_io_out_valid; // @[dcache.scala:463:27, :468:63]
assign _io_lsu_req_ready_T = _metaReadArb_io_in_4_ready & _dataReadArb_io_in_2_ready; // @[dcache.scala:445:27, :463:27, :480:50]
assign io_lsu_req_ready_0 = _io_lsu_req_ready_T; // @[dcache.scala:413:7, :480:50]
wire [33:0] _metaReadArb_io_in_4_bits_req_0_idx_T = io_lsu_req_bits_0_bits_addr_0[39:6]; // @[dcache.scala:413:7, :485:77]
wire [3:0] replay_req_0_uop_ctrl_br_type; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_ctrl_op1_sel; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_op2_sel; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_imm_sel; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_ctrl_op_fcn; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_load; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_sta; // @[dcache.scala:496:24]
wire replay_req_0_uop_ctrl_is_std; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_uopc; // @[dcache.scala:496:24]
wire [31:0] replay_req_0_uop_inst; // @[dcache.scala:496:24]
wire [31:0] replay_req_0_uop_debug_inst; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_rvc; // @[dcache.scala:496:24]
wire [39:0] replay_req_0_uop_debug_pc; // @[dcache.scala:496:24]
wire [2:0] replay_req_0_uop_iq_type; // @[dcache.scala:496:24]
wire [9:0] replay_req_0_uop_fu_code; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_iw_state; // @[dcache.scala:496:24]
wire replay_req_0_uop_iw_p1_poisoned; // @[dcache.scala:496:24]
wire replay_req_0_uop_iw_p2_poisoned; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_br; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_jalr; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_jal; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_sfb; // @[dcache.scala:496:24]
wire [15:0] replay_req_0_uop_br_mask; // @[dcache.scala:496:24]
wire [3:0] replay_req_0_uop_br_tag; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_ftq_idx; // @[dcache.scala:496:24]
wire replay_req_0_uop_edge_inst; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_pc_lob; // @[dcache.scala:496:24]
wire replay_req_0_uop_taken; // @[dcache.scala:496:24]
wire [19:0] replay_req_0_uop_imm_packed; // @[dcache.scala:496:24]
wire [11:0] replay_req_0_uop_csr_addr; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_rob_idx; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_ldq_idx; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_stq_idx; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_rxq_idx; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_pdst; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_prs1; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_prs2; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_prs3; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_ppred; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs1_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs2_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_prs3_busy; // @[dcache.scala:496:24]
wire replay_req_0_uop_ppred_busy; // @[dcache.scala:496:24]
wire [6:0] replay_req_0_uop_stale_pdst; // @[dcache.scala:496:24]
wire replay_req_0_uop_exception; // @[dcache.scala:496:24]
wire [63:0] replay_req_0_uop_exc_cause; // @[dcache.scala:496:24]
wire replay_req_0_uop_bypassable; // @[dcache.scala:496:24]
wire [4:0] replay_req_0_uop_mem_cmd; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_mem_size; // @[dcache.scala:496:24]
wire replay_req_0_uop_mem_signed; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_fence; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_fencei; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_amo; // @[dcache.scala:496:24]
wire replay_req_0_uop_uses_ldq; // @[dcache.scala:496:24]
wire replay_req_0_uop_uses_stq; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_sys_pc2epc; // @[dcache.scala:496:24]
wire replay_req_0_uop_is_unique; // @[dcache.scala:496:24]
wire replay_req_0_uop_flush_on_commit; // @[dcache.scala:496:24]
wire replay_req_0_uop_ldst_is_rs1; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_ldst; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs1; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs2; // @[dcache.scala:496:24]
wire [5:0] replay_req_0_uop_lrs3; // @[dcache.scala:496:24]
wire replay_req_0_uop_ldst_val; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_dst_rtype; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_lrs1_rtype; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_lrs2_rtype; // @[dcache.scala:496:24]
wire replay_req_0_uop_frs3_en; // @[dcache.scala:496:24]
wire replay_req_0_uop_fp_val; // @[dcache.scala:496:24]
wire replay_req_0_uop_fp_single; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_pf_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_ae_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_xcpt_ma_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_bp_debug_if; // @[dcache.scala:496:24]
wire replay_req_0_uop_bp_xcpt_if; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_debug_fsrc; // @[dcache.scala:496:24]
wire [1:0] replay_req_0_uop_debug_tsrc; // @[dcache.scala:496:24]
wire [39:0] replay_req_0_addr; // @[dcache.scala:496:24]
wire [63:0] replay_req_0_data; // @[dcache.scala:496:24]
wire replay_req_0_is_hella; // @[dcache.scala:496:24]
wire [33:0] _metaReadArb_io_in_0_bits_req_0_idx_T = _mshrs_io_replay_bits_addr[39:6]; // @[dcache.scala:433:21, :506:72]
wire [39:0] mshr_read_req_0_addr; // @[dcache.scala:517:27]
wire [25:0] _mshr_read_req_0_addr_T = {_mshrs_io_meta_read_bits_tag, _mshrs_io_meta_read_bits_idx}; // @[dcache.scala:433:21, :520:35]
wire [31:0] _mshr_read_req_0_addr_T_1 = {_mshr_read_req_0_addr_T, 6'h0}; // @[dcache.scala:520:{35,94}]
assign mshr_read_req_0_addr = {8'h0, _mshr_read_req_0_addr_T_1}; // @[dcache.scala:517:27, :520:{29,94}]
wire _wb_io_meta_read_ready_T; // @[dcache.scala:542:55]
wire _wb_fire_T = _wb_io_meta_read_ready_T & _wb_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire _wb_io_data_req_ready_T; // @[dcache.scala:547:55]
wire _wb_fire_T_1 = _wb_io_data_req_ready_T & _wb_io_data_req_valid; // @[Decoupled.scala:51:35]
wire wb_fire = _wb_fire_T & _wb_fire_T_1; // @[Decoupled.scala:51:35]
wire [39:0] wb_req_0_addr; // @[dcache.scala:532:20]
wire [31:0] _wb_req_0_addr_T = {_wb_io_meta_read_bits_tag, _wb_io_data_req_bits_addr}; // @[dcache.scala:431:18, :535:28]
assign wb_req_0_addr = {8'h0, _wb_req_0_addr_T}; // @[dcache.scala:532:20, :535:{22,28}]
wire _GEN = _metaReadArb_io_in_2_ready & _dataReadArb_io_in_1_ready; // @[dcache.scala:445:27, :463:27, :542:55]
assign _wb_io_meta_read_ready_T = _GEN; // @[dcache.scala:542:55]
assign _wb_io_data_req_ready_T = _GEN; // @[dcache.scala:542:55, :547:55]
wire prober_fire = _metaReadArb_io_in_1_ready & _prober_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire [39:0] prober_req_0_addr; // @[dcache.scala:553:26]
wire [25:0] _prober_req_0_addr_T = {_prober_io_meta_read_bits_tag, _prober_io_meta_read_bits_idx}; // @[dcache.scala:432:22, :556:32]
wire [31:0] _prober_req_0_addr_T_1 = {_prober_req_0_addr_T, 6'h0}; // @[dcache.scala:556:{32,93}]
assign prober_req_0_addr = {8'h0, _prober_req_0_addr_T_1}; // @[dcache.scala:553:26, :556:{26,93}]
wire _T_7 = io_lsu_req_ready_0 & io_lsu_req_valid_0; // @[Decoupled.scala:51:35]
wire _s0_valid_T; // @[Decoupled.scala:51:35]
assign _s0_valid_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_req_T; // @[Decoupled.scala:51:35]
assign _s0_req_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_type_T; // @[Decoupled.scala:51:35]
assign _s0_type_T = _T_7; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T; // @[Decoupled.scala:51:35]
assign _s0_send_resp_or_nack_T = _T_7; // @[Decoupled.scala:51:35]
wire _s1_valid_T_7; // @[Decoupled.scala:51:35]
assign _s1_valid_T_7 = _T_7; // @[Decoupled.scala:51:35]
wire _mshrs_io_replay_ready_T; // @[dcache.scala:502:58]
wire _GEN_0 = _mshrs_io_replay_ready_T & _mshrs_io_replay_valid; // @[Decoupled.scala:51:35]
wire _s0_valid_T_1; // @[Decoupled.scala:51:35]
assign _s0_valid_T_1 = _GEN_0; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_1; // @[Decoupled.scala:51:35]
assign _s0_send_resp_or_nack_T_1 = _GEN_0; // @[Decoupled.scala:51:35]
wire _s0_valid_T_2 = _s0_valid_T_1 | wb_fire; // @[Decoupled.scala:51:35]
wire _s0_valid_T_3 = _s0_valid_T_2 | prober_fire; // @[Decoupled.scala:51:35]
wire _s0_valid_T_4 = _s0_valid_T_3; // @[dcache.scala:580:{54,69}]
wire _GEN_1 = _metaReadArb_io_in_3_ready & _mshrs_io_meta_read_valid; // @[Decoupled.scala:51:35]
wire _s0_valid_T_5; // @[Decoupled.scala:51:35]
assign _s0_valid_T_5 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_req_T_1; // @[Decoupled.scala:51:35]
assign _s0_req_T_1 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_type_T_1; // @[Decoupled.scala:51:35]
assign _s0_type_T_1 = _GEN_1; // @[Decoupled.scala:51:35]
wire _s0_valid_T_6 = _s0_valid_T_4 | _s0_valid_T_5; // @[Decoupled.scala:51:35]
wire _s0_valid_T_7_0 = _s0_valid_T_6; // @[dcache.scala:580:{21,86}]
wire s0_valid_0 = _s0_valid_T ? _s0_valid_WIRE_0 : _s0_valid_T_7_0; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_uopc = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_2_0_uop_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_2_0_uop_debug_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_rvc = ~_s0_req_T_1 & replay_req_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_2_0_uop_debug_pc = _s0_req_T_1 ? 40'h0 : replay_req_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_iq_type = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] _s0_req_T_2_0_uop_fu_code = _s0_req_T_1 ? 10'h0 : replay_req_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_ctrl_br_type = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_ctrl_op1_sel = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_op2_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_imm_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_ctrl_op_fcn = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_fcn_dw = ~_s0_req_T_1 & replay_req_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_2_0_uop_ctrl_csr_cmd = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_load = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_sta = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ctrl_is_std = ~_s0_req_T_1 & replay_req_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_iw_state = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p1_poisoned = ~_s0_req_T_1 & replay_req_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_iw_p2_poisoned = ~_s0_req_T_1 & replay_req_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_br = ~_s0_req_T_1 & replay_req_0_uop_is_br; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_jalr = ~_s0_req_T_1 & replay_req_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_jal = ~_s0_req_T_1 & replay_req_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sfb = ~_s0_req_T_1 & replay_req_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [15:0] _s0_req_T_2_0_uop_br_mask = _s0_req_T_1 ? 16'h0 : replay_req_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_2_0_uop_br_tag = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_ftq_idx = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_edge_inst = ~_s0_req_T_1 & replay_req_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_pc_lob = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_taken = ~_s0_req_T_1 & replay_req_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] _s0_req_T_2_0_uop_imm_packed = _s0_req_T_1 ? 20'h0 : replay_req_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] _s0_req_T_2_0_uop_csr_addr = _s0_req_T_1 ? 12'h0 : replay_req_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_rob_idx = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_ldq_idx = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_stq_idx = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_rxq_idx = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs1 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs2 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_prs3 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_ppred = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ppred; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs1_busy = ~_s0_req_T_1 & replay_req_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs2_busy = ~_s0_req_T_1 & replay_req_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_prs3_busy = ~_s0_req_T_1 & replay_req_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ppred_busy = ~_s0_req_T_1 & replay_req_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_2_0_uop_stale_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_exception = ~_s0_req_T_1 & replay_req_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_2_0_uop_exc_cause = _s0_req_T_1 ? 64'h0 : replay_req_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bypassable = ~_s0_req_T_1 & replay_req_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_2_0_uop_mem_cmd = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_mem_size = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_mem_signed = ~_s0_req_T_1 & replay_req_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_fence = ~_s0_req_T_1 & replay_req_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_fencei = ~_s0_req_T_1 & replay_req_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_amo = ~_s0_req_T_1 & replay_req_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_uses_ldq = ~_s0_req_T_1 & replay_req_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_uses_stq = ~_s0_req_T_1 & replay_req_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_sys_pc2epc = ~_s0_req_T_1 & replay_req_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_is_unique = ~_s0_req_T_1 & replay_req_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_flush_on_commit = ~_s0_req_T_1 & replay_req_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ldst_is_rs1 = ~_s0_req_T_1 & replay_req_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_ldst = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs1 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs2 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_2_0_uop_lrs3 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_ldst_val = ~_s0_req_T_1 & replay_req_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_dst_rtype = _s0_req_T_1 ? 2'h2 : replay_req_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_lrs1_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_lrs2_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_frs3_en = ~_s0_req_T_1 & replay_req_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_val = ~_s0_req_T_1 & replay_req_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_fp_single = ~_s0_req_T_1 & replay_req_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_pf_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_ae_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_xcpt_ma_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bp_debug_if = ~_s0_req_T_1 & replay_req_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_uop_bp_xcpt_if = ~_s0_req_T_1 & replay_req_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_debug_fsrc = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_2_0_uop_debug_tsrc = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_2_0_addr = _s0_req_T_1 ? mshr_read_req_0_addr : replay_req_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_2_0_data = _s0_req_T_1 ? 64'h0 : replay_req_0_data; // @[Decoupled.scala:51:35]
wire _s0_req_T_2_0_is_hella = ~_s0_req_T_1 & replay_req_0_is_hella; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_3_0_uop_uopc = _s0_req_T_2_0_uop_uopc; // @[dcache.scala:585:21, :586:21]
wire [31:0] _s0_req_T_3_0_uop_inst = _s0_req_T_2_0_uop_inst; // @[dcache.scala:585:21, :586:21]
wire [31:0] _s0_req_T_3_0_uop_debug_inst = _s0_req_T_2_0_uop_debug_inst; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_rvc = _s0_req_T_2_0_uop_is_rvc; // @[dcache.scala:585:21, :586:21]
wire [39:0] _s0_req_T_3_0_uop_debug_pc = _s0_req_T_2_0_uop_debug_pc; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_iq_type = _s0_req_T_2_0_uop_iq_type; // @[dcache.scala:585:21, :586:21]
wire [9:0] _s0_req_T_3_0_uop_fu_code = _s0_req_T_2_0_uop_fu_code; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_ctrl_br_type = _s0_req_T_2_0_uop_ctrl_br_type; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_ctrl_op1_sel = _s0_req_T_2_0_uop_ctrl_op1_sel; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_op2_sel = _s0_req_T_2_0_uop_ctrl_op2_sel; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_imm_sel = _s0_req_T_2_0_uop_ctrl_imm_sel; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_ctrl_op_fcn = _s0_req_T_2_0_uop_ctrl_op_fcn; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_fcn_dw = _s0_req_T_2_0_uop_ctrl_fcn_dw; // @[dcache.scala:585:21, :586:21]
wire [2:0] _s0_req_T_3_0_uop_ctrl_csr_cmd = _s0_req_T_2_0_uop_ctrl_csr_cmd; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_load = _s0_req_T_2_0_uop_ctrl_is_load; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_sta = _s0_req_T_2_0_uop_ctrl_is_sta; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ctrl_is_std = _s0_req_T_2_0_uop_ctrl_is_std; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_iw_state = _s0_req_T_2_0_uop_iw_state; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_iw_p1_poisoned = _s0_req_T_2_0_uop_iw_p1_poisoned; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_iw_p2_poisoned = _s0_req_T_2_0_uop_iw_p2_poisoned; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_br = _s0_req_T_2_0_uop_is_br; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_jalr = _s0_req_T_2_0_uop_is_jalr; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_jal = _s0_req_T_2_0_uop_is_jal; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_sfb = _s0_req_T_2_0_uop_is_sfb; // @[dcache.scala:585:21, :586:21]
wire [15:0] _s0_req_T_3_0_uop_br_mask = _s0_req_T_2_0_uop_br_mask; // @[dcache.scala:585:21, :586:21]
wire [3:0] _s0_req_T_3_0_uop_br_tag = _s0_req_T_2_0_uop_br_tag; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_ftq_idx = _s0_req_T_2_0_uop_ftq_idx; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_edge_inst = _s0_req_T_2_0_uop_edge_inst; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_pc_lob = _s0_req_T_2_0_uop_pc_lob; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_taken = _s0_req_T_2_0_uop_taken; // @[dcache.scala:585:21, :586:21]
wire [19:0] _s0_req_T_3_0_uop_imm_packed = _s0_req_T_2_0_uop_imm_packed; // @[dcache.scala:585:21, :586:21]
wire [11:0] _s0_req_T_3_0_uop_csr_addr = _s0_req_T_2_0_uop_csr_addr; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_rob_idx = _s0_req_T_2_0_uop_rob_idx; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_ldq_idx = _s0_req_T_2_0_uop_ldq_idx; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_stq_idx = _s0_req_T_2_0_uop_stq_idx; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_rxq_idx = _s0_req_T_2_0_uop_rxq_idx; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_pdst = _s0_req_T_2_0_uop_pdst; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_prs1 = _s0_req_T_2_0_uop_prs1; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_prs2 = _s0_req_T_2_0_uop_prs2; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_prs3 = _s0_req_T_2_0_uop_prs3; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_ppred = _s0_req_T_2_0_uop_ppred; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs1_busy = _s0_req_T_2_0_uop_prs1_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs2_busy = _s0_req_T_2_0_uop_prs2_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_prs3_busy = _s0_req_T_2_0_uop_prs3_busy; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ppred_busy = _s0_req_T_2_0_uop_ppred_busy; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_3_0_uop_stale_pdst = _s0_req_T_2_0_uop_stale_pdst; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_exception = _s0_req_T_2_0_uop_exception; // @[dcache.scala:585:21, :586:21]
wire [63:0] _s0_req_T_3_0_uop_exc_cause = _s0_req_T_2_0_uop_exc_cause; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bypassable = _s0_req_T_2_0_uop_bypassable; // @[dcache.scala:585:21, :586:21]
wire [4:0] _s0_req_T_3_0_uop_mem_cmd = _s0_req_T_2_0_uop_mem_cmd; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_mem_size = _s0_req_T_2_0_uop_mem_size; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_mem_signed = _s0_req_T_2_0_uop_mem_signed; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_fence = _s0_req_T_2_0_uop_is_fence; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_fencei = _s0_req_T_2_0_uop_is_fencei; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_amo = _s0_req_T_2_0_uop_is_amo; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_uses_ldq = _s0_req_T_2_0_uop_uses_ldq; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_uses_stq = _s0_req_T_2_0_uop_uses_stq; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_sys_pc2epc = _s0_req_T_2_0_uop_is_sys_pc2epc; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_is_unique = _s0_req_T_2_0_uop_is_unique; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_flush_on_commit = _s0_req_T_2_0_uop_flush_on_commit; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ldst_is_rs1 = _s0_req_T_2_0_uop_ldst_is_rs1; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_ldst = _s0_req_T_2_0_uop_ldst; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs1 = _s0_req_T_2_0_uop_lrs1; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs2 = _s0_req_T_2_0_uop_lrs2; // @[dcache.scala:585:21, :586:21]
wire [5:0] _s0_req_T_3_0_uop_lrs3 = _s0_req_T_2_0_uop_lrs3; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_ldst_val = _s0_req_T_2_0_uop_ldst_val; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_dst_rtype = _s0_req_T_2_0_uop_dst_rtype; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_lrs1_rtype = _s0_req_T_2_0_uop_lrs1_rtype; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_lrs2_rtype = _s0_req_T_2_0_uop_lrs2_rtype; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_frs3_en = _s0_req_T_2_0_uop_frs3_en; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_fp_val = _s0_req_T_2_0_uop_fp_val; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_fp_single = _s0_req_T_2_0_uop_fp_single; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_pf_if = _s0_req_T_2_0_uop_xcpt_pf_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_ae_if = _s0_req_T_2_0_uop_xcpt_ae_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_xcpt_ma_if = _s0_req_T_2_0_uop_xcpt_ma_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bp_debug_if = _s0_req_T_2_0_uop_bp_debug_if; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_uop_bp_xcpt_if = _s0_req_T_2_0_uop_bp_xcpt_if; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_debug_fsrc = _s0_req_T_2_0_uop_debug_fsrc; // @[dcache.scala:585:21, :586:21]
wire [1:0] _s0_req_T_3_0_uop_debug_tsrc = _s0_req_T_2_0_uop_debug_tsrc; // @[dcache.scala:585:21, :586:21]
wire [39:0] _s0_req_T_3_0_addr = _s0_req_T_2_0_addr; // @[dcache.scala:585:21, :586:21]
wire [63:0] _s0_req_T_3_0_data = _s0_req_T_2_0_data; // @[dcache.scala:585:21, :586:21]
wire _s0_req_T_3_0_is_hella = _s0_req_T_2_0_is_hella; // @[dcache.scala:585:21, :586:21]
wire [6:0] _s0_req_T_4_0_uop_uopc = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_4_0_uop_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] _s0_req_T_4_0_uop_debug_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_rvc = ~prober_fire & _s0_req_T_3_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_4_0_uop_debug_pc = prober_fire ? 40'h0 : _s0_req_T_3_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_iq_type = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] _s0_req_T_4_0_uop_fu_code = prober_fire ? 10'h0 : _s0_req_T_3_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_ctrl_br_type = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_ctrl_op1_sel = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_op2_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_imm_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_ctrl_op_fcn = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_fcn_dw = ~prober_fire & _s0_req_T_3_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] _s0_req_T_4_0_uop_ctrl_csr_cmd = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_load = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_sta = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ctrl_is_std = ~prober_fire & _s0_req_T_3_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_iw_state = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p1_poisoned = ~prober_fire & _s0_req_T_3_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_iw_p2_poisoned = ~prober_fire & _s0_req_T_3_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_br = ~prober_fire & _s0_req_T_3_0_uop_is_br; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_jalr = ~prober_fire & _s0_req_T_3_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_jal = ~prober_fire & _s0_req_T_3_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sfb = ~prober_fire & _s0_req_T_3_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [15:0] _s0_req_T_4_0_uop_br_mask = prober_fire ? 16'h0 : _s0_req_T_3_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [3:0] _s0_req_T_4_0_uop_br_tag = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_ftq_idx = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_edge_inst = ~prober_fire & _s0_req_T_3_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_pc_lob = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_taken = ~prober_fire & _s0_req_T_3_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] _s0_req_T_4_0_uop_imm_packed = prober_fire ? 20'h0 : _s0_req_T_3_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] _s0_req_T_4_0_uop_csr_addr = prober_fire ? 12'h0 : _s0_req_T_3_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_rob_idx = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_ldq_idx = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_stq_idx = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_rxq_idx = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs1 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs2 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_prs3 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_ppred = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ppred; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs1_busy = ~prober_fire & _s0_req_T_3_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs2_busy = ~prober_fire & _s0_req_T_3_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_prs3_busy = ~prober_fire & _s0_req_T_3_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ppred_busy = ~prober_fire & _s0_req_T_3_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_4_0_uop_stale_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_exception = ~prober_fire & _s0_req_T_3_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_4_0_uop_exc_cause = prober_fire ? 64'h0 : _s0_req_T_3_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bypassable = ~prober_fire & _s0_req_T_3_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] _s0_req_T_4_0_uop_mem_cmd = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_mem_size = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_mem_signed = ~prober_fire & _s0_req_T_3_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_fence = ~prober_fire & _s0_req_T_3_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_fencei = ~prober_fire & _s0_req_T_3_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_amo = ~prober_fire & _s0_req_T_3_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_uses_ldq = ~prober_fire & _s0_req_T_3_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_uses_stq = ~prober_fire & _s0_req_T_3_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_sys_pc2epc = ~prober_fire & _s0_req_T_3_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_is_unique = ~prober_fire & _s0_req_T_3_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_flush_on_commit = ~prober_fire & _s0_req_T_3_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ldst_is_rs1 = ~prober_fire & _s0_req_T_3_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_ldst = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs1 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs2 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] _s0_req_T_4_0_uop_lrs3 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_ldst_val = ~prober_fire & _s0_req_T_3_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_dst_rtype = prober_fire ? 2'h2 : _s0_req_T_3_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_lrs1_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_lrs2_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_frs3_en = ~prober_fire & _s0_req_T_3_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_val = ~prober_fire & _s0_req_T_3_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_fp_single = ~prober_fire & _s0_req_T_3_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_pf_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_ae_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_xcpt_ma_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bp_debug_if = ~prober_fire & _s0_req_T_3_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_uop_bp_xcpt_if = ~prober_fire & _s0_req_T_3_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_debug_fsrc = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] _s0_req_T_4_0_uop_debug_tsrc = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] _s0_req_T_4_0_addr = prober_fire ? prober_req_0_addr : _s0_req_T_3_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] _s0_req_T_4_0_data = prober_fire ? 64'h0 : _s0_req_T_3_0_data; // @[Decoupled.scala:51:35]
wire _s0_req_T_4_0_is_hella = ~prober_fire & _s0_req_T_3_0_is_hella; // @[Decoupled.scala:51:35]
wire [6:0] _s0_req_T_5_0_uop_uopc = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_uopc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [31:0] _s0_req_T_5_0_uop_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [31:0] _s0_req_T_5_0_uop_debug_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_debug_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_rvc = ~wb_fire & _s0_req_T_4_0_uop_is_rvc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [39:0] _s0_req_T_5_0_uop_debug_pc = wb_fire ? 40'h0 : _s0_req_T_4_0_uop_debug_pc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_iq_type = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_iq_type; // @[dcache.scala:531:38, :583:21, :584:21]
wire [9:0] _s0_req_T_5_0_uop_fu_code = wb_fire ? 10'h0 : _s0_req_T_4_0_uop_fu_code; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_ctrl_br_type = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_ctrl_br_type; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_ctrl_op1_sel = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_ctrl_op1_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_op2_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_op2_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_imm_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_imm_sel; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_ctrl_op_fcn = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ctrl_op_fcn; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_fcn_dw = ~wb_fire & _s0_req_T_4_0_uop_ctrl_fcn_dw; // @[dcache.scala:531:38, :583:21, :584:21]
wire [2:0] _s0_req_T_5_0_uop_ctrl_csr_cmd = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_ctrl_csr_cmd; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_load = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_load; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_sta = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_sta; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ctrl_is_std = ~wb_fire & _s0_req_T_4_0_uop_ctrl_is_std; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_iw_state = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_iw_state; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_iw_p1_poisoned = ~wb_fire & _s0_req_T_4_0_uop_iw_p1_poisoned; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_iw_p2_poisoned = ~wb_fire & _s0_req_T_4_0_uop_iw_p2_poisoned; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_br = ~wb_fire & _s0_req_T_4_0_uop_is_br; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_jalr = ~wb_fire & _s0_req_T_4_0_uop_is_jalr; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_jal = ~wb_fire & _s0_req_T_4_0_uop_is_jal; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_sfb = ~wb_fire & _s0_req_T_4_0_uop_is_sfb; // @[dcache.scala:531:38, :583:21, :584:21]
wire [15:0] _s0_req_T_5_0_uop_br_mask = wb_fire ? 16'h0 : _s0_req_T_4_0_uop_br_mask; // @[dcache.scala:531:38, :583:21, :584:21]
wire [3:0] _s0_req_T_5_0_uop_br_tag = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_br_tag; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_ftq_idx = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ftq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_edge_inst = ~wb_fire & _s0_req_T_4_0_uop_edge_inst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_pc_lob = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_pc_lob; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_taken = ~wb_fire & _s0_req_T_4_0_uop_taken; // @[dcache.scala:531:38, :583:21, :584:21]
wire [19:0] _s0_req_T_5_0_uop_imm_packed = wb_fire ? 20'h0 : _s0_req_T_4_0_uop_imm_packed; // @[dcache.scala:531:38, :583:21, :584:21]
wire [11:0] _s0_req_T_5_0_uop_csr_addr = wb_fire ? 12'h0 : _s0_req_T_4_0_uop_csr_addr; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_rob_idx = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_rob_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_ldq_idx = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ldq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_stq_idx = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_stq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_rxq_idx = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_rxq_idx; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_pdst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_prs1 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_prs2 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs2; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_prs3 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs3; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_ppred = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ppred; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs1_busy = ~wb_fire & _s0_req_T_4_0_uop_prs1_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs2_busy = ~wb_fire & _s0_req_T_4_0_uop_prs2_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_prs3_busy = ~wb_fire & _s0_req_T_4_0_uop_prs3_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ppred_busy = ~wb_fire & _s0_req_T_4_0_uop_ppred_busy; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] _s0_req_T_5_0_uop_stale_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_stale_pdst; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_exception = ~wb_fire & _s0_req_T_4_0_uop_exception; // @[dcache.scala:531:38, :583:21, :584:21]
wire [63:0] _s0_req_T_5_0_uop_exc_cause = wb_fire ? 64'h0 : _s0_req_T_4_0_uop_exc_cause; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bypassable = ~wb_fire & _s0_req_T_4_0_uop_bypassable; // @[dcache.scala:531:38, :583:21, :584:21]
wire [4:0] _s0_req_T_5_0_uop_mem_cmd = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_mem_cmd; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_mem_size = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_mem_size; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_mem_signed = ~wb_fire & _s0_req_T_4_0_uop_mem_signed; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_fence = ~wb_fire & _s0_req_T_4_0_uop_is_fence; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_fencei = ~wb_fire & _s0_req_T_4_0_uop_is_fencei; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_amo = ~wb_fire & _s0_req_T_4_0_uop_is_amo; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_uses_ldq = ~wb_fire & _s0_req_T_4_0_uop_uses_ldq; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_uses_stq = ~wb_fire & _s0_req_T_4_0_uop_uses_stq; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_sys_pc2epc = ~wb_fire & _s0_req_T_4_0_uop_is_sys_pc2epc; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_is_unique = ~wb_fire & _s0_req_T_4_0_uop_is_unique; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_flush_on_commit = ~wb_fire & _s0_req_T_4_0_uop_flush_on_commit; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ldst_is_rs1 = ~wb_fire & _s0_req_T_4_0_uop_ldst_is_rs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_ldst = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_ldst; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs1 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs1; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs2 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs2; // @[dcache.scala:531:38, :583:21, :584:21]
wire [5:0] _s0_req_T_5_0_uop_lrs3 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs3; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_ldst_val = ~wb_fire & _s0_req_T_4_0_uop_ldst_val; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_dst_rtype = wb_fire ? 2'h2 : _s0_req_T_4_0_uop_dst_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_lrs1_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs1_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_lrs2_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs2_rtype; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_frs3_en = ~wb_fire & _s0_req_T_4_0_uop_frs3_en; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_fp_val = ~wb_fire & _s0_req_T_4_0_uop_fp_val; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_fp_single = ~wb_fire & _s0_req_T_4_0_uop_fp_single; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_pf_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_pf_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_ae_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ae_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_xcpt_ma_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ma_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bp_debug_if = ~wb_fire & _s0_req_T_4_0_uop_bp_debug_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_uop_bp_xcpt_if = ~wb_fire & _s0_req_T_4_0_uop_bp_xcpt_if; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_debug_fsrc = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_debug_fsrc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [1:0] _s0_req_T_5_0_uop_debug_tsrc = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_debug_tsrc; // @[dcache.scala:531:38, :583:21, :584:21]
wire [39:0] _s0_req_T_5_0_addr = wb_fire ? wb_req_0_addr : _s0_req_T_4_0_addr; // @[dcache.scala:531:38, :532:20, :583:21, :584:21]
wire [63:0] _s0_req_T_5_0_data = wb_fire ? 64'h0 : _s0_req_T_4_0_data; // @[dcache.scala:531:38, :583:21, :584:21]
wire _s0_req_T_5_0_is_hella = ~wb_fire & _s0_req_T_4_0_is_hella; // @[dcache.scala:531:38, :583:21, :584:21]
wire [6:0] s0_req_0_uop_uopc = _s0_req_T ? _s0_req_WIRE_0_uop_uopc : _s0_req_T_5_0_uop_uopc; // @[Decoupled.scala:51:35]
wire [31:0] s0_req_0_uop_inst = _s0_req_T ? _s0_req_WIRE_0_uop_inst : _s0_req_T_5_0_uop_inst; // @[Decoupled.scala:51:35]
wire [31:0] s0_req_0_uop_debug_inst = _s0_req_T ? _s0_req_WIRE_0_uop_debug_inst : _s0_req_T_5_0_uop_debug_inst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_rvc = _s0_req_T ? _s0_req_WIRE_0_uop_is_rvc : _s0_req_T_5_0_uop_is_rvc; // @[Decoupled.scala:51:35]
wire [39:0] s0_req_0_uop_debug_pc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_pc : _s0_req_T_5_0_uop_debug_pc; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_iq_type = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type : _s0_req_T_5_0_uop_iq_type; // @[Decoupled.scala:51:35]
wire [9:0] s0_req_0_uop_fu_code = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code : _s0_req_T_5_0_uop_fu_code; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_ctrl_br_type = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_br_type : _s0_req_T_5_0_uop_ctrl_br_type; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_ctrl_op1_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op1_sel : _s0_req_T_5_0_uop_ctrl_op1_sel; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_op2_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op2_sel : _s0_req_T_5_0_uop_ctrl_op2_sel; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_imm_sel = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_imm_sel : _s0_req_T_5_0_uop_ctrl_imm_sel; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_ctrl_op_fcn = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_op_fcn : _s0_req_T_5_0_uop_ctrl_op_fcn; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_fcn_dw = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_fcn_dw : _s0_req_T_5_0_uop_ctrl_fcn_dw; // @[Decoupled.scala:51:35]
wire [2:0] s0_req_0_uop_ctrl_csr_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_csr_cmd : _s0_req_T_5_0_uop_ctrl_csr_cmd; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_load = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_load : _s0_req_T_5_0_uop_ctrl_is_load; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_sta = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_sta : _s0_req_T_5_0_uop_ctrl_is_sta; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ctrl_is_std = _s0_req_T ? _s0_req_WIRE_0_uop_ctrl_is_std : _s0_req_T_5_0_uop_ctrl_is_std; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_iw_state = _s0_req_T ? _s0_req_WIRE_0_uop_iw_state : _s0_req_T_5_0_uop_iw_state; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p1_poisoned = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p1_poisoned : _s0_req_T_5_0_uop_iw_p1_poisoned; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_iw_p2_poisoned = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p2_poisoned : _s0_req_T_5_0_uop_iw_p2_poisoned; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_br = _s0_req_T ? _s0_req_WIRE_0_uop_is_br : _s0_req_T_5_0_uop_is_br; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_jalr = _s0_req_T ? _s0_req_WIRE_0_uop_is_jalr : _s0_req_T_5_0_uop_is_jalr; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_jal = _s0_req_T ? _s0_req_WIRE_0_uop_is_jal : _s0_req_T_5_0_uop_is_jal; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sfb = _s0_req_T ? _s0_req_WIRE_0_uop_is_sfb : _s0_req_T_5_0_uop_is_sfb; // @[Decoupled.scala:51:35]
wire [15:0] s0_req_0_uop_br_mask = _s0_req_T ? _s0_req_WIRE_0_uop_br_mask : _s0_req_T_5_0_uop_br_mask; // @[Decoupled.scala:51:35]
wire [3:0] s0_req_0_uop_br_tag = _s0_req_T ? _s0_req_WIRE_0_uop_br_tag : _s0_req_T_5_0_uop_br_tag; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_ftq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ftq_idx : _s0_req_T_5_0_uop_ftq_idx; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_edge_inst = _s0_req_T ? _s0_req_WIRE_0_uop_edge_inst : _s0_req_T_5_0_uop_edge_inst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_pc_lob = _s0_req_T ? _s0_req_WIRE_0_uop_pc_lob : _s0_req_T_5_0_uop_pc_lob; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_taken = _s0_req_T ? _s0_req_WIRE_0_uop_taken : _s0_req_T_5_0_uop_taken; // @[Decoupled.scala:51:35]
wire [19:0] s0_req_0_uop_imm_packed = _s0_req_T ? _s0_req_WIRE_0_uop_imm_packed : _s0_req_T_5_0_uop_imm_packed; // @[Decoupled.scala:51:35]
wire [11:0] s0_req_0_uop_csr_addr = _s0_req_T ? _s0_req_WIRE_0_uop_csr_addr : _s0_req_T_5_0_uop_csr_addr; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_rob_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rob_idx : _s0_req_T_5_0_uop_rob_idx; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_ldq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ldq_idx : _s0_req_T_5_0_uop_ldq_idx; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_stq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_stq_idx : _s0_req_T_5_0_uop_stq_idx; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_rxq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rxq_idx : _s0_req_T_5_0_uop_rxq_idx; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_pdst : _s0_req_T_5_0_uop_pdst; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs1 = _s0_req_T ? _s0_req_WIRE_0_uop_prs1 : _s0_req_T_5_0_uop_prs1; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs2 = _s0_req_T ? _s0_req_WIRE_0_uop_prs2 : _s0_req_T_5_0_uop_prs2; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_prs3 = _s0_req_T ? _s0_req_WIRE_0_uop_prs3 : _s0_req_T_5_0_uop_prs3; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_ppred = _s0_req_T ? _s0_req_WIRE_0_uop_ppred : _s0_req_T_5_0_uop_ppred; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs1_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs1_busy : _s0_req_T_5_0_uop_prs1_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs2_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs2_busy : _s0_req_T_5_0_uop_prs2_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_prs3_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs3_busy : _s0_req_T_5_0_uop_prs3_busy; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ppred_busy = _s0_req_T ? _s0_req_WIRE_0_uop_ppred_busy : _s0_req_T_5_0_uop_ppred_busy; // @[Decoupled.scala:51:35]
wire [6:0] s0_req_0_uop_stale_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_stale_pdst : _s0_req_T_5_0_uop_stale_pdst; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_exception = _s0_req_T ? _s0_req_WIRE_0_uop_exception : _s0_req_T_5_0_uop_exception; // @[Decoupled.scala:51:35]
wire [63:0] s0_req_0_uop_exc_cause = _s0_req_T ? _s0_req_WIRE_0_uop_exc_cause : _s0_req_T_5_0_uop_exc_cause; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bypassable = _s0_req_T ? _s0_req_WIRE_0_uop_bypassable : _s0_req_T_5_0_uop_bypassable; // @[Decoupled.scala:51:35]
wire [4:0] s0_req_0_uop_mem_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_mem_cmd : _s0_req_T_5_0_uop_mem_cmd; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_mem_size = _s0_req_T ? _s0_req_WIRE_0_uop_mem_size : _s0_req_T_5_0_uop_mem_size; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_mem_signed = _s0_req_T ? _s0_req_WIRE_0_uop_mem_signed : _s0_req_T_5_0_uop_mem_signed; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_fence = _s0_req_T ? _s0_req_WIRE_0_uop_is_fence : _s0_req_T_5_0_uop_is_fence; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_fencei = _s0_req_T ? _s0_req_WIRE_0_uop_is_fencei : _s0_req_T_5_0_uop_is_fencei; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_amo = _s0_req_T ? _s0_req_WIRE_0_uop_is_amo : _s0_req_T_5_0_uop_is_amo; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_uses_ldq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_ldq : _s0_req_T_5_0_uop_uses_ldq; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_uses_stq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_stq : _s0_req_T_5_0_uop_uses_stq; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_sys_pc2epc = _s0_req_T ? _s0_req_WIRE_0_uop_is_sys_pc2epc : _s0_req_T_5_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_is_unique = _s0_req_T ? _s0_req_WIRE_0_uop_is_unique : _s0_req_T_5_0_uop_is_unique; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_flush_on_commit = _s0_req_T ? _s0_req_WIRE_0_uop_flush_on_commit : _s0_req_T_5_0_uop_flush_on_commit; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ldst_is_rs1 = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_is_rs1 : _s0_req_T_5_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_ldst = _s0_req_T ? _s0_req_WIRE_0_uop_ldst : _s0_req_T_5_0_uop_ldst; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs1 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1 : _s0_req_T_5_0_uop_lrs1; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs2 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2 : _s0_req_T_5_0_uop_lrs2; // @[Decoupled.scala:51:35]
wire [5:0] s0_req_0_uop_lrs3 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs3 : _s0_req_T_5_0_uop_lrs3; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_ldst_val = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_val : _s0_req_T_5_0_uop_ldst_val; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_dst_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_dst_rtype : _s0_req_T_5_0_uop_dst_rtype; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_lrs1_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1_rtype : _s0_req_T_5_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_lrs2_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2_rtype : _s0_req_T_5_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_frs3_en = _s0_req_T ? _s0_req_WIRE_0_uop_frs3_en : _s0_req_T_5_0_uop_frs3_en; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_val = _s0_req_T ? _s0_req_WIRE_0_uop_fp_val : _s0_req_T_5_0_uop_fp_val; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_fp_single = _s0_req_T ? _s0_req_WIRE_0_uop_fp_single : _s0_req_T_5_0_uop_fp_single; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_pf_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_pf_if : _s0_req_T_5_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_ae_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ae_if : _s0_req_T_5_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_xcpt_ma_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ma_if : _s0_req_T_5_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bp_debug_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_debug_if : _s0_req_T_5_0_uop_bp_debug_if; // @[Decoupled.scala:51:35]
wire s0_req_0_uop_bp_xcpt_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_xcpt_if : _s0_req_T_5_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_debug_fsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_fsrc : _s0_req_T_5_0_uop_debug_fsrc; // @[Decoupled.scala:51:35]
wire [1:0] s0_req_0_uop_debug_tsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_tsrc : _s0_req_T_5_0_uop_debug_tsrc; // @[Decoupled.scala:51:35]
wire [39:0] s0_req_0_addr = _s0_req_T ? _s0_req_WIRE_0_addr : _s0_req_T_5_0_addr; // @[Decoupled.scala:51:35]
wire [63:0] s0_req_0_data = _s0_req_T ? _s0_req_WIRE_0_data : _s0_req_T_5_0_data; // @[Decoupled.scala:51:35]
wire s0_req_0_is_hella = _s0_req_T ? _s0_req_WIRE_0_is_hella : _s0_req_T_5_0_is_hella; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_2 = _s0_type_T_1 ? 3'h3 : 3'h0; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_3 = _s0_type_T_2; // @[dcache.scala:591:21, :592:21]
wire [2:0] _s0_type_T_4 = prober_fire ? 3'h1 : _s0_type_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _s0_type_T_5 = wb_fire ? 3'h2 : _s0_type_T_4; // @[dcache.scala:531:38, :589:21, :590:21]
wire [2:0] s0_type = _s0_type_T ? 3'h4 : _s0_type_T_5; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_2 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_3 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_4 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_5 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_6 = _s0_send_resp_or_nack_T_2 | _s0_send_resp_or_nack_T_3; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_7 = _s0_send_resp_or_nack_T_6 | _s0_send_resp_or_nack_T_4; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_8 = _s0_send_resp_or_nack_T_7 | _s0_send_resp_or_nack_T_5; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_9 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_10 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_11 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_12 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_13 = _s0_send_resp_or_nack_T_9 | _s0_send_resp_or_nack_T_10; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_14 = _s0_send_resp_or_nack_T_13 | _s0_send_resp_or_nack_T_11; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_15 = _s0_send_resp_or_nack_T_14 | _s0_send_resp_or_nack_T_12; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_16 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_17 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_18 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_19 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_20 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _s0_send_resp_or_nack_T_21 = _s0_send_resp_or_nack_T_16 | _s0_send_resp_or_nack_T_17; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_22 = _s0_send_resp_or_nack_T_21 | _s0_send_resp_or_nack_T_18; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_23 = _s0_send_resp_or_nack_T_22 | _s0_send_resp_or_nack_T_19; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_24 = _s0_send_resp_or_nack_T_23 | _s0_send_resp_or_nack_T_20; // @[package.scala:16:47, :81:59]
wire _s0_send_resp_or_nack_T_25 = _s0_send_resp_or_nack_T_15 | _s0_send_resp_or_nack_T_24; // @[package.scala:81:59]
wire _s0_send_resp_or_nack_T_26 = _s0_send_resp_or_nack_T_8 | _s0_send_resp_or_nack_T_25; // @[package.scala:81:59]
wire _s0_send_resp_or_nack_T_27 = _s0_send_resp_or_nack_T_1 & _s0_send_resp_or_nack_T_26; // @[Decoupled.scala:51:35]
wire _s0_send_resp_or_nack_T_28 = _s0_send_resp_or_nack_T_27; // @[dcache.scala:597:{16,38}]
wire _s0_send_resp_or_nack_T_29 = _s0_send_resp_or_nack_T_28; // @[dcache.scala:597:{16,117}]
wire _s0_send_resp_or_nack_WIRE_0 = _s0_send_resp_or_nack_T_29; // @[dcache.scala:597:{12,117}]
wire s0_send_resp_or_nack_0 = _s0_send_resp_or_nack_T ? s0_valid_0 : _s0_send_resp_or_nack_WIRE_0; // @[Decoupled.scala:51:35]
reg [6:0] s1_req_0_uop_uopc; // @[dcache.scala:600:32]
reg [31:0] s1_req_0_uop_inst; // @[dcache.scala:600:32]
reg [31:0] s1_req_0_uop_debug_inst; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_rvc; // @[dcache.scala:600:32]
reg [39:0] s1_req_0_uop_debug_pc; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_iq_type; // @[dcache.scala:600:32]
reg [9:0] s1_req_0_uop_fu_code; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_ctrl_br_type; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_ctrl_op1_sel; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_op2_sel; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_imm_sel; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_ctrl_op_fcn; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:600:32]
reg [2:0] s1_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_load; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_sta; // @[dcache.scala:600:32]
reg s1_req_0_uop_ctrl_is_std; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_iw_state; // @[dcache.scala:600:32]
reg s1_req_0_uop_iw_p1_poisoned; // @[dcache.scala:600:32]
reg s1_req_0_uop_iw_p2_poisoned; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_br; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_jalr; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_jal; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_sfb; // @[dcache.scala:600:32]
reg [15:0] s1_req_0_uop_br_mask; // @[dcache.scala:600:32]
reg [3:0] s1_req_0_uop_br_tag; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_ftq_idx; // @[dcache.scala:600:32]
reg s1_req_0_uop_edge_inst; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_pc_lob; // @[dcache.scala:600:32]
reg s1_req_0_uop_taken; // @[dcache.scala:600:32]
reg [19:0] s1_req_0_uop_imm_packed; // @[dcache.scala:600:32]
reg [11:0] s1_req_0_uop_csr_addr; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_rob_idx; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_ldq_idx; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_stq_idx; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_rxq_idx; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_pdst; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_prs1; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_prs2; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_prs3; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_ppred; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs1_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs2_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_prs3_busy; // @[dcache.scala:600:32]
reg s1_req_0_uop_ppred_busy; // @[dcache.scala:600:32]
reg [6:0] s1_req_0_uop_stale_pdst; // @[dcache.scala:600:32]
reg s1_req_0_uop_exception; // @[dcache.scala:600:32]
reg [63:0] s1_req_0_uop_exc_cause; // @[dcache.scala:600:32]
reg s1_req_0_uop_bypassable; // @[dcache.scala:600:32]
reg [4:0] s1_req_0_uop_mem_cmd; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_mem_size; // @[dcache.scala:600:32]
reg s1_req_0_uop_mem_signed; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_fence; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_fencei; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_amo; // @[dcache.scala:600:32]
reg s1_req_0_uop_uses_ldq; // @[dcache.scala:600:32]
reg s1_req_0_uop_uses_stq; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_sys_pc2epc; // @[dcache.scala:600:32]
reg s1_req_0_uop_is_unique; // @[dcache.scala:600:32]
reg s1_req_0_uop_flush_on_commit; // @[dcache.scala:600:32]
reg s1_req_0_uop_ldst_is_rs1; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_ldst; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs1; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs2; // @[dcache.scala:600:32]
reg [5:0] s1_req_0_uop_lrs3; // @[dcache.scala:600:32]
reg s1_req_0_uop_ldst_val; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_dst_rtype; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_lrs1_rtype; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_lrs2_rtype; // @[dcache.scala:600:32]
reg s1_req_0_uop_frs3_en; // @[dcache.scala:600:32]
reg s1_req_0_uop_fp_val; // @[dcache.scala:600:32]
reg s1_req_0_uop_fp_single; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_pf_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_ae_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_xcpt_ma_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_bp_debug_if; // @[dcache.scala:600:32]
reg s1_req_0_uop_bp_xcpt_if; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_debug_fsrc; // @[dcache.scala:600:32]
reg [1:0] s1_req_0_uop_debug_tsrc; // @[dcache.scala:600:32]
reg [39:0] s1_req_0_addr; // @[dcache.scala:600:32]
reg [63:0] s1_req_0_data; // @[dcache.scala:600:32]
reg s1_req_0_is_hella; // @[dcache.scala:600:32]
wire [15:0] _s1_req_0_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _s1_req_0_uop_br_mask_T_1 = s0_req_0_uop_br_mask & _s1_req_0_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire _s2_store_failed_T_2; // @[dcache.scala:742:67]
wire s2_store_failed; // @[dcache.scala:603:29]
wire [15:0] _s1_valid_T = io_lsu_brupdate_b1_mispredict_mask_0 & s0_req_0_uop_br_mask; // @[util.scala:118:51]
wire _s1_valid_T_1 = |_s1_valid_T; // @[util.scala:118:{51,59}]
wire _s1_valid_T_2 = ~_s1_valid_T_1; // @[util.scala:118:59]
wire _s1_valid_T_3 = s0_valid_0 & _s1_valid_T_2; // @[dcache.scala:579:21, :605:74, :606:26]
wire _s1_valid_T_4 = io_lsu_exception_0 & s0_req_0_uop_uses_ldq; // @[dcache.scala:413:7, :582:21, :607:45]
wire _s1_valid_T_5 = ~_s1_valid_T_4; // @[dcache.scala:607:{26,45}]
wire _s1_valid_T_6 = _s1_valid_T_3 & _s1_valid_T_5; // @[dcache.scala:605:74, :606:76, :607:26]
wire _s1_valid_T_8 = s2_store_failed & _s1_valid_T_7; // @[Decoupled.scala:51:35]
wire _s1_valid_T_9 = _s1_valid_T_8 & s0_req_0_uop_uses_stq; // @[dcache.scala:582:21, :608:{44,63}]
wire _s1_valid_T_10 = ~_s1_valid_T_9; // @[dcache.scala:608:{26,63}]
wire _s1_valid_T_11 = _s1_valid_T_6 & _s1_valid_T_10; // @[dcache.scala:606:76, :607:74, :608:26]
reg s1_valid_REG; // @[dcache.scala:605:25]
wire s1_valid_0 = s1_valid_REG; // @[dcache.scala:427:49, :605:25]
reg REG; // @[dcache.scala:611:43]
reg REG_1; // @[dcache.scala:611:72]
wire [5:0] _s1_nack_T = s1_req_0_addr[11:6]; // @[dcache.scala:600:32, :613:43]
wire [5:0] _s1_wb_idx_matches_T = s1_req_0_addr[11:6]; // @[dcache.scala:600:32, :613:43, :630:52]
wire _s1_nack_T_1 = _s1_nack_T == _prober_io_meta_write_bits_idx; // @[dcache.scala:432:22, :613:{43,59}]
wire _s1_nack_T_2 = ~_prober_io_req_ready; // @[dcache.scala:432:22, :613:96]
wire s1_nack_0 = _s1_nack_T_1 & _s1_nack_T_2; // @[dcache.scala:613:{59,93,96}]
wire _s2_nack_hit_WIRE_0 = s1_nack_0; // @[dcache.scala:613:93, :722:39]
reg s1_send_resp_or_nack_0; // @[dcache.scala:614:37]
reg [2:0] s1_type; // @[dcache.scala:615:32]
reg [7:0] s1_mshr_meta_read_way_en; // @[dcache.scala:617:41]
reg [7:0] s1_replay_way_en; // @[dcache.scala:618:41]
reg [7:0] s1_wb_way_en; // @[dcache.scala:619:41]
wire [27:0] _s1_tag_eq_way_T = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_2 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_4 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_6 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_8 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_10 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_12 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire [27:0] _s1_tag_eq_way_T_14 = s1_req_0_addr[39:12]; // @[dcache.scala:600:32, :623:95]
wire _s1_tag_eq_way_T_1 = {8'h0, _meta_0_io_resp_0_tag} == _s1_tag_eq_way_T; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_0 = _s1_tag_eq_way_T_1; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_3 = {8'h0, _meta_0_io_resp_1_tag} == _s1_tag_eq_way_T_2; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_1 = _s1_tag_eq_way_T_3; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_5 = {8'h0, _meta_0_io_resp_2_tag} == _s1_tag_eq_way_T_4; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_2 = _s1_tag_eq_way_T_5; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_7 = {8'h0, _meta_0_io_resp_3_tag} == _s1_tag_eq_way_T_6; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_3 = _s1_tag_eq_way_T_7; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_9 = {8'h0, _meta_0_io_resp_4_tag} == _s1_tag_eq_way_T_8; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_4 = _s1_tag_eq_way_T_9; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_11 = {8'h0, _meta_0_io_resp_5_tag} == _s1_tag_eq_way_T_10; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_5 = _s1_tag_eq_way_T_11; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_13 = {8'h0, _meta_0_io_resp_6_tag} == _s1_tag_eq_way_T_12; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_6 = _s1_tag_eq_way_T_13; // @[dcache.scala:622:47, :623:79]
wire _s1_tag_eq_way_T_15 = {8'h0, _meta_0_io_resp_7_tag} == _s1_tag_eq_way_T_14; // @[dcache.scala:442:41, :623:{79,95}]
wire _s1_tag_eq_way_WIRE_7 = _s1_tag_eq_way_T_15; // @[dcache.scala:622:47, :623:79]
wire [1:0] s1_tag_eq_way_lo_lo = {_s1_tag_eq_way_WIRE_1, _s1_tag_eq_way_WIRE_0}; // @[dcache.scala:622:47, :623:110]
wire [1:0] s1_tag_eq_way_lo_hi = {_s1_tag_eq_way_WIRE_3, _s1_tag_eq_way_WIRE_2}; // @[dcache.scala:622:47, :623:110]
wire [3:0] s1_tag_eq_way_lo = {s1_tag_eq_way_lo_hi, s1_tag_eq_way_lo_lo}; // @[dcache.scala:623:110]
wire [1:0] s1_tag_eq_way_hi_lo = {_s1_tag_eq_way_WIRE_5, _s1_tag_eq_way_WIRE_4}; // @[dcache.scala:622:47, :623:110]
wire [1:0] s1_tag_eq_way_hi_hi = {_s1_tag_eq_way_WIRE_7, _s1_tag_eq_way_WIRE_6}; // @[dcache.scala:622:47, :623:110]
wire [3:0] s1_tag_eq_way_hi = {s1_tag_eq_way_hi_hi, s1_tag_eq_way_hi_lo}; // @[dcache.scala:623:110]
wire [7:0] _s1_tag_eq_way_T_16 = {s1_tag_eq_way_hi, s1_tag_eq_way_lo}; // @[dcache.scala:623:110]
wire [7:0] s1_tag_eq_way_0 = _s1_tag_eq_way_T_16; // @[dcache.scala:427:49, :623:110]
wire _s1_tag_match_way_T = s1_type == 3'h0; // @[dcache.scala:615:32, :625:38]
wire _s1_tag_match_way_T_1 = s1_type == 3'h2; // @[dcache.scala:615:32, :626:38]
wire _s1_tag_match_way_T_2 = s1_type == 3'h3; // @[dcache.scala:615:32, :627:38]
wire _s1_tag_match_way_T_3 = s1_tag_eq_way_0[0]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_4 = |_meta_0_io_resp_0_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_5 = _s1_tag_match_way_T_3 & _s1_tag_match_way_T_4; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_0 = _s1_tag_match_way_T_5; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_6 = s1_tag_eq_way_0[1]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_7 = |_meta_0_io_resp_1_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_8 = _s1_tag_match_way_T_6 & _s1_tag_match_way_T_7; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_1 = _s1_tag_match_way_T_8; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_9 = s1_tag_eq_way_0[2]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_10 = |_meta_0_io_resp_2_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_11 = _s1_tag_match_way_T_9 & _s1_tag_match_way_T_10; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_2 = _s1_tag_match_way_T_11; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_12 = s1_tag_eq_way_0[3]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_13 = |_meta_0_io_resp_3_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_14 = _s1_tag_match_way_T_12 & _s1_tag_match_way_T_13; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_3 = _s1_tag_match_way_T_14; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_15 = s1_tag_eq_way_0[4]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_16 = |_meta_0_io_resp_4_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_17 = _s1_tag_match_way_T_15 & _s1_tag_match_way_T_16; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_4 = _s1_tag_match_way_T_17; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_18 = s1_tag_eq_way_0[5]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_19 = |_meta_0_io_resp_5_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_20 = _s1_tag_match_way_T_18 & _s1_tag_match_way_T_19; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_5 = _s1_tag_match_way_T_20; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_21 = s1_tag_eq_way_0[6]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_22 = |_meta_0_io_resp_6_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_23 = _s1_tag_match_way_T_21 & _s1_tag_match_way_T_22; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_6 = _s1_tag_match_way_T_23; // @[dcache.scala:622:47, :628:67]
wire _s1_tag_match_way_T_24 = s1_tag_eq_way_0[7]; // @[dcache.scala:427:49, :628:63]
wire _s1_tag_match_way_T_25 = |_meta_0_io_resp_7_coh_state; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_T_26 = _s1_tag_match_way_T_24 & _s1_tag_match_way_T_25; // @[Metadata.scala:50:45]
wire _s1_tag_match_way_WIRE_7 = _s1_tag_match_way_T_26; // @[dcache.scala:622:47, :628:67]
wire [1:0] s1_tag_match_way_lo_lo = {_s1_tag_match_way_WIRE_1, _s1_tag_match_way_WIRE_0}; // @[dcache.scala:622:47, :628:104]
wire [1:0] s1_tag_match_way_lo_hi = {_s1_tag_match_way_WIRE_3, _s1_tag_match_way_WIRE_2}; // @[dcache.scala:622:47, :628:104]
wire [3:0] s1_tag_match_way_lo = {s1_tag_match_way_lo_hi, s1_tag_match_way_lo_lo}; // @[dcache.scala:628:104]
wire [1:0] s1_tag_match_way_hi_lo = {_s1_tag_match_way_WIRE_5, _s1_tag_match_way_WIRE_4}; // @[dcache.scala:622:47, :628:104]
wire [1:0] s1_tag_match_way_hi_hi = {_s1_tag_match_way_WIRE_7, _s1_tag_match_way_WIRE_6}; // @[dcache.scala:622:47, :628:104]
wire [3:0] s1_tag_match_way_hi = {s1_tag_match_way_hi_hi, s1_tag_match_way_hi_lo}; // @[dcache.scala:628:104]
wire [7:0] _s1_tag_match_way_T_27 = {s1_tag_match_way_hi, s1_tag_match_way_lo}; // @[dcache.scala:628:104]
wire [7:0] _s1_tag_match_way_T_28 = _s1_tag_match_way_T_2 ? s1_mshr_meta_read_way_en : _s1_tag_match_way_T_27; // @[dcache.scala:617:41, :627:{29,38}, :628:104]
wire [7:0] _s1_tag_match_way_T_29 = _s1_tag_match_way_T_1 ? s1_wb_way_en : _s1_tag_match_way_T_28; // @[dcache.scala:619:41, :626:{29,38}, :627:29]
wire [7:0] _s1_tag_match_way_T_30 = _s1_tag_match_way_T ? s1_replay_way_en : _s1_tag_match_way_T_29; // @[dcache.scala:618:41, :625:{29,38}, :626:29]
wire [7:0] s1_tag_match_way_0 = _s1_tag_match_way_T_30; // @[dcache.scala:427:49, :625:29]
wire _s1_wb_idx_matches_T_1 = _s1_wb_idx_matches_T == _wb_io_idx_bits; // @[dcache.scala:431:18, :630:{52,79}]
wire _s1_wb_idx_matches_T_2 = _s1_wb_idx_matches_T_1 & _wb_io_idx_valid; // @[dcache.scala:431:18, :630:{79,99}]
wire s1_wb_idx_matches_0 = _s1_wb_idx_matches_T_2; // @[dcache.scala:427:49, :630:99]
reg [6:0] s2_req_0_uop_uopc; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_uopc = s2_req_0_uop_uopc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uopc = s2_req_0_uop_uopc; // @[util.scala:101:23]
reg [31:0] s2_req_0_uop_inst; // @[dcache.scala:632:25]
wire [31:0] cache_resp_0_bits_uop_inst = s2_req_0_uop_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_inst = s2_req_0_uop_inst; // @[util.scala:101:23]
reg [31:0] s2_req_0_uop_debug_inst; // @[dcache.scala:632:25]
wire [31:0] cache_resp_0_bits_uop_debug_inst = s2_req_0_uop_debug_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_inst = s2_req_0_uop_debug_inst; // @[util.scala:101:23]
reg s2_req_0_uop_is_rvc; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_rvc = s2_req_0_uop_is_rvc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_rvc = s2_req_0_uop_is_rvc; // @[util.scala:101:23]
reg [39:0] s2_req_0_uop_debug_pc; // @[dcache.scala:632:25]
wire [39:0] cache_resp_0_bits_uop_debug_pc = s2_req_0_uop_debug_pc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_pc = s2_req_0_uop_debug_pc; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_iq_type; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_iq_type = s2_req_0_uop_iq_type; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iq_type = s2_req_0_uop_iq_type; // @[util.scala:101:23]
reg [9:0] s2_req_0_uop_fu_code; // @[dcache.scala:632:25]
wire [9:0] cache_resp_0_bits_uop_fu_code = s2_req_0_uop_fu_code; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fu_code = s2_req_0_uop_fu_code; // @[util.scala:101:23]
reg [3:0] s2_req_0_uop_ctrl_br_type; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_ctrl_br_type = s2_req_0_uop_ctrl_br_type; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_br_type = s2_req_0_uop_ctrl_br_type; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_ctrl_op1_sel; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_ctrl_op1_sel = s2_req_0_uop_ctrl_op1_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op1_sel = s2_req_0_uop_ctrl_op1_sel; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_op2_sel; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_op2_sel = s2_req_0_uop_ctrl_op2_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op2_sel = s2_req_0_uop_ctrl_op2_sel; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_imm_sel; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_imm_sel = s2_req_0_uop_ctrl_imm_sel; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_imm_sel = s2_req_0_uop_ctrl_imm_sel; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_ctrl_op_fcn; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_ctrl_op_fcn = s2_req_0_uop_ctrl_op_fcn; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_op_fcn = s2_req_0_uop_ctrl_op_fcn; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_fcn_dw = s2_req_0_uop_ctrl_fcn_dw; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw = s2_req_0_uop_ctrl_fcn_dw; // @[util.scala:101:23]
reg [2:0] s2_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:632:25]
wire [2:0] cache_resp_0_bits_uop_ctrl_csr_cmd = s2_req_0_uop_ctrl_csr_cmd; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd = s2_req_0_uop_ctrl_csr_cmd; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_load; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_load = s2_req_0_uop_ctrl_is_load; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_load = s2_req_0_uop_ctrl_is_load; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_sta; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_sta = s2_req_0_uop_ctrl_is_sta; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_sta = s2_req_0_uop_ctrl_is_sta; // @[util.scala:101:23]
reg s2_req_0_uop_ctrl_is_std; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ctrl_is_std = s2_req_0_uop_ctrl_is_std; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ctrl_is_std = s2_req_0_uop_ctrl_is_std; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_iw_state; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_iw_state = s2_req_0_uop_iw_state; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_state = s2_req_0_uop_iw_state; // @[util.scala:101:23]
reg s2_req_0_uop_iw_p1_poisoned; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_iw_p1_poisoned = s2_req_0_uop_iw_p1_poisoned; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_p1_poisoned = s2_req_0_uop_iw_p1_poisoned; // @[util.scala:101:23]
reg s2_req_0_uop_iw_p2_poisoned; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_iw_p2_poisoned = s2_req_0_uop_iw_p2_poisoned; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_iw_p2_poisoned = s2_req_0_uop_iw_p2_poisoned; // @[util.scala:101:23]
reg s2_req_0_uop_is_br; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_br = s2_req_0_uop_is_br; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_br = s2_req_0_uop_is_br; // @[util.scala:101:23]
reg s2_req_0_uop_is_jalr; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_jalr = s2_req_0_uop_is_jalr; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_jalr = s2_req_0_uop_is_jalr; // @[util.scala:101:23]
reg s2_req_0_uop_is_jal; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_jal = s2_req_0_uop_is_jal; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_jal = s2_req_0_uop_is_jal; // @[util.scala:101:23]
reg s2_req_0_uop_is_sfb; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_sfb = s2_req_0_uop_is_sfb; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_sfb = s2_req_0_uop_is_sfb; // @[util.scala:101:23]
reg [15:0] s2_req_0_uop_br_mask; // @[dcache.scala:632:25]
wire [15:0] cache_resp_0_bits_uop_br_mask = s2_req_0_uop_br_mask; // @[dcache.scala:632:25, :833:26]
reg [3:0] s2_req_0_uop_br_tag; // @[dcache.scala:632:25]
wire [3:0] cache_resp_0_bits_uop_br_tag = s2_req_0_uop_br_tag; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_br_tag = s2_req_0_uop_br_tag; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_ftq_idx; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_ftq_idx = s2_req_0_uop_ftq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ftq_idx = s2_req_0_uop_ftq_idx; // @[util.scala:101:23]
reg s2_req_0_uop_edge_inst; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_edge_inst = s2_req_0_uop_edge_inst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_edge_inst = s2_req_0_uop_edge_inst; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_pc_lob; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_pc_lob = s2_req_0_uop_pc_lob; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_pc_lob = s2_req_0_uop_pc_lob; // @[util.scala:101:23]
reg s2_req_0_uop_taken; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_taken = s2_req_0_uop_taken; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_taken = s2_req_0_uop_taken; // @[util.scala:101:23]
reg [19:0] s2_req_0_uop_imm_packed; // @[dcache.scala:632:25]
wire [19:0] cache_resp_0_bits_uop_imm_packed = s2_req_0_uop_imm_packed; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_imm_packed = s2_req_0_uop_imm_packed; // @[util.scala:101:23]
reg [11:0] s2_req_0_uop_csr_addr; // @[dcache.scala:632:25]
wire [11:0] cache_resp_0_bits_uop_csr_addr = s2_req_0_uop_csr_addr; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_csr_addr = s2_req_0_uop_csr_addr; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_rob_idx; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_rob_idx = s2_req_0_uop_rob_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_rob_idx = s2_req_0_uop_rob_idx; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_ldq_idx; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_ldq_idx = s2_req_0_uop_ldq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldq_idx = s2_req_0_uop_ldq_idx; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_stq_idx; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_stq_idx = s2_req_0_uop_stq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_stq_idx = s2_req_0_uop_stq_idx; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_rxq_idx; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_rxq_idx = s2_req_0_uop_rxq_idx; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_rxq_idx = s2_req_0_uop_rxq_idx; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_pdst; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_pdst = s2_req_0_uop_pdst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_pdst = s2_req_0_uop_pdst; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_prs1; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_prs1 = s2_req_0_uop_prs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs1 = s2_req_0_uop_prs1; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_prs2; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_prs2 = s2_req_0_uop_prs2; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs2 = s2_req_0_uop_prs2; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_prs3; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_prs3 = s2_req_0_uop_prs3; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs3 = s2_req_0_uop_prs3; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_ppred; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_ppred = s2_req_0_uop_ppred; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ppred = s2_req_0_uop_ppred; // @[util.scala:101:23]
reg s2_req_0_uop_prs1_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs1_busy = s2_req_0_uop_prs1_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs1_busy = s2_req_0_uop_prs1_busy; // @[util.scala:101:23]
reg s2_req_0_uop_prs2_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs2_busy = s2_req_0_uop_prs2_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs2_busy = s2_req_0_uop_prs2_busy; // @[util.scala:101:23]
reg s2_req_0_uop_prs3_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_prs3_busy = s2_req_0_uop_prs3_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_prs3_busy = s2_req_0_uop_prs3_busy; // @[util.scala:101:23]
reg s2_req_0_uop_ppred_busy; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ppred_busy = s2_req_0_uop_ppred_busy; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ppred_busy = s2_req_0_uop_ppred_busy; // @[util.scala:101:23]
reg [6:0] s2_req_0_uop_stale_pdst; // @[dcache.scala:632:25]
wire [6:0] cache_resp_0_bits_uop_stale_pdst = s2_req_0_uop_stale_pdst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_stale_pdst = s2_req_0_uop_stale_pdst; // @[util.scala:101:23]
reg s2_req_0_uop_exception; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_exception = s2_req_0_uop_exception; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_exception = s2_req_0_uop_exception; // @[util.scala:101:23]
reg [63:0] s2_req_0_uop_exc_cause; // @[dcache.scala:632:25]
wire [63:0] cache_resp_0_bits_uop_exc_cause = s2_req_0_uop_exc_cause; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_exc_cause = s2_req_0_uop_exc_cause; // @[util.scala:101:23]
reg s2_req_0_uop_bypassable; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bypassable = s2_req_0_uop_bypassable; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bypassable = s2_req_0_uop_bypassable; // @[util.scala:101:23]
reg [4:0] s2_req_0_uop_mem_cmd; // @[dcache.scala:632:25]
wire [4:0] cache_resp_0_bits_uop_mem_cmd = s2_req_0_uop_mem_cmd; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_cmd = s2_req_0_uop_mem_cmd; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_mem_size; // @[dcache.scala:632:25]
wire [1:0] size = s2_req_0_uop_mem_size; // @[AMOALU.scala:11:18]
wire [1:0] cache_resp_0_bits_uop_mem_size = s2_req_0_uop_mem_size; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_size = s2_req_0_uop_mem_size; // @[util.scala:101:23]
wire [1:0] amoalu_io_mask_size = s2_req_0_uop_mem_size; // @[AMOALU.scala:11:18]
reg s2_req_0_uop_mem_signed; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_mem_signed = s2_req_0_uop_mem_signed; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_mem_signed = s2_req_0_uop_mem_signed; // @[util.scala:101:23]
reg s2_req_0_uop_is_fence; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_fence = s2_req_0_uop_is_fence; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_fence = s2_req_0_uop_is_fence; // @[util.scala:101:23]
reg s2_req_0_uop_is_fencei; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_fencei = s2_req_0_uop_is_fencei; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_fencei = s2_req_0_uop_is_fencei; // @[util.scala:101:23]
reg s2_req_0_uop_is_amo; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_amo = s2_req_0_uop_is_amo; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_amo = s2_req_0_uop_is_amo; // @[util.scala:101:23]
reg s2_req_0_uop_uses_ldq; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_uses_ldq = s2_req_0_uop_uses_ldq; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uses_ldq = s2_req_0_uop_uses_ldq; // @[util.scala:101:23]
reg s2_req_0_uop_uses_stq; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_uses_stq = s2_req_0_uop_uses_stq; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_uses_stq = s2_req_0_uop_uses_stq; // @[util.scala:101:23]
reg s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_sys_pc2epc = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_sys_pc2epc = s2_req_0_uop_is_sys_pc2epc; // @[util.scala:101:23]
reg s2_req_0_uop_is_unique; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_is_unique = s2_req_0_uop_is_unique; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_is_unique = s2_req_0_uop_is_unique; // @[util.scala:101:23]
reg s2_req_0_uop_flush_on_commit; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_flush_on_commit = s2_req_0_uop_flush_on_commit; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_flush_on_commit = s2_req_0_uop_flush_on_commit; // @[util.scala:101:23]
reg s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ldst_is_rs1 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst_is_rs1 = s2_req_0_uop_ldst_is_rs1; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_ldst; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_ldst = s2_req_0_uop_ldst; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst = s2_req_0_uop_ldst; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs1; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs1 = s2_req_0_uop_lrs1; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs1 = s2_req_0_uop_lrs1; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs2; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs2 = s2_req_0_uop_lrs2; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs2 = s2_req_0_uop_lrs2; // @[util.scala:101:23]
reg [5:0] s2_req_0_uop_lrs3; // @[dcache.scala:632:25]
wire [5:0] cache_resp_0_bits_uop_lrs3 = s2_req_0_uop_lrs3; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs3 = s2_req_0_uop_lrs3; // @[util.scala:101:23]
reg s2_req_0_uop_ldst_val; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_ldst_val = s2_req_0_uop_ldst_val; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_ldst_val = s2_req_0_uop_ldst_val; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_dst_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_dst_rtype = s2_req_0_uop_dst_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_dst_rtype = s2_req_0_uop_dst_rtype; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_lrs1_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_lrs1_rtype = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs1_rtype = s2_req_0_uop_lrs1_rtype; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_lrs2_rtype; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_lrs2_rtype = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_lrs2_rtype = s2_req_0_uop_lrs2_rtype; // @[util.scala:101:23]
reg s2_req_0_uop_frs3_en; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_frs3_en = s2_req_0_uop_frs3_en; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_frs3_en = s2_req_0_uop_frs3_en; // @[util.scala:101:23]
reg s2_req_0_uop_fp_val; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_fp_val = s2_req_0_uop_fp_val; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fp_val = s2_req_0_uop_fp_val; // @[util.scala:101:23]
reg s2_req_0_uop_fp_single; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_fp_single = s2_req_0_uop_fp_single; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_fp_single = s2_req_0_uop_fp_single; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_pf_if = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_pf_if = s2_req_0_uop_xcpt_pf_if; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_ae_if = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_ae_if = s2_req_0_uop_xcpt_ae_if; // @[util.scala:101:23]
reg s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_xcpt_ma_if = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_xcpt_ma_if = s2_req_0_uop_xcpt_ma_if; // @[util.scala:101:23]
reg s2_req_0_uop_bp_debug_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bp_debug_if = s2_req_0_uop_bp_debug_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bp_debug_if = s2_req_0_uop_bp_debug_if; // @[util.scala:101:23]
reg s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:632:25]
wire cache_resp_0_bits_uop_bp_xcpt_if = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_bp_xcpt_if = s2_req_0_uop_bp_xcpt_if; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_debug_fsrc; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_debug_fsrc = s2_req_0_uop_debug_fsrc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_fsrc = s2_req_0_uop_debug_fsrc; // @[util.scala:101:23]
reg [1:0] s2_req_0_uop_debug_tsrc; // @[dcache.scala:632:25]
wire [1:0] cache_resp_0_bits_uop_debug_tsrc = s2_req_0_uop_debug_tsrc; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_uop_debug_tsrc = s2_req_0_uop_debug_tsrc; // @[util.scala:101:23]
reg [39:0] s2_req_0_addr; // @[dcache.scala:632:25]
assign io_lsu_nack_0_bits_out_addr = s2_req_0_addr; // @[util.scala:101:23]
reg [63:0] s2_req_0_data; // @[dcache.scala:632:25]
assign io_lsu_nack_0_bits_out_data = s2_req_0_data; // @[util.scala:101:23]
reg s2_req_0_is_hella; // @[dcache.scala:632:25]
wire cache_resp_0_bits_is_hella = s2_req_0_is_hella; // @[dcache.scala:632:25, :833:26]
assign io_lsu_nack_0_bits_out_is_hella = s2_req_0_is_hella; // @[util.scala:101:23]
reg [2:0] s2_type; // @[dcache.scala:633:25]
wire _s2_valid_T = ~io_lsu_s1_kill_0_0; // @[dcache.scala:413:7, :636:26]
wire _s2_valid_T_1 = s1_valid_0 & _s2_valid_T; // @[dcache.scala:427:49, :635:39, :636:26]
wire [15:0] _s2_valid_T_2 = io_lsu_brupdate_b1_mispredict_mask_0 & s1_req_0_uop_br_mask; // @[util.scala:118:51]
wire _s2_valid_T_3 = |_s2_valid_T_2; // @[util.scala:118:{51,59}]
wire _s2_valid_T_4 = ~_s2_valid_T_3; // @[util.scala:118:59]
wire _s2_valid_T_5 = _s2_valid_T_1 & _s2_valid_T_4; // @[dcache.scala:635:39, :636:45, :637:26]
wire _s2_valid_T_6 = io_lsu_exception_0 & s1_req_0_uop_uses_ldq; // @[dcache.scala:413:7, :600:32, :638:45]
wire _s2_valid_T_7 = ~_s2_valid_T_6; // @[dcache.scala:638:{26,45}]
wire _s2_valid_T_8 = _s2_valid_T_5 & _s2_valid_T_7; // @[dcache.scala:636:45, :637:76, :638:26]
wire _s2_valid_T_9 = s1_type == 3'h4; // @[dcache.scala:615:32, :639:56]
wire _s2_valid_T_10 = s2_store_failed & _s2_valid_T_9; // @[dcache.scala:603:29, :639:{44,56}]
wire _s2_valid_T_11 = _s2_valid_T_10 & s1_req_0_uop_uses_stq; // @[dcache.scala:600:32, :639:{44,67}]
wire _s2_valid_T_12 = ~_s2_valid_T_11; // @[dcache.scala:639:{26,67}]
wire _s2_valid_T_13 = _s2_valid_T_8 & _s2_valid_T_12; // @[dcache.scala:637:76, :638:72, :639:26]
reg s2_valid_REG; // @[dcache.scala:635:26]
wire s2_valid_0 = s2_valid_REG; // @[dcache.scala:427:49, :635:26]
wire [15:0] _s2_req_0_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _s2_req_0_uop_br_mask_T_1 = s1_req_0_uop_br_mask & _s2_req_0_uop_br_mask_T; // @[util.scala:85:{25,27}]
reg [7:0] s2_tag_match_way_0; // @[dcache.scala:643:33]
wire s2_tag_match_0 = |s2_tag_match_way_0; // @[dcache.scala:643:33, :644:49]
reg [1:0] s2_hit_state_REG_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_0_state = s2_hit_state_REG_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_1_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_1_state_0 = s2_hit_state_REG_1_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_2_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_2_state = s2_hit_state_REG_2_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_3_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_3_state = s2_hit_state_REG_3_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_4_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_4_state = s2_hit_state_REG_4_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_5_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_5_state = s2_hit_state_REG_5_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_6_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_6_state = s2_hit_state_REG_6_state; // @[dcache.scala:622:47, :645:93]
reg [1:0] s2_hit_state_REG_7_state; // @[dcache.scala:645:93]
wire [1:0] _s2_hit_state_WIRE_7_state = s2_hit_state_REG_7_state; // @[dcache.scala:622:47, :645:93]
wire _s2_hit_state_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_4 = s2_tag_match_way_0[4]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_4 = s2_tag_match_way_0[4]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_4 = s2_tag_match_way_0[4]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_5 = s2_tag_match_way_0[5]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_5 = s2_tag_match_way_0[5]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_5 = s2_tag_match_way_0[5]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_6 = s2_tag_match_way_0[6]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_6 = s2_tag_match_way_0[6]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_6 = s2_tag_match_way_0[6]; // @[Mux.scala:32:36]
wire _s2_hit_state_T_7 = s2_tag_match_way_0[7]; // @[Mux.scala:32:36]
wire _s2_data_muxed_T_7 = s2_tag_match_way_0[7]; // @[Mux.scala:32:36]
wire _mshrs_io_meta_resp_bits_T_7 = s2_tag_match_way_0[7]; // @[Mux.scala:32:36]
wire [1:0] _s2_hit_state_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] s2_hit_state_0_state = _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_8 = _s2_hit_state_T ? _s2_hit_state_WIRE_0_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_9 = _s2_hit_state_T_1 ? _s2_hit_state_WIRE_1_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_10 = _s2_hit_state_T_2 ? _s2_hit_state_WIRE_2_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_11 = _s2_hit_state_T_3 ? _s2_hit_state_WIRE_3_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_12 = _s2_hit_state_T_4 ? _s2_hit_state_WIRE_4_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_13 = _s2_hit_state_T_5 ? _s2_hit_state_WIRE_5_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_14 = _s2_hit_state_T_6 ? _s2_hit_state_WIRE_6_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_15 = _s2_hit_state_T_7 ? _s2_hit_state_WIRE_7_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_hit_state_T_16 = _s2_hit_state_T_8 | _s2_hit_state_T_9; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_17 = _s2_hit_state_T_16 | _s2_hit_state_T_10; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_18 = _s2_hit_state_T_17 | _s2_hit_state_T_11; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_19 = _s2_hit_state_T_18 | _s2_hit_state_T_12; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_20 = _s2_hit_state_T_19 | _s2_hit_state_T_13; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_21 = _s2_hit_state_T_20 | _s2_hit_state_T_14; // @[Mux.scala:30:73]
wire [1:0] _s2_hit_state_T_22 = _s2_hit_state_T_21 | _s2_hit_state_T_15; // @[Mux.scala:30:73]
assign _s2_hit_state_WIRE_2 = _s2_hit_state_T_22; // @[Mux.scala:30:73]
assign _s2_hit_state_WIRE_1_state = _s2_hit_state_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] mshrs_io_req_0_bits_old_meta_meta_coh_state = s2_hit_state_0_state; // @[HellaCache.scala:305:20]
wire _GEN_2 = s2_req_0_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _s2_has_permission_r_c_cat_T; // @[Consts.scala:90:32]
assign _s2_has_permission_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32]
wire _s2_has_permission_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _s2_has_permission_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32]
wire _s2_new_hit_state_r_c_cat_T; // @[Consts.scala:90:32]
assign _s2_new_hit_state_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32]
wire _s2_new_hit_state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _s2_new_hit_state_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32]
wire _s2_send_resp_T_3; // @[Consts.scala:90:32]
assign _s2_send_resp_T_3 = _GEN_2; // @[Consts.scala:90:32]
wire _mshrs_io_req_0_valid_T_50; // @[Consts.scala:90:32]
assign _mshrs_io_req_0_valid_T_50 = _GEN_2; // @[Consts.scala:90:32]
wire _s3_valid_T_1; // @[Consts.scala:90:32]
assign _s3_valid_T_1 = _GEN_2; // @[Consts.scala:90:32]
wire _GEN_3 = s2_req_0_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _s2_has_permission_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _s2_has_permission_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _s2_new_hit_state_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _s2_new_hit_state_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_send_resp_T_4; // @[Consts.scala:90:49]
assign _s2_send_resp_T_4 = _GEN_3; // @[Consts.scala:90:49]
wire _mshrs_io_req_0_valid_T_51; // @[Consts.scala:90:49]
assign _mshrs_io_req_0_valid_T_51 = _GEN_3; // @[Consts.scala:90:49]
wire _s3_valid_T_2; // @[Consts.scala:90:49]
assign _s3_valid_T_2 = _GEN_3; // @[Consts.scala:90:49]
wire _s2_has_permission_r_c_cat_T_2 = _s2_has_permission_r_c_cat_T | _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_4 = s2_req_0_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _s2_has_permission_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _s2_has_permission_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _s2_new_hit_state_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _s2_new_hit_state_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_sc_T; // @[dcache.scala:664:37]
assign _s2_sc_T = _GEN_4; // @[Consts.scala:90:66]
wire _s2_send_resp_T_6; // @[Consts.scala:90:66]
assign _s2_send_resp_T_6 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_send_resp_T_30; // @[package.scala:16:47]
assign _s2_send_resp_T_30 = _GEN_4; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_27; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_27 = _GEN_4; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_53; // @[Consts.scala:90:66]
assign _mshrs_io_req_0_valid_T_53 = _GEN_4; // @[Consts.scala:90:66]
wire _s3_valid_T_4; // @[Consts.scala:90:66]
assign _s3_valid_T_4 = _GEN_4; // @[Consts.scala:90:66]
wire _s2_has_permission_r_c_cat_T_4 = _s2_has_permission_r_c_cat_T_2 | _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_5 = s2_req_0_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_5; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_28; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_5; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_28; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47]
wire _s2_send_resp_T_8; // @[package.scala:16:47]
assign _s2_send_resp_T_8 = _GEN_5; // @[package.scala:16:47]
wire _s2_send_resp_T_34; // @[package.scala:16:47]
assign _s2_send_resp_T_34 = _GEN_5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_31; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_31 = _GEN_5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_55; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_55 = _GEN_5; // @[package.scala:16:47]
wire _s3_valid_T_6; // @[package.scala:16:47]
assign _s3_valid_T_6 = _GEN_5; // @[package.scala:16:47]
wire _GEN_6 = s2_req_0_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47]
wire _s2_send_resp_T_9; // @[package.scala:16:47]
assign _s2_send_resp_T_9 = _GEN_6; // @[package.scala:16:47]
wire _s2_send_resp_T_35; // @[package.scala:16:47]
assign _s2_send_resp_T_35 = _GEN_6; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_32; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_32 = _GEN_6; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_56; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_56 = _GEN_6; // @[package.scala:16:47]
wire _s3_valid_T_7; // @[package.scala:16:47]
assign _s3_valid_T_7 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = s2_req_0_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47]
wire _s2_send_resp_T_10; // @[package.scala:16:47]
assign _s2_send_resp_T_10 = _GEN_7; // @[package.scala:16:47]
wire _s2_send_resp_T_36; // @[package.scala:16:47]
assign _s2_send_resp_T_36 = _GEN_7; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_33; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_33 = _GEN_7; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_57; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_57 = _GEN_7; // @[package.scala:16:47]
wire _s3_valid_T_8; // @[package.scala:16:47]
assign _s3_valid_T_8 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = s2_req_0_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47]
wire _s2_send_resp_T_11; // @[package.scala:16:47]
assign _s2_send_resp_T_11 = _GEN_8; // @[package.scala:16:47]
wire _s2_send_resp_T_37; // @[package.scala:16:47]
assign _s2_send_resp_T_37 = _GEN_8; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_34; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_34 = _GEN_8; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_58; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_58 = _GEN_8; // @[package.scala:16:47]
wire _s3_valid_T_9; // @[package.scala:16:47]
assign _s3_valid_T_9 = _GEN_8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_9 = _s2_has_permission_r_c_cat_T_5 | _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_10 = _s2_has_permission_r_c_cat_T_9 | _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_11 = _s2_has_permission_r_c_cat_T_10 | _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_9 = s2_req_0_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_12; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_35; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_12; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_35; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47]
wire _s2_send_resp_T_15; // @[package.scala:16:47]
assign _s2_send_resp_T_15 = _GEN_9; // @[package.scala:16:47]
wire _s2_send_resp_T_41; // @[package.scala:16:47]
assign _s2_send_resp_T_41 = _GEN_9; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_38; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_38 = _GEN_9; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_62; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_62 = _GEN_9; // @[package.scala:16:47]
wire _s3_valid_T_13; // @[package.scala:16:47]
assign _s3_valid_T_13 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = s2_req_0_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47]
wire _s2_send_resp_T_16; // @[package.scala:16:47]
assign _s2_send_resp_T_16 = _GEN_10; // @[package.scala:16:47]
wire _s2_send_resp_T_42; // @[package.scala:16:47]
assign _s2_send_resp_T_42 = _GEN_10; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_39; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_39 = _GEN_10; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_63; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_63 = _GEN_10; // @[package.scala:16:47]
wire _s3_valid_T_14; // @[package.scala:16:47]
assign _s3_valid_T_14 = _GEN_10; // @[package.scala:16:47]
wire _GEN_11 = s2_req_0_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47]
wire _s2_send_resp_T_17; // @[package.scala:16:47]
assign _s2_send_resp_T_17 = _GEN_11; // @[package.scala:16:47]
wire _s2_send_resp_T_43; // @[package.scala:16:47]
assign _s2_send_resp_T_43 = _GEN_11; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_40; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_40 = _GEN_11; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_64; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_64 = _GEN_11; // @[package.scala:16:47]
wire _s3_valid_T_15; // @[package.scala:16:47]
assign _s3_valid_T_15 = _GEN_11; // @[package.scala:16:47]
wire _GEN_12 = s2_req_0_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47]
wire _s2_send_resp_T_18; // @[package.scala:16:47]
assign _s2_send_resp_T_18 = _GEN_12; // @[package.scala:16:47]
wire _s2_send_resp_T_44; // @[package.scala:16:47]
assign _s2_send_resp_T_44 = _GEN_12; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_41; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_41 = _GEN_12; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_65; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_65 = _GEN_12; // @[package.scala:16:47]
wire _s3_valid_T_16; // @[package.scala:16:47]
assign _s3_valid_T_16 = _GEN_12; // @[package.scala:16:47]
wire _GEN_13 = s2_req_0_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47]
assign _s2_has_permission_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47]
wire _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47]
assign _s2_new_hit_state_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47]
wire _s2_send_resp_T_19; // @[package.scala:16:47]
assign _s2_send_resp_T_19 = _GEN_13; // @[package.scala:16:47]
wire _s2_send_resp_T_45; // @[package.scala:16:47]
assign _s2_send_resp_T_45 = _GEN_13; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_42; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_42 = _GEN_13; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_66; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_66 = _GEN_13; // @[package.scala:16:47]
wire _s3_valid_T_17; // @[package.scala:16:47]
assign _s3_valid_T_17 = _GEN_13; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_17 = _s2_has_permission_r_c_cat_T_12 | _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_18 = _s2_has_permission_r_c_cat_T_17 | _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_19 = _s2_has_permission_r_c_cat_T_18 | _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_20 = _s2_has_permission_r_c_cat_T_19 | _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_21 = _s2_has_permission_r_c_cat_T_11 | _s2_has_permission_r_c_cat_T_20; // @[package.scala:81:59]
wire _s2_has_permission_r_c_cat_T_22 = _s2_has_permission_r_c_cat_T_4 | _s2_has_permission_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_has_permission_r_c_cat_T_25 = _s2_has_permission_r_c_cat_T_23 | _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _s2_has_permission_r_c_cat_T_27 = _s2_has_permission_r_c_cat_T_25 | _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _s2_has_permission_r_c_cat_T_32 = _s2_has_permission_r_c_cat_T_28 | _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_33 = _s2_has_permission_r_c_cat_T_32 | _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_34 = _s2_has_permission_r_c_cat_T_33 | _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_40 = _s2_has_permission_r_c_cat_T_35 | _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_41 = _s2_has_permission_r_c_cat_T_40 | _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_42 = _s2_has_permission_r_c_cat_T_41 | _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_43 = _s2_has_permission_r_c_cat_T_42 | _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _s2_has_permission_r_c_cat_T_44 = _s2_has_permission_r_c_cat_T_34 | _s2_has_permission_r_c_cat_T_43; // @[package.scala:81:59]
wire _s2_has_permission_r_c_cat_T_45 = _s2_has_permission_r_c_cat_T_27 | _s2_has_permission_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_14 = s2_req_0_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _s2_has_permission_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54]
wire _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _s2_new_hit_state_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54]
wire _mshrs_io_req_0_valid_T_22; // @[Consts.scala:88:52]
assign _mshrs_io_req_0_valid_T_22 = _GEN_14; // @[Consts.scala:88:52, :91:54]
wire _s2_has_permission_r_c_cat_T_47 = _s2_has_permission_r_c_cat_T_45 | _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_15 = s2_req_0_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _s2_has_permission_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71]
wire _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _s2_new_hit_state_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71]
wire _s2_lr_T; // @[dcache.scala:663:37]
assign _s2_lr_T = _GEN_15; // @[Consts.scala:91:71]
wire _s2_send_resp_T_29; // @[package.scala:16:47]
assign _s2_send_resp_T_29 = _GEN_15; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_26; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_26 = _GEN_15; // @[package.scala:16:47]
wire _s2_has_permission_r_c_cat_T_49 = _s2_has_permission_r_c_cat_T_47 | _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] s2_has_permission_r_c = {_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _s2_has_permission_r_T = {s2_has_permission_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19]
wire _s2_has_permission_r_T_25 = _s2_has_permission_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_27 = {1'h0, _s2_has_permission_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_28 = _s2_has_permission_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_30 = _s2_has_permission_r_T_28 ? 2'h2 : _s2_has_permission_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_31 = _s2_has_permission_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_33 = _s2_has_permission_r_T_31 ? 2'h1 : _s2_has_permission_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_34 = _s2_has_permission_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_36 = _s2_has_permission_r_T_34 ? 2'h2 : _s2_has_permission_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_37 = _s2_has_permission_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _s2_has_permission_r_T_39 = _s2_has_permission_r_T_37 ? 2'h0 : _s2_has_permission_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_40 = _s2_has_permission_r_T == 4'hE; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_41 = _s2_has_permission_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_42 = _s2_has_permission_r_T_40 ? 2'h3 : _s2_has_permission_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_43 = &_s2_has_permission_r_T; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_44 = _s2_has_permission_r_T_43 | _s2_has_permission_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_45 = _s2_has_permission_r_T_43 ? 2'h3 : _s2_has_permission_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_46 = _s2_has_permission_r_T == 4'h6; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_47 = _s2_has_permission_r_T_46 | _s2_has_permission_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_48 = _s2_has_permission_r_T_46 ? 2'h2 : _s2_has_permission_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_49 = _s2_has_permission_r_T == 4'h7; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_50 = _s2_has_permission_r_T_49 | _s2_has_permission_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_51 = _s2_has_permission_r_T_49 ? 2'h3 : _s2_has_permission_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_52 = _s2_has_permission_r_T == 4'h1; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_53 = _s2_has_permission_r_T_52 | _s2_has_permission_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_54 = _s2_has_permission_r_T_52 ? 2'h1 : _s2_has_permission_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_55 = _s2_has_permission_r_T == 4'h2; // @[Misc.scala:49:20]
wire _s2_has_permission_r_T_56 = _s2_has_permission_r_T_55 | _s2_has_permission_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_has_permission_r_T_57 = _s2_has_permission_r_T_55 ? 2'h2 : _s2_has_permission_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _s2_has_permission_r_T_58 = _s2_has_permission_r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_has_permission_r_1 = _s2_has_permission_r_T_58 | _s2_has_permission_r_T_56; // @[Misc.scala:35:9, :49:20]
wire s2_has_permission_0 = s2_has_permission_r_1; // @[Misc.scala:35:9]
wire [1:0] s2_has_permission_r_2 = _s2_has_permission_r_T_58 ? 2'h3 : _s2_has_permission_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_has_permission_meta_state = s2_has_permission_r_2; // @[Misc.scala:35:36]
wire _s2_new_hit_state_r_c_cat_T_2 = _s2_new_hit_state_r_c_cat_T | _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s2_new_hit_state_r_c_cat_T_4 = _s2_new_hit_state_r_c_cat_T_2 | _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s2_new_hit_state_r_c_cat_T_9 = _s2_new_hit_state_r_c_cat_T_5 | _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_10 = _s2_new_hit_state_r_c_cat_T_9 | _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_11 = _s2_new_hit_state_r_c_cat_T_10 | _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_17 = _s2_new_hit_state_r_c_cat_T_12 | _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_18 = _s2_new_hit_state_r_c_cat_T_17 | _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_19 = _s2_new_hit_state_r_c_cat_T_18 | _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_20 = _s2_new_hit_state_r_c_cat_T_19 | _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_21 = _s2_new_hit_state_r_c_cat_T_11 | _s2_new_hit_state_r_c_cat_T_20; // @[package.scala:81:59]
wire _s2_new_hit_state_r_c_cat_T_22 = _s2_new_hit_state_r_c_cat_T_4 | _s2_new_hit_state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_new_hit_state_r_c_cat_T_25 = _s2_new_hit_state_r_c_cat_T_23 | _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _s2_new_hit_state_r_c_cat_T_27 = _s2_new_hit_state_r_c_cat_T_25 | _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _s2_new_hit_state_r_c_cat_T_32 = _s2_new_hit_state_r_c_cat_T_28 | _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_33 = _s2_new_hit_state_r_c_cat_T_32 | _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_34 = _s2_new_hit_state_r_c_cat_T_33 | _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_40 = _s2_new_hit_state_r_c_cat_T_35 | _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_41 = _s2_new_hit_state_r_c_cat_T_40 | _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_42 = _s2_new_hit_state_r_c_cat_T_41 | _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_43 = _s2_new_hit_state_r_c_cat_T_42 | _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _s2_new_hit_state_r_c_cat_T_44 = _s2_new_hit_state_r_c_cat_T_34 | _s2_new_hit_state_r_c_cat_T_43; // @[package.scala:81:59]
wire _s2_new_hit_state_r_c_cat_T_45 = _s2_new_hit_state_r_c_cat_T_27 | _s2_new_hit_state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_new_hit_state_r_c_cat_T_47 = _s2_new_hit_state_r_c_cat_T_45 | _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _s2_new_hit_state_r_c_cat_T_49 = _s2_new_hit_state_r_c_cat_T_47 | _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] s2_new_hit_state_r_c = {_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _s2_new_hit_state_r_T = {s2_new_hit_state_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19]
wire _s2_new_hit_state_r_T_25 = _s2_new_hit_state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_27 = {1'h0, _s2_new_hit_state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_28 = _s2_new_hit_state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_30 = _s2_new_hit_state_r_T_28 ? 2'h2 : _s2_new_hit_state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_31 = _s2_new_hit_state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_33 = _s2_new_hit_state_r_T_31 ? 2'h1 : _s2_new_hit_state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_34 = _s2_new_hit_state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_36 = _s2_new_hit_state_r_T_34 ? 2'h2 : _s2_new_hit_state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_37 = _s2_new_hit_state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _s2_new_hit_state_r_T_39 = _s2_new_hit_state_r_T_37 ? 2'h0 : _s2_new_hit_state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_40 = _s2_new_hit_state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_41 = _s2_new_hit_state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_42 = _s2_new_hit_state_r_T_40 ? 2'h3 : _s2_new_hit_state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_43 = &_s2_new_hit_state_r_T; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_44 = _s2_new_hit_state_r_T_43 | _s2_new_hit_state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_45 = _s2_new_hit_state_r_T_43 ? 2'h3 : _s2_new_hit_state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_46 = _s2_new_hit_state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_47 = _s2_new_hit_state_r_T_46 | _s2_new_hit_state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_48 = _s2_new_hit_state_r_T_46 ? 2'h2 : _s2_new_hit_state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_49 = _s2_new_hit_state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_50 = _s2_new_hit_state_r_T_49 | _s2_new_hit_state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_51 = _s2_new_hit_state_r_T_49 ? 2'h3 : _s2_new_hit_state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_52 = _s2_new_hit_state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_53 = _s2_new_hit_state_r_T_52 | _s2_new_hit_state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_54 = _s2_new_hit_state_r_T_52 ? 2'h1 : _s2_new_hit_state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_55 = _s2_new_hit_state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _s2_new_hit_state_r_T_56 = _s2_new_hit_state_r_T_55 | _s2_new_hit_state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _s2_new_hit_state_r_T_57 = _s2_new_hit_state_r_T_55 ? 2'h2 : _s2_new_hit_state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _s2_new_hit_state_r_T_58 = _s2_new_hit_state_r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_new_hit_state_r_1 = _s2_new_hit_state_r_T_58 | _s2_new_hit_state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] s2_new_hit_state_r_2 = _s2_new_hit_state_r_T_58 ? 2'h3 : _s2_new_hit_state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_new_hit_state_meta_state = s2_new_hit_state_r_2; // @[Misc.scala:35:36]
wire [1:0] s2_new_hit_state_0_state = s2_new_hit_state_meta_state; // @[Metadata.scala:160:20]
wire _s2_hit_T = s2_tag_match_0 & s2_has_permission_0; // @[dcache.scala:427:49, :644:49, :649:47]
wire _s2_hit_T_1 = s2_hit_state_0_state == s2_new_hit_state_0_state; // @[Metadata.scala:46:46]
wire _s2_hit_T_2 = _s2_hit_T & _s2_hit_T_1; // @[Metadata.scala:46:46]
wire _s2_hit_T_3 = ~_mshrs_io_block_hit_0; // @[dcache.scala:433:21, :649:117]
wire _s2_hit_T_4 = _s2_hit_T_2 & _s2_hit_T_3; // @[dcache.scala:649:{71,114,117}]
wire _T_67 = s2_type == 3'h0; // @[package.scala:16:47]
wire _s2_hit_T_5; // @[package.scala:16:47]
assign _s2_hit_T_5 = _T_67; // @[package.scala:16:47]
wire _s2_lr_T_2; // @[dcache.scala:663:83]
assign _s2_lr_T_2 = _T_67; // @[package.scala:16:47]
wire _s2_sc_T_2; // @[dcache.scala:664:83]
assign _s2_sc_T_2 = _T_67; // @[package.scala:16:47]
wire _s2_hit_T_6 = s2_type == 3'h2; // @[package.scala:16:47]
wire _s2_hit_T_7 = _s2_hit_T_5 | _s2_hit_T_6; // @[package.scala:16:47, :81:59]
wire _s2_hit_T_8 = _s2_hit_T_4 | _s2_hit_T_7; // @[package.scala:81:59]
wire s2_hit_0 = _s2_hit_T_8; // @[dcache.scala:427:49, :649:141]
wire s2_nack_0; // @[dcache.scala:650:21]
reg s2_wb_idx_matches_0; // @[dcache.scala:654:34]
reg [39:0] debug_sc_fail_addr; // @[dcache.scala:657:35]
reg [7:0] debug_sc_fail_cnt; // @[dcache.scala:658:35]
reg [6:0] lrsc_count; // @[dcache.scala:660:27]
wire lrsc_valid = |(lrsc_count[6:2]); // @[dcache.scala:660:27, :661:31]
reg [33:0] lrsc_addr; // @[dcache.scala:662:23]
reg s2_lr_REG; // @[dcache.scala:663:59]
wire _s2_lr_T_1 = ~s2_lr_REG; // @[dcache.scala:663:{51,59}]
wire _s2_lr_T_3 = _s2_lr_T_1 | _s2_lr_T_2; // @[dcache.scala:663:{51,72,83}]
wire s2_lr = _s2_lr_T & _s2_lr_T_3; // @[dcache.scala:663:{37,47,72}]
reg s2_sc_REG; // @[dcache.scala:664:59]
wire _s2_sc_T_1 = ~s2_sc_REG; // @[dcache.scala:664:{51,59}]
wire _s2_sc_T_3 = _s2_sc_T_1 | _s2_sc_T_2; // @[dcache.scala:664:{51,72,83}]
wire s2_sc = _s2_sc_T & _s2_sc_T_3; // @[dcache.scala:664:{37,47,72}]
wire cache_resp_0_bits_data_doZero_2 = s2_sc; // @[AMOALU.scala:43:31]
wire [33:0] _s2_lrsc_addr_match_T = s2_req_0_addr[39:6]; // @[dcache.scala:632:25, :665:86]
wire [33:0] _lrsc_addr_T = s2_req_0_addr[39:6]; // @[dcache.scala:632:25, :665:86, :672:35]
wire _s2_lrsc_addr_match_T_1 = lrsc_addr == _s2_lrsc_addr_match_T; // @[dcache.scala:662:23, :665:{66,86}]
wire _s2_lrsc_addr_match_T_2 = lrsc_valid & _s2_lrsc_addr_match_T_1; // @[dcache.scala:661:31, :665:{53,66}]
wire s2_lrsc_addr_match_0 = _s2_lrsc_addr_match_T_2; // @[dcache.scala:427:49, :665:53]
wire _s2_sc_fail_T = ~s2_lrsc_addr_match_0; // @[dcache.scala:427:49, :666:29]
wire s2_sc_fail = s2_sc & _s2_sc_fail_T; // @[dcache.scala:664:47, :666:{26,29}]
wire [7:0] _lrsc_count_T = {1'h0, lrsc_count} - 8'h1; // @[dcache.scala:660:27, :667:54]
wire [6:0] _lrsc_count_T_1 = _lrsc_count_T[6:0]; // @[dcache.scala:667:54]
wire _mshrs_io_req_0_valid_T_10 = s2_type == 3'h4; // @[package.scala:16:47]
wire [8:0] _debug_sc_fail_cnt_T = {1'h0, debug_sc_fail_cnt} + 9'h1; // @[dcache.scala:658:35, :692:48]
wire [7:0] _debug_sc_fail_cnt_T_1 = _debug_sc_fail_cnt_T[7:0]; // @[dcache.scala:692:48]
wire [127:0] s2_data_0_0; // @[dcache.scala:705:21]
wire [127:0] s2_data_0_1; // @[dcache.scala:705:21]
wire [127:0] s2_data_0_2; // @[dcache.scala:705:21]
wire [127:0] s2_data_0_3; // @[dcache.scala:705:21]
wire [127:0] s2_data_0_4; // @[dcache.scala:705:21]
wire [127:0] s2_data_0_5; // @[dcache.scala:705:21]
wire [127:0] s2_data_0_6; // @[dcache.scala:705:21]
wire [127:0] s2_data_0_7; // @[dcache.scala:705:21]
wire [127:0] _s2_data_muxed_T_8 = _s2_data_muxed_T ? s2_data_0_0 : 128'h0; // @[Mux.scala:30:73, :32:36]
wire [127:0] _s2_data_muxed_T_9 = _s2_data_muxed_T_1 ? s2_data_0_1 : 128'h0; // @[Mux.scala:30:73, :32:36]
wire [127:0] _s2_data_muxed_T_10 = _s2_data_muxed_T_2 ? s2_data_0_2 : 128'h0; // @[Mux.scala:30:73, :32:36]
wire [127:0] _s2_data_muxed_T_11 = _s2_data_muxed_T_3 ? s2_data_0_3 : 128'h0; // @[Mux.scala:30:73, :32:36]
wire [127:0] _s2_data_muxed_T_12 = _s2_data_muxed_T_4 ? s2_data_0_4 : 128'h0; // @[Mux.scala:30:73, :32:36]
wire [127:0] _s2_data_muxed_T_13 = _s2_data_muxed_T_5 ? s2_data_0_5 : 128'h0; // @[Mux.scala:30:73, :32:36]
wire [127:0] _s2_data_muxed_T_14 = _s2_data_muxed_T_6 ? s2_data_0_6 : 128'h0; // @[Mux.scala:30:73, :32:36]
wire [127:0] _s2_data_muxed_T_15 = _s2_data_muxed_T_7 ? s2_data_0_7 : 128'h0; // @[Mux.scala:30:73, :32:36]
wire [127:0] _s2_data_muxed_T_16 = _s2_data_muxed_T_8 | _s2_data_muxed_T_9; // @[Mux.scala:30:73]
wire [127:0] _s2_data_muxed_T_17 = _s2_data_muxed_T_16 | _s2_data_muxed_T_10; // @[Mux.scala:30:73]
wire [127:0] _s2_data_muxed_T_18 = _s2_data_muxed_T_17 | _s2_data_muxed_T_11; // @[Mux.scala:30:73]
wire [127:0] _s2_data_muxed_T_19 = _s2_data_muxed_T_18 | _s2_data_muxed_T_12; // @[Mux.scala:30:73]
wire [127:0] _s2_data_muxed_T_20 = _s2_data_muxed_T_19 | _s2_data_muxed_T_13; // @[Mux.scala:30:73]
wire [127:0] _s2_data_muxed_T_21 = _s2_data_muxed_T_20 | _s2_data_muxed_T_14; // @[Mux.scala:30:73]
wire [127:0] _s2_data_muxed_T_22 = _s2_data_muxed_T_21 | _s2_data_muxed_T_15; // @[Mux.scala:30:73]
wire [127:0] _s2_data_muxed_WIRE = _s2_data_muxed_T_22; // @[Mux.scala:30:73]
wire [127:0] s2_data_muxed_0 = _s2_data_muxed_WIRE; // @[Mux.scala:30:73]
wire _s2_word_idx_T = s2_req_0_addr[3]; // @[dcache.scala:632:25, :713:79]
wire s2_word_idx_0 = _s2_word_idx_T; // @[dcache.scala:427:49, :713:79]
wire replace; // @[Replacement.scala:37:29]
wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17]
wire [2:0] _s1_replaced_way_en_T = lfsr[2:0]; // @[PRNG.scala:95:17]
wire [2:0] _s2_replaced_way_en_T = lfsr[2:0]; // @[PRNG.scala:95:17]
wire [7:0] s1_replaced_way_en = 8'h1 << _s1_replaced_way_en_T; // @[OneHot.scala:58:35]
reg [2:0] s2_replaced_way_en_REG; // @[dcache.scala:718:44]
wire [7:0] s2_replaced_way_en = 8'h1 << s2_replaced_way_en_REG; // @[OneHot.scala:58:35]
reg [1:0] s2_repl_meta_REG_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_0_coh_state = s2_repl_meta_REG_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_0_tag = s2_repl_meta_REG_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_1_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_1_coh_state_0 = s2_repl_meta_REG_1_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_1_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_1_tag_0 = s2_repl_meta_REG_1_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_2_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_2_coh_state = s2_repl_meta_REG_2_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_2_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_2_tag = s2_repl_meta_REG_2_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_3_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_3_coh_state = s2_repl_meta_REG_3_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_3_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_3_tag = s2_repl_meta_REG_3_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_4_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_4_coh_state = s2_repl_meta_REG_4_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_4_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_4_tag = s2_repl_meta_REG_4_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_5_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_5_coh_state = s2_repl_meta_REG_5_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_5_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_5_tag = s2_repl_meta_REG_5_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_6_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_6_coh_state = s2_repl_meta_REG_6_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_6_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_6_tag = s2_repl_meta_REG_6_tag; // @[dcache.scala:622:47, :719:88]
reg [1:0] s2_repl_meta_REG_7_coh_state; // @[dcache.scala:719:88]
wire [1:0] _s2_repl_meta_WIRE_7_coh_state = s2_repl_meta_REG_7_coh_state; // @[dcache.scala:622:47, :719:88]
reg [19:0] s2_repl_meta_REG_7_tag; // @[dcache.scala:719:88]
wire [19:0] _s2_repl_meta_WIRE_7_tag = s2_repl_meta_REG_7_tag; // @[dcache.scala:622:47, :719:88]
wire _s2_repl_meta_T = s2_replaced_way_en[0]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_1 = s2_replaced_way_en[1]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_2 = s2_replaced_way_en[2]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_3 = s2_replaced_way_en[3]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_4 = s2_replaced_way_en[4]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_5 = s2_replaced_way_en[5]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_6 = s2_replaced_way_en[6]; // @[OneHot.scala:58:35]
wire _s2_repl_meta_T_7 = s2_replaced_way_en[7]; // @[OneHot.scala:58:35]
wire [1:0] _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] s2_repl_meta_0_coh_state = _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73]
wire [19:0] s2_repl_meta_0_tag = _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_8 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_9 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_tag_0 : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_10 = _s2_repl_meta_T_2 ? _s2_repl_meta_WIRE_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_11 = _s2_repl_meta_T_3 ? _s2_repl_meta_WIRE_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_12 = _s2_repl_meta_T_4 ? _s2_repl_meta_WIRE_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_13 = _s2_repl_meta_T_5 ? _s2_repl_meta_WIRE_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_14 = _s2_repl_meta_T_6 ? _s2_repl_meta_WIRE_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_15 = _s2_repl_meta_T_7 ? _s2_repl_meta_WIRE_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _s2_repl_meta_T_16 = _s2_repl_meta_T_8 | _s2_repl_meta_T_9; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_17 = _s2_repl_meta_T_16 | _s2_repl_meta_T_10; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_18 = _s2_repl_meta_T_17 | _s2_repl_meta_T_11; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_19 = _s2_repl_meta_T_18 | _s2_repl_meta_T_12; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_20 = _s2_repl_meta_T_19 | _s2_repl_meta_T_13; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_21 = _s2_repl_meta_T_20 | _s2_repl_meta_T_14; // @[Mux.scala:30:73]
wire [19:0] _s2_repl_meta_T_22 = _s2_repl_meta_T_21 | _s2_repl_meta_T_15; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_2 = _s2_repl_meta_T_22; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_1_tag = _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_1_coh_state = _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_23 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_24 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_coh_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_25 = _s2_repl_meta_T_2 ? _s2_repl_meta_WIRE_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_26 = _s2_repl_meta_T_3 ? _s2_repl_meta_WIRE_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_27 = _s2_repl_meta_T_4 ? _s2_repl_meta_WIRE_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_28 = _s2_repl_meta_T_5 ? _s2_repl_meta_WIRE_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_29 = _s2_repl_meta_T_6 ? _s2_repl_meta_WIRE_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_30 = _s2_repl_meta_T_7 ? _s2_repl_meta_WIRE_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_repl_meta_T_31 = _s2_repl_meta_T_23 | _s2_repl_meta_T_24; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_32 = _s2_repl_meta_T_31 | _s2_repl_meta_T_25; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_33 = _s2_repl_meta_T_32 | _s2_repl_meta_T_26; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_34 = _s2_repl_meta_T_33 | _s2_repl_meta_T_27; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_35 = _s2_repl_meta_T_34 | _s2_repl_meta_T_28; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_36 = _s2_repl_meta_T_35 | _s2_repl_meta_T_29; // @[Mux.scala:30:73]
wire [1:0] _s2_repl_meta_T_37 = _s2_repl_meta_T_36 | _s2_repl_meta_T_30; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_4 = _s2_repl_meta_T_37; // @[Mux.scala:30:73]
assign _s2_repl_meta_WIRE_3_state = _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73]
wire [19:0] mshrs_io_req_0_bits_old_meta_meta_tag = s2_repl_meta_0_tag; // @[HellaCache.scala:305:20]
reg s2_nack_hit_0; // @[dcache.scala:722:31]
wire _GEN_16 = s2_valid_0 & s2_hit_0; // @[dcache.scala:427:49, :724:50]
wire _s2_nack_victim_T; // @[dcache.scala:724:50]
assign _s2_nack_victim_T = _GEN_16; // @[dcache.scala:724:50]
wire _s3_valid_T; // @[dcache.scala:871:38]
assign _s3_valid_T = _GEN_16; // @[dcache.scala:724:50, :871:38]
wire _s2_nack_victim_T_1 = _s2_nack_victim_T & _mshrs_io_secondary_miss_0; // @[dcache.scala:433:21, :724:{50,64}]
wire s2_nack_victim_0 = _s2_nack_victim_T_1; // @[dcache.scala:427:49, :724:64]
wire _s2_nack_miss_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :726:53]
wire _s2_nack_miss_T_1 = s2_valid_0 & _s2_nack_miss_T; // @[dcache.scala:427:49, :726:{50,53}]
wire _s2_nack_miss_T_2 = ~_mshrs_io_req_0_ready; // @[dcache.scala:433:21, :726:67]
wire _s2_nack_miss_T_3 = _s2_nack_miss_T_1 & _s2_nack_miss_T_2; // @[dcache.scala:726:{50,64,67}]
wire s2_nack_miss_0 = _s2_nack_miss_T_3; // @[dcache.scala:427:49, :726:64]
wire _s2_nack_wb_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :730:53]
wire _s2_nack_wb_T_1 = s2_valid_0 & _s2_nack_wb_T; // @[dcache.scala:427:49, :730:{50,53}]
wire _s2_nack_wb_T_2 = _s2_nack_wb_T_1 & s2_wb_idx_matches_0; // @[dcache.scala:654:34, :730:{50,64}]
wire s2_nack_wb_0 = _s2_nack_wb_T_2; // @[dcache.scala:427:49, :730:64]
assign s2_nack_0 = (s2_nack_miss_0 | s2_nack_hit_0 | s2_nack_victim_0 | s2_nack_wb_0) & (|s2_type); // @[dcache.scala:427:49, :633:25, :650:21, :722:31, :732:{55,73,113,131,142}]
reg s2_send_resp_REG; // @[dcache.scala:733:44]
wire _s2_send_resp_T = ~s2_nack_0; // @[dcache.scala:650:21, :668:60, :733:73]
wire _s2_send_resp_T_1 = s2_send_resp_REG & _s2_send_resp_T; // @[dcache.scala:733:{44,70,73}]
wire _mshrs_io_req_0_valid_T_74; // @[dcache.scala:754:77]
wire _T_73 = _mshrs_io_req_0_ready & _mshrs_io_req_0_valid_T_74; // @[Decoupled.scala:51:35]
assign replace = _T_73; // @[Decoupled.scala:51:35]
wire _s2_send_resp_T_2; // @[Decoupled.scala:51:35]
assign _s2_send_resp_T_2 = _T_73; // @[Decoupled.scala:51:35]
wire _s2_send_resp_T_5 = _s2_send_resp_T_3 | _s2_send_resp_T_4; // @[Consts.scala:90:{32,42,49}]
wire _s2_send_resp_T_7 = _s2_send_resp_T_5 | _s2_send_resp_T_6; // @[Consts.scala:90:{42,59,66}]
wire _s2_send_resp_T_12 = _s2_send_resp_T_8 | _s2_send_resp_T_9; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_13 = _s2_send_resp_T_12 | _s2_send_resp_T_10; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_14 = _s2_send_resp_T_13 | _s2_send_resp_T_11; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_20 = _s2_send_resp_T_15 | _s2_send_resp_T_16; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_21 = _s2_send_resp_T_20 | _s2_send_resp_T_17; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_22 = _s2_send_resp_T_21 | _s2_send_resp_T_18; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_23 = _s2_send_resp_T_22 | _s2_send_resp_T_19; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_24 = _s2_send_resp_T_14 | _s2_send_resp_T_23; // @[package.scala:81:59]
wire _s2_send_resp_T_25 = _s2_send_resp_T_7 | _s2_send_resp_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _s2_send_resp_T_26 = _s2_send_resp_T_2 & _s2_send_resp_T_25; // @[Decoupled.scala:51:35]
wire _GEN_17 = s2_req_0_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _s2_send_resp_T_27; // @[package.scala:16:47]
assign _s2_send_resp_T_27 = _GEN_17; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_24; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_24 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = s2_req_0_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _s2_send_resp_T_28; // @[package.scala:16:47]
assign _s2_send_resp_T_28 = _GEN_18; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_25; // @[package.scala:16:47]
assign _mshrs_io_req_0_valid_T_25 = _GEN_18; // @[package.scala:16:47]
wire _s2_send_resp_T_31 = _s2_send_resp_T_27 | _s2_send_resp_T_28; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_32 = _s2_send_resp_T_31 | _s2_send_resp_T_29; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_33 = _s2_send_resp_T_32 | _s2_send_resp_T_30; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_38 = _s2_send_resp_T_34 | _s2_send_resp_T_35; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_39 = _s2_send_resp_T_38 | _s2_send_resp_T_36; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_40 = _s2_send_resp_T_39 | _s2_send_resp_T_37; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_46 = _s2_send_resp_T_41 | _s2_send_resp_T_42; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_47 = _s2_send_resp_T_46 | _s2_send_resp_T_43; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_48 = _s2_send_resp_T_47 | _s2_send_resp_T_44; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_49 = _s2_send_resp_T_48 | _s2_send_resp_T_45; // @[package.scala:16:47, :81:59]
wire _s2_send_resp_T_50 = _s2_send_resp_T_40 | _s2_send_resp_T_49; // @[package.scala:81:59]
wire _s2_send_resp_T_51 = _s2_send_resp_T_33 | _s2_send_resp_T_50; // @[package.scala:81:59]
wire _s2_send_resp_T_52 = ~_s2_send_resp_T_51; // @[Consts.scala:89:68]
wire _s2_send_resp_T_53 = _s2_send_resp_T_26 & _s2_send_resp_T_52; // @[dcache.scala:734:{59,93,96}]
wire _s2_send_resp_T_54 = s2_hit_0 | _s2_send_resp_T_53; // @[dcache.scala:427:49, :734:{34,93}]
wire _s2_send_resp_T_55 = _s2_send_resp_T_1 & _s2_send_resp_T_54; // @[dcache.scala:733:{70,85}, :734:34]
wire s2_send_resp_0 = _s2_send_resp_T_55; // @[dcache.scala:427:49, :733:85]
reg s2_send_nack_REG; // @[dcache.scala:735:44]
wire _s2_send_nack_T = s2_send_nack_REG & s2_nack_0; // @[dcache.scala:650:21, :735:{44,70}]
wire s2_send_nack_0 = _s2_send_nack_T; // @[dcache.scala:427:49, :735:70]
wire _s2_store_failed_T = s2_valid_0 & s2_nack_0; // @[dcache.scala:427:49, :650:21, :742:34]
wire _s2_store_failed_T_1 = _s2_store_failed_T & s2_send_nack_0; // @[dcache.scala:427:49, :742:{34,48}]
assign _s2_store_failed_T_2 = _s2_store_failed_T_1 & s2_req_0_uop_uses_stq; // @[dcache.scala:632:25, :742:{48,67}]
assign s2_store_failed = _s2_store_failed_T_2; // @[dcache.scala:603:29, :742:67]
wire _mshrs_io_req_0_valid_T = ~s2_hit_0; // @[dcache.scala:427:49, :651:36, :747:29]
wire _mshrs_io_req_0_valid_T_1 = s2_valid_0 & _mshrs_io_req_0_valid_T; // @[dcache.scala:427:49, :746:51, :747:29]
wire _mshrs_io_req_0_valid_T_2 = ~s2_nack_hit_0; // @[dcache.scala:722:31, :748:29]
wire _mshrs_io_req_0_valid_T_3 = _mshrs_io_req_0_valid_T_1 & _mshrs_io_req_0_valid_T_2; // @[dcache.scala:746:51, :747:51, :748:29]
wire _mshrs_io_req_0_valid_T_4 = ~s2_nack_victim_0; // @[dcache.scala:427:49, :749:29]
wire _mshrs_io_req_0_valid_T_5 = _mshrs_io_req_0_valid_T_3 & _mshrs_io_req_0_valid_T_4; // @[dcache.scala:747:51, :748:51, :749:29]
wire _mshrs_io_req_0_valid_T_7 = _mshrs_io_req_0_valid_T_5; // @[dcache.scala:748:51, :749:51]
wire _mshrs_io_req_0_valid_T_8 = ~s2_nack_wb_0; // @[dcache.scala:427:49, :751:29]
wire _mshrs_io_req_0_valid_T_9 = _mshrs_io_req_0_valid_T_7 & _mshrs_io_req_0_valid_T_8; // @[dcache.scala:749:51, :750:51, :751:29]
wire _mshrs_io_req_0_valid_T_11 = s2_type == 3'h5; // @[package.scala:16:47]
wire _mshrs_io_req_0_valid_T_12 = _mshrs_io_req_0_valid_T_10 | _mshrs_io_req_0_valid_T_11; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_13 = _mshrs_io_req_0_valid_T_9 & _mshrs_io_req_0_valid_T_12; // @[package.scala:81:59]
wire [15:0] _GEN_19 = io_lsu_brupdate_b1_mispredict_mask_0 & s2_req_0_uop_br_mask; // @[util.scala:118:51]
wire [15:0] _mshrs_io_req_0_valid_T_14; // @[util.scala:118:51]
assign _mshrs_io_req_0_valid_T_14 = _GEN_19; // @[util.scala:118:51]
wire [15:0] _io_lsu_nack_0_valid_T_4; // @[util.scala:118:51]
assign _io_lsu_nack_0_valid_T_4 = _GEN_19; // @[util.scala:118:51]
wire _mshrs_io_req_0_valid_T_15 = |_mshrs_io_req_0_valid_T_14; // @[util.scala:118:{51,59}]
wire _mshrs_io_req_0_valid_T_16 = ~_mshrs_io_req_0_valid_T_15; // @[util.scala:118:59]
wire _mshrs_io_req_0_valid_T_17 = _mshrs_io_req_0_valid_T_13 & _mshrs_io_req_0_valid_T_16; // @[dcache.scala:751:51, :752:77, :753:29]
wire _GEN_20 = io_lsu_exception_0 & s2_req_0_uop_uses_ldq; // @[dcache.scala:413:7, :632:25, :754:48]
wire _mshrs_io_req_0_valid_T_18; // @[dcache.scala:754:48]
assign _mshrs_io_req_0_valid_T_18 = _GEN_20; // @[dcache.scala:754:48]
wire _io_lsu_nack_0_valid_T_1; // @[dcache.scala:863:48]
assign _io_lsu_nack_0_valid_T_1 = _GEN_20; // @[dcache.scala:754:48, :863:48]
wire _mshrs_io_req_0_valid_T_19 = ~_mshrs_io_req_0_valid_T_18; // @[dcache.scala:754:{29,48}]
wire _mshrs_io_req_0_valid_T_20 = _mshrs_io_req_0_valid_T_17 & _mshrs_io_req_0_valid_T_19; // @[dcache.scala:752:77, :753:79, :754:29]
wire _mshrs_io_req_0_valid_T_21 = s2_req_0_uop_mem_cmd == 5'h2; // @[Consts.scala:88:35]
wire _mshrs_io_req_0_valid_T_23 = _mshrs_io_req_0_valid_T_21 | _mshrs_io_req_0_valid_T_22; // @[Consts.scala:88:{35,45,52}]
wire _mshrs_io_req_0_valid_T_28 = _mshrs_io_req_0_valid_T_24 | _mshrs_io_req_0_valid_T_25; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_29 = _mshrs_io_req_0_valid_T_28 | _mshrs_io_req_0_valid_T_26; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_30 = _mshrs_io_req_0_valid_T_29 | _mshrs_io_req_0_valid_T_27; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_35 = _mshrs_io_req_0_valid_T_31 | _mshrs_io_req_0_valid_T_32; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_36 = _mshrs_io_req_0_valid_T_35 | _mshrs_io_req_0_valid_T_33; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_37 = _mshrs_io_req_0_valid_T_36 | _mshrs_io_req_0_valid_T_34; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_43 = _mshrs_io_req_0_valid_T_38 | _mshrs_io_req_0_valid_T_39; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_44 = _mshrs_io_req_0_valid_T_43 | _mshrs_io_req_0_valid_T_40; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_45 = _mshrs_io_req_0_valid_T_44 | _mshrs_io_req_0_valid_T_41; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_46 = _mshrs_io_req_0_valid_T_45 | _mshrs_io_req_0_valid_T_42; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_47 = _mshrs_io_req_0_valid_T_37 | _mshrs_io_req_0_valid_T_46; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_48 = _mshrs_io_req_0_valid_T_30 | _mshrs_io_req_0_valid_T_47; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_49 = _mshrs_io_req_0_valid_T_23 | _mshrs_io_req_0_valid_T_48; // @[Consts.scala:88:45, :89:68]
wire _mshrs_io_req_0_valid_T_52 = _mshrs_io_req_0_valid_T_50 | _mshrs_io_req_0_valid_T_51; // @[Consts.scala:90:{32,42,49}]
wire _mshrs_io_req_0_valid_T_54 = _mshrs_io_req_0_valid_T_52 | _mshrs_io_req_0_valid_T_53; // @[Consts.scala:90:{42,59,66}]
wire _mshrs_io_req_0_valid_T_59 = _mshrs_io_req_0_valid_T_55 | _mshrs_io_req_0_valid_T_56; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_60 = _mshrs_io_req_0_valid_T_59 | _mshrs_io_req_0_valid_T_57; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_61 = _mshrs_io_req_0_valid_T_60 | _mshrs_io_req_0_valid_T_58; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_67 = _mshrs_io_req_0_valid_T_62 | _mshrs_io_req_0_valid_T_63; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_68 = _mshrs_io_req_0_valid_T_67 | _mshrs_io_req_0_valid_T_64; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_69 = _mshrs_io_req_0_valid_T_68 | _mshrs_io_req_0_valid_T_65; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_70 = _mshrs_io_req_0_valid_T_69 | _mshrs_io_req_0_valid_T_66; // @[package.scala:16:47, :81:59]
wire _mshrs_io_req_0_valid_T_71 = _mshrs_io_req_0_valid_T_61 | _mshrs_io_req_0_valid_T_70; // @[package.scala:81:59]
wire _mshrs_io_req_0_valid_T_72 = _mshrs_io_req_0_valid_T_54 | _mshrs_io_req_0_valid_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _mshrs_io_req_0_valid_T_73 = _mshrs_io_req_0_valid_T_49 | _mshrs_io_req_0_valid_T_72; // @[Consts.scala:90:76]
assign _mshrs_io_req_0_valid_T_74 = _mshrs_io_req_0_valid_T_20 & _mshrs_io_req_0_valid_T_73; // @[dcache.scala:753:79, :754:77, :756:65]
wire [15:0] _mshrs_io_req_0_bits_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _mshrs_io_req_0_bits_uop_br_mask_T_1 = s2_req_0_uop_br_mask & _mshrs_io_req_0_bits_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire [1:0] _mshrs_io_req_0_bits_old_meta_T_coh_state = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_coh_state : s2_repl_meta_0_coh_state; // @[HellaCache.scala:305:20]
wire [19:0] _mshrs_io_req_0_bits_old_meta_T_tag = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_tag : s2_repl_meta_0_tag; // @[HellaCache.scala:305:20]
wire [7:0] _mshrs_io_req_0_bits_way_en_T = s2_tag_match_0 ? s2_tag_match_way_0 : s2_replaced_way_en; // @[OneHot.scala:58:35]
wire _mshrs_io_req_is_probe_0_T = s2_type == 3'h1; // @[dcache.scala:633:25, :769:49]
wire _mshrs_io_req_is_probe_0_T_1 = _mshrs_io_req_is_probe_0_T & s2_valid_0; // @[dcache.scala:427:49, :769:{49,61}]
wire _mshrs_io_meta_resp_valid_T = ~s2_nack_hit_0; // @[dcache.scala:722:31, :748:29, :772:36]
wire _mshrs_io_meta_resp_valid_T_1 = _mshrs_io_meta_resp_valid_T | _prober_io_mshr_wb_rdy; // @[dcache.scala:432:22, :772:{36,52}]
reg [1:0] mshrs_io_meta_resp_bits_REG_0_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_0_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_1_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_1_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_2_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_2_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_3_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_3_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_4_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_4_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_5_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_5_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_6_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_6_tag; // @[dcache.scala:773:70]
reg [1:0] mshrs_io_meta_resp_bits_REG_7_coh_state; // @[dcache.scala:773:70]
reg [19:0] mshrs_io_meta_resp_bits_REG_7_tag; // @[dcache.scala:773:70]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_8 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_9 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_10 = _mshrs_io_meta_resp_bits_T_2 ? mshrs_io_meta_resp_bits_REG_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_11 = _mshrs_io_meta_resp_bits_T_3 ? mshrs_io_meta_resp_bits_REG_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_12 = _mshrs_io_meta_resp_bits_T_4 ? mshrs_io_meta_resp_bits_REG_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_13 = _mshrs_io_meta_resp_bits_T_5 ? mshrs_io_meta_resp_bits_REG_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_14 = _mshrs_io_meta_resp_bits_T_6 ? mshrs_io_meta_resp_bits_REG_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_15 = _mshrs_io_meta_resp_bits_T_7 ? mshrs_io_meta_resp_bits_REG_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36]
wire [19:0] _mshrs_io_meta_resp_bits_T_16 = _mshrs_io_meta_resp_bits_T_8 | _mshrs_io_meta_resp_bits_T_9; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_17 = _mshrs_io_meta_resp_bits_T_16 | _mshrs_io_meta_resp_bits_T_10; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_18 = _mshrs_io_meta_resp_bits_T_17 | _mshrs_io_meta_resp_bits_T_11; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_19 = _mshrs_io_meta_resp_bits_T_18 | _mshrs_io_meta_resp_bits_T_12; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_20 = _mshrs_io_meta_resp_bits_T_19 | _mshrs_io_meta_resp_bits_T_13; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_21 = _mshrs_io_meta_resp_bits_T_20 | _mshrs_io_meta_resp_bits_T_14; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_T_22 = _mshrs_io_meta_resp_bits_T_21 | _mshrs_io_meta_resp_bits_T_15; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_1 = _mshrs_io_meta_resp_bits_T_22; // @[Mux.scala:30:73]
wire [19:0] _mshrs_io_meta_resp_bits_WIRE_tag = _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_WIRE_coh_state = _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_23 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_24 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_25 = _mshrs_io_meta_resp_bits_T_2 ? mshrs_io_meta_resp_bits_REG_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_26 = _mshrs_io_meta_resp_bits_T_3 ? mshrs_io_meta_resp_bits_REG_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_27 = _mshrs_io_meta_resp_bits_T_4 ? mshrs_io_meta_resp_bits_REG_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_28 = _mshrs_io_meta_resp_bits_T_5 ? mshrs_io_meta_resp_bits_REG_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_29 = _mshrs_io_meta_resp_bits_T_6 ? mshrs_io_meta_resp_bits_REG_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_30 = _mshrs_io_meta_resp_bits_T_7 ? mshrs_io_meta_resp_bits_REG_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _mshrs_io_meta_resp_bits_T_31 = _mshrs_io_meta_resp_bits_T_23 | _mshrs_io_meta_resp_bits_T_24; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_32 = _mshrs_io_meta_resp_bits_T_31 | _mshrs_io_meta_resp_bits_T_25; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_33 = _mshrs_io_meta_resp_bits_T_32 | _mshrs_io_meta_resp_bits_T_26; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_34 = _mshrs_io_meta_resp_bits_T_33 | _mshrs_io_meta_resp_bits_T_27; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_35 = _mshrs_io_meta_resp_bits_T_34 | _mshrs_io_meta_resp_bits_T_28; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_36 = _mshrs_io_meta_resp_bits_T_35 | _mshrs_io_meta_resp_bits_T_29; // @[Mux.scala:30:73]
wire [1:0] _mshrs_io_meta_resp_bits_T_37 = _mshrs_io_meta_resp_bits_T_36 | _mshrs_io_meta_resp_bits_T_30; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_3 = _mshrs_io_meta_resp_bits_T_37; // @[Mux.scala:30:73]
assign _mshrs_io_meta_resp_bits_WIRE_2_state = _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73]
wire _prober_io_req_valid_T = ~lrsc_valid; // @[dcache.scala:661:31, :778:46]
wire _prober_io_req_valid_T_1 = nodeOut_b_valid & _prober_io_req_valid_T; // @[MixedNode.scala:542:17]
wire _nodeOut_b_ready_T = ~lrsc_valid; // @[dcache.scala:661:31, :778:46, :779:51]
assign _nodeOut_b_ready_T_1 = _prober_io_req_ready & _nodeOut_b_ready_T; // @[dcache.scala:432:22, :779:{48,51}]
assign nodeOut_b_ready = _nodeOut_b_ready_T_1; // @[MixedNode.scala:542:17]
wire _prober_io_wb_rdy_T = _prober_io_meta_write_bits_idx != _wb_io_idx_bits; // @[dcache.scala:431:18, :432:22, :785:59]
wire _prober_io_wb_rdy_T_1 = ~_wb_io_idx_valid; // @[dcache.scala:431:18, :785:82]
wire _prober_io_wb_rdy_T_2 = _prober_io_wb_rdy_T | _prober_io_wb_rdy_T_1; // @[dcache.scala:785:{59,79,82}]
wire _wb_io_mem_grant_T_1 = nodeOut_d_bits_source == 3'h4; // @[MixedNode.scala:542:17]
assign nodeOut_d_ready = _wb_io_mem_grant_T_1 | _mshrs_io_mem_grant_ready; // @[MixedNode.scala:542:17]
wire _wb_io_mem_grant_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _wb_io_mem_grant_T_2 = _wb_io_mem_grant_T & _wb_io_mem_grant_T_1; // @[Decoupled.scala:51:35]
wire opdata = _wb_io_release_bits_opcode[0]; // @[Edges.scala:102:36]
wire [26:0] _decode_T_3 = 27'hFFF << _prober_io_rep_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_4 = _decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] decode_1 = _decode_T_5[11:4]; // @[package.scala:243:46]
reg [7:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_c_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {_prober_io_rep_valid, _wb_io_release_valid}; // @[Arbiter.scala:68:51]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & _wb_io_release_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & _prober_io_rep_valid; // @[Arbiter.scala:68:27, :71:69]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_c_valid_T = _wb_io_release_valid | _prober_io_rep_valid; // @[Arbiter.scala:79:31, :96:46]
wire [7:0] maskedBeats_0 = winner_0 & opdata ? 8'h3 : 8'h0; // @[Edges.scala:102:36, :221:14]
wire [7:0] initBeats = maskedBeats_0; // @[Arbiter.scala:82:69, :84:44]
wire _GEN_21 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35]
wire _beatsLeft_T; // @[Decoupled.scala:51:35]
assign _beatsLeft_T = _GEN_21; // @[Decoupled.scala:51:35]
wire _io_lsu_perf_release_T; // @[Decoupled.scala:51:35]
assign _io_lsu_perf_release_T = _GEN_21; // @[Decoupled.scala:51:35]
wire [8:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {8'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35]
wire [7:0] _beatsLeft_T_2 = _beatsLeft_T_1[7:0]; // @[Arbiter.scala:85:52]
wire [7:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25]
wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24]
wire _wb_io_release_ready_T = nodeOut_c_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31]
wire _prober_io_rep_ready_T = nodeOut_c_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31]
wire _nodeOut_c_valid_T_1 = state_0 & _wb_io_release_valid; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_T_2 = state_1 & _prober_io_rep_valid; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_T_3 = _nodeOut_c_valid_T_1 | _nodeOut_c_valid_T_2; // @[Mux.scala:30:73]
wire _nodeOut_c_valid_WIRE = _nodeOut_c_valid_T_3; // @[Mux.scala:30:73]
assign _nodeOut_c_valid_T_4 = idle ? _nodeOut_c_valid_T : _nodeOut_c_valid_WIRE; // @[Mux.scala:30:73]
assign nodeOut_c_valid = _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24]
wire [2:0] _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73]
assign nodeOut_c_bits_opcode = _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73]
assign nodeOut_c_bits_param = _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73]
assign nodeOut_c_bits_size = _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73]
assign nodeOut_c_bits_source = _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73]
assign nodeOut_c_bits_address = _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73]
wire [127:0] _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73]
assign nodeOut_c_bits_data = _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73]
wire [127:0] _nodeOut_c_bits_T_3 = muxState_0 ? _wb_io_release_bits_data : 128'h0; // @[Mux.scala:30:73]
wire [127:0] _nodeOut_c_bits_T_5 = _nodeOut_c_bits_T_3; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_2 = _nodeOut_c_bits_T_5; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_data = _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_6 = muxState_0 ? _wb_io_release_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_7 = muxState_1 ? _prober_io_rep_bits_address : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _nodeOut_c_bits_T_8 = _nodeOut_c_bits_T_6 | _nodeOut_c_bits_T_7; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_5 = _nodeOut_c_bits_T_8; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_address = _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_9 = {muxState_0, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_10 = muxState_1 ? _prober_io_rep_bits_source : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_11 = _nodeOut_c_bits_T_9 | _nodeOut_c_bits_T_10; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_6 = _nodeOut_c_bits_T_11; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_source = _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_12 = muxState_0 ? 4'h6 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_13 = muxState_1 ? _prober_io_rep_bits_size : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _nodeOut_c_bits_T_14 = _nodeOut_c_bits_T_12 | _nodeOut_c_bits_T_13; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_7 = _nodeOut_c_bits_T_14; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_size = _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_15 = muxState_0 ? _wb_io_release_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_16 = muxState_1 ? _prober_io_rep_bits_param : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_17 = _nodeOut_c_bits_T_15 | _nodeOut_c_bits_T_16; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_8 = _nodeOut_c_bits_T_17; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_param = _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_18 = muxState_0 ? _wb_io_release_bits_opcode : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_19 = {muxState_1, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_c_bits_T_20 = _nodeOut_c_bits_T_18 | _nodeOut_c_bits_T_19; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_9 = _nodeOut_c_bits_T_20; // @[Mux.scala:30:73]
assign _nodeOut_c_bits_WIRE_opcode = _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73]
wire [26:0] _io_lsu_perf_release_beats1_decode_T = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71]
wire [11:0] _io_lsu_perf_release_beats1_decode_T_1 = _io_lsu_perf_release_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_lsu_perf_release_beats1_decode_T_2 = ~_io_lsu_perf_release_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] io_lsu_perf_release_beats1_decode = _io_lsu_perf_release_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire io_lsu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36]
wire [7:0] io_lsu_perf_release_beats1 = io_lsu_perf_release_beats1_opdata ? io_lsu_perf_release_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [7:0] io_lsu_perf_release_counter; // @[Edges.scala:229:27]
wire [8:0] _io_lsu_perf_release_counter1_T = {1'h0, io_lsu_perf_release_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] io_lsu_perf_release_counter1 = _io_lsu_perf_release_counter1_T[7:0]; // @[Edges.scala:230:28]
wire io_lsu_perf_release_first = io_lsu_perf_release_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _io_lsu_perf_release_last_T = io_lsu_perf_release_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _io_lsu_perf_release_last_T_1 = io_lsu_perf_release_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire io_lsu_perf_release_last = _io_lsu_perf_release_last_T | _io_lsu_perf_release_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_lsu_perf_release_done = io_lsu_perf_release_last & _io_lsu_perf_release_T; // @[Decoupled.scala:51:35]
assign io_lsu_perf_release_0 = io_lsu_perf_release_done; // @[Edges.scala:233:22]
wire [7:0] _io_lsu_perf_release_count_T = ~io_lsu_perf_release_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] io_lsu_perf_release_count = io_lsu_perf_release_beats1 & _io_lsu_perf_release_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _io_lsu_perf_release_counter_T = io_lsu_perf_release_first ? io_lsu_perf_release_beats1 : io_lsu_perf_release_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _io_lsu_perf_acquire_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] _io_lsu_perf_acquire_beats1_decode_T = 27'hFFF << nodeOut_a_bits_size; // @[package.scala:243:71]
wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_1 = _io_lsu_perf_acquire_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_2 = ~_io_lsu_perf_acquire_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] io_lsu_perf_acquire_beats1_decode = _io_lsu_perf_acquire_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _io_lsu_perf_acquire_beats1_opdata_T = nodeOut_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire io_lsu_perf_acquire_beats1_opdata = ~_io_lsu_perf_acquire_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] io_lsu_perf_acquire_beats1 = io_lsu_perf_acquire_beats1_opdata ? io_lsu_perf_acquire_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] io_lsu_perf_acquire_counter; // @[Edges.scala:229:27]
wire [8:0] _io_lsu_perf_acquire_counter1_T = {1'h0, io_lsu_perf_acquire_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] io_lsu_perf_acquire_counter1 = _io_lsu_perf_acquire_counter1_T[7:0]; // @[Edges.scala:230:28]
wire io_lsu_perf_acquire_first = io_lsu_perf_acquire_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _io_lsu_perf_acquire_last_T = io_lsu_perf_acquire_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _io_lsu_perf_acquire_last_T_1 = io_lsu_perf_acquire_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire io_lsu_perf_acquire_last = _io_lsu_perf_acquire_last_T | _io_lsu_perf_acquire_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_lsu_perf_acquire_done = io_lsu_perf_acquire_last & _io_lsu_perf_acquire_T; // @[Decoupled.scala:51:35]
assign io_lsu_perf_acquire_0 = io_lsu_perf_acquire_done; // @[Edges.scala:233:22]
wire [7:0] _io_lsu_perf_acquire_count_T = ~io_lsu_perf_acquire_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] io_lsu_perf_acquire_count = io_lsu_perf_acquire_beats1 & _io_lsu_perf_acquire_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _io_lsu_perf_acquire_counter_T = io_lsu_perf_acquire_first ? io_lsu_perf_acquire_beats1 : io_lsu_perf_acquire_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [6:0] _s2_data_word_prebypass_T = {s2_word_idx_0, 6'h0}; // @[dcache.scala:427:49, :825:69]
wire [127:0] _s2_data_word_prebypass_T_1 = s2_data_muxed_0 >> _s2_data_word_prebypass_T; // @[dcache.scala:427:49, :825:{63,69}]
wire [127:0] s2_data_word_prebypass_0 = _s2_data_word_prebypass_T_1; // @[dcache.scala:427:49, :825:63]
wire [127:0] _s2_data_word_0_T_2; // @[dcache.scala:891:27]
wire [127:0] s2_data_word_0; // @[dcache.scala:826:26]
wire [127:0] size_dat_padded = s2_data_word_0; // @[AMOALU.scala:13:27]
wire _cache_resp_0_valid_T; // @[dcache.scala:835:48]
wire [63:0] _cache_resp_0_bits_data_T_24; // @[dcache.scala:837:52]
wire [63:0] cache_resp_0_bits_data; // @[dcache.scala:833:26]
wire cache_resp_0_valid; // @[dcache.scala:833:26]
assign _cache_resp_0_valid_T = s2_valid_0 & s2_send_resp_0; // @[dcache.scala:427:49, :835:48]
assign cache_resp_0_valid = _cache_resp_0_valid_T; // @[dcache.scala:833:26, :835:48]
wire _cache_resp_0_bits_data_shifted_T = s2_req_0_addr[2]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T_8 = s2_req_0_addr[2]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T_2 = s2_req_0_addr[2]; // @[AMOALU.scala:21:27, :42:29]
wire [31:0] _cache_resp_0_bits_data_shifted_T_1 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _cache_resp_0_bits_data_T_5 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _cache_resp_0_bits_data_shifted_T_2 = s2_data_word_0[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] cache_resp_0_bits_data_shifted = _cache_resp_0_bits_data_shifted_T ? _cache_resp_0_bits_data_shifted_T_1 : _cache_resp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] cache_resp_0_bits_data_zeroed = cache_resp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _cache_resp_0_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_1 = _cache_resp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _cache_resp_0_bits_data_T_2 = cache_resp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_3 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _cache_resp_0_bits_data_T_4 = {32{_cache_resp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _cache_resp_0_bits_data_T_6 = _cache_resp_0_bits_data_T_1 ? _cache_resp_0_bits_data_T_4 : _cache_resp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_7 = {_cache_resp_0_bits_data_T_6, cache_resp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _cache_resp_0_bits_data_shifted_T_3 = s2_req_0_addr[1]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T_4 = s2_req_0_addr[1]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T_1 = s2_req_0_addr[1]; // @[AMOALU.scala:21:27, :42:29]
wire [15:0] _cache_resp_0_bits_data_shifted_T_4 = _cache_resp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _cache_resp_0_bits_data_shifted_T_5 = _cache_resp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] cache_resp_0_bits_data_shifted_1 = _cache_resp_0_bits_data_shifted_T_3 ? _cache_resp_0_bits_data_shifted_T_4 : _cache_resp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] cache_resp_0_bits_data_zeroed_1 = cache_resp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _cache_resp_0_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_9 = _cache_resp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _cache_resp_0_bits_data_T_10 = cache_resp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_11 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _cache_resp_0_bits_data_T_12 = {48{_cache_resp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _cache_resp_0_bits_data_T_13 = _cache_resp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _cache_resp_0_bits_data_T_14 = _cache_resp_0_bits_data_T_9 ? _cache_resp_0_bits_data_T_12 : _cache_resp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_15 = {_cache_resp_0_bits_data_T_14, cache_resp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _cache_resp_0_bits_data_shifted_T_6 = s2_req_0_addr[0]; // @[AMOALU.scala:42:29]
wire _amoalu_io_mask_upper_T = s2_req_0_addr[0]; // @[AMOALU.scala:20:27, :42:29]
wire _amoalu_io_mask_lower_T = s2_req_0_addr[0]; // @[AMOALU.scala:21:27, :42:29]
wire [7:0] _cache_resp_0_bits_data_shifted_T_7 = _cache_resp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _cache_resp_0_bits_data_shifted_T_8 = _cache_resp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] cache_resp_0_bits_data_shifted_2 = _cache_resp_0_bits_data_shifted_T_6 ? _cache_resp_0_bits_data_shifted_T_7 : _cache_resp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] cache_resp_0_bits_data_zeroed_2 = cache_resp_0_bits_data_doZero_2 ? 8'h0 : cache_resp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :43:31, :44:23]
wire _cache_resp_0_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _cache_resp_0_bits_data_T_17 = _cache_resp_0_bits_data_T_16 | cache_resp_0_bits_data_doZero_2; // @[AMOALU.scala:43:31, :45:{26,34}]
wire _cache_resp_0_bits_data_T_18 = cache_resp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _cache_resp_0_bits_data_T_19 = s2_req_0_uop_mem_signed & _cache_resp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _cache_resp_0_bits_data_T_20 = {56{_cache_resp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _cache_resp_0_bits_data_T_21 = _cache_resp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _cache_resp_0_bits_data_T_22 = _cache_resp_0_bits_data_T_17 ? _cache_resp_0_bits_data_T_20 : _cache_resp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _cache_resp_0_bits_data_T_23 = {_cache_resp_0_bits_data_T_22, cache_resp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign _cache_resp_0_bits_data_T_24 = {_cache_resp_0_bits_data_T_23[63:1], _cache_resp_0_bits_data_T_23[0] | s2_sc_fail}; // @[AMOALU.scala:45:16]
assign cache_resp_0_bits_data = _cache_resp_0_bits_data_T_24; // @[dcache.scala:833:26, :837:52]
wire [3:0] uncache_resp_bits_uop_ctrl_br_type; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_ctrl_op1_sel; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_op2_sel; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_imm_sel; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_ctrl_op_fcn; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_fcn_dw; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_ctrl_csr_cmd; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_load; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_sta; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ctrl_is_std; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_uopc; // @[dcache.scala:841:26]
wire [31:0] uncache_resp_bits_uop_inst; // @[dcache.scala:841:26]
wire [31:0] uncache_resp_bits_uop_debug_inst; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_rvc; // @[dcache.scala:841:26]
wire [39:0] uncache_resp_bits_uop_debug_pc; // @[dcache.scala:841:26]
wire [2:0] uncache_resp_bits_uop_iq_type; // @[dcache.scala:841:26]
wire [9:0] uncache_resp_bits_uop_fu_code; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_iw_state; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_iw_p1_poisoned; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_iw_p2_poisoned; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_br; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_jalr; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_jal; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_sfb; // @[dcache.scala:841:26]
wire [15:0] uncache_resp_bits_uop_br_mask; // @[dcache.scala:841:26]
wire [3:0] uncache_resp_bits_uop_br_tag; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_ftq_idx; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_edge_inst; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_pc_lob; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_taken; // @[dcache.scala:841:26]
wire [19:0] uncache_resp_bits_uop_imm_packed; // @[dcache.scala:841:26]
wire [11:0] uncache_resp_bits_uop_csr_addr; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_rob_idx; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_ldq_idx; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_stq_idx; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_rxq_idx; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_pdst; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_prs1; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_prs2; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_prs3; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_ppred; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs1_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs2_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_prs3_busy; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ppred_busy; // @[dcache.scala:841:26]
wire [6:0] uncache_resp_bits_uop_stale_pdst; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_exception; // @[dcache.scala:841:26]
wire [63:0] uncache_resp_bits_uop_exc_cause; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bypassable; // @[dcache.scala:841:26]
wire [4:0] uncache_resp_bits_uop_mem_cmd; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_mem_size; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_mem_signed; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_fence; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_fencei; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_amo; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_uses_ldq; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_uses_stq; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_sys_pc2epc; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_is_unique; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_flush_on_commit; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ldst_is_rs1; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_ldst; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs1; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs2; // @[dcache.scala:841:26]
wire [5:0] uncache_resp_bits_uop_lrs3; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_ldst_val; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_dst_rtype; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_lrs1_rtype; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_lrs2_rtype; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_frs3_en; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_fp_val; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_fp_single; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_pf_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_ae_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_xcpt_ma_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bp_debug_if; // @[dcache.scala:841:26]
wire uncache_resp_bits_uop_bp_xcpt_if; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_debug_fsrc; // @[dcache.scala:841:26]
wire [1:0] uncache_resp_bits_uop_debug_tsrc; // @[dcache.scala:841:26]
wire [63:0] uncache_resp_bits_data; // @[dcache.scala:841:26]
wire uncache_resp_bits_is_hella; // @[dcache.scala:841:26]
wire uncache_resp_valid; // @[dcache.scala:841:26]
wire _mshrs_io_resp_ready_T = ~cache_resp_0_valid; // @[dcache.scala:833:26, :844:26]
assign io_lsu_resp_0_bits_out_uop_uopc = resp_0_bits_uop_uopc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_inst = resp_0_bits_uop_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_inst = resp_0_bits_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_rvc = resp_0_bits_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_pc = resp_0_bits_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iq_type = resp_0_bits_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fu_code = resp_0_bits_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_br_type = resp_0_bits_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op1_sel = resp_0_bits_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op2_sel = resp_0_bits_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_imm_sel = resp_0_bits_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_op_fcn = resp_0_bits_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw = resp_0_bits_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd = resp_0_bits_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_load = resp_0_bits_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_sta = resp_0_bits_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ctrl_is_std = resp_0_bits_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_state = resp_0_bits_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_p1_poisoned = resp_0_bits_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_iw_p2_poisoned = resp_0_bits_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_br = resp_0_bits_uop_is_br; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_jalr = resp_0_bits_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_jal = resp_0_bits_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_sfb = resp_0_bits_uop_is_sfb; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_br_tag = resp_0_bits_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ftq_idx = resp_0_bits_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_edge_inst = resp_0_bits_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_pc_lob = resp_0_bits_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_taken = resp_0_bits_uop_taken; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_imm_packed = resp_0_bits_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_csr_addr = resp_0_bits_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_rob_idx = resp_0_bits_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldq_idx = resp_0_bits_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_stq_idx = resp_0_bits_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_rxq_idx = resp_0_bits_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_pdst = resp_0_bits_uop_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs1 = resp_0_bits_uop_prs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs2 = resp_0_bits_uop_prs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs3 = resp_0_bits_uop_prs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ppred = resp_0_bits_uop_ppred; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs1_busy = resp_0_bits_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs2_busy = resp_0_bits_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_prs3_busy = resp_0_bits_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ppred_busy = resp_0_bits_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_stale_pdst = resp_0_bits_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_exception = resp_0_bits_uop_exception; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_exc_cause = resp_0_bits_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bypassable = resp_0_bits_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_cmd = resp_0_bits_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_size = resp_0_bits_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_mem_signed = resp_0_bits_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_fence = resp_0_bits_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_fencei = resp_0_bits_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_amo = resp_0_bits_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_uses_ldq = resp_0_bits_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_uses_stq = resp_0_bits_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_sys_pc2epc = resp_0_bits_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_is_unique = resp_0_bits_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_flush_on_commit = resp_0_bits_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst_is_rs1 = resp_0_bits_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst = resp_0_bits_uop_ldst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs1 = resp_0_bits_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs2 = resp_0_bits_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs3 = resp_0_bits_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_ldst_val = resp_0_bits_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_dst_rtype = resp_0_bits_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs1_rtype = resp_0_bits_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_lrs2_rtype = resp_0_bits_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_frs3_en = resp_0_bits_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fp_val = resp_0_bits_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_fp_single = resp_0_bits_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_pf_if = resp_0_bits_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_ae_if = resp_0_bits_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_xcpt_ma_if = resp_0_bits_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bp_debug_if = resp_0_bits_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_bp_xcpt_if = resp_0_bits_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_fsrc = resp_0_bits_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_uop_debug_tsrc = resp_0_bits_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_data = resp_0_bits_data; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_out_is_hella = resp_0_bits_is_hella; // @[util.scala:101:23]
wire [15:0] resp_0_bits_uop_br_mask; // @[dcache.scala:846:22]
wire resp_0_valid; // @[dcache.scala:846:22]
wire _uncache_respond_T = ~cache_resp_0_valid; // @[dcache.scala:833:26, :844:26, :849:27]
wire uncache_respond = _uncache_respond_T; // @[dcache.scala:849:{27,48}]
assign resp_0_valid = uncache_respond ? uncache_resp_valid : cache_resp_0_valid; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uopc = uncache_respond ? uncache_resp_bits_uop_uopc : cache_resp_0_bits_uop_uopc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_inst = uncache_respond ? uncache_resp_bits_uop_inst : cache_resp_0_bits_uop_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_inst = uncache_respond ? uncache_resp_bits_uop_debug_inst : cache_resp_0_bits_uop_debug_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_rvc = uncache_respond ? uncache_resp_bits_uop_is_rvc : cache_resp_0_bits_uop_is_rvc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_pc = uncache_respond ? uncache_resp_bits_uop_debug_pc : cache_resp_0_bits_uop_debug_pc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iq_type = uncache_respond ? uncache_resp_bits_uop_iq_type : cache_resp_0_bits_uop_iq_type; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fu_code = uncache_respond ? uncache_resp_bits_uop_fu_code : cache_resp_0_bits_uop_fu_code; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_br_type = uncache_respond ? uncache_resp_bits_uop_ctrl_br_type : cache_resp_0_bits_uop_ctrl_br_type; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op1_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_op1_sel : cache_resp_0_bits_uop_ctrl_op1_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op2_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_op2_sel : cache_resp_0_bits_uop_ctrl_op2_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_imm_sel = uncache_respond ? uncache_resp_bits_uop_ctrl_imm_sel : cache_resp_0_bits_uop_ctrl_imm_sel; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_op_fcn = uncache_respond ? uncache_resp_bits_uop_ctrl_op_fcn : cache_resp_0_bits_uop_ctrl_op_fcn; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_fcn_dw = uncache_respond ? uncache_resp_bits_uop_ctrl_fcn_dw : cache_resp_0_bits_uop_ctrl_fcn_dw; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_csr_cmd = uncache_respond ? uncache_resp_bits_uop_ctrl_csr_cmd : cache_resp_0_bits_uop_ctrl_csr_cmd; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_load = uncache_respond ? uncache_resp_bits_uop_ctrl_is_load : cache_resp_0_bits_uop_ctrl_is_load; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_sta = uncache_respond ? uncache_resp_bits_uop_ctrl_is_sta : cache_resp_0_bits_uop_ctrl_is_sta; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ctrl_is_std = uncache_respond ? uncache_resp_bits_uop_ctrl_is_std : cache_resp_0_bits_uop_ctrl_is_std; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_state = uncache_respond ? uncache_resp_bits_uop_iw_state : cache_resp_0_bits_uop_iw_state; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_p1_poisoned = uncache_respond ? uncache_resp_bits_uop_iw_p1_poisoned : cache_resp_0_bits_uop_iw_p1_poisoned; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_iw_p2_poisoned = uncache_respond ? uncache_resp_bits_uop_iw_p2_poisoned : cache_resp_0_bits_uop_iw_p2_poisoned; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_br = uncache_respond ? uncache_resp_bits_uop_is_br : cache_resp_0_bits_uop_is_br; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_jalr = uncache_respond ? uncache_resp_bits_uop_is_jalr : cache_resp_0_bits_uop_is_jalr; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_jal = uncache_respond ? uncache_resp_bits_uop_is_jal : cache_resp_0_bits_uop_is_jal; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_sfb = uncache_respond ? uncache_resp_bits_uop_is_sfb : cache_resp_0_bits_uop_is_sfb; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_br_mask = uncache_respond ? uncache_resp_bits_uop_br_mask : cache_resp_0_bits_uop_br_mask; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_br_tag = uncache_respond ? uncache_resp_bits_uop_br_tag : cache_resp_0_bits_uop_br_tag; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ftq_idx = uncache_respond ? uncache_resp_bits_uop_ftq_idx : cache_resp_0_bits_uop_ftq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_edge_inst = uncache_respond ? uncache_resp_bits_uop_edge_inst : cache_resp_0_bits_uop_edge_inst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_pc_lob = uncache_respond ? uncache_resp_bits_uop_pc_lob : cache_resp_0_bits_uop_pc_lob; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_taken = uncache_respond ? uncache_resp_bits_uop_taken : cache_resp_0_bits_uop_taken; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_imm_packed = uncache_respond ? uncache_resp_bits_uop_imm_packed : cache_resp_0_bits_uop_imm_packed; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_csr_addr = uncache_respond ? uncache_resp_bits_uop_csr_addr : cache_resp_0_bits_uop_csr_addr; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_rob_idx = uncache_respond ? uncache_resp_bits_uop_rob_idx : cache_resp_0_bits_uop_rob_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldq_idx = uncache_respond ? uncache_resp_bits_uop_ldq_idx : cache_resp_0_bits_uop_ldq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_stq_idx = uncache_respond ? uncache_resp_bits_uop_stq_idx : cache_resp_0_bits_uop_stq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_rxq_idx = uncache_respond ? uncache_resp_bits_uop_rxq_idx : cache_resp_0_bits_uop_rxq_idx; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_pdst = uncache_respond ? uncache_resp_bits_uop_pdst : cache_resp_0_bits_uop_pdst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs1 = uncache_respond ? uncache_resp_bits_uop_prs1 : cache_resp_0_bits_uop_prs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs2 = uncache_respond ? uncache_resp_bits_uop_prs2 : cache_resp_0_bits_uop_prs2; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs3 = uncache_respond ? uncache_resp_bits_uop_prs3 : cache_resp_0_bits_uop_prs3; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ppred = uncache_respond ? uncache_resp_bits_uop_ppred : cache_resp_0_bits_uop_ppred; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs1_busy = uncache_respond ? uncache_resp_bits_uop_prs1_busy : cache_resp_0_bits_uop_prs1_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs2_busy = uncache_respond ? uncache_resp_bits_uop_prs2_busy : cache_resp_0_bits_uop_prs2_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_prs3_busy = uncache_respond ? uncache_resp_bits_uop_prs3_busy : cache_resp_0_bits_uop_prs3_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ppred_busy = uncache_respond ? uncache_resp_bits_uop_ppred_busy : cache_resp_0_bits_uop_ppred_busy; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_stale_pdst = uncache_respond ? uncache_resp_bits_uop_stale_pdst : cache_resp_0_bits_uop_stale_pdst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_exception = uncache_respond ? uncache_resp_bits_uop_exception : cache_resp_0_bits_uop_exception; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_exc_cause = uncache_respond ? uncache_resp_bits_uop_exc_cause : cache_resp_0_bits_uop_exc_cause; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bypassable = uncache_respond ? uncache_resp_bits_uop_bypassable : cache_resp_0_bits_uop_bypassable; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_cmd = uncache_respond ? uncache_resp_bits_uop_mem_cmd : cache_resp_0_bits_uop_mem_cmd; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_size = uncache_respond ? uncache_resp_bits_uop_mem_size : cache_resp_0_bits_uop_mem_size; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_mem_signed = uncache_respond ? uncache_resp_bits_uop_mem_signed : cache_resp_0_bits_uop_mem_signed; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_fence = uncache_respond ? uncache_resp_bits_uop_is_fence : cache_resp_0_bits_uop_is_fence; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_fencei = uncache_respond ? uncache_resp_bits_uop_is_fencei : cache_resp_0_bits_uop_is_fencei; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_amo = uncache_respond ? uncache_resp_bits_uop_is_amo : cache_resp_0_bits_uop_is_amo; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uses_ldq = uncache_respond ? uncache_resp_bits_uop_uses_ldq : cache_resp_0_bits_uop_uses_ldq; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_uses_stq = uncache_respond ? uncache_resp_bits_uop_uses_stq : cache_resp_0_bits_uop_uses_stq; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_sys_pc2epc = uncache_respond ? uncache_resp_bits_uop_is_sys_pc2epc : cache_resp_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_is_unique = uncache_respond ? uncache_resp_bits_uop_is_unique : cache_resp_0_bits_uop_is_unique; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_flush_on_commit = uncache_respond ? uncache_resp_bits_uop_flush_on_commit : cache_resp_0_bits_uop_flush_on_commit; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst_is_rs1 = uncache_respond ? uncache_resp_bits_uop_ldst_is_rs1 : cache_resp_0_bits_uop_ldst_is_rs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst = uncache_respond ? uncache_resp_bits_uop_ldst : cache_resp_0_bits_uop_ldst; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs1 = uncache_respond ? uncache_resp_bits_uop_lrs1 : cache_resp_0_bits_uop_lrs1; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs2 = uncache_respond ? uncache_resp_bits_uop_lrs2 : cache_resp_0_bits_uop_lrs2; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs3 = uncache_respond ? uncache_resp_bits_uop_lrs3 : cache_resp_0_bits_uop_lrs3; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_ldst_val = uncache_respond ? uncache_resp_bits_uop_ldst_val : cache_resp_0_bits_uop_ldst_val; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_dst_rtype = uncache_respond ? uncache_resp_bits_uop_dst_rtype : cache_resp_0_bits_uop_dst_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs1_rtype = uncache_respond ? uncache_resp_bits_uop_lrs1_rtype : cache_resp_0_bits_uop_lrs1_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_lrs2_rtype = uncache_respond ? uncache_resp_bits_uop_lrs2_rtype : cache_resp_0_bits_uop_lrs2_rtype; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_frs3_en = uncache_respond ? uncache_resp_bits_uop_frs3_en : cache_resp_0_bits_uop_frs3_en; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fp_val = uncache_respond ? uncache_resp_bits_uop_fp_val : cache_resp_0_bits_uop_fp_val; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_fp_single = uncache_respond ? uncache_resp_bits_uop_fp_single : cache_resp_0_bits_uop_fp_single; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_pf_if = uncache_respond ? uncache_resp_bits_uop_xcpt_pf_if : cache_resp_0_bits_uop_xcpt_pf_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_ae_if = uncache_respond ? uncache_resp_bits_uop_xcpt_ae_if : cache_resp_0_bits_uop_xcpt_ae_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_xcpt_ma_if = uncache_respond ? uncache_resp_bits_uop_xcpt_ma_if : cache_resp_0_bits_uop_xcpt_ma_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bp_debug_if = uncache_respond ? uncache_resp_bits_uop_bp_debug_if : cache_resp_0_bits_uop_bp_debug_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_bp_xcpt_if = uncache_respond ? uncache_resp_bits_uop_bp_xcpt_if : cache_resp_0_bits_uop_bp_xcpt_if; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_fsrc = uncache_respond ? uncache_resp_bits_uop_debug_fsrc : cache_resp_0_bits_uop_debug_fsrc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_uop_debug_tsrc = uncache_respond ? uncache_resp_bits_uop_debug_tsrc : cache_resp_0_bits_uop_debug_tsrc; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_data = uncache_respond ? uncache_resp_bits_data : cache_resp_0_bits_data; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
assign resp_0_bits_is_hella = uncache_respond ? uncache_resp_bits_is_hella : cache_resp_0_bits_is_hella; // @[dcache.scala:833:26, :841:26, :846:22, :849:48, :850:28, :851:15]
wire _io_lsu_resp_0_valid_T = io_lsu_exception_0 & resp_0_bits_uop_uses_ldq; // @[dcache.scala:413:7, :846:22, :858:48]
wire _io_lsu_resp_0_valid_T_1 = ~_io_lsu_resp_0_valid_T; // @[dcache.scala:858:{29,48}]
wire _io_lsu_resp_0_valid_T_2 = resp_0_valid & _io_lsu_resp_0_valid_T_1; // @[dcache.scala:846:22, :857:43, :858:29]
wire [15:0] _io_lsu_resp_0_valid_T_3 = io_lsu_brupdate_b1_mispredict_mask_0 & resp_0_bits_uop_br_mask; // @[util.scala:118:51]
wire _io_lsu_resp_0_valid_T_4 = |_io_lsu_resp_0_valid_T_3; // @[util.scala:118:{51,59}]
wire _io_lsu_resp_0_valid_T_5 = ~_io_lsu_resp_0_valid_T_4; // @[util.scala:118:59]
assign _io_lsu_resp_0_valid_T_6 = _io_lsu_resp_0_valid_T_2 & _io_lsu_resp_0_valid_T_5; // @[dcache.scala:857:43, :858:78, :859:29]
assign io_lsu_resp_0_valid_0 = _io_lsu_resp_0_valid_T_6; // @[dcache.scala:413:7, :858:78]
assign io_lsu_resp_0_bits_uop_uopc_0 = io_lsu_resp_0_bits_out_uop_uopc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_inst_0 = io_lsu_resp_0_bits_out_uop_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_inst_0 = io_lsu_resp_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_rvc_0 = io_lsu_resp_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_pc_0 = io_lsu_resp_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iq_type_0 = io_lsu_resp_0_bits_out_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fu_code_0 = io_lsu_resp_0_bits_out_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_br_type_0 = io_lsu_resp_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op1_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op2_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_imm_sel_0 = io_lsu_resp_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_op_fcn_0 = io_lsu_resp_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_resp_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_resp_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_load_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_sta_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ctrl_is_std_0 = io_lsu_resp_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_state_0 = io_lsu_resp_0_bits_out_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_p1_poisoned_0 = io_lsu_resp_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_iw_p2_poisoned_0 = io_lsu_resp_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_br_0 = io_lsu_resp_0_bits_out_uop_is_br; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_jalr_0 = io_lsu_resp_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_jal_0 = io_lsu_resp_0_bits_out_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_sfb_0 = io_lsu_resp_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [15:0] _io_lsu_resp_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21]
assign io_lsu_resp_0_bits_uop_br_mask_0 = io_lsu_resp_0_bits_out_uop_br_mask; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_br_tag_0 = io_lsu_resp_0_bits_out_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ftq_idx_0 = io_lsu_resp_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_edge_inst_0 = io_lsu_resp_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_pc_lob_0 = io_lsu_resp_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_taken_0 = io_lsu_resp_0_bits_out_uop_taken; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_imm_packed_0 = io_lsu_resp_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_csr_addr_0 = io_lsu_resp_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_rob_idx_0 = io_lsu_resp_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldq_idx_0 = io_lsu_resp_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_stq_idx_0 = io_lsu_resp_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_rxq_idx_0 = io_lsu_resp_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_pdst_0 = io_lsu_resp_0_bits_out_uop_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs1_0 = io_lsu_resp_0_bits_out_uop_prs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs2_0 = io_lsu_resp_0_bits_out_uop_prs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs3_0 = io_lsu_resp_0_bits_out_uop_prs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ppred_0 = io_lsu_resp_0_bits_out_uop_ppred; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs1_busy_0 = io_lsu_resp_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs2_busy_0 = io_lsu_resp_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_prs3_busy_0 = io_lsu_resp_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ppred_busy_0 = io_lsu_resp_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_stale_pdst_0 = io_lsu_resp_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_exception_0 = io_lsu_resp_0_bits_out_uop_exception; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_exc_cause_0 = io_lsu_resp_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bypassable_0 = io_lsu_resp_0_bits_out_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_cmd_0 = io_lsu_resp_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_size_0 = io_lsu_resp_0_bits_out_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_mem_signed_0 = io_lsu_resp_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_fence_0 = io_lsu_resp_0_bits_out_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_fencei_0 = io_lsu_resp_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_amo_0 = io_lsu_resp_0_bits_out_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_uses_ldq_0 = io_lsu_resp_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_uses_stq_0 = io_lsu_resp_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_resp_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_is_unique_0 = io_lsu_resp_0_bits_out_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_flush_on_commit_0 = io_lsu_resp_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_is_rs1_0 = io_lsu_resp_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_0 = io_lsu_resp_0_bits_out_uop_ldst; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs1_0 = io_lsu_resp_0_bits_out_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs2_0 = io_lsu_resp_0_bits_out_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs3_0 = io_lsu_resp_0_bits_out_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_ldst_val_0 = io_lsu_resp_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_dst_rtype_0 = io_lsu_resp_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs1_rtype_0 = io_lsu_resp_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_lrs2_rtype_0 = io_lsu_resp_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_frs3_en_0 = io_lsu_resp_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fp_val_0 = io_lsu_resp_0_bits_out_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_fp_single_0 = io_lsu_resp_0_bits_out_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_pf_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_ae_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_xcpt_ma_if_0 = io_lsu_resp_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bp_debug_if_0 = io_lsu_resp_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_bp_xcpt_if_0 = io_lsu_resp_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_fsrc_0 = io_lsu_resp_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_uop_debug_tsrc_0 = io_lsu_resp_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_data_0 = io_lsu_resp_0_bits_out_data; // @[util.scala:101:23]
assign io_lsu_resp_0_bits_is_hella_0 = io_lsu_resp_0_bits_out_is_hella; // @[util.scala:101:23]
wire [15:0] _io_lsu_resp_0_bits_out_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _io_lsu_resp_0_bits_out_uop_br_mask_T_1 = resp_0_bits_uop_br_mask & _io_lsu_resp_0_bits_out_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign io_lsu_resp_0_bits_out_uop_br_mask = _io_lsu_resp_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21, :101:23]
wire _io_lsu_nack_0_valid_T = s2_valid_0 & s2_send_nack_0; // @[dcache.scala:427:49, :862:41]
wire _io_lsu_nack_0_valid_T_2 = ~_io_lsu_nack_0_valid_T_1; // @[dcache.scala:863:{29,48}]
wire _io_lsu_nack_0_valid_T_3 = _io_lsu_nack_0_valid_T & _io_lsu_nack_0_valid_T_2; // @[dcache.scala:862:{41,60}, :863:29]
wire _io_lsu_nack_0_valid_T_5 = |_io_lsu_nack_0_valid_T_4; // @[util.scala:118:{51,59}]
wire _io_lsu_nack_0_valid_T_6 = ~_io_lsu_nack_0_valid_T_5; // @[util.scala:118:59]
assign _io_lsu_nack_0_valid_T_7 = _io_lsu_nack_0_valid_T_3 & _io_lsu_nack_0_valid_T_6; // @[dcache.scala:862:60, :863:75, :864:29]
assign io_lsu_nack_0_valid_0 = _io_lsu_nack_0_valid_T_7; // @[dcache.scala:413:7, :863:75]
assign io_lsu_nack_0_bits_uop_uopc_0 = io_lsu_nack_0_bits_out_uop_uopc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_inst_0 = io_lsu_nack_0_bits_out_uop_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_inst_0 = io_lsu_nack_0_bits_out_uop_debug_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_rvc_0 = io_lsu_nack_0_bits_out_uop_is_rvc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_pc_0 = io_lsu_nack_0_bits_out_uop_debug_pc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iq_type_0 = io_lsu_nack_0_bits_out_uop_iq_type; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fu_code_0 = io_lsu_nack_0_bits_out_uop_fu_code; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_br_type_0 = io_lsu_nack_0_bits_out_uop_ctrl_br_type; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op1_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_op1_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op2_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_op2_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_imm_sel_0 = io_lsu_nack_0_bits_out_uop_ctrl_imm_sel; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_op_fcn_0 = io_lsu_nack_0_bits_out_uop_ctrl_op_fcn; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_fcn_dw_0 = io_lsu_nack_0_bits_out_uop_ctrl_fcn_dw; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_csr_cmd_0 = io_lsu_nack_0_bits_out_uop_ctrl_csr_cmd; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_load_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_load; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_sta_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_sta; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ctrl_is_std_0 = io_lsu_nack_0_bits_out_uop_ctrl_is_std; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_state_0 = io_lsu_nack_0_bits_out_uop_iw_state; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_p1_poisoned_0 = io_lsu_nack_0_bits_out_uop_iw_p1_poisoned; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_iw_p2_poisoned_0 = io_lsu_nack_0_bits_out_uop_iw_p2_poisoned; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_br_0 = io_lsu_nack_0_bits_out_uop_is_br; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_jalr_0 = io_lsu_nack_0_bits_out_uop_is_jalr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_jal_0 = io_lsu_nack_0_bits_out_uop_is_jal; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_sfb_0 = io_lsu_nack_0_bits_out_uop_is_sfb; // @[util.scala:101:23]
wire [15:0] _io_lsu_nack_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21]
assign io_lsu_nack_0_bits_uop_br_mask_0 = io_lsu_nack_0_bits_out_uop_br_mask; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_br_tag_0 = io_lsu_nack_0_bits_out_uop_br_tag; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ftq_idx_0 = io_lsu_nack_0_bits_out_uop_ftq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_edge_inst_0 = io_lsu_nack_0_bits_out_uop_edge_inst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_pc_lob_0 = io_lsu_nack_0_bits_out_uop_pc_lob; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_taken_0 = io_lsu_nack_0_bits_out_uop_taken; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_imm_packed_0 = io_lsu_nack_0_bits_out_uop_imm_packed; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_csr_addr_0 = io_lsu_nack_0_bits_out_uop_csr_addr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_rob_idx_0 = io_lsu_nack_0_bits_out_uop_rob_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldq_idx_0 = io_lsu_nack_0_bits_out_uop_ldq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_stq_idx_0 = io_lsu_nack_0_bits_out_uop_stq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_rxq_idx_0 = io_lsu_nack_0_bits_out_uop_rxq_idx; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_pdst_0 = io_lsu_nack_0_bits_out_uop_pdst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs1_0 = io_lsu_nack_0_bits_out_uop_prs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs2_0 = io_lsu_nack_0_bits_out_uop_prs2; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs3_0 = io_lsu_nack_0_bits_out_uop_prs3; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ppred_0 = io_lsu_nack_0_bits_out_uop_ppred; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs1_busy_0 = io_lsu_nack_0_bits_out_uop_prs1_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs2_busy_0 = io_lsu_nack_0_bits_out_uop_prs2_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_prs3_busy_0 = io_lsu_nack_0_bits_out_uop_prs3_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ppred_busy_0 = io_lsu_nack_0_bits_out_uop_ppred_busy; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_stale_pdst_0 = io_lsu_nack_0_bits_out_uop_stale_pdst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_exception_0 = io_lsu_nack_0_bits_out_uop_exception; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_exc_cause_0 = io_lsu_nack_0_bits_out_uop_exc_cause; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bypassable_0 = io_lsu_nack_0_bits_out_uop_bypassable; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_cmd_0 = io_lsu_nack_0_bits_out_uop_mem_cmd; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_size_0 = io_lsu_nack_0_bits_out_uop_mem_size; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_mem_signed_0 = io_lsu_nack_0_bits_out_uop_mem_signed; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_fence_0 = io_lsu_nack_0_bits_out_uop_is_fence; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_fencei_0 = io_lsu_nack_0_bits_out_uop_is_fencei; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_amo_0 = io_lsu_nack_0_bits_out_uop_is_amo; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_uses_ldq_0 = io_lsu_nack_0_bits_out_uop_uses_ldq; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_uses_stq_0 = io_lsu_nack_0_bits_out_uop_uses_stq; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_sys_pc2epc_0 = io_lsu_nack_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_is_unique_0 = io_lsu_nack_0_bits_out_uop_is_unique; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_flush_on_commit_0 = io_lsu_nack_0_bits_out_uop_flush_on_commit; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_is_rs1_0 = io_lsu_nack_0_bits_out_uop_ldst_is_rs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_0 = io_lsu_nack_0_bits_out_uop_ldst; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs1_0 = io_lsu_nack_0_bits_out_uop_lrs1; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs2_0 = io_lsu_nack_0_bits_out_uop_lrs2; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs3_0 = io_lsu_nack_0_bits_out_uop_lrs3; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_ldst_val_0 = io_lsu_nack_0_bits_out_uop_ldst_val; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_dst_rtype_0 = io_lsu_nack_0_bits_out_uop_dst_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs1_rtype_0 = io_lsu_nack_0_bits_out_uop_lrs1_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_lrs2_rtype_0 = io_lsu_nack_0_bits_out_uop_lrs2_rtype; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_frs3_en_0 = io_lsu_nack_0_bits_out_uop_frs3_en; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fp_val_0 = io_lsu_nack_0_bits_out_uop_fp_val; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_fp_single_0 = io_lsu_nack_0_bits_out_uop_fp_single; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_pf_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_pf_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_ae_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_ae_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_xcpt_ma_if_0 = io_lsu_nack_0_bits_out_uop_xcpt_ma_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bp_debug_if_0 = io_lsu_nack_0_bits_out_uop_bp_debug_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_bp_xcpt_if_0 = io_lsu_nack_0_bits_out_uop_bp_xcpt_if; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_fsrc_0 = io_lsu_nack_0_bits_out_uop_debug_fsrc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_uop_debug_tsrc_0 = io_lsu_nack_0_bits_out_uop_debug_tsrc; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_addr_0 = io_lsu_nack_0_bits_out_addr; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_data_0 = io_lsu_nack_0_bits_out_data; // @[util.scala:101:23]
assign io_lsu_nack_0_bits_is_hella_0 = io_lsu_nack_0_bits_out_is_hella; // @[util.scala:101:23]
wire [15:0] _io_lsu_nack_0_bits_out_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23]
assign _io_lsu_nack_0_bits_out_uop_br_mask_T_1 = s2_req_0_uop_br_mask & _io_lsu_nack_0_bits_out_uop_br_mask_T; // @[util.scala:89:{21,23}]
assign io_lsu_nack_0_bits_out_uop_br_mask = _io_lsu_nack_0_bits_out_uop_br_mask_T_1; // @[util.scala:89:21, :101:23] |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_postMul_e8_s24_53( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_187( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
File fNFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object fNFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in)
val isSubnormal = rawIn.sExp < minNormExp.S
val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0)
val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0)
val expOut =
Mux(isSubnormal,
0.U,
rawIn.sExp(expWidth - 1, 0) -
((BigInt(1)<<(expWidth - 1)) + 1).U
) | Fill(expWidth, rawIn.isNaN || rawIn.isInf)
val fractOut =
Mux(isSubnormal,
denormFract,
Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0))
)
Cat(rawIn.sign, expOut, fractOut)
}
}
File rawFloatFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object rawFloatFromFN {
def apply(expWidth: Int, sigWidth: Int, in: Bits) = {
val sign = in(expWidth + sigWidth - 1)
val expIn = in(expWidth + sigWidth - 2, sigWidth - 1)
val fractIn = in(sigWidth - 2, 0)
val isZeroExpIn = (expIn === 0.U)
val isZeroFractIn = (fractIn === 0.U)
val normDist = countLeadingZeros(fractIn)
val subnormFract = (fractIn << normDist) (sigWidth - 3, 0) << 1
val adjustedExp =
Mux(isZeroExpIn,
normDist ^ ((BigInt(1) << (expWidth + 1)) - 1).U,
expIn
) + ((BigInt(1) << (expWidth - 1)).U
| Mux(isZeroExpIn, 2.U, 1.U))
val isZero = isZeroExpIn && isZeroFractIn
val isSpecial = adjustedExp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && !isZeroFractIn
out.isInf := isSpecial && isZeroFractIn
out.isZero := isZero
out.sign := sign
out.sExp := adjustedExp(expWidth, 0).zext
out.sig :=
0.U(1.W) ## !isZero ## Mux(isZeroExpIn, subnormFract, fractIn)
out
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module FPU_1( // @[FPU.scala:735:7]
input clock, // @[FPU.scala:735:7]
input reset, // @[FPU.scala:735:7]
input io_hartid, // @[FPU.scala:736:14]
input [63:0] io_time, // @[FPU.scala:736:14]
input [31:0] io_inst, // @[FPU.scala:736:14]
input [63:0] io_fromint_data, // @[FPU.scala:736:14]
input [2:0] io_fcsr_rm, // @[FPU.scala:736:14]
output io_fcsr_flags_valid, // @[FPU.scala:736:14]
output [4:0] io_fcsr_flags_bits, // @[FPU.scala:736:14]
output [63:0] io_store_data, // @[FPU.scala:736:14]
output [63:0] io_toint_data, // @[FPU.scala:736:14]
input io_ll_resp_val, // @[FPU.scala:736:14]
input [2:0] io_ll_resp_type, // @[FPU.scala:736:14]
input [4:0] io_ll_resp_tag, // @[FPU.scala:736:14]
input [63:0] io_ll_resp_data, // @[FPU.scala:736:14]
input io_valid, // @[FPU.scala:736:14]
output io_fcsr_rdy, // @[FPU.scala:736:14]
output io_nack_mem, // @[FPU.scala:736:14]
output io_illegal_rm, // @[FPU.scala:736:14]
input io_killx, // @[FPU.scala:736:14]
input io_killm, // @[FPU.scala:736:14]
output io_dec_ldst, // @[FPU.scala:736:14]
output io_dec_wen, // @[FPU.scala:736:14]
output io_dec_ren1, // @[FPU.scala:736:14]
output io_dec_ren2, // @[FPU.scala:736:14]
output io_dec_ren3, // @[FPU.scala:736:14]
output io_dec_swap12, // @[FPU.scala:736:14]
output io_dec_swap23, // @[FPU.scala:736:14]
output [1:0] io_dec_typeTagIn, // @[FPU.scala:736:14]
output [1:0] io_dec_typeTagOut, // @[FPU.scala:736:14]
output io_dec_fromint, // @[FPU.scala:736:14]
output io_dec_toint, // @[FPU.scala:736:14]
output io_dec_fastpipe, // @[FPU.scala:736:14]
output io_dec_fma, // @[FPU.scala:736:14]
output io_dec_div, // @[FPU.scala:736:14]
output io_dec_sqrt, // @[FPU.scala:736:14]
output io_dec_wflags, // @[FPU.scala:736:14]
output io_dec_vec, // @[FPU.scala:736:14]
output io_sboard_set, // @[FPU.scala:736:14]
output io_sboard_clr, // @[FPU.scala:736:14]
output [4:0] io_sboard_clra, // @[FPU.scala:736:14]
input io_keep_clock_enabled // @[FPU.scala:736:14]
);
wire wdata_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire wdata_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire wdata_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire _divSqrt_2_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_2_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_2_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [64:0] _divSqrt_2_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_2_io_exceptionFlags; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [32:0] _divSqrt_1_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_1_io_exceptionFlags; // @[FPU.scala:1027:55]
wire _divSqrt_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [16:0] _divSqrt_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_io_exceptionFlags; // @[FPU.scala:1027:55]
wire [64:0] _hfma_io_out_bits_data; // @[FPU.scala:919:28]
wire [4:0] _hfma_io_out_bits_exc; // @[FPU.scala:919:28]
wire [64:0] _dfma_io_out_bits_data; // @[FPU.scala:913:28]
wire [4:0] _dfma_io_out_bits_exc; // @[FPU.scala:913:28]
wire [64:0] _fpmu_io_out_bits_data; // @[FPU.scala:891:20]
wire [4:0] _fpmu_io_out_bits_exc; // @[FPU.scala:891:20]
wire [64:0] _ifpu_io_out_bits_data; // @[FPU.scala:886:20]
wire [4:0] _ifpu_io_out_bits_exc; // @[FPU.scala:886:20]
wire [2:0] _fpiu_io_out_bits_in_rm; // @[FPU.scala:876:20]
wire [64:0] _fpiu_io_out_bits_in_in1; // @[FPU.scala:876:20]
wire [64:0] _fpiu_io_out_bits_in_in2; // @[FPU.scala:876:20]
wire _fpiu_io_out_bits_lt; // @[FPU.scala:876:20]
wire [4:0] _fpiu_io_out_bits_exc; // @[FPU.scala:876:20]
wire [64:0] _sfma_io_out_bits_data; // @[FPU.scala:872:20]
wire [4:0] _sfma_io_out_bits_exc; // @[FPU.scala:872:20]
wire [64:0] _regfile_ext_R0_data; // @[FPU.scala:818:20]
wire [64:0] _regfile_ext_R1_data; // @[FPU.scala:818:20]
wire [64:0] _regfile_ext_R2_data; // @[FPU.scala:818:20]
wire io_hartid_0 = io_hartid; // @[FPU.scala:735:7]
wire [63:0] io_time_0 = io_time; // @[FPU.scala:735:7]
wire [31:0] io_inst_0 = io_inst; // @[FPU.scala:735:7]
wire [63:0] io_fromint_data_0 = io_fromint_data; // @[FPU.scala:735:7]
wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[FPU.scala:735:7]
wire io_ll_resp_val_0 = io_ll_resp_val; // @[FPU.scala:735:7]
wire [2:0] io_ll_resp_type_0 = io_ll_resp_type; // @[FPU.scala:735:7]
wire [4:0] io_ll_resp_tag_0 = io_ll_resp_tag; // @[FPU.scala:735:7]
wire [63:0] io_ll_resp_data_0 = io_ll_resp_data; // @[FPU.scala:735:7]
wire io_valid_0 = io_valid; // @[FPU.scala:735:7]
wire io_killx_0 = io_killx; // @[FPU.scala:735:7]
wire io_killm_0 = io_killm; // @[FPU.scala:735:7]
wire io_keep_clock_enabled_0 = io_keep_clock_enabled; // @[FPU.scala:735:7]
wire frfWriteBundle_0_clock = clock; // @[FPU.scala:805:44]
wire frfWriteBundle_0_reset = reset; // @[FPU.scala:805:44]
wire frfWriteBundle_1_clock = clock; // @[FPU.scala:805:44]
wire frfWriteBundle_1_reset = reset; // @[FPU.scala:805:44]
wire clock_en = 1'h1; // @[FPU.scala:735:7, :745:31]
wire _killm_T_1 = 1'h1; // @[FPU.scala:735:7, :785:44]
wire prevOK_prevOK = 1'h1; // @[FPU.scala:384:33, :735:7]
wire _wdata_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42, :735:7]
wire _wdata_opts_bigger_T = 1'h1; // @[FPU.scala:249:56, :735:7]
wire _wdata_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42, :735:7]
wire _wdata_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56, :735:7]
wire prevOK_prevOK_1 = 1'h1; // @[FPU.scala:384:33, :735:7]
wire _io_cp_req_ready_T_3 = 1'h1; // @[FPU.scala:735:7, :991:39]
wire _io_nack_mem_T_2 = 1'h1; // @[FPU.scala:735:7, :1003:86]
wire _io_sboard_set_T = 1'h1; // @[FPU.scala:735:7, :1006:36]
wire _io_sboard_clr_T = 1'h1; // @[FPU.scala:735:7, :1007:20]
wire _clock_en_reg_T = 1'h1; // @[FPU.scala:735:7, :1051:19]
wire _clock_en_reg_T_1 = 1'h1; // @[FPU.scala:735:7, :1051:37]
wire _clock_en_reg_T_2 = 1'h1; // @[FPU.scala:735:7, :1052:27]
wire _clock_en_reg_T_3 = 1'h1; // @[FPU.scala:735:7, :1053:14]
wire _clock_en_reg_T_4 = 1'h1; // @[FPU.scala:735:7, :1054:15]
wire _clock_en_reg_T_5 = 1'h1; // @[FPU.scala:735:7, :1055:19]
wire _clock_en_reg_T_6 = 1'h1; // @[FPU.scala:735:7, :1055:35]
wire _clock_en_reg_T_7 = 1'h1; // @[FPU.scala:735:7, :1056:18]
wire _clock_en_reg_T_9 = 1'h1; // @[FPU.scala:735:7, :1056:33]
wire _clock_en_reg_T_10 = 1'h1; // @[FPU.scala:735:7, :1057:13]
wire _clock_en_reg_T_11 = 1'h1; // @[FPU.scala:735:7, :1057:33]
wire io_cp_req_valid = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_ldst = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_wen = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_ren1 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_ren2 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_ren3 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_swap12 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_swap23 = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_fromint = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_toint = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_fastpipe = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_fma = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_div = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_sqrt = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_wflags = 1'h0; // @[FPU.scala:735:7]
wire io_cp_req_bits_vec = 1'h0; // @[FPU.scala:735:7]
wire io_cp_resp_ready = 1'h0; // @[FPU.scala:735:7]
wire ex_cp_valid = 1'h0; // @[Decoupled.scala:51:35]
wire cp_ctrl_ldst = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_wen = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_ren1 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_ren2 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_ren3 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_swap12 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_swap23 = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_fromint = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_toint = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_fastpipe = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_fma = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_div = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_sqrt = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_wflags = 1'h0; // @[FPU.scala:794:21]
wire cp_ctrl_vec = 1'h0; // @[FPU.scala:794:21]
wire frfWriteBundle_0_excpt = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_0_valid = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_0_wrenx = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_1_excpt = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_1_valid = 1'h0; // @[FPU.scala:805:44]
wire frfWriteBundle_1_wrenx = 1'h0; // @[FPU.scala:805:44]
wire _wbInfo_0_pipeid_T = 1'h0; // @[FPU.scala:928:63]
wire _wbInfo_1_pipeid_T = 1'h0; // @[FPU.scala:928:63]
wire _wbInfo_2_pipeid_T = 1'h0; // @[FPU.scala:928:63]
wire _io_cp_req_ready_T_2 = 1'h0; // @[FPU.scala:991:55]
wire [64:0] io_cp_req_bits_in1 = 65'h0; // @[FPU.scala:735:7]
wire [64:0] io_cp_req_bits_in2 = 65'h0; // @[FPU.scala:735:7]
wire [64:0] io_cp_req_bits_in3 = 65'h0; // @[FPU.scala:735:7]
wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31]
wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31]
wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31]
wire [2:0] io_v_sew = 3'h0; // @[FPU.scala:735:7]
wire [2:0] io_cp_req_bits_rm = 3'h0; // @[FPU.scala:735:7]
wire [2:0] frfWriteBundle_0_priv_mode = 3'h0; // @[FPU.scala:805:44]
wire [2:0] frfWriteBundle_1_priv_mode = 3'h0; // @[FPU.scala:805:44]
wire [1:0] io_cp_req_bits_typeTagIn = 2'h0; // @[FPU.scala:735:7]
wire [1:0] io_cp_req_bits_typeTagOut = 2'h0; // @[FPU.scala:735:7]
wire [1:0] io_cp_req_bits_fmaCmd = 2'h0; // @[FPU.scala:735:7]
wire [1:0] io_cp_req_bits_typ = 2'h0; // @[FPU.scala:735:7]
wire [1:0] io_cp_req_bits_fmt = 2'h0; // @[FPU.scala:735:7]
wire [1:0] cp_ctrl_typeTagIn = 2'h0; // @[FPU.scala:794:21]
wire [1:0] cp_ctrl_typeTagOut = 2'h0; // @[FPU.scala:794:21]
wire [4:0] io_cp_resp_bits_exc = 5'h0; // @[FPU.scala:735:7]
wire [4:0] frfWriteBundle_0_rd0src = 5'h0; // @[FPU.scala:805:44]
wire [4:0] frfWriteBundle_0_rd1src = 5'h0; // @[FPU.scala:805:44]
wire [4:0] frfWriteBundle_1_rd0src = 5'h0; // @[FPU.scala:805:44]
wire [4:0] frfWriteBundle_1_rd1src = 5'h0; // @[FPU.scala:805:44]
wire [64:0] _divSqrt_wdata_maskedNaN_T_1 = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27]
wire [32:0] _divSqrt_wdata_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27]
wire [4:0] wdata_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26]
wire [4:0] wdata_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26]
wire [31:0] frfWriteBundle_0_inst = 32'h0; // @[FPU.scala:805:44]
wire [31:0] frfWriteBundle_1_inst = 32'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_0_pc = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_0_rd0val = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_0_rd1val = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_1_pc = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_1_rd0val = 64'h0; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_1_rd1val = 64'h0; // @[FPU.scala:805:44]
wire _io_fcsr_flags_valid_T_2; // @[FPU.scala:995:56]
wire [4:0] _io_fcsr_flags_bits_T_5; // @[FPU.scala:998:42]
wire _io_fcsr_rdy_T_8; // @[FPU.scala:1002:18]
wire _io_nack_mem_T_3; // @[FPU.scala:1003:83]
wire _io_illegal_rm_T_8; // @[FPU.scala:1011:53]
wire id_ctrl_ldst; // @[FPU.scala:752:25]
wire id_ctrl_wen; // @[FPU.scala:752:25]
wire id_ctrl_ren1; // @[FPU.scala:752:25]
wire id_ctrl_ren2; // @[FPU.scala:752:25]
wire id_ctrl_ren3; // @[FPU.scala:752:25]
wire id_ctrl_swap12; // @[FPU.scala:752:25]
wire id_ctrl_swap23; // @[FPU.scala:752:25]
wire [1:0] id_ctrl_typeTagIn; // @[FPU.scala:752:25]
wire [1:0] id_ctrl_typeTagOut; // @[FPU.scala:752:25]
wire id_ctrl_fromint; // @[FPU.scala:752:25]
wire id_ctrl_toint; // @[FPU.scala:752:25]
wire id_ctrl_fastpipe; // @[FPU.scala:752:25]
wire id_ctrl_fma; // @[FPU.scala:752:25]
wire id_ctrl_div; // @[FPU.scala:752:25]
wire id_ctrl_sqrt; // @[FPU.scala:752:25]
wire id_ctrl_wflags; // @[FPU.scala:752:25]
wire id_ctrl_vec; // @[FPU.scala:752:25]
wire _io_sboard_set_T_8; // @[FPU.scala:1006:49]
wire _io_sboard_clr_T_6; // @[FPU.scala:1007:33]
wire [4:0] waddr; // @[FPU.scala:963:18]
wire _io_cp_req_ready_T_6; // @[FPU.scala:991:71]
wire io_fcsr_flags_valid_0; // @[FPU.scala:735:7]
wire [4:0] io_fcsr_flags_bits_0; // @[FPU.scala:735:7]
wire io_dec_ldst_0; // @[FPU.scala:735:7]
wire io_dec_wen_0; // @[FPU.scala:735:7]
wire io_dec_ren1_0; // @[FPU.scala:735:7]
wire io_dec_ren2_0; // @[FPU.scala:735:7]
wire io_dec_ren3_0; // @[FPU.scala:735:7]
wire io_dec_swap12_0; // @[FPU.scala:735:7]
wire io_dec_swap23_0; // @[FPU.scala:735:7]
wire [1:0] io_dec_typeTagIn_0; // @[FPU.scala:735:7]
wire [1:0] io_dec_typeTagOut_0; // @[FPU.scala:735:7]
wire io_dec_fromint_0; // @[FPU.scala:735:7]
wire io_dec_toint_0; // @[FPU.scala:735:7]
wire io_dec_fastpipe_0; // @[FPU.scala:735:7]
wire io_dec_fma_0; // @[FPU.scala:735:7]
wire io_dec_div_0; // @[FPU.scala:735:7]
wire io_dec_sqrt_0; // @[FPU.scala:735:7]
wire io_dec_wflags_0; // @[FPU.scala:735:7]
wire io_dec_vec_0; // @[FPU.scala:735:7]
wire io_cp_req_ready; // @[FPU.scala:735:7]
wire [64:0] io_cp_resp_bits_data; // @[FPU.scala:735:7]
wire io_cp_resp_valid; // @[FPU.scala:735:7]
wire [63:0] io_store_data_0; // @[FPU.scala:735:7]
wire [63:0] io_toint_data_0; // @[FPU.scala:735:7]
wire io_fcsr_rdy_0; // @[FPU.scala:735:7]
wire io_nack_mem_0; // @[FPU.scala:735:7]
wire io_illegal_rm_0; // @[FPU.scala:735:7]
wire io_sboard_set_0; // @[FPU.scala:735:7]
wire io_sboard_clr_0; // @[FPU.scala:735:7]
wire [4:0] io_sboard_clra_0; // @[FPU.scala:735:7]
assign io_dec_ldst_0 = id_ctrl_ldst; // @[FPU.scala:735:7, :752:25]
assign io_dec_wen_0 = id_ctrl_wen; // @[FPU.scala:735:7, :752:25]
assign io_dec_ren1_0 = id_ctrl_ren1; // @[FPU.scala:735:7, :752:25]
assign io_dec_ren2_0 = id_ctrl_ren2; // @[FPU.scala:735:7, :752:25]
assign io_dec_ren3_0 = id_ctrl_ren3; // @[FPU.scala:735:7, :752:25]
assign io_dec_swap12_0 = id_ctrl_swap12; // @[FPU.scala:735:7, :752:25]
assign io_dec_swap23_0 = id_ctrl_swap23; // @[FPU.scala:735:7, :752:25]
assign io_dec_typeTagIn_0 = id_ctrl_typeTagIn; // @[FPU.scala:735:7, :752:25]
assign io_dec_typeTagOut_0 = id_ctrl_typeTagOut; // @[FPU.scala:735:7, :752:25]
assign io_dec_fromint_0 = id_ctrl_fromint; // @[FPU.scala:735:7, :752:25]
assign io_dec_toint_0 = id_ctrl_toint; // @[FPU.scala:735:7, :752:25]
assign io_dec_fastpipe_0 = id_ctrl_fastpipe; // @[FPU.scala:735:7, :752:25]
assign io_dec_fma_0 = id_ctrl_fma; // @[FPU.scala:735:7, :752:25]
assign io_dec_div_0 = id_ctrl_div; // @[FPU.scala:735:7, :752:25]
assign io_dec_sqrt_0 = id_ctrl_sqrt; // @[FPU.scala:735:7, :752:25]
assign io_dec_wflags_0 = id_ctrl_wflags; // @[FPU.scala:735:7, :752:25]
assign io_dec_vec_0 = id_ctrl_vec; // @[FPU.scala:735:7, :752:25]
reg ex_reg_valid; // @[FPU.scala:767:29]
wire req_valid = ex_reg_valid; // @[FPU.scala:767:29, :780:32]
reg [31:0] ex_reg_inst; // @[FPU.scala:768:30]
reg ex_reg_ctrl_ldst; // @[FPU.scala:769:30]
wire ex_ctrl_ldst = ex_reg_ctrl_ldst; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_wen; // @[FPU.scala:769:30]
wire ex_ctrl_wen = ex_reg_ctrl_wen; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_ren1; // @[FPU.scala:769:30]
wire ex_ctrl_ren1 = ex_reg_ctrl_ren1; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_ren2; // @[FPU.scala:769:30]
wire ex_ctrl_ren2 = ex_reg_ctrl_ren2; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_ren3; // @[FPU.scala:769:30]
wire ex_ctrl_ren3 = ex_reg_ctrl_ren3; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_swap12; // @[FPU.scala:769:30]
wire ex_ctrl_swap12 = ex_reg_ctrl_swap12; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_swap23; // @[FPU.scala:769:30]
wire ex_ctrl_swap23 = ex_reg_ctrl_swap23; // @[FPU.scala:769:30, :800:20]
reg [1:0] ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30]
wire [1:0] ex_ctrl_typeTagIn = ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30, :800:20]
reg [1:0] ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30]
wire [1:0] ex_ctrl_typeTagOut = ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_fromint; // @[FPU.scala:769:30]
wire ex_ctrl_fromint = ex_reg_ctrl_fromint; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_toint; // @[FPU.scala:769:30]
wire ex_ctrl_toint = ex_reg_ctrl_toint; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30]
wire ex_ctrl_fastpipe = ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_fma; // @[FPU.scala:769:30]
wire ex_ctrl_fma = ex_reg_ctrl_fma; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_div; // @[FPU.scala:769:30]
wire ex_ctrl_div = ex_reg_ctrl_div; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_sqrt; // @[FPU.scala:769:30]
wire ex_ctrl_sqrt = ex_reg_ctrl_sqrt; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_wflags; // @[FPU.scala:769:30]
wire ex_ctrl_wflags = ex_reg_ctrl_wflags; // @[FPU.scala:769:30, :800:20]
reg ex_reg_ctrl_vec; // @[FPU.scala:769:30]
wire ex_ctrl_vec = ex_reg_ctrl_vec; // @[FPU.scala:769:30, :800:20]
reg [4:0] ex_ra_0; // @[FPU.scala:770:31]
wire [4:0] _ex_rs_T = ex_ra_0; // @[FPU.scala:770:31, :832:37]
reg [4:0] ex_ra_1; // @[FPU.scala:770:31]
wire [4:0] _ex_rs_T_2 = ex_ra_1; // @[FPU.scala:770:31, :832:37]
reg [4:0] ex_ra_2; // @[FPU.scala:770:31]
wire [4:0] _ex_rs_T_4 = ex_ra_2; // @[FPU.scala:770:31, :832:37]
reg load_wb; // @[FPU.scala:773:24]
wire frfWriteBundle_0_wrenf = load_wb; // @[FPU.scala:773:24, :805:44]
wire [1:0] _load_wb_typeTag_T = io_ll_resp_type_0[1:0]; // @[FPU.scala:735:7, :774:50]
wire [2:0] _load_wb_typeTag_T_1 = {1'h0, _load_wb_typeTag_T} - 3'h1; // @[FPU.scala:774:{50,56}]
wire [1:0] _load_wb_typeTag_T_2 = _load_wb_typeTag_T_1[1:0]; // @[FPU.scala:774:56]
reg [1:0] load_wb_typeTag; // @[FPU.scala:774:34]
reg [63:0] load_wb_data; // @[FPU.scala:775:31]
reg [4:0] load_wb_tag; // @[FPU.scala:776:30]
wire [4:0] frfWriteBundle_0_wrdst = load_wb_tag; // @[FPU.scala:776:30, :805:44]
reg mem_reg_valid; // @[FPU.scala:784:30]
wire _killm_T = io_killm_0 | io_nack_mem_0; // @[FPU.scala:735:7, :785:25]
wire killm = _killm_T; // @[FPU.scala:785:{25,41}]
wire _killx_T = mem_reg_valid & killm; // @[FPU.scala:784:30, :785:41, :789:41]
wire killx = io_killx_0 | _killx_T; // @[FPU.scala:735:7, :789:{24,41}]
wire _mem_reg_valid_T = ~killx; // @[FPU.scala:789:24, :790:36]
wire _mem_reg_valid_T_1 = ex_reg_valid & _mem_reg_valid_T; // @[FPU.scala:767:29, :790:{33,36}]
wire _mem_reg_valid_T_2 = _mem_reg_valid_T_1; // @[FPU.scala:790:{33,43}]
reg [31:0] mem_reg_inst; // @[FPU.scala:791:31]
wire _wb_reg_valid_T = ~killm; // @[FPU.scala:785:41, :792:48]
wire _wb_reg_valid_T_1 = _wb_reg_valid_T; // @[FPU.scala:792:{48,55}]
wire _wb_reg_valid_T_2 = mem_reg_valid & _wb_reg_valid_T_1; // @[FPU.scala:784:30, :792:{44,55}]
reg wb_reg_valid; // @[FPU.scala:792:29]
wire _io_sboard_set_T_1 = wb_reg_valid; // @[FPU.scala:792:29, :1006:33]
wire sfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19]
wire [1:0] sfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19]
wire [1:0] fpiu_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19]
wire [1:0] dfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19]
wire [1:0] hfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19]
wire [1:0] sfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19]
wire [1:0] fpiu_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19]
wire [1:0] dfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19]
wire [1:0] hfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19]
wire sfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19]
wire fpiu_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19]
wire dfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19]
wire hfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19]
reg mem_ctrl_ldst; // @[FPU.scala:801:27]
reg mem_ctrl_wen; // @[FPU.scala:801:27]
reg mem_ctrl_ren1; // @[FPU.scala:801:27]
reg mem_ctrl_ren2; // @[FPU.scala:801:27]
reg mem_ctrl_ren3; // @[FPU.scala:801:27]
reg mem_ctrl_swap12; // @[FPU.scala:801:27]
reg mem_ctrl_swap23; // @[FPU.scala:801:27]
reg [1:0] mem_ctrl_typeTagIn; // @[FPU.scala:801:27]
reg [1:0] mem_ctrl_typeTagOut; // @[FPU.scala:801:27]
reg mem_ctrl_fromint; // @[FPU.scala:801:27]
wire _memLatencyMask_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :926:23]
wire _wbInfo_0_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63]
wire _wbInfo_1_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63]
wire _wbInfo_2_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63]
reg mem_ctrl_toint; // @[FPU.scala:801:27]
reg mem_ctrl_fastpipe; // @[FPU.scala:801:27]
wire _memLatencyMask_T = mem_ctrl_fastpipe; // @[FPU.scala:801:27, :926:23]
reg mem_ctrl_fma; // @[FPU.scala:801:27]
reg mem_ctrl_div; // @[FPU.scala:801:27]
reg mem_ctrl_sqrt; // @[FPU.scala:801:27]
reg mem_ctrl_wflags; // @[FPU.scala:801:27]
reg mem_ctrl_vec; // @[FPU.scala:801:27]
reg wb_ctrl_ldst; // @[FPU.scala:802:26]
reg wb_ctrl_wen; // @[FPU.scala:802:26]
reg wb_ctrl_ren1; // @[FPU.scala:802:26]
reg wb_ctrl_ren2; // @[FPU.scala:802:26]
reg wb_ctrl_ren3; // @[FPU.scala:802:26]
reg wb_ctrl_swap12; // @[FPU.scala:802:26]
reg wb_ctrl_swap23; // @[FPU.scala:802:26]
reg [1:0] wb_ctrl_typeTagIn; // @[FPU.scala:802:26]
reg [1:0] wb_ctrl_typeTagOut; // @[FPU.scala:802:26]
reg wb_ctrl_fromint; // @[FPU.scala:802:26]
reg wb_ctrl_toint; // @[FPU.scala:802:26]
reg wb_ctrl_fastpipe; // @[FPU.scala:802:26]
reg wb_ctrl_fma; // @[FPU.scala:802:26]
reg wb_ctrl_div; // @[FPU.scala:802:26]
reg wb_ctrl_sqrt; // @[FPU.scala:802:26]
reg wb_ctrl_wflags; // @[FPU.scala:802:26]
reg wb_ctrl_vec; // @[FPU.scala:802:26]
wire [31:0] _frfWriteBundle_0_timer_T; // @[FPU.scala:810:23]
wire [63:0] _frfWriteBundle_0_wrdata_T_5; // @[FPU.scala:446:10]
wire [63:0] frfWriteBundle_0_hartid; // @[FPU.scala:805:44]
wire [31:0] frfWriteBundle_0_timer; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_0_wrdata; // @[FPU.scala:805:44]
wire [31:0] _frfWriteBundle_1_timer_T; // @[FPU.scala:810:23]
wire [63:0] _frfWriteBundle_1_wrdata_T_5; // @[FPU.scala:446:10]
wire [63:0] frfWriteBundle_1_hartid; // @[FPU.scala:805:44]
wire [31:0] frfWriteBundle_1_timer; // @[FPU.scala:805:44]
wire [4:0] frfWriteBundle_1_wrdst; // @[FPU.scala:805:44]
wire [63:0] frfWriteBundle_1_wrdata; // @[FPU.scala:805:44]
wire frfWriteBundle_1_wrenf; // @[FPU.scala:805:44]
wire [63:0] _GEN = {63'h0, io_hartid_0}; // @[FPU.scala:735:7, :809:14]
assign frfWriteBundle_0_hartid = _GEN; // @[FPU.scala:805:44, :809:14]
assign frfWriteBundle_1_hartid = _GEN; // @[FPU.scala:805:44, :809:14]
assign _frfWriteBundle_0_timer_T = io_time_0[31:0]; // @[FPU.scala:735:7, :810:23]
assign _frfWriteBundle_1_timer_T = io_time_0[31:0]; // @[FPU.scala:735:7, :810:23]
assign frfWriteBundle_0_timer = _frfWriteBundle_0_timer_T; // @[FPU.scala:805:44, :810:23]
assign frfWriteBundle_1_timer = _frfWriteBundle_1_timer_T; // @[FPU.scala:805:44, :810:23]
wire _wdata_T = load_wb_typeTag == 2'h1; // @[package.scala:39:86]
wire [63:0] _wdata_T_1 = _wdata_T ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000; // @[package.scala:39:{76,86}]
wire _wdata_T_2 = load_wb_typeTag == 2'h2; // @[package.scala:39:86]
wire [63:0] _wdata_T_3 = _wdata_T_2 ? 64'h0 : _wdata_T_1; // @[package.scala:39:{76,86}]
wire _wdata_T_4 = &load_wb_typeTag; // @[package.scala:39:86]
wire [63:0] _wdata_T_5 = _wdata_T_4 ? 64'h0 : _wdata_T_3; // @[package.scala:39:{76,86}]
wire [63:0] _wdata_T_6 = _wdata_T_5 | load_wb_data; // @[package.scala:39:76]
wire wdata_rawIn_sign = _wdata_T_6[63]; // @[FPU.scala:431:23]
wire wdata_rawIn_sign_0 = wdata_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [10:0] wdata_rawIn_expIn = _wdata_T_6[62:52]; // @[FPU.scala:431:23]
wire [51:0] wdata_rawIn_fractIn = _wdata_T_6[51:0]; // @[FPU.scala:431:23]
wire wdata_rawIn_isZeroExpIn = wdata_rawIn_expIn == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire wdata_rawIn_isZeroFractIn = wdata_rawIn_fractIn == 52'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _wdata_rawIn_normDist_T = wdata_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_1 = wdata_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_2 = wdata_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_3 = wdata_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_4 = wdata_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_5 = wdata_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_6 = wdata_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_7 = wdata_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_8 = wdata_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_9 = wdata_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_10 = wdata_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_11 = wdata_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_12 = wdata_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_13 = wdata_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_14 = wdata_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_15 = wdata_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_16 = wdata_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_17 = wdata_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_18 = wdata_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_19 = wdata_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_20 = wdata_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_21 = wdata_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_22 = wdata_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_23 = wdata_rawIn_fractIn[23]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_24 = wdata_rawIn_fractIn[24]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_25 = wdata_rawIn_fractIn[25]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_26 = wdata_rawIn_fractIn[26]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_27 = wdata_rawIn_fractIn[27]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_28 = wdata_rawIn_fractIn[28]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_29 = wdata_rawIn_fractIn[29]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_30 = wdata_rawIn_fractIn[30]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_31 = wdata_rawIn_fractIn[31]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_32 = wdata_rawIn_fractIn[32]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_33 = wdata_rawIn_fractIn[33]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_34 = wdata_rawIn_fractIn[34]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_35 = wdata_rawIn_fractIn[35]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_36 = wdata_rawIn_fractIn[36]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_37 = wdata_rawIn_fractIn[37]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_38 = wdata_rawIn_fractIn[38]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_39 = wdata_rawIn_fractIn[39]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_40 = wdata_rawIn_fractIn[40]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_41 = wdata_rawIn_fractIn[41]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_42 = wdata_rawIn_fractIn[42]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_43 = wdata_rawIn_fractIn[43]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_44 = wdata_rawIn_fractIn[44]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_45 = wdata_rawIn_fractIn[45]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_46 = wdata_rawIn_fractIn[46]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_47 = wdata_rawIn_fractIn[47]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_48 = wdata_rawIn_fractIn[48]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_49 = wdata_rawIn_fractIn[49]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_50 = wdata_rawIn_fractIn[50]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_51 = wdata_rawIn_fractIn[51]; // @[rawFloatFromFN.scala:46:21]
wire [5:0] _wdata_rawIn_normDist_T_52 = {5'h19, ~_wdata_rawIn_normDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_53 = _wdata_rawIn_normDist_T_2 ? 6'h31 : _wdata_rawIn_normDist_T_52; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_54 = _wdata_rawIn_normDist_T_3 ? 6'h30 : _wdata_rawIn_normDist_T_53; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_55 = _wdata_rawIn_normDist_T_4 ? 6'h2F : _wdata_rawIn_normDist_T_54; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_56 = _wdata_rawIn_normDist_T_5 ? 6'h2E : _wdata_rawIn_normDist_T_55; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_57 = _wdata_rawIn_normDist_T_6 ? 6'h2D : _wdata_rawIn_normDist_T_56; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_58 = _wdata_rawIn_normDist_T_7 ? 6'h2C : _wdata_rawIn_normDist_T_57; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_59 = _wdata_rawIn_normDist_T_8 ? 6'h2B : _wdata_rawIn_normDist_T_58; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_60 = _wdata_rawIn_normDist_T_9 ? 6'h2A : _wdata_rawIn_normDist_T_59; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_61 = _wdata_rawIn_normDist_T_10 ? 6'h29 : _wdata_rawIn_normDist_T_60; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_62 = _wdata_rawIn_normDist_T_11 ? 6'h28 : _wdata_rawIn_normDist_T_61; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_63 = _wdata_rawIn_normDist_T_12 ? 6'h27 : _wdata_rawIn_normDist_T_62; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_64 = _wdata_rawIn_normDist_T_13 ? 6'h26 : _wdata_rawIn_normDist_T_63; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_65 = _wdata_rawIn_normDist_T_14 ? 6'h25 : _wdata_rawIn_normDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_66 = _wdata_rawIn_normDist_T_15 ? 6'h24 : _wdata_rawIn_normDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_67 = _wdata_rawIn_normDist_T_16 ? 6'h23 : _wdata_rawIn_normDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_68 = _wdata_rawIn_normDist_T_17 ? 6'h22 : _wdata_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_69 = _wdata_rawIn_normDist_T_18 ? 6'h21 : _wdata_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_70 = _wdata_rawIn_normDist_T_19 ? 6'h20 : _wdata_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_71 = _wdata_rawIn_normDist_T_20 ? 6'h1F : _wdata_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_72 = _wdata_rawIn_normDist_T_21 ? 6'h1E : _wdata_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_73 = _wdata_rawIn_normDist_T_22 ? 6'h1D : _wdata_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_74 = _wdata_rawIn_normDist_T_23 ? 6'h1C : _wdata_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_75 = _wdata_rawIn_normDist_T_24 ? 6'h1B : _wdata_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_76 = _wdata_rawIn_normDist_T_25 ? 6'h1A : _wdata_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_77 = _wdata_rawIn_normDist_T_26 ? 6'h19 : _wdata_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_78 = _wdata_rawIn_normDist_T_27 ? 6'h18 : _wdata_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_79 = _wdata_rawIn_normDist_T_28 ? 6'h17 : _wdata_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_80 = _wdata_rawIn_normDist_T_29 ? 6'h16 : _wdata_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_81 = _wdata_rawIn_normDist_T_30 ? 6'h15 : _wdata_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_82 = _wdata_rawIn_normDist_T_31 ? 6'h14 : _wdata_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_83 = _wdata_rawIn_normDist_T_32 ? 6'h13 : _wdata_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_84 = _wdata_rawIn_normDist_T_33 ? 6'h12 : _wdata_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_85 = _wdata_rawIn_normDist_T_34 ? 6'h11 : _wdata_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_86 = _wdata_rawIn_normDist_T_35 ? 6'h10 : _wdata_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_87 = _wdata_rawIn_normDist_T_36 ? 6'hF : _wdata_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_88 = _wdata_rawIn_normDist_T_37 ? 6'hE : _wdata_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_89 = _wdata_rawIn_normDist_T_38 ? 6'hD : _wdata_rawIn_normDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_90 = _wdata_rawIn_normDist_T_39 ? 6'hC : _wdata_rawIn_normDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_91 = _wdata_rawIn_normDist_T_40 ? 6'hB : _wdata_rawIn_normDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_92 = _wdata_rawIn_normDist_T_41 ? 6'hA : _wdata_rawIn_normDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_93 = _wdata_rawIn_normDist_T_42 ? 6'h9 : _wdata_rawIn_normDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_94 = _wdata_rawIn_normDist_T_43 ? 6'h8 : _wdata_rawIn_normDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_95 = _wdata_rawIn_normDist_T_44 ? 6'h7 : _wdata_rawIn_normDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_96 = _wdata_rawIn_normDist_T_45 ? 6'h6 : _wdata_rawIn_normDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_97 = _wdata_rawIn_normDist_T_46 ? 6'h5 : _wdata_rawIn_normDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_98 = _wdata_rawIn_normDist_T_47 ? 6'h4 : _wdata_rawIn_normDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_99 = _wdata_rawIn_normDist_T_48 ? 6'h3 : _wdata_rawIn_normDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_100 = _wdata_rawIn_normDist_T_49 ? 6'h2 : _wdata_rawIn_normDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_normDist_T_101 = _wdata_rawIn_normDist_T_50 ? 6'h1 : _wdata_rawIn_normDist_T_100; // @[Mux.scala:50:70]
wire [5:0] wdata_rawIn_normDist = _wdata_rawIn_normDist_T_51 ? 6'h0 : _wdata_rawIn_normDist_T_101; // @[Mux.scala:50:70]
wire [114:0] _wdata_rawIn_subnormFract_T = {63'h0, wdata_rawIn_fractIn} << wdata_rawIn_normDist; // @[Mux.scala:50:70]
wire [50:0] _wdata_rawIn_subnormFract_T_1 = _wdata_rawIn_subnormFract_T[50:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [51:0] wdata_rawIn_subnormFract = {_wdata_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [11:0] _wdata_rawIn_adjustedExp_T = {6'h3F, ~wdata_rawIn_normDist}; // @[Mux.scala:50:70]
wire [11:0] _wdata_rawIn_adjustedExp_T_1 = wdata_rawIn_isZeroExpIn ? _wdata_rawIn_adjustedExp_T : {1'h0, wdata_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _wdata_rawIn_adjustedExp_T_2 = wdata_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [10:0] _wdata_rawIn_adjustedExp_T_3 = {9'h100, _wdata_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [12:0] _wdata_rawIn_adjustedExp_T_4 = {1'h0, _wdata_rawIn_adjustedExp_T_1} + {2'h0, _wdata_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [11:0] wdata_rawIn_adjustedExp = _wdata_rawIn_adjustedExp_T_4[11:0]; // @[rawFloatFromFN.scala:57:9]
wire [11:0] _wdata_rawIn_out_sExp_T = wdata_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire wdata_rawIn_isZero = wdata_rawIn_isZeroExpIn & wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire wdata_rawIn_isZero_0 = wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _wdata_rawIn_isSpecial_T = wdata_rawIn_adjustedExp[11:10]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire wdata_rawIn_isSpecial = &_wdata_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _wdata_T_9 = wdata_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [12:0] _wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [53:0] _wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire wdata_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [12:0] wdata_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [53:0] wdata_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _wdata_rawIn_out_isNaN_T = ~wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _wdata_rawIn_out_isNaN_T_1 = wdata_rawIn_isSpecial & _wdata_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign wdata_rawIn_isNaN = _wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _wdata_rawIn_out_isInf_T = wdata_rawIn_isSpecial & wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign wdata_rawIn_isInf = _wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _wdata_rawIn_out_sExp_T_1 = {1'h0, _wdata_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign wdata_rawIn_sExp = _wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _wdata_rawIn_out_sig_T = ~wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _wdata_rawIn_out_sig_T_1 = {1'h0, _wdata_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [51:0] _wdata_rawIn_out_sig_T_2 = wdata_rawIn_isZeroExpIn ? wdata_rawIn_subnormFract : wdata_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _wdata_rawIn_out_sig_T_3 = {_wdata_rawIn_out_sig_T_1, _wdata_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign wdata_rawIn_sig = _wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _wdata_T_7 = wdata_rawIn_sExp[11:9]; // @[recFNFromFN.scala:48:50]
wire [2:0] _wdata_T_8 = wdata_rawIn_isZero_0 ? 3'h0 : _wdata_T_7; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _wdata_T_10 = {_wdata_T_8[2:1], _wdata_T_8[0] | _wdata_T_9}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _wdata_T_11 = {wdata_rawIn_sign_0, _wdata_T_10}; // @[recFNFromFN.scala:47:20, :48:76]
wire [8:0] _wdata_T_12 = wdata_rawIn_sExp[8:0]; // @[recFNFromFN.scala:50:23]
wire [12:0] _wdata_T_13 = {_wdata_T_11, _wdata_T_12}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [51:0] _wdata_T_14 = wdata_rawIn_sig[51:0]; // @[recFNFromFN.scala:51:22]
wire [64:0] _wdata_T_15 = {_wdata_T_13, _wdata_T_14}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire wdata_rawIn_sign_1 = _wdata_T_6[31]; // @[FPU.scala:431:23]
wire wdata_rawIn_1_sign = wdata_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] wdata_rawIn_expIn_1 = _wdata_T_6[30:23]; // @[FPU.scala:431:23]
wire [22:0] wdata_rawIn_fractIn_1 = _wdata_T_6[22:0]; // @[FPU.scala:431:23]
wire wdata_rawIn_isZeroExpIn_1 = wdata_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire wdata_rawIn_isZeroFractIn_1 = wdata_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _wdata_rawIn_normDist_T_102 = wdata_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_103 = wdata_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_104 = wdata_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_105 = wdata_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_106 = wdata_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_107 = wdata_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_108 = wdata_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_109 = wdata_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_110 = wdata_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_111 = wdata_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_112 = wdata_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_113 = wdata_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_114 = wdata_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_115 = wdata_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_116 = wdata_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_117 = wdata_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_118 = wdata_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_119 = wdata_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_120 = wdata_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_121 = wdata_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_122 = wdata_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_123 = wdata_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_124 = wdata_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _wdata_rawIn_normDist_T_125 = _wdata_rawIn_normDist_T_103 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_126 = _wdata_rawIn_normDist_T_104 ? 5'h14 : _wdata_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_127 = _wdata_rawIn_normDist_T_105 ? 5'h13 : _wdata_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_128 = _wdata_rawIn_normDist_T_106 ? 5'h12 : _wdata_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_129 = _wdata_rawIn_normDist_T_107 ? 5'h11 : _wdata_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_130 = _wdata_rawIn_normDist_T_108 ? 5'h10 : _wdata_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_131 = _wdata_rawIn_normDist_T_109 ? 5'hF : _wdata_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_132 = _wdata_rawIn_normDist_T_110 ? 5'hE : _wdata_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_133 = _wdata_rawIn_normDist_T_111 ? 5'hD : _wdata_rawIn_normDist_T_132; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_134 = _wdata_rawIn_normDist_T_112 ? 5'hC : _wdata_rawIn_normDist_T_133; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_135 = _wdata_rawIn_normDist_T_113 ? 5'hB : _wdata_rawIn_normDist_T_134; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_136 = _wdata_rawIn_normDist_T_114 ? 5'hA : _wdata_rawIn_normDist_T_135; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_137 = _wdata_rawIn_normDist_T_115 ? 5'h9 : _wdata_rawIn_normDist_T_136; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_138 = _wdata_rawIn_normDist_T_116 ? 5'h8 : _wdata_rawIn_normDist_T_137; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_139 = _wdata_rawIn_normDist_T_117 ? 5'h7 : _wdata_rawIn_normDist_T_138; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_140 = _wdata_rawIn_normDist_T_118 ? 5'h6 : _wdata_rawIn_normDist_T_139; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_141 = _wdata_rawIn_normDist_T_119 ? 5'h5 : _wdata_rawIn_normDist_T_140; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_142 = _wdata_rawIn_normDist_T_120 ? 5'h4 : _wdata_rawIn_normDist_T_141; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_143 = _wdata_rawIn_normDist_T_121 ? 5'h3 : _wdata_rawIn_normDist_T_142; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_144 = _wdata_rawIn_normDist_T_122 ? 5'h2 : _wdata_rawIn_normDist_T_143; // @[Mux.scala:50:70]
wire [4:0] _wdata_rawIn_normDist_T_145 = _wdata_rawIn_normDist_T_123 ? 5'h1 : _wdata_rawIn_normDist_T_144; // @[Mux.scala:50:70]
wire [4:0] wdata_rawIn_normDist_1 = _wdata_rawIn_normDist_T_124 ? 5'h0 : _wdata_rawIn_normDist_T_145; // @[Mux.scala:50:70]
wire [53:0] _wdata_rawIn_subnormFract_T_2 = {31'h0, wdata_rawIn_fractIn_1} << wdata_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _wdata_rawIn_subnormFract_T_3 = _wdata_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] wdata_rawIn_subnormFract_1 = {_wdata_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _wdata_rawIn_adjustedExp_T_5 = {4'hF, ~wdata_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _wdata_rawIn_adjustedExp_T_6 = wdata_rawIn_isZeroExpIn_1 ? _wdata_rawIn_adjustedExp_T_5 : {1'h0, wdata_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _wdata_rawIn_adjustedExp_T_7 = wdata_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _wdata_rawIn_adjustedExp_T_8 = {6'h20, _wdata_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _wdata_rawIn_adjustedExp_T_9 = {1'h0, _wdata_rawIn_adjustedExp_T_6} + {2'h0, _wdata_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] wdata_rawIn_adjustedExp_1 = _wdata_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _wdata_rawIn_out_sExp_T_2 = wdata_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire wdata_rawIn_isZero_1 = wdata_rawIn_isZeroExpIn_1 & wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire wdata_rawIn_1_isZero = wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _wdata_rawIn_isSpecial_T_1 = wdata_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire wdata_rawIn_isSpecial_1 = &_wdata_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _wdata_T_18 = wdata_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire wdata_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] wdata_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] wdata_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _wdata_rawIn_out_isNaN_T_2 = ~wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _wdata_rawIn_out_isNaN_T_3 = wdata_rawIn_isSpecial_1 & _wdata_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign wdata_rawIn_1_isNaN = _wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _wdata_rawIn_out_isInf_T_1 = wdata_rawIn_isSpecial_1 & wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign wdata_rawIn_1_isInf = _wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _wdata_rawIn_out_sExp_T_3 = {1'h0, _wdata_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign wdata_rawIn_1_sExp = _wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _wdata_rawIn_out_sig_T_4 = ~wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _wdata_rawIn_out_sig_T_5 = {1'h0, _wdata_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _wdata_rawIn_out_sig_T_6 = wdata_rawIn_isZeroExpIn_1 ? wdata_rawIn_subnormFract_1 : wdata_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _wdata_rawIn_out_sig_T_7 = {_wdata_rawIn_out_sig_T_5, _wdata_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign wdata_rawIn_1_sig = _wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _wdata_T_16 = wdata_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _wdata_T_17 = wdata_rawIn_1_isZero ? 3'h0 : _wdata_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _wdata_T_19 = {_wdata_T_17[2:1], _wdata_T_17[0] | _wdata_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _wdata_T_20 = {wdata_rawIn_1_sign, _wdata_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _wdata_T_21 = wdata_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _wdata_T_22 = {_wdata_T_20, _wdata_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _wdata_T_23 = wdata_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] _wdata_T_24 = {_wdata_T_22, _wdata_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire wdata_rawIn_sign_2 = _wdata_T_6[15]; // @[FPU.scala:431:23]
wire wdata_rawIn_2_sign = wdata_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [4:0] wdata_rawIn_expIn_2 = _wdata_T_6[14:10]; // @[FPU.scala:431:23]
wire [9:0] wdata_rawIn_fractIn_2 = _wdata_T_6[9:0]; // @[FPU.scala:431:23]
wire wdata_rawIn_isZeroExpIn_2 = wdata_rawIn_expIn_2 == 5'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire wdata_rawIn_isZeroFractIn_2 = wdata_rawIn_fractIn_2 == 10'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _wdata_rawIn_normDist_T_146 = wdata_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_147 = wdata_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_148 = wdata_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_149 = wdata_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_150 = wdata_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_151 = wdata_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_152 = wdata_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_153 = wdata_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_154 = wdata_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _wdata_rawIn_normDist_T_155 = wdata_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire [3:0] _wdata_rawIn_normDist_T_156 = {3'h4, ~_wdata_rawIn_normDist_T_147}; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_157 = _wdata_rawIn_normDist_T_148 ? 4'h7 : _wdata_rawIn_normDist_T_156; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_158 = _wdata_rawIn_normDist_T_149 ? 4'h6 : _wdata_rawIn_normDist_T_157; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_159 = _wdata_rawIn_normDist_T_150 ? 4'h5 : _wdata_rawIn_normDist_T_158; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_160 = _wdata_rawIn_normDist_T_151 ? 4'h4 : _wdata_rawIn_normDist_T_159; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_161 = _wdata_rawIn_normDist_T_152 ? 4'h3 : _wdata_rawIn_normDist_T_160; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_162 = _wdata_rawIn_normDist_T_153 ? 4'h2 : _wdata_rawIn_normDist_T_161; // @[Mux.scala:50:70]
wire [3:0] _wdata_rawIn_normDist_T_163 = _wdata_rawIn_normDist_T_154 ? 4'h1 : _wdata_rawIn_normDist_T_162; // @[Mux.scala:50:70]
wire [3:0] wdata_rawIn_normDist_2 = _wdata_rawIn_normDist_T_155 ? 4'h0 : _wdata_rawIn_normDist_T_163; // @[Mux.scala:50:70]
wire [24:0] _wdata_rawIn_subnormFract_T_4 = {15'h0, wdata_rawIn_fractIn_2} << wdata_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [8:0] _wdata_rawIn_subnormFract_T_5 = _wdata_rawIn_subnormFract_T_4[8:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [9:0] wdata_rawIn_subnormFract_2 = {_wdata_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [5:0] _wdata_rawIn_adjustedExp_T_10 = {2'h3, ~wdata_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_adjustedExp_T_11 = wdata_rawIn_isZeroExpIn_2 ? _wdata_rawIn_adjustedExp_T_10 : {1'h0, wdata_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _wdata_rawIn_adjustedExp_T_12 = wdata_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [4:0] _wdata_rawIn_adjustedExp_T_13 = {3'h4, _wdata_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [6:0] _wdata_rawIn_adjustedExp_T_14 = {1'h0, _wdata_rawIn_adjustedExp_T_11} + {2'h0, _wdata_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [5:0] wdata_rawIn_adjustedExp_2 = _wdata_rawIn_adjustedExp_T_14[5:0]; // @[rawFloatFromFN.scala:57:9]
wire [5:0] _wdata_rawIn_out_sExp_T_4 = wdata_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire wdata_rawIn_isZero_2 = wdata_rawIn_isZeroExpIn_2 & wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire wdata_rawIn_2_isZero = wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _wdata_rawIn_isSpecial_T_2 = wdata_rawIn_adjustedExp_2[5:4]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire wdata_rawIn_isSpecial_2 = &_wdata_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _wdata_T_27 = wdata_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [6:0] _wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [11:0] _wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire wdata_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [6:0] wdata_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [11:0] wdata_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _wdata_rawIn_out_isNaN_T_4 = ~wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _wdata_rawIn_out_isNaN_T_5 = wdata_rawIn_isSpecial_2 & _wdata_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign wdata_rawIn_2_isNaN = _wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _wdata_rawIn_out_isInf_T_2 = wdata_rawIn_isSpecial_2 & wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign wdata_rawIn_2_isInf = _wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _wdata_rawIn_out_sExp_T_5 = {1'h0, _wdata_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign wdata_rawIn_2_sExp = _wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _wdata_rawIn_out_sig_T_8 = ~wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _wdata_rawIn_out_sig_T_9 = {1'h0, _wdata_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [9:0] _wdata_rawIn_out_sig_T_10 = wdata_rawIn_isZeroExpIn_2 ? wdata_rawIn_subnormFract_2 : wdata_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _wdata_rawIn_out_sig_T_11 = {_wdata_rawIn_out_sig_T_9, _wdata_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign wdata_rawIn_2_sig = _wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _wdata_T_25 = wdata_rawIn_2_sExp[5:3]; // @[recFNFromFN.scala:48:50]
wire [2:0] _wdata_T_26 = wdata_rawIn_2_isZero ? 3'h0 : _wdata_T_25; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _wdata_T_28 = {_wdata_T_26[2:1], _wdata_T_26[0] | _wdata_T_27}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _wdata_T_29 = {wdata_rawIn_2_sign, _wdata_T_28}; // @[recFNFromFN.scala:47:20, :48:76]
wire [2:0] _wdata_T_30 = wdata_rawIn_2_sExp[2:0]; // @[recFNFromFN.scala:50:23]
wire [6:0] _wdata_T_31 = {_wdata_T_29, _wdata_T_30}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [9:0] _wdata_T_32 = wdata_rawIn_2_sig[9:0]; // @[recFNFromFN.scala:51:22]
wire [16:0] _wdata_T_33 = {_wdata_T_31, _wdata_T_32}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [3:0] _wdata_swizzledNaN_T = _wdata_T_24[32:29]; // @[FPU.scala:337:8]
wire [6:0] _wdata_swizzledNaN_T_1 = _wdata_T_24[22:16]; // @[FPU.scala:338:8]
wire [6:0] _wdata_swizzledNaN_T_5 = _wdata_T_24[22:16]; // @[FPU.scala:338:8, :341:8]
wire _wdata_swizzledNaN_T_2 = &_wdata_swizzledNaN_T_1; // @[FPU.scala:338:{8,42}]
wire [3:0] _wdata_swizzledNaN_T_3 = _wdata_T_24[27:24]; // @[FPU.scala:339:8]
wire _wdata_swizzledNaN_T_4 = _wdata_T_33[15]; // @[FPU.scala:340:8]
wire _wdata_swizzledNaN_T_6 = _wdata_T_33[16]; // @[FPU.scala:342:8]
wire [14:0] _wdata_swizzledNaN_T_7 = _wdata_T_33[14:0]; // @[FPU.scala:343:8]
wire [7:0] wdata_swizzledNaN_lo_hi = {_wdata_swizzledNaN_T_5, _wdata_swizzledNaN_T_6}; // @[FPU.scala:336:26, :341:8, :342:8]
wire [22:0] wdata_swizzledNaN_lo = {wdata_swizzledNaN_lo_hi, _wdata_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8]
wire [4:0] wdata_swizzledNaN_hi_lo = {_wdata_swizzledNaN_T_3, _wdata_swizzledNaN_T_4}; // @[FPU.scala:336:26, :339:8, :340:8]
wire [4:0] wdata_swizzledNaN_hi_hi = {_wdata_swizzledNaN_T, _wdata_swizzledNaN_T_2}; // @[FPU.scala:336:26, :337:8, :338:42]
wire [9:0] wdata_swizzledNaN_hi = {wdata_swizzledNaN_hi_hi, wdata_swizzledNaN_hi_lo}; // @[FPU.scala:336:26]
wire [32:0] wdata_swizzledNaN = {wdata_swizzledNaN_hi, wdata_swizzledNaN_lo}; // @[FPU.scala:336:26]
wire [2:0] _wdata_T_34 = _wdata_T_24[31:29]; // @[FPU.scala:249:25]
wire _wdata_T_35 = &_wdata_T_34; // @[FPU.scala:249:{25,56}]
wire [32:0] _wdata_T_36 = _wdata_T_35 ? wdata_swizzledNaN : _wdata_T_24; // @[FPU.scala:249:56, :336:26, :344:8]
wire [3:0] _wdata_swizzledNaN_T_8 = _wdata_T_15[64:61]; // @[FPU.scala:337:8]
wire [19:0] _wdata_swizzledNaN_T_9 = _wdata_T_15[51:32]; // @[FPU.scala:338:8]
wire [19:0] _wdata_swizzledNaN_T_13 = _wdata_T_15[51:32]; // @[FPU.scala:338:8, :341:8]
wire _wdata_swizzledNaN_T_10 = &_wdata_swizzledNaN_T_9; // @[FPU.scala:338:{8,42}]
wire [6:0] _wdata_swizzledNaN_T_11 = _wdata_T_15[59:53]; // @[FPU.scala:339:8]
wire _wdata_swizzledNaN_T_12 = _wdata_T_36[31]; // @[FPU.scala:340:8, :344:8]
wire _wdata_swizzledNaN_T_14 = _wdata_T_36[32]; // @[FPU.scala:342:8, :344:8]
wire [30:0] _wdata_swizzledNaN_T_15 = _wdata_T_36[30:0]; // @[FPU.scala:343:8, :344:8]
wire [20:0] wdata_swizzledNaN_lo_hi_1 = {_wdata_swizzledNaN_T_13, _wdata_swizzledNaN_T_14}; // @[FPU.scala:336:26, :341:8, :342:8]
wire [51:0] wdata_swizzledNaN_lo_1 = {wdata_swizzledNaN_lo_hi_1, _wdata_swizzledNaN_T_15}; // @[FPU.scala:336:26, :343:8]
wire [7:0] wdata_swizzledNaN_hi_lo_1 = {_wdata_swizzledNaN_T_11, _wdata_swizzledNaN_T_12}; // @[FPU.scala:336:26, :339:8, :340:8]
wire [4:0] wdata_swizzledNaN_hi_hi_1 = {_wdata_swizzledNaN_T_8, _wdata_swizzledNaN_T_10}; // @[FPU.scala:336:26, :337:8, :338:42]
wire [12:0] wdata_swizzledNaN_hi_1 = {wdata_swizzledNaN_hi_hi_1, wdata_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26]
wire [64:0] wdata_swizzledNaN_1 = {wdata_swizzledNaN_hi_1, wdata_swizzledNaN_lo_1}; // @[FPU.scala:336:26]
wire [2:0] _wdata_T_37 = _wdata_T_15[63:61]; // @[FPU.scala:249:25]
wire _wdata_T_38 = &_wdata_T_37; // @[FPU.scala:249:{25,56}]
wire [64:0] wdata = _wdata_T_38 ? wdata_swizzledNaN_1 : _wdata_T_15; // @[FPU.scala:249:56, :336:26, :344:8]
wire _unswizzled_T = wdata[31]; // @[FPU.scala:344:8, :381:10]
wire _frfWriteBundle_0_wrdata_prevRecoded_T = wdata[31]; // @[FPU.scala:344:8, :381:10, :442:10]
wire _unswizzled_T_1 = wdata[52]; // @[FPU.scala:344:8, :382:10]
wire _frfWriteBundle_0_wrdata_prevRecoded_T_1 = wdata[52]; // @[FPU.scala:344:8, :382:10, :443:10]
wire [30:0] _unswizzled_T_2 = wdata[30:0]; // @[FPU.scala:344:8, :383:10]
wire [30:0] _frfWriteBundle_0_wrdata_prevRecoded_T_2 = wdata[30:0]; // @[FPU.scala:344:8, :383:10, :444:10]
wire [1:0] unswizzled_hi = {_unswizzled_T, _unswizzled_T_1}; // @[FPU.scala:380:27, :381:10, :382:10]
wire [32:0] unswizzled = {unswizzled_hi, _unswizzled_T_2}; // @[FPU.scala:380:27, :383:10]
wire [4:0] _prevOK_T = wdata[64:60]; // @[FPU.scala:332:49, :344:8]
wire _prevOK_T_1 = &_prevOK_T; // @[FPU.scala:332:{49,84}]
wire _prevOK_T_2 = ~_prevOK_T_1; // @[FPU.scala:332:84, :384:20]
wire _prevOK_unswizzled_T = unswizzled[15]; // @[FPU.scala:380:27, :381:10]
wire _prevOK_unswizzled_T_1 = unswizzled[23]; // @[FPU.scala:380:27, :382:10]
wire [14:0] _prevOK_unswizzled_T_2 = unswizzled[14:0]; // @[FPU.scala:380:27, :383:10]
wire [1:0] prevOK_unswizzled_hi = {_prevOK_unswizzled_T, _prevOK_unswizzled_T_1}; // @[FPU.scala:380:27, :381:10, :382:10]
wire [16:0] prevOK_unswizzled = {prevOK_unswizzled_hi, _prevOK_unswizzled_T_2}; // @[FPU.scala:380:27, :383:10]
wire [4:0] _prevOK_prevOK_T = unswizzled[32:28]; // @[FPU.scala:332:49, :380:27]
wire _prevOK_prevOK_T_1 = &_prevOK_prevOK_T; // @[FPU.scala:332:{49,84}]
wire _prevOK_prevOK_T_2 = ~_prevOK_prevOK_T_1; // @[FPU.scala:332:84, :384:20]
wire [2:0] _prevOK_curOK_T = unswizzled[31:29]; // @[FPU.scala:249:25, :380:27]
wire _prevOK_curOK_T_1 = &_prevOK_curOK_T; // @[FPU.scala:249:{25,56}]
wire _prevOK_curOK_T_2 = ~_prevOK_curOK_T_1; // @[FPU.scala:249:56, :385:19]
wire _prevOK_curOK_T_3 = unswizzled[28]; // @[FPU.scala:380:27, :385:35]
wire [6:0] _prevOK_curOK_T_4 = unswizzled[22:16]; // @[FPU.scala:380:27, :385:60]
wire _prevOK_curOK_T_5 = &_prevOK_curOK_T_4; // @[FPU.scala:385:{60,96}]
wire _prevOK_curOK_T_6 = _prevOK_curOK_T_3 == _prevOK_curOK_T_5; // @[FPU.scala:385:{35,55,96}]
wire prevOK_curOK = _prevOK_curOK_T_2 | _prevOK_curOK_T_6; // @[FPU.scala:385:{19,31,55}]
wire _prevOK_T_3 = prevOK_curOK; // @[FPU.scala:385:31, :386:14]
wire prevOK = _prevOK_T_2 | _prevOK_T_3; // @[FPU.scala:384:{20,33}, :386:14]
wire [2:0] _curOK_T = wdata[63:61]; // @[FPU.scala:249:25, :344:8]
wire [2:0] _frfWriteBundle_0_wrdata_T_1 = wdata[63:61]; // @[FPU.scala:249:25, :344:8]
wire _curOK_T_1 = &_curOK_T; // @[FPU.scala:249:{25,56}]
wire _curOK_T_2 = ~_curOK_T_1; // @[FPU.scala:249:56, :385:19]
wire _curOK_T_3 = wdata[60]; // @[FPU.scala:344:8, :385:35]
wire [19:0] _curOK_T_4 = wdata[51:32]; // @[FPU.scala:344:8, :385:60]
wire _curOK_T_5 = &_curOK_T_4; // @[FPU.scala:385:{60,96}]
wire _curOK_T_6 = _curOK_T_3 == _curOK_T_5; // @[FPU.scala:385:{35,55,96}]
wire curOK = _curOK_T_2 | _curOK_T_6; // @[FPU.scala:385:{19,31,55}]
wire [11:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_exp = wdata[63:52]; // @[FPU.scala:344:8]
wire [2:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T = wdata[64]; // @[FPU.scala:344:8]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2 = wdata[51:0]; // @[FPU.scala:344:8]
assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire frfWriteBundle_0_wrdata_unrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] frfWriteBundle_0_wrdata_unrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _frfWriteBundle_0_wrdata_unrecoded_denormFract_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_unrecoded_denormFract_T >> frfWriteBundle_0_wrdata_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] frfWriteBundle_0_wrdata_unrecoded_denormFract = _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_unrecoded_isSubnormal ? 11'h0 : _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _frfWriteBundle_0_wrdata_unrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5 = {11{_frfWriteBundle_0_wrdata_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] frfWriteBundle_0_wrdata_unrecoded_expOut = _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_fractOut_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf ? 52'h0 : _frfWriteBundle_0_wrdata_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] frfWriteBundle_0_wrdata_unrecoded_fractOut = frfWriteBundle_0_wrdata_unrecoded_isSubnormal ? frfWriteBundle_0_wrdata_unrecoded_denormFract : _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] frfWriteBundle_0_wrdata_unrecoded_hi = {frfWriteBundle_0_wrdata_unrecoded_rawIn_sign, frfWriteBundle_0_wrdata_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] frfWriteBundle_0_wrdata_unrecoded = {frfWriteBundle_0_wrdata_unrecoded_hi, frfWriteBundle_0_wrdata_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [1:0] frfWriteBundle_0_wrdata_prevRecoded_hi = {_frfWriteBundle_0_wrdata_prevRecoded_T, _frfWriteBundle_0_wrdata_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] frfWriteBundle_0_wrdata_prevRecoded = {frfWriteBundle_0_wrdata_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [8:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp = frfWriteBundle_0_wrdata_prevRecoded[31:23]; // @[FPU.scala:441:28]
wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = frfWriteBundle_0_wrdata_prevRecoded[32]; // @[FPU.scala:441:28]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = frfWriteBundle_0_wrdata_prevRecoded[22:0]; // @[FPU.scala:441:28]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T >> frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5 = {8{_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal ? frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi = {frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T = frfWriteBundle_0_wrdata_prevRecoded[15]; // @[FPU.scala:441:28, :442:10]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1 = frfWriteBundle_0_wrdata_prevRecoded[23]; // @[FPU.scala:441:28, :443:10]
wire [14:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2 = frfWriteBundle_0_wrdata_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10]
wire [1:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi = {_frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [16:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [5:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28]
wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28]
assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23]
wire [3:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [3:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35]
wire [10:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T >> frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [4:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal ? frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [5:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi = {frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [15:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21]
wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_1 = frfWriteBundle_0_wrdata_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28]
wire _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 = &_frfWriteBundle_0_wrdata_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}]
wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81]
wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_4 = _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 ? frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded : _frfWriteBundle_0_wrdata_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}]
wire [31:0] frfWriteBundle_0_wrdata_prevUnrecoded = {_frfWriteBundle_0_wrdata_prevUnrecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _frfWriteBundle_0_wrdata_T = frfWriteBundle_0_wrdata_unrecoded[63:32]; // @[FPU.scala:446:21]
wire _frfWriteBundle_0_wrdata_T_2 = &_frfWriteBundle_0_wrdata_T_1; // @[FPU.scala:249:{25,56}]
wire [31:0] _frfWriteBundle_0_wrdata_T_3 = frfWriteBundle_0_wrdata_unrecoded[31:0]; // @[FPU.scala:446:81]
wire [31:0] _frfWriteBundle_0_wrdata_T_4 = _frfWriteBundle_0_wrdata_T_2 ? frfWriteBundle_0_wrdata_prevUnrecoded : _frfWriteBundle_0_wrdata_T_3; // @[FPU.scala:249:56, :446:{10,44,81}]
assign _frfWriteBundle_0_wrdata_T_5 = {_frfWriteBundle_0_wrdata_T, _frfWriteBundle_0_wrdata_T_4}; // @[FPU.scala:446:{10,21,44}]
assign frfWriteBundle_0_wrdata = _frfWriteBundle_0_wrdata_T_5; // @[FPU.scala:446:10, :805:44]
wire [4:0] _ex_rs_T_1 = _ex_rs_T; // @[FPU.scala:832:37]
wire [4:0] _ex_rs_T_3 = _ex_rs_T_2; // @[FPU.scala:832:37]
wire [4:0] _ex_rs_T_5 = _ex_rs_T_4; // @[FPU.scala:832:37]
wire [4:0] _ex_ra_0_T = io_inst_0[19:15]; // @[FPU.scala:735:7, :835:51]
wire [4:0] _ex_ra_1_T = io_inst_0[19:15]; // @[FPU.scala:735:7, :835:51, :836:50]
wire [4:0] _ex_ra_0_T_1 = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50]
wire [4:0] _ex_ra_2_T = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50, :840:50]
wire [4:0] _ex_ra_1_T_1 = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50, :841:70]
wire [4:0] _ex_ra_2_T_1 = io_inst_0[31:27]; // @[FPU.scala:735:7, :843:46]
wire [2:0] _ex_rm_T = ex_reg_inst[14:12]; // @[FPU.scala:768:30, :845:30]
wire [2:0] _ex_rm_T_2 = ex_reg_inst[14:12]; // @[FPU.scala:768:30, :845:{30,70}]
wire _ex_rm_T_1 = &_ex_rm_T; // @[FPU.scala:845:{30,38}]
wire [2:0] ex_rm = _ex_rm_T_1 ? io_fcsr_rm_0 : _ex_rm_T_2; // @[FPU.scala:735:7, :845:{18,38,70}]
wire [2:0] sfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19]
wire [2:0] fpiu_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19]
wire [2:0] dfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19]
wire [2:0] hfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19]
wire _GEN_0 = req_valid & ex_ctrl_fma; // @[FPU.scala:780:32, :800:20, :873:33]
wire _sfma_io_in_valid_T; // @[FPU.scala:873:33]
assign _sfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33]
wire _dfma_io_in_valid_T; // @[FPU.scala:914:41]
assign _dfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33, :914:41]
wire _hfma_io_in_valid_T; // @[FPU.scala:920:41]
assign _hfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33, :920:41]
wire _GEN_1 = ex_ctrl_typeTagOut == 2'h1; // @[FPU.scala:800:20, :873:70]
wire _sfma_io_in_valid_T_1; // @[FPU.scala:873:70]
assign _sfma_io_in_valid_T_1 = _GEN_1; // @[FPU.scala:873:70]
wire _write_port_busy_T_2; // @[FPU.scala:911:72]
assign _write_port_busy_T_2 = _GEN_1; // @[FPU.scala:873:70, :911:72]
wire _write_port_busy_T_20; // @[FPU.scala:911:72]
assign _write_port_busy_T_20 = _GEN_1; // @[FPU.scala:873:70, :911:72]
wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T & _sfma_io_in_valid_T_1; // @[FPU.scala:873:{33,48,70}]
wire [1:0] _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36]
wire [1:0] _sfma_io_in_bits_req_typ_T; // @[FPU.scala:855:27]
wire [1:0] _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:856:27]
wire [1:0] sfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19]
wire [1:0] sfma_io_in_bits_req_typ; // @[FPU.scala:848:19]
wire [1:0] sfma_io_in_bits_req_fmt; // @[FPU.scala:848:19]
wire [64:0] sfma_io_in_bits_req_in1; // @[FPU.scala:848:19]
wire [64:0] sfma_io_in_bits_req_in2; // @[FPU.scala:848:19]
wire [64:0] sfma_io_in_bits_req_in3; // @[FPU.scala:848:19]
wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20]
wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20]
wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20]
wire _hfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20]
wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20]
wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20]
wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20]
wire _hfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20]
wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _hfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in1_floats_1[15]; // @[FPU.scala:356:31, :357:14]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in1_floats_1[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in1_floats_1[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31]
wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}]
wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in1_floats_1[32:28]; // @[FPU.scala:332:49, :356:31]
wire sfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in1_prev_prev_0_1 = sfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _hfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in1_oks_1 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox & sfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in1_sign = _regfile_ext_R2_data[64]; // @[FPU.scala:274:17, :818:20]
wire hfma_io_in_bits_req_in1_sign = _regfile_ext_R2_data[64]; // @[FPU.scala:274:17, :818:20]
wire [51:0] sfma_io_in_bits_req_in1_fractIn = _regfile_ext_R2_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [51:0] hfma_io_in_bits_req_in1_fractIn = _regfile_ext_R2_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [11:0] sfma_io_in_bits_req_in1_expIn = _regfile_ext_R2_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [11:0] hfma_io_in_bits_req_in1_expIn = _regfile_ext_R2_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T | _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in1_floats_2 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_1 | _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26, :848:19, :852:13]
wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20]
wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20]
wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20]
wire _hfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20]
wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20]
wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20]
wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20]
wire _hfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20]
wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _hfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in2_floats_1[15]; // @[FPU.scala:356:31, :357:14]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in2_floats_1[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in2_floats_1[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31]
wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}]
wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in2_floats_1[32:28]; // @[FPU.scala:332:49, :356:31]
wire sfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in2_prev_prev_0_1 = sfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _hfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in2_oks_1 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox & sfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in2_sign = _regfile_ext_R1_data[64]; // @[FPU.scala:274:17, :818:20]
wire hfma_io_in_bits_req_in2_sign = _regfile_ext_R1_data[64]; // @[FPU.scala:274:17, :818:20]
wire [51:0] sfma_io_in_bits_req_in2_fractIn = _regfile_ext_R1_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [51:0] hfma_io_in_bits_req_in2_fractIn = _regfile_ext_R1_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [11:0] sfma_io_in_bits_req_in2_expIn = _regfile_ext_R1_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [11:0] hfma_io_in_bits_req_in2_expIn = _regfile_ext_R1_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T | _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in2_floats_2 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_1 | _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26, :848:19, :853:13]
wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20]
wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20]
wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20]
wire _hfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20]
wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20]
wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20]
wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20]
wire _hfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20]
wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [30:0] _hfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20]
wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in3_floats_1[15]; // @[FPU.scala:356:31, :357:14]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in3_floats_1[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in3_floats_1[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31]
wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}]
wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in3_floats_1[32:28]; // @[FPU.scala:332:49, :356:31]
wire sfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in3_prev_prev_0_1 = sfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire [4:0] _hfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20]
wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire sfma_io_in_bits_req_in3_oks_1 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox & sfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire sfma_io_in_bits_req_in3_sign = _regfile_ext_R0_data[64]; // @[FPU.scala:274:17, :818:20]
wire hfma_io_in_bits_req_in3_sign = _regfile_ext_R0_data[64]; // @[FPU.scala:274:17, :818:20]
wire [51:0] sfma_io_in_bits_req_in3_fractIn = _regfile_ext_R0_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [51:0] hfma_io_in_bits_req_in3_fractIn = _regfile_ext_R0_data[51:0]; // @[FPU.scala:275:20, :818:20]
wire [11:0] sfma_io_in_bits_req_in3_expIn = _regfile_ext_R0_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [11:0] hfma_io_in_bits_req_in3_expIn = _regfile_ext_R0_data[63:52]; // @[FPU.scala:276:18, :818:20]
wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T | _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] sfma_io_in_bits_req_in3_floats_2 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_1 | _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}]
assign sfma_io_in_bits_req_in3 = {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26, :848:19, :854:13]
assign _sfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27]
wire [1:0] _fpiu_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27]
wire [1:0] _dfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27]
wire [1:0] _hfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27]
assign sfma_io_in_bits_req_typ = _sfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27]
assign _sfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27]
wire [1:0] _fpiu_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27]
wire [1:0] _dfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27]
wire [1:0] _hfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27]
assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27]
wire [1:0] _sfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30]
wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30]
wire [1:0] _dfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30]
wire [1:0] _hfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30]
wire _sfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39]
wire _sfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67]
wire _fpiu_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67]
wire _dfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67]
wire _hfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67]
wire _sfma_io_in_bits_req_fmaCmd_T_3 = _sfma_io_in_bits_req_fmaCmd_T_1 & _sfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}]
assign _sfma_io_in_bits_req_fmaCmd_T_4 = {_sfma_io_in_bits_req_fmaCmd_T[1], _sfma_io_in_bits_req_fmaCmd_T[0] | _sfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}]
assign sfma_io_in_bits_req_fmaCmd = _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36]
wire _fpiu_io_in_valid_T = ex_ctrl_toint | ex_ctrl_div; // @[FPU.scala:800:20, :877:51]
wire _fpiu_io_in_valid_T_1 = _fpiu_io_in_valid_T | ex_ctrl_sqrt; // @[FPU.scala:800:20, :877:{51,66}]
wire _fpiu_io_in_valid_T_2 = ex_ctrl_fastpipe & ex_ctrl_wflags; // @[FPU.scala:800:20, :877:103]
wire _fpiu_io_in_valid_T_3 = _fpiu_io_in_valid_T_1 | _fpiu_io_in_valid_T_2; // @[FPU.scala:877:{66,82,103}]
wire _fpiu_io_in_valid_T_4 = req_valid & _fpiu_io_in_valid_T_3; // @[FPU.scala:780:32, :877:{33,82}]
wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36]
wire [64:0] _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10]
wire [64:0] _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10]
wire [64:0] _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10]
wire [1:0] fpiu_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19]
wire [1:0] fpiu_io_in_bits_req_typ; // @[FPU.scala:848:19]
wire [1:0] fpiu_io_in_bits_req_fmt; // @[FPU.scala:848:19]
wire [64:0] fpiu_io_in_bits_req_in1; // @[FPU.scala:848:19]
wire [64:0] fpiu_io_in_bits_req_in2; // @[FPU.scala:848:19]
wire [64:0] fpiu_io_in_bits_req_in3; // @[FPU.scala:848:19]
wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire fpiu_io_in_bits_req_in1_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in1_prev_prev_0_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in1_floats_1 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in1_oks_1 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox & fpiu_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire _GEN_2 = ex_ctrl_typeTagIn == 2'h1; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in1_T = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_6; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in1_T_6 = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in2_T = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T_6; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in2_T_6 = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in3_T = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T_6; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in3_T_6 = _GEN_2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T ? fpiu_io_in_bits_req_in1_oks_1 : fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}]
wire _GEN_3 = ex_ctrl_typeTagIn == 2'h2; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_2; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in1_T_2 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_8; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in1_T_8 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T_2; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in2_T_2 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T_8; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in2_T_8 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T_2; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in3_T_2 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T_8; // @[package.scala:39:86]
assign _fpiu_io_in_bits_req_in3_T_8 = _GEN_3; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 | _fpiu_io_in_bits_req_in1_T_1; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in1_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in1_T_5 = _fpiu_io_in_bits_req_in1_T_4 | _fpiu_io_in_bits_req_in1_T_3; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in1_T_7 = _fpiu_io_in_bits_req_in1_T_6 ? fpiu_io_in_bits_req_in1_floats_1 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in1_T_9 = _fpiu_io_in_bits_req_in1_T_8 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in1_T_7; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in1_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire [64:0] _fpiu_io_in_bits_req_in1_T_11 = _fpiu_io_in_bits_req_in1_T_10 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in1_T_9; // @[package.scala:39:{76,86}]
assign _fpiu_io_in_bits_req_in1_T_12 = _fpiu_io_in_bits_req_in1_T_5 ? _fpiu_io_in_bits_req_in1_T_11 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10, :848:19]
wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire fpiu_io_in_bits_req_in2_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in2_prev_prev_0_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in2_floats_1 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in2_oks_1 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox & fpiu_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T ? fpiu_io_in_bits_req_in2_oks_1 : fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 | _fpiu_io_in_bits_req_in2_T_1; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in2_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in2_T_5 = _fpiu_io_in_bits_req_in2_T_4 | _fpiu_io_in_bits_req_in2_T_3; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in2_T_7 = _fpiu_io_in_bits_req_in2_T_6 ? fpiu_io_in_bits_req_in2_floats_1 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in2_T_9 = _fpiu_io_in_bits_req_in2_T_8 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in2_T_7; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in2_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire [64:0] _fpiu_io_in_bits_req_in2_T_11 = _fpiu_io_in_bits_req_in2_T_10 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in2_T_9; // @[package.scala:39:{76,86}]
assign _fpiu_io_in_bits_req_in2_T_12 = _fpiu_io_in_bits_req_in2_T_5 ? _fpiu_io_in_bits_req_in2_T_11 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10, :848:19]
wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire fpiu_io_in_bits_req_in3_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in3_prev_prev_0_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] fpiu_io_in_bits_req_in3_floats_1 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire fpiu_io_in_bits_req_in3_oks_1 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox & fpiu_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T ? fpiu_io_in_bits_req_in3_oks_1 : fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 | _fpiu_io_in_bits_req_in3_T_1; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in3_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire _fpiu_io_in_bits_req_in3_T_5 = _fpiu_io_in_bits_req_in3_T_4 | _fpiu_io_in_bits_req_in3_T_3; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in3_T_7 = _fpiu_io_in_bits_req_in3_T_6 ? fpiu_io_in_bits_req_in3_floats_1 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}]
wire [64:0] _fpiu_io_in_bits_req_in3_T_9 = _fpiu_io_in_bits_req_in3_T_8 ? _regfile_ext_R0_data : _fpiu_io_in_bits_req_in3_T_7; // @[package.scala:39:{76,86}]
wire _fpiu_io_in_bits_req_in3_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86]
wire [64:0] _fpiu_io_in_bits_req_in3_T_11 = _fpiu_io_in_bits_req_in3_T_10 ? _regfile_ext_R0_data : _fpiu_io_in_bits_req_in3_T_9; // @[package.scala:39:{76,86}]
assign _fpiu_io_in_bits_req_in3_T_12 = _fpiu_io_in_bits_req_in3_T_5 ? _fpiu_io_in_bits_req_in3_T_11 : 65'hE008000000000000; // @[package.scala:39:76]
assign fpiu_io_in_bits_req_in3 = _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10, :848:19]
assign fpiu_io_in_bits_req_typ = _fpiu_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27]
assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27]
wire _fpiu_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39]
wire _fpiu_io_in_bits_req_fmaCmd_T_3 = _fpiu_io_in_bits_req_fmaCmd_T_1 & _fpiu_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}]
assign _fpiu_io_in_bits_req_fmaCmd_T_4 = {_fpiu_io_in_bits_req_fmaCmd_T[1], _fpiu_io_in_bits_req_fmaCmd_T[0] | _fpiu_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}]
assign fpiu_io_in_bits_req_fmaCmd = _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36]
wire _ifpu_io_in_valid_T = req_valid & ex_ctrl_fromint; // @[FPU.scala:780:32, :800:20, :887:33]
wire [64:0] _ifpu_io_in_bits_in1_T = {1'h0, io_fromint_data_0}; // @[FPU.scala:735:7, :889:29]
wire _fpmu_io_in_valid_T = req_valid & ex_ctrl_fastpipe; // @[FPU.scala:780:32, :800:20, :892:33]
wire divSqrt_wen; // @[FPU.scala:896:32]
wire divSqrt_inFlight; // @[FPU.scala:897:37]
reg [4:0] divSqrt_waddr; // @[FPU.scala:898:26]
reg divSqrt_cp; // @[FPU.scala:899:23]
wire [1:0] divSqrt_typeTag; // @[FPU.scala:900:29]
wire [64:0] divSqrt_wdata; // @[FPU.scala:901:27]
wire [4:0] divSqrt_flags; // @[FPU.scala:902:27]
wire _GEN_4 = ex_ctrl_typeTagOut == 2'h2; // @[FPU.scala:800:20, :914:78]
wire _dfma_io_in_valid_T_1; // @[FPU.scala:914:78]
assign _dfma_io_in_valid_T_1 = _GEN_4; // @[FPU.scala:914:78]
wire _write_port_busy_T_5; // @[FPU.scala:916:78]
assign _write_port_busy_T_5 = _GEN_4; // @[FPU.scala:914:78, :916:78]
wire _write_port_busy_T_23; // @[FPU.scala:916:78]
assign _write_port_busy_T_23 = _GEN_4; // @[FPU.scala:914:78, :916:78]
wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T & _dfma_io_in_valid_T_1; // @[FPU.scala:914:{41,56,78}]
wire [1:0] _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36]
wire [64:0] _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26]
wire [64:0] _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26]
wire [64:0] _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26]
wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19]
wire [1:0] dfma_io_in_bits_req_typ; // @[FPU.scala:848:19]
wire [1:0] dfma_io_in_bits_req_fmt; // @[FPU.scala:848:19]
wire [64:0] dfma_io_in_bits_req_in1; // @[FPU.scala:848:19]
wire [64:0] dfma_io_in_bits_req_in2; // @[FPU.scala:848:19]
wire [64:0] dfma_io_in_bits_req_in3; // @[FPU.scala:848:19]
wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire dfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in1_prev_prev_0_1 = dfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in1_floats_1 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in1_oks_1 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox & dfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26, :848:19]
wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire dfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in2_prev_prev_0_1 = dfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in2_floats_1 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in2_oks_1 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox & dfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26, :848:19]
wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31]
wire [9:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31]
wire [5:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31]
wire [62:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [4:0] _dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire dfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in3_prev_prev_0_1 = dfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] dfma_io_in_bits_req_in3_floats_1 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire dfma_io_in_bits_req_in3_oks_1 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox & dfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
assign dfma_io_in_bits_req_in3 = _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26, :848:19]
assign dfma_io_in_bits_req_typ = _dfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27]
assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27]
wire _dfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39]
wire _dfma_io_in_bits_req_fmaCmd_T_3 = _dfma_io_in_bits_req_fmaCmd_T_1 & _dfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}]
assign _dfma_io_in_bits_req_fmaCmd_T_4 = {_dfma_io_in_bits_req_fmaCmd_T[1], _dfma_io_in_bits_req_fmaCmd_T[0] | _dfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}]
assign dfma_io_in_bits_req_fmaCmd = _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36]
wire _GEN_5 = ex_ctrl_typeTagOut == 2'h0; // @[FPU.scala:800:20, :920:78]
wire _hfma_io_in_valid_T_1; // @[FPU.scala:920:78]
assign _hfma_io_in_valid_T_1 = _GEN_5; // @[FPU.scala:920:78]
wire _write_port_busy_T_8; // @[FPU.scala:922:78]
assign _write_port_busy_T_8 = _GEN_5; // @[FPU.scala:920:78, :922:78]
wire _write_port_busy_T_26; // @[FPU.scala:922:78]
assign _write_port_busy_T_26 = _GEN_5; // @[FPU.scala:920:78, :922:78]
wire _hfma_io_in_valid_T_2 = _hfma_io_in_valid_T & _hfma_io_in_valid_T_1; // @[FPU.scala:920:{41,56,78}]
wire [1:0] _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36]
wire [1:0] hfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19]
wire [1:0] hfma_io_in_bits_req_typ; // @[FPU.scala:848:19]
wire [1:0] hfma_io_in_bits_req_fmt; // @[FPU.scala:848:19]
wire [64:0] hfma_io_in_bits_req_in1; // @[FPU.scala:848:19]
wire [64:0] hfma_io_in_bits_req_in2; // @[FPU.scala:848:19]
wire [64:0] hfma_io_in_bits_req_in3; // @[FPU.scala:848:19]
wire [1:0] hfma_io_in_bits_req_in1_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] hfma_io_in_bits_req_in1_prev_unswizzled = {hfma_io_in_bits_req_in1_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] hfma_io_in_bits_req_in1_floats_0 = {hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire hfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in1_prev_prev_0_1 = hfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in1_prev_prev_sign = hfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] hfma_io_in_bits_req_in1_prev_prev_fractIn = hfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expIn = hfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _hfma_io_in_bits_req_in1_prev_prev_fractOut_T = {hfma_io_in_bits_req_in1_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in1_prev_prev_fractOut = _hfma_io_in_bits_req_in1_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in1_prev_prev_expOut_expCode = hfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31]
wire [8:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}]
wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in1_prev_prev_expOut_T | _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in1_prev_prev_expOut = _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in1_prev_prev_hi = {hfma_io_in_bits_req_in1_prev_prev_sign, hfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in1_floats_1 = {hfma_io_in_bits_req_in1_prev_prev_hi, hfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire hfma_io_in_bits_req_in1_prev_isbox = &_hfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in1_oks_1 = hfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in1_oks_0 = hfma_io_in_bits_req_in1_prev_isbox & hfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire [62:0] _hfma_io_in_bits_req_in1_fractOut_T = {hfma_io_in_bits_req_in1_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in1_fractOut = _hfma_io_in_bits_req_in1_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in1_expOut_expCode = hfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] hfma_io_in_bits_req_in1_expOut_commonCase = _hfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in1_expOut_T = hfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in1_expOut_T_1 = hfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in1_expOut_T_2 = _hfma_io_in_bits_req_in1_expOut_T | _hfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in1_expOut_T_3 = hfma_io_in_bits_req_in1_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_4 = {hfma_io_in_bits_req_in1_expOut_expCode, _hfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_5 = hfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in1_expOut = _hfma_io_in_bits_req_in1_expOut_T_2 ? _hfma_io_in_bits_req_in1_expOut_T_4 : _hfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in1_hi = {hfma_io_in_bits_req_in1_sign, hfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in1_floats_2 = {hfma_io_in_bits_req_in1_hi, hfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [16:0] _hfma_io_in_bits_req_in1_T = hfma_io_in_bits_req_in1_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31]
wire [16:0] _hfma_io_in_bits_req_in1_T_1 = hfma_io_in_bits_req_in1_floats_0 | _hfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}]
assign hfma_io_in_bits_req_in1 = {48'h0, _hfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26, :848:19, :852:13]
wire [1:0] hfma_io_in_bits_req_in2_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] hfma_io_in_bits_req_in2_prev_unswizzled = {hfma_io_in_bits_req_in2_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] hfma_io_in_bits_req_in2_floats_0 = {hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire hfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in2_prev_prev_0_1 = hfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in2_prev_prev_sign = hfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] hfma_io_in_bits_req_in2_prev_prev_fractIn = hfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expIn = hfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _hfma_io_in_bits_req_in2_prev_prev_fractOut_T = {hfma_io_in_bits_req_in2_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in2_prev_prev_fractOut = _hfma_io_in_bits_req_in2_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in2_prev_prev_expOut_expCode = hfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31]
wire [8:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}]
wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in2_prev_prev_expOut_T | _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in2_prev_prev_expOut = _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in2_prev_prev_hi = {hfma_io_in_bits_req_in2_prev_prev_sign, hfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in2_floats_1 = {hfma_io_in_bits_req_in2_prev_prev_hi, hfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire hfma_io_in_bits_req_in2_prev_isbox = &_hfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in2_oks_1 = hfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in2_oks_0 = hfma_io_in_bits_req_in2_prev_isbox & hfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire [62:0] _hfma_io_in_bits_req_in2_fractOut_T = {hfma_io_in_bits_req_in2_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in2_fractOut = _hfma_io_in_bits_req_in2_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in2_expOut_expCode = hfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] hfma_io_in_bits_req_in2_expOut_commonCase = _hfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in2_expOut_T = hfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in2_expOut_T_1 = hfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in2_expOut_T_2 = _hfma_io_in_bits_req_in2_expOut_T | _hfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in2_expOut_T_3 = hfma_io_in_bits_req_in2_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_4 = {hfma_io_in_bits_req_in2_expOut_expCode, _hfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_5 = hfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in2_expOut = _hfma_io_in_bits_req_in2_expOut_T_2 ? _hfma_io_in_bits_req_in2_expOut_T_4 : _hfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in2_hi = {hfma_io_in_bits_req_in2_sign, hfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in2_floats_2 = {hfma_io_in_bits_req_in2_hi, hfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [16:0] _hfma_io_in_bits_req_in2_T = hfma_io_in_bits_req_in2_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31]
wire [16:0] _hfma_io_in_bits_req_in2_T_1 = hfma_io_in_bits_req_in2_floats_0 | _hfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}]
assign hfma_io_in_bits_req_in2 = {48'h0, _hfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26, :848:19, :852:13, :853:13]
wire [1:0] hfma_io_in_bits_req_in3_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] hfma_io_in_bits_req_in3_prev_unswizzled = {hfma_io_in_bits_req_in3_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14]
wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14]
wire [14:0] _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14]
wire [1:0] hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [16:0] hfma_io_in_bits_req_in3_floats_0 = {hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31]
wire hfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in3_prev_prev_0_1 = hfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in3_prev_prev_sign = hfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] hfma_io_in_bits_req_in3_prev_prev_fractIn = hfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expIn = hfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [33:0] _hfma_io_in_bits_req_in3_prev_prev_fractOut_T = {hfma_io_in_bits_req_in3_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in3_prev_prev_fractOut = _hfma_io_in_bits_req_in3_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in3_prev_prev_expOut_expCode = hfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31]
wire [8:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31]
wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}]
wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in3_prev_prev_expOut_T | _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in3_prev_prev_expOut = _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in3_prev_prev_hi = {hfma_io_in_bits_req_in3_prev_prev_sign, hfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in3_floats_1 = {hfma_io_in_bits_req_in3_prev_prev_hi, hfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire hfma_io_in_bits_req_in3_prev_isbox = &_hfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire hfma_io_in_bits_req_in3_oks_1 = hfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire hfma_io_in_bits_req_in3_oks_0 = hfma_io_in_bits_req_in3_prev_isbox & hfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32]
wire [62:0] _hfma_io_in_bits_req_in3_fractOut_T = {hfma_io_in_bits_req_in3_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] hfma_io_in_bits_req_in3_fractOut = _hfma_io_in_bits_req_in3_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] hfma_io_in_bits_req_in3_expOut_expCode = hfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] hfma_io_in_bits_req_in3_expOut_commonCase = _hfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _hfma_io_in_bits_req_in3_expOut_T = hfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _hfma_io_in_bits_req_in3_expOut_T_1 = hfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _hfma_io_in_bits_req_in3_expOut_T_2 = _hfma_io_in_bits_req_in3_expOut_T | _hfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _hfma_io_in_bits_req_in3_expOut_T_3 = hfma_io_in_bits_req_in3_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_4 = {hfma_io_in_bits_req_in3_expOut_expCode, _hfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_5 = hfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] hfma_io_in_bits_req_in3_expOut = _hfma_io_in_bits_req_in3_expOut_T_2 ? _hfma_io_in_bits_req_in3_expOut_T_4 : _hfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] hfma_io_in_bits_req_in3_hi = {hfma_io_in_bits_req_in3_sign, hfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] hfma_io_in_bits_req_in3_floats_2 = {hfma_io_in_bits_req_in3_hi, hfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [16:0] _hfma_io_in_bits_req_in3_T = hfma_io_in_bits_req_in3_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31]
wire [16:0] _hfma_io_in_bits_req_in3_T_1 = hfma_io_in_bits_req_in3_floats_0 | _hfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}]
assign hfma_io_in_bits_req_in3 = {48'h0, _hfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26, :848:19, :852:13, :854:13]
assign hfma_io_in_bits_req_typ = _hfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27]
assign hfma_io_in_bits_req_fmt = _hfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27]
wire _hfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39]
wire _hfma_io_in_bits_req_fmaCmd_T_3 = _hfma_io_in_bits_req_fmaCmd_T_1 & _hfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}]
assign _hfma_io_in_bits_req_fmaCmd_T_4 = {_hfma_io_in_bits_req_fmaCmd_T[1], _hfma_io_in_bits_req_fmaCmd_T[0] | _hfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}]
assign hfma_io_in_bits_req_fmaCmd = _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36]
wire _GEN_6 = mem_ctrl_typeTagOut == 2'h1; // @[FPU.scala:801:27, :911:72]
wire _memLatencyMask_T_2; // @[FPU.scala:911:72]
assign _memLatencyMask_T_2 = _GEN_6; // @[FPU.scala:911:72]
wire _wbInfo_0_pipeid_T_2; // @[FPU.scala:911:72]
assign _wbInfo_0_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72]
wire _wbInfo_1_pipeid_T_2; // @[FPU.scala:911:72]
assign _wbInfo_1_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72]
wire _wbInfo_2_pipeid_T_2; // @[FPU.scala:911:72]
assign _wbInfo_2_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72]
wire _divSqrt_io_inValid_T_2; // @[FPU.scala:1028:52]
assign _divSqrt_io_inValid_T_2 = _GEN_6; // @[FPU.scala:911:72, :1028:52]
wire _memLatencyMask_T_3 = mem_ctrl_fma & _memLatencyMask_T_2; // @[FPU.scala:801:27, :911:{56,72}]
wire [1:0] _memLatencyMask_T_4 = {_memLatencyMask_T_3, 1'h0}; // @[FPU.scala:911:56, :926:23]
wire _GEN_7 = mem_ctrl_typeTagOut == 2'h2; // @[FPU.scala:801:27, :916:78]
wire _memLatencyMask_T_5; // @[FPU.scala:916:78]
assign _memLatencyMask_T_5 = _GEN_7; // @[FPU.scala:916:78]
wire _wbInfo_0_pipeid_T_5; // @[FPU.scala:916:78]
assign _wbInfo_0_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78]
wire _wbInfo_1_pipeid_T_5; // @[FPU.scala:916:78]
assign _wbInfo_1_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78]
wire _wbInfo_2_pipeid_T_5; // @[FPU.scala:916:78]
assign _wbInfo_2_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78]
wire _io_sboard_set_T_2; // @[FPU.scala:916:78]
assign _io_sboard_set_T_2 = _GEN_7; // @[FPU.scala:916:78]
wire _divSqrt_io_inValid_T_4; // @[FPU.scala:1028:52]
assign _divSqrt_io_inValid_T_4 = _GEN_7; // @[FPU.scala:916:78, :1028:52]
wire _memLatencyMask_T_6 = mem_ctrl_fma & _memLatencyMask_T_5; // @[FPU.scala:801:27, :916:{62,78}]
wire [2:0] _memLatencyMask_T_7 = {_memLatencyMask_T_6, 2'h0}; // @[FPU.scala:916:62, :926:23]
wire _GEN_8 = mem_ctrl_typeTagOut == 2'h0; // @[FPU.scala:801:27, :922:78]
wire _memLatencyMask_T_8; // @[FPU.scala:922:78]
assign _memLatencyMask_T_8 = _GEN_8; // @[FPU.scala:922:78]
wire _wbInfo_0_pipeid_T_8; // @[FPU.scala:922:78]
assign _wbInfo_0_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78]
wire _wbInfo_1_pipeid_T_8; // @[FPU.scala:922:78]
assign _wbInfo_1_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78]
wire _wbInfo_2_pipeid_T_8; // @[FPU.scala:922:78]
assign _wbInfo_2_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78]
wire _divSqrt_io_inValid_T; // @[FPU.scala:1028:52]
assign _divSqrt_io_inValid_T = _GEN_8; // @[FPU.scala:922:78, :1028:52]
wire _memLatencyMask_T_9 = mem_ctrl_fma & _memLatencyMask_T_8; // @[FPU.scala:801:27, :922:{62,78}]
wire [1:0] _memLatencyMask_T_10 = {_memLatencyMask_T_9, 1'h0}; // @[FPU.scala:922:62, :926:23]
wire _memLatencyMask_T_11 = _memLatencyMask_T | _memLatencyMask_T_1; // @[FPU.scala:926:{23,72}]
wire [1:0] _memLatencyMask_T_12 = {1'h0, _memLatencyMask_T_11} | _memLatencyMask_T_4; // @[FPU.scala:926:{23,72}]
wire [2:0] _memLatencyMask_T_13 = {1'h0, _memLatencyMask_T_12} | _memLatencyMask_T_7; // @[FPU.scala:926:{23,72}]
wire [2:0] memLatencyMask = {_memLatencyMask_T_13[2], _memLatencyMask_T_13[1:0] | _memLatencyMask_T_10}; // @[FPU.scala:926:{23,72}]
reg [2:0] wen; // @[FPU.scala:939:20]
reg [4:0] wbInfo_0_rd; // @[FPU.scala:940:19]
reg [1:0] wbInfo_0_typeTag; // @[FPU.scala:940:19]
reg wbInfo_0_cp; // @[FPU.scala:940:19]
reg [2:0] wbInfo_0_pipeid; // @[FPU.scala:940:19]
reg [4:0] wbInfo_1_rd; // @[FPU.scala:940:19]
reg [1:0] wbInfo_1_typeTag; // @[FPU.scala:940:19]
reg wbInfo_1_cp; // @[FPU.scala:940:19]
reg [2:0] wbInfo_1_pipeid; // @[FPU.scala:940:19]
reg [4:0] wbInfo_2_rd; // @[FPU.scala:940:19]
reg [1:0] wbInfo_2_typeTag; // @[FPU.scala:940:19]
reg wbInfo_2_cp; // @[FPU.scala:940:19]
reg [2:0] wbInfo_2_pipeid; // @[FPU.scala:940:19]
wire _mem_wen_T = mem_ctrl_fma | mem_ctrl_fastpipe; // @[FPU.scala:801:27, :941:48]
wire _mem_wen_T_1 = _mem_wen_T | mem_ctrl_fromint; // @[FPU.scala:801:27, :941:{48,69}]
wire mem_wen = mem_reg_valid & _mem_wen_T_1; // @[FPU.scala:784:30, :941:{31,69}]
wire [1:0] _write_port_busy_T = {ex_ctrl_fastpipe, 1'h0}; // @[FPU.scala:800:20, :926:23]
wire [1:0] _write_port_busy_T_1 = {ex_ctrl_fromint, 1'h0}; // @[FPU.scala:800:20, :926:23]
wire _write_port_busy_T_3 = ex_ctrl_fma & _write_port_busy_T_2; // @[FPU.scala:800:20, :911:{56,72}]
wire [2:0] _write_port_busy_T_4 = {_write_port_busy_T_3, 2'h0}; // @[FPU.scala:911:56, :926:23]
wire _write_port_busy_T_6 = ex_ctrl_fma & _write_port_busy_T_5; // @[FPU.scala:800:20, :916:{62,78}]
wire [3:0] _write_port_busy_T_7 = {_write_port_busy_T_6, 3'h0}; // @[FPU.scala:916:62, :926:23]
wire _write_port_busy_T_9 = ex_ctrl_fma & _write_port_busy_T_8; // @[FPU.scala:800:20, :922:{62,78}]
wire [2:0] _write_port_busy_T_10 = {_write_port_busy_T_9, 2'h0}; // @[FPU.scala:922:62, :926:23]
wire [1:0] _write_port_busy_T_11 = _write_port_busy_T | _write_port_busy_T_1; // @[FPU.scala:926:{23,72}]
wire [2:0] _write_port_busy_T_12 = {1'h0, _write_port_busy_T_11} | _write_port_busy_T_4; // @[FPU.scala:926:{23,72}]
wire [3:0] _write_port_busy_T_13 = {1'h0, _write_port_busy_T_12} | _write_port_busy_T_7; // @[FPU.scala:926:{23,72}]
wire [3:0] _write_port_busy_T_14 = {_write_port_busy_T_13[3], _write_port_busy_T_13[2:0] | _write_port_busy_T_10}; // @[FPU.scala:926:{23,72}]
wire [3:0] _write_port_busy_T_15 = {1'h0, _write_port_busy_T_14[2:0] & memLatencyMask}; // @[FPU.scala:926:72, :942:62]
wire _write_port_busy_T_16 = |_write_port_busy_T_15; // @[FPU.scala:942:{62,89}]
wire _write_port_busy_T_17 = mem_wen & _write_port_busy_T_16; // @[FPU.scala:941:31, :942:{43,89}]
wire [2:0] _write_port_busy_T_18 = {ex_ctrl_fastpipe, 2'h0}; // @[FPU.scala:800:20, :926:23]
wire [2:0] _write_port_busy_T_19 = {ex_ctrl_fromint, 2'h0}; // @[FPU.scala:800:20, :926:23]
wire _write_port_busy_T_21 = ex_ctrl_fma & _write_port_busy_T_20; // @[FPU.scala:800:20, :911:{56,72}]
wire [3:0] _write_port_busy_T_22 = {_write_port_busy_T_21, 3'h0}; // @[FPU.scala:911:56, :926:23]
wire _write_port_busy_T_24 = ex_ctrl_fma & _write_port_busy_T_23; // @[FPU.scala:800:20, :916:{62,78}]
wire [4:0] _write_port_busy_T_25 = {_write_port_busy_T_24, 4'h0}; // @[FPU.scala:916:62, :926:23]
wire _write_port_busy_T_27 = ex_ctrl_fma & _write_port_busy_T_26; // @[FPU.scala:800:20, :922:{62,78}]
wire [3:0] _write_port_busy_T_28 = {_write_port_busy_T_27, 3'h0}; // @[FPU.scala:922:62, :926:23]
wire [2:0] _write_port_busy_T_29 = _write_port_busy_T_18 | _write_port_busy_T_19; // @[FPU.scala:926:{23,72}]
wire [3:0] _write_port_busy_T_30 = {1'h0, _write_port_busy_T_29} | _write_port_busy_T_22; // @[FPU.scala:926:{23,72}]
wire [4:0] _write_port_busy_T_31 = {1'h0, _write_port_busy_T_30} | _write_port_busy_T_25; // @[FPU.scala:926:{23,72}]
wire [4:0] _write_port_busy_T_32 = {_write_port_busy_T_31[4], _write_port_busy_T_31[3:0] | _write_port_busy_T_28}; // @[FPU.scala:926:{23,72}]
wire [4:0] _write_port_busy_T_33 = {2'h0, _write_port_busy_T_32[2:0] & wen}; // @[FPU.scala:926:72, :939:20, :942:101]
wire _write_port_busy_T_34 = |_write_port_busy_T_33; // @[FPU.scala:942:{101,128}]
wire _write_port_busy_T_35 = _write_port_busy_T_17 | _write_port_busy_T_34; // @[FPU.scala:942:{43,93,128}]
reg write_port_busy; // @[FPU.scala:942:34]
wire [1:0] _wen_T = wen[2:1]; // @[FPU.scala:939:20, :948:14]
wire [1:0] _wen_T_1 = wen[2:1]; // @[FPU.scala:939:20, :948:14, :951:18]
wire [2:0] _wen_T_2 = {1'h0, _wen_T_1} | memLatencyMask; // @[FPU.scala:926:72, :951:{18,23}]
wire _wbInfo_0_pipeid_T_11 = _wbInfo_0_pipeid_T_1; // @[FPU.scala:928:{63,100}]
wire _wbInfo_0_pipeid_T_3 = mem_ctrl_fma & _wbInfo_0_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}]
wire [1:0] _wbInfo_0_pipeid_T_4 = {_wbInfo_0_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63]
wire _wbInfo_0_pipeid_T_6 = mem_ctrl_fma & _wbInfo_0_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}]
wire [1:0] _wbInfo_0_pipeid_T_7 = {2{_wbInfo_0_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63]
wire _wbInfo_0_pipeid_T_9 = mem_ctrl_fma & _wbInfo_0_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}]
wire [2:0] _wbInfo_0_pipeid_T_10 = {_wbInfo_0_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63]
wire [1:0] _wbInfo_0_pipeid_T_12 = {1'h0, _wbInfo_0_pipeid_T_11} | _wbInfo_0_pipeid_T_4; // @[FPU.scala:928:{63,100}]
wire [1:0] _wbInfo_0_pipeid_T_13 = _wbInfo_0_pipeid_T_12 | _wbInfo_0_pipeid_T_7; // @[FPU.scala:928:{63,100}]
wire [2:0] _wbInfo_0_pipeid_T_14 = {1'h0, _wbInfo_0_pipeid_T_13} | _wbInfo_0_pipeid_T_10; // @[FPU.scala:928:{63,100}]
wire [4:0] _wbInfo_0_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37]
wire [4:0] _wbInfo_1_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37]
wire [4:0] _wbInfo_2_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37]
wire [4:0] _divSqrt_waddr_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37, :1017:36]
wire _wbInfo_1_pipeid_T_11 = _wbInfo_1_pipeid_T_1; // @[FPU.scala:928:{63,100}]
wire _wbInfo_1_pipeid_T_3 = mem_ctrl_fma & _wbInfo_1_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}]
wire [1:0] _wbInfo_1_pipeid_T_4 = {_wbInfo_1_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63]
wire _wbInfo_1_pipeid_T_6 = mem_ctrl_fma & _wbInfo_1_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}]
wire [1:0] _wbInfo_1_pipeid_T_7 = {2{_wbInfo_1_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63]
wire _wbInfo_1_pipeid_T_9 = mem_ctrl_fma & _wbInfo_1_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}]
wire [2:0] _wbInfo_1_pipeid_T_10 = {_wbInfo_1_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63]
wire [1:0] _wbInfo_1_pipeid_T_12 = {1'h0, _wbInfo_1_pipeid_T_11} | _wbInfo_1_pipeid_T_4; // @[FPU.scala:928:{63,100}]
wire [1:0] _wbInfo_1_pipeid_T_13 = _wbInfo_1_pipeid_T_12 | _wbInfo_1_pipeid_T_7; // @[FPU.scala:928:{63,100}]
wire [2:0] _wbInfo_1_pipeid_T_14 = {1'h0, _wbInfo_1_pipeid_T_13} | _wbInfo_1_pipeid_T_10; // @[FPU.scala:928:{63,100}]
wire _wbInfo_2_pipeid_T_11 = _wbInfo_2_pipeid_T_1; // @[FPU.scala:928:{63,100}]
wire _wbInfo_2_pipeid_T_3 = mem_ctrl_fma & _wbInfo_2_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}]
wire [1:0] _wbInfo_2_pipeid_T_4 = {_wbInfo_2_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63]
wire _wbInfo_2_pipeid_T_6 = mem_ctrl_fma & _wbInfo_2_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}]
wire [1:0] _wbInfo_2_pipeid_T_7 = {2{_wbInfo_2_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63]
wire _wbInfo_2_pipeid_T_9 = mem_ctrl_fma & _wbInfo_2_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}]
wire [2:0] _wbInfo_2_pipeid_T_10 = {_wbInfo_2_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63]
wire [1:0] _wbInfo_2_pipeid_T_12 = {1'h0, _wbInfo_2_pipeid_T_11} | _wbInfo_2_pipeid_T_4; // @[FPU.scala:928:{63,100}]
wire [1:0] _wbInfo_2_pipeid_T_13 = _wbInfo_2_pipeid_T_12 | _wbInfo_2_pipeid_T_7; // @[FPU.scala:928:{63,100}]
wire [2:0] _wbInfo_2_pipeid_T_14 = {1'h0, _wbInfo_2_pipeid_T_13} | _wbInfo_2_pipeid_T_10; // @[FPU.scala:928:{63,100}]
assign waddr = divSqrt_wen ? divSqrt_waddr : wbInfo_0_rd; // @[FPU.scala:896:32, :898:26, :940:19, :963:18]
assign io_sboard_clra_0 = waddr; // @[FPU.scala:735:7, :963:18]
assign frfWriteBundle_1_wrdst = waddr; // @[FPU.scala:805:44, :963:18]
wire wb_cp = divSqrt_wen ? divSqrt_cp : wbInfo_0_cp; // @[FPU.scala:896:32, :899:23, :940:19, :964:18]
wire [1:0] wtypeTag = divSqrt_wen ? divSqrt_typeTag : wbInfo_0_typeTag; // @[FPU.scala:896:32, :900:29, :940:19, :965:21]
wire _GEN_9 = wbInfo_0_pipeid == 3'h1; // @[package.scala:39:86]
wire _wdata_T_39; // @[package.scala:39:86]
assign _wdata_T_39 = _GEN_9; // @[package.scala:39:86]
wire _wexc_T; // @[package.scala:39:86]
assign _wexc_T = _GEN_9; // @[package.scala:39:86]
wire [64:0] _wdata_T_40 = _wdata_T_39 ? _ifpu_io_out_bits_data : _fpmu_io_out_bits_data; // @[package.scala:39:{76,86}]
wire _GEN_10 = wbInfo_0_pipeid == 3'h2; // @[package.scala:39:86]
wire _wdata_T_41; // @[package.scala:39:86]
assign _wdata_T_41 = _GEN_10; // @[package.scala:39:86]
wire _wexc_T_2; // @[package.scala:39:86]
assign _wexc_T_2 = _GEN_10; // @[package.scala:39:86]
wire [64:0] _wdata_T_42 = _wdata_T_41 ? _sfma_io_out_bits_data : _wdata_T_40; // @[package.scala:39:{76,86}]
wire _GEN_11 = wbInfo_0_pipeid == 3'h3; // @[package.scala:39:86]
wire _wdata_T_43; // @[package.scala:39:86]
assign _wdata_T_43 = _GEN_11; // @[package.scala:39:86]
wire _wexc_T_4; // @[package.scala:39:86]
assign _wexc_T_4 = _GEN_11; // @[package.scala:39:86]
wire _io_sboard_clr_T_2; // @[FPU.scala:1007:99]
assign _io_sboard_clr_T_2 = _GEN_11; // @[package.scala:39:86]
wire [64:0] _wdata_T_44 = _wdata_T_43 ? _dfma_io_out_bits_data : _wdata_T_42; // @[package.scala:39:{76,86}]
wire _GEN_12 = wbInfo_0_pipeid == 3'h4; // @[package.scala:39:86]
wire _wdata_T_45; // @[package.scala:39:86]
assign _wdata_T_45 = _GEN_12; // @[package.scala:39:86]
wire _wexc_T_6; // @[package.scala:39:86]
assign _wexc_T_6 = _GEN_12; // @[package.scala:39:86]
wire [64:0] _wdata_T_46 = _wdata_T_45 ? _hfma_io_out_bits_data : _wdata_T_44; // @[package.scala:39:{76,86}]
wire _GEN_13 = wbInfo_0_pipeid == 3'h5; // @[package.scala:39:86]
wire _wdata_T_47; // @[package.scala:39:86]
assign _wdata_T_47 = _GEN_13; // @[package.scala:39:86]
wire _wexc_T_8; // @[package.scala:39:86]
assign _wexc_T_8 = _GEN_13; // @[package.scala:39:86]
wire [64:0] _wdata_T_48 = _wdata_T_47 ? _hfma_io_out_bits_data : _wdata_T_46; // @[package.scala:39:{76,86}]
wire _GEN_14 = wbInfo_0_pipeid == 3'h6; // @[package.scala:39:86]
wire _wdata_T_49; // @[package.scala:39:86]
assign _wdata_T_49 = _GEN_14; // @[package.scala:39:86]
wire _wexc_T_10; // @[package.scala:39:86]
assign _wexc_T_10 = _GEN_14; // @[package.scala:39:86]
wire [64:0] _wdata_T_50 = _wdata_T_49 ? _hfma_io_out_bits_data : _wdata_T_48; // @[package.scala:39:{76,86}]
wire _wdata_T_51 = &wbInfo_0_pipeid; // @[package.scala:39:86]
wire [64:0] _wdata_T_52 = _wdata_T_51 ? _hfma_io_out_bits_data : _wdata_T_50; // @[package.scala:39:{76,86}]
wire [64:0] _wdata_T_53 = divSqrt_wen ? divSqrt_wdata : _wdata_T_52; // @[package.scala:39:76]
wire _wdata_opts_bigger_swizzledNaN_T_1 = _wdata_T_53[15]; // @[FPU.scala:340:8, :966:22]
wire _wdata_opts_bigger_swizzledNaN_T_2 = _wdata_T_53[16]; // @[FPU.scala:342:8, :966:22]
wire [14:0] _wdata_opts_bigger_swizzledNaN_T_3 = _wdata_T_53[14:0]; // @[FPU.scala:343:8, :966:22]
wire [7:0] wdata_opts_bigger_swizzledNaN_lo_hi = {7'h7F, _wdata_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8]
wire [22:0] wdata_opts_bigger_swizzledNaN_lo = {wdata_opts_bigger_swizzledNaN_lo_hi, _wdata_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8]
wire [4:0] wdata_opts_bigger_swizzledNaN_hi_lo = {4'hF, _wdata_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8]
wire [9:0] wdata_opts_bigger_swizzledNaN_hi = {5'h1F, wdata_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26]
wire [32:0] wdata_opts_bigger_swizzledNaN = {wdata_opts_bigger_swizzledNaN_hi, wdata_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26]
wire [32:0] wdata_opts_bigger = wdata_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8]
wire [64:0] wdata_opts_0 = {32'hFFFFFFFF, wdata_opts_bigger}; // @[FPU.scala:344:8, :398:14]
wire _wdata_opts_bigger_swizzledNaN_T_5 = _wdata_T_53[31]; // @[FPU.scala:340:8, :966:22]
wire _wdata_opts_bigger_swizzledNaN_T_6 = _wdata_T_53[32]; // @[FPU.scala:342:8, :966:22]
wire [30:0] _wdata_opts_bigger_swizzledNaN_T_7 = _wdata_T_53[30:0]; // @[FPU.scala:343:8, :966:22]
wire [20:0] wdata_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _wdata_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8]
wire [51:0] wdata_opts_bigger_swizzledNaN_lo_1 = {wdata_opts_bigger_swizzledNaN_lo_hi_1, _wdata_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8]
wire [7:0] wdata_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _wdata_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8]
wire [12:0] wdata_opts_bigger_swizzledNaN_hi_1 = {5'h1F, wdata_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26]
wire [64:0] wdata_opts_bigger_swizzledNaN_1 = {wdata_opts_bigger_swizzledNaN_hi_1, wdata_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26]
wire [64:0] wdata_opts_bigger_1 = wdata_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8]
wire [64:0] wdata_opts_1 = wdata_opts_bigger_1; // @[FPU.scala:344:8, :398:14]
wire _wdata_T_54 = wtypeTag == 2'h1; // @[package.scala:39:86]
wire [64:0] _wdata_T_55 = _wdata_T_54 ? wdata_opts_1 : wdata_opts_0; // @[package.scala:39:{76,86}]
wire _wdata_T_56 = wtypeTag == 2'h2; // @[package.scala:39:86]
wire [64:0] _wdata_T_57 = _wdata_T_56 ? _wdata_T_53 : _wdata_T_55; // @[package.scala:39:{76,86}]
wire _wdata_T_58 = &wtypeTag; // @[package.scala:39:86]
wire [64:0] wdata_1 = _wdata_T_58 ? _wdata_T_53 : _wdata_T_57; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_1 = _wexc_T ? _ifpu_io_out_bits_exc : _fpmu_io_out_bits_exc; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_3 = _wexc_T_2 ? _sfma_io_out_bits_exc : _wexc_T_1; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_5 = _wexc_T_4 ? _dfma_io_out_bits_exc : _wexc_T_3; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_7 = _wexc_T_6 ? _hfma_io_out_bits_exc : _wexc_T_5; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_9 = _wexc_T_8 ? _hfma_io_out_bits_exc : _wexc_T_7; // @[package.scala:39:{76,86}]
wire [4:0] _wexc_T_11 = _wexc_T_10 ? _hfma_io_out_bits_exc : _wexc_T_9; // @[package.scala:39:{76,86}]
wire _wexc_T_12 = &wbInfo_0_pipeid; // @[package.scala:39:86]
wire [4:0] wexc = _wexc_T_12 ? _hfma_io_out_bits_exc : _wexc_T_11; // @[package.scala:39:{76,86}]
wire _io_fcsr_flags_valid_T_1 = wen[0]; // @[FPU.scala:939:20, :968:30, :995:62]
wire _io_fcsr_flags_bits_T_3 = wen[0]; // @[FPU.scala:939:20, :968:30, :999:12]
wire _io_sboard_clr_T_1 = wen[0]; // @[FPU.scala:939:20, :968:30, :1007:56]
assign frfWriteBundle_1_wrenf = ~wbInfo_0_cp & wen[0] | divSqrt_wen; // @[FPU.scala:805:44, :896:32, :939:20, :940:19, :968:{10,24,30,35}]
wire _unswizzled_T_3 = wdata_1[31]; // @[package.scala:39:76]
wire _frfWriteBundle_1_wrdata_prevRecoded_T = wdata_1[31]; // @[package.scala:39:76]
wire _unswizzled_T_4 = wdata_1[52]; // @[package.scala:39:76]
wire _frfWriteBundle_1_wrdata_prevRecoded_T_1 = wdata_1[52]; // @[package.scala:39:76]
wire [30:0] _unswizzled_T_5 = wdata_1[30:0]; // @[package.scala:39:76]
wire [30:0] _frfWriteBundle_1_wrdata_prevRecoded_T_2 = wdata_1[30:0]; // @[package.scala:39:76]
wire [1:0] unswizzled_hi_1 = {_unswizzled_T_3, _unswizzled_T_4}; // @[FPU.scala:380:27, :381:10, :382:10]
wire [32:0] unswizzled_1 = {unswizzled_hi_1, _unswizzled_T_5}; // @[FPU.scala:380:27, :383:10]
wire [4:0] _prevOK_T_4 = wdata_1[64:60]; // @[package.scala:39:76]
wire _prevOK_T_5 = &_prevOK_T_4; // @[FPU.scala:332:{49,84}]
wire _prevOK_T_6 = ~_prevOK_T_5; // @[FPU.scala:332:84, :384:20]
wire _prevOK_unswizzled_T_3 = unswizzled_1[15]; // @[FPU.scala:380:27, :381:10]
wire _prevOK_unswizzled_T_4 = unswizzled_1[23]; // @[FPU.scala:380:27, :382:10]
wire [14:0] _prevOK_unswizzled_T_5 = unswizzled_1[14:0]; // @[FPU.scala:380:27, :383:10]
wire [1:0] prevOK_unswizzled_hi_1 = {_prevOK_unswizzled_T_3, _prevOK_unswizzled_T_4}; // @[FPU.scala:380:27, :381:10, :382:10]
wire [16:0] prevOK_unswizzled_1 = {prevOK_unswizzled_hi_1, _prevOK_unswizzled_T_5}; // @[FPU.scala:380:27, :383:10]
wire [4:0] _prevOK_prevOK_T_3 = unswizzled_1[32:28]; // @[FPU.scala:332:49, :380:27]
wire _prevOK_prevOK_T_4 = &_prevOK_prevOK_T_3; // @[FPU.scala:332:{49,84}]
wire _prevOK_prevOK_T_5 = ~_prevOK_prevOK_T_4; // @[FPU.scala:332:84, :384:20]
wire [2:0] _prevOK_curOK_T_7 = unswizzled_1[31:29]; // @[FPU.scala:249:25, :380:27]
wire _prevOK_curOK_T_8 = &_prevOK_curOK_T_7; // @[FPU.scala:249:{25,56}]
wire _prevOK_curOK_T_9 = ~_prevOK_curOK_T_8; // @[FPU.scala:249:56, :385:19]
wire _prevOK_curOK_T_10 = unswizzled_1[28]; // @[FPU.scala:380:27, :385:35]
wire [6:0] _prevOK_curOK_T_11 = unswizzled_1[22:16]; // @[FPU.scala:380:27, :385:60]
wire _prevOK_curOK_T_12 = &_prevOK_curOK_T_11; // @[FPU.scala:385:{60,96}]
wire _prevOK_curOK_T_13 = _prevOK_curOK_T_10 == _prevOK_curOK_T_12; // @[FPU.scala:385:{35,55,96}]
wire prevOK_curOK_1 = _prevOK_curOK_T_9 | _prevOK_curOK_T_13; // @[FPU.scala:385:{19,31,55}]
wire _prevOK_T_7 = prevOK_curOK_1; // @[FPU.scala:385:31, :386:14]
wire prevOK_1 = _prevOK_T_6 | _prevOK_T_7; // @[FPU.scala:384:{20,33}, :386:14]
wire [2:0] _curOK_T_7 = wdata_1[63:61]; // @[package.scala:39:76]
wire [2:0] _frfWriteBundle_1_wrdata_T_1 = wdata_1[63:61]; // @[package.scala:39:76]
wire _curOK_T_8 = &_curOK_T_7; // @[FPU.scala:249:{25,56}]
wire _curOK_T_9 = ~_curOK_T_8; // @[FPU.scala:249:56, :385:19]
wire _curOK_T_10 = wdata_1[60]; // @[package.scala:39:76]
wire [19:0] _curOK_T_11 = wdata_1[51:32]; // @[package.scala:39:76]
wire _curOK_T_12 = &_curOK_T_11; // @[FPU.scala:385:{60,96}]
wire _curOK_T_13 = _curOK_T_10 == _curOK_T_12; // @[FPU.scala:385:{35,55,96}]
wire curOK_1 = _curOK_T_9 | _curOK_T_13; // @[FPU.scala:385:{19,31,55}] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_194( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File Logger.scala:
// See LICENSE for license details
package roccaccutils.logger
import chisel3._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.diplomacy.{ValName}
trait Logger {
// --------------------------
// MUST BE DEFINED BY CHILD
// --------------------------
def logInfoImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf
def logCriticalImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf
// --------------------------
def trimValName()(implicit valName: ValName): String = {
// TODO: For now don't trim since it can have different pre/post-fixes
//val trimAmt = if (valName.value.startsWith("<local")) 6 else 1
//println(s"Got this: ${valName.value}")
//"<" + valName.value.substring(trimAmt, valName.value.length)
valName.value
}
def createPrefix(typ: String)(implicit valName: ValName, withMod: Boolean, prefix: String): String = {
val s = Seq(s"${typ}", "%d") ++ (if (withMod) Seq(trimValName()) else Seq.empty) ++ (if (prefix != "") Seq(prefix) else Seq.empty)
":" + s.mkString(":") + ": "
}
def createFmtAndArgs(typ: String, format: String, args: Bits*)(implicit valName: ValName, withMod: Boolean, prefix: String): (String, Seq[Bits]) = {
val loginfo_cycles = RegInit(0.U(64.W))
loginfo_cycles := loginfo_cycles + 1.U
val allargs = Seq(loginfo_cycles) ++ args
val allfmt = createPrefix(typ) + format
(allfmt, allargs)
}
def logInfoImpl(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName, withMod: Boolean, prefix: String): Unit = {
val (allfmt, allargs) = createFmtAndArgs("INFO", format, args:_*)
logInfoImplPrintWrapper(printf(Printable.pack(allfmt, allargs:_*)))
}
def logCriticalImpl(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName, withMod: Boolean, prefix: String): Unit = {
val (allfmt, allargs) = createFmtAndArgs("CRIT", format, args:_*)
logCriticalImplPrintWrapper(printf(Printable.pack(allfmt, allargs:_*)))
}
// ---- USE THE FUNCTIONS BELOW ----
def logInfo(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName = ValName("<UnknownMod>"), prefix: String = ""): Unit = {
implicit val withMod = true
logInfoImpl(format, args:_*)
}
def logCritical(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName = ValName("<UnknownMod>"), prefix: String = ""): Unit = {
implicit val withMod = true
logCriticalImpl(format, args:_*)
}
def logInfoNoMod(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName = ValName("<UnknownMod>"), prefix: String = ""): Unit = {
implicit val withMod = false
logInfoImpl(format, args:_*)
}
def logCriticalNoMod(format: String, args: Bits*)(implicit p: Parameters = Parameters.empty, valName: ValName = ValName("<UnknownMod>"), prefix: String = ""): Unit = {
implicit val withMod = false
logCriticalImpl(format, args:_*)
}
}
// An example of a custom logger (that optionally only synthesizes critical messages):
//
// object MyLogger extends Logger {
// // just print info msgs
// def logInfoImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf = {
// printf
// }
//
// // optionally synthesize critical msgs
// def logCriticalImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf = {
// if (p(EnablePrintfSynthesis)) {
// SynthesizePrintf(printf) // function comes from midas.targetutils
// } else {
// printf
// }
// }
// }
object DefaultLogger extends Logger {
// just print info msgs
def logInfoImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf = {
printf
}
// just print critical msgs
def logCriticalImplPrintWrapper(printf: chisel3.printf.Printf)(implicit p: Parameters = Parameters.empty): chisel3.printf.Printf = {
printf
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File L2MemHelper.scala:
// See LICENSE for license details
package roccaccutils
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.tile.{HasCoreParameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.{TLBConfig, TLBPTWIO, TLB, MStatus, PRV}
import freechips.rocketchip.util.{DecoupledHelper}
import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
import freechips.rocketchip.rocket.{RAS}
import freechips.rocketchip.tilelink._
import roccaccutils.logger._
case class L2MemHelperParams (
busBits: Int = 256
)
trait HasL2MemHelperParams {
implicit val hp: L2MemHelperParams
def BUS_SZ_BITS = hp.busBits
def BUS_SZ_BYTES = BUS_SZ_BITS / 8
def BUS_SZ_BYTES_LG2UP = log2Up(BUS_SZ_BYTES)
def BUS_BIT_MASK = ((1 << BUS_SZ_BYTES_LG2UP) - 1)
}
class L2ReqInternal(implicit val hp: L2MemHelperParams) extends Bundle with HasL2MemHelperParams {
val addr = UInt()
val size = UInt()
val data = UInt(BUS_SZ_BITS.W)
val cmd = UInt()
}
class L2RespInternal(implicit val hp: L2MemHelperParams) extends Bundle with HasL2MemHelperParams {
val data = UInt(BUS_SZ_BITS.W)
}
class L2InternalTracking(implicit val hp: L2MemHelperParams) extends Bundle with HasL2MemHelperParams {
val addrindex = UInt(BUS_SZ_BYTES_LG2UP.W)
val tag = UInt()
}
class L2MemHelperBundle(implicit val hp: L2MemHelperParams) extends Bundle with HasL2MemHelperParams {
val req = Decoupled(new L2ReqInternal)
val resp = Flipped(Decoupled(new L2RespInternal))
val no_memops_inflight = Input(Bool())
}
class L2MemHelper(tlbConfig: TLBConfig, printInfo: String = "", numOutstandingReqs: Int = 32, queueRequests: Boolean = true, queueResponses: Boolean = true, printWriteBytes: Boolean = false, logger: Logger = DefaultLogger, busBits: Int = 256)(implicit p: Parameters) extends LazyModule {
val numOutstandingRequestsAllowed = numOutstandingReqs
val tlTagBits = log2Ceil(numOutstandingRequestsAllowed)
lazy val module = new L2MemHelperModule(this, tlbConfig, printInfo, queueRequests, queueResponses, printWriteBytes, logger, busBits)
val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1(
name = printInfo,
sourceId = IdRange(0, numOutstandingRequestsAllowed))))))
}
class L2MemHelperModule(outer: L2MemHelper, tlbConfig: TLBConfig, printInfo: String = "", queueRequests: Boolean = true, queueResponses: Boolean = true, printWriteBytes: Boolean = false, logger: Logger = DefaultLogger, busBits: Int = 256)(implicit p: Parameters) extends LazyModuleImp(outer)
with HasCoreParameters
with MemoryOpConstants {
implicit val hp: L2MemHelperParams = L2MemHelperParams(busBits)
val io = IO(new Bundle {
val userif = Flipped(new L2MemHelperBundle)
val sfence = Input(Bool())
val ptw = new TLBPTWIO
val status = Flipped(Valid(new MStatus))
})
val (dmem, edge) = outer.masterNode.out.head
val request_input = Wire(Decoupled(new L2ReqInternal))
if (!queueRequests) {
request_input <> io.userif.req
} else {
val requestQueue = Module(new Queue(new L2ReqInternal, 4))
request_input <> requestQueue.io.deq
requestQueue.io.enq <> io.userif.req
}
val response_output = Wire(Decoupled(new L2RespInternal))
if (!queueResponses) {
io.userif.resp <> response_output
} else {
val responseQueue = Module(new Queue(new L2RespInternal, 4))
responseQueue.io.enq <> response_output
io.userif.resp <> responseQueue.io.deq
}
val status = Reg(new MStatus)
when (io.status.valid) {
logger.logInfo(printInfo + " setting status.dprv to: %x compare %x\n", io.status.bits.dprv, PRV.M.U)
status := io.status.bits
}
val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), tlbConfig)(edge, p))
tlb.io.req.valid := request_input.valid
tlb.io.req.bits.vaddr := request_input.bits.addr
tlb.io.req.bits.size := request_input.bits.size
tlb.io.req.bits.cmd := request_input.bits.cmd
tlb.io.req.bits.passthrough := false.B
val tlb_ready = tlb.io.req.ready && !tlb.io.resp.miss
io.ptw <> tlb.io.ptw
tlb.io.ptw.status := status
tlb.io.sfence.valid := io.sfence
tlb.io.sfence.bits.rs1 := false.B
tlb.io.sfence.bits.rs2 := false.B
tlb.io.sfence.bits.addr := 0.U
tlb.io.sfence.bits.asid := 0.U
tlb.io.kill := false.B
tlb.io.req.bits.prv := 0.U
tlb.io.req.bits.v := 0.U
tlb.io.sfence.bits.hv := 0.U
tlb.io.sfence.bits.hg := 0.U
val outstanding_req_addr = Module(new Queue(new L2InternalTracking, outer.numOutstandingRequestsAllowed * 4))
val tags_for_issue_Q = Module(new Queue(UInt(outer.tlTagBits.W), outer.numOutstandingRequestsAllowed * 2))
// overridden below
tags_for_issue_Q.io.enq.valid := false.B
tags_for_issue_Q.io.enq.bits := 0.U
val tags_init_reg = RegInit(0.U((outer.tlTagBits+1).W))
when (tags_init_reg =/= (outer.numOutstandingRequestsAllowed).U) {
tags_for_issue_Q.io.enq.bits := tags_init_reg
tags_for_issue_Q.io.enq.valid := true.B
when (tags_for_issue_Q.io.enq.ready) {
logger.logInfo(printInfo + " tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits)
tags_init_reg := tags_init_reg + 1.U
}
}
val addr_mask_check = (1.U(64.W) << request_input.bits.size) - 1.U
val assertcheck = RegNext((!request_input.valid) || ((request_input.bits.addr & addr_mask_check) === 0.U))
when (!assertcheck) {
logger.logInfo(printInfo + " L2IF: access addr must be aligned to write width\n")
}
assert(assertcheck,
printInfo + " L2IF: access addr must be aligned to write width\n")
val global_memop_accepted = RegInit(0.U(64.W))
when (io.userif.req.fire) {
global_memop_accepted := global_memop_accepted + 1.U
}
val global_memop_sent = RegInit(0.U(64.W))
val global_memop_ackd = RegInit(0.U(64.W))
val global_memop_resp_to_user = RegInit(0.U(64.W))
io.userif.no_memops_inflight := global_memop_accepted === global_memop_ackd
val free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) < (1 << outer.tlTagBits).U
val assert_free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) <= (1 << outer.tlTagBits).U
when (!assert_free_outstanding_op_slots) {
logger.logInfo(printInfo + " L2IF: Too many outstanding requests for tag count.\n")
}
assert(assert_free_outstanding_op_slots,
printInfo + " L2IF: Too many outstanding requests for tag count.\n")
when (request_input.fire) {
global_memop_sent := global_memop_sent + 1.U
}
val sendtag = tags_for_issue_Q.io.deq.bits
when (request_input.bits.cmd === M_XRD) {
val (legal, bundle) = edge.Get(fromSource=sendtag,
toAddress=tlb.io.resp.paddr,
lgSize=request_input.bits.size)
dmem.a.bits := bundle
} .elsewhen (request_input.bits.cmd === M_XWR) {
val (legal, bundle) = edge.Put(fromSource=sendtag,
toAddress=tlb.io.resp.paddr,
lgSize=request_input.bits.size,
data=request_input.bits.data << ((request_input.bits.addr(4, 0) << 3)))
dmem.a.bits := bundle
} .elsewhen (request_input.valid) {
logger.logInfo(printInfo + " ERR")
assert(false.B, "ERR")
}
val tl_resp_queues = VecInit.fill(outer.numOutstandingRequestsAllowed)(
Module(new Queue(new L2RespInternal, 4, flow=true)).io)
val current_request_tag_has_response_space = tl_resp_queues(tags_for_issue_Q.io.deq.bits).enq.ready
val fire_req = DecoupledHelper(
request_input.valid,
dmem.a.ready,
tlb_ready,
outstanding_req_addr.io.enq.ready,
free_outstanding_op_slots,
tags_for_issue_Q.io.deq.valid,
current_request_tag_has_response_space
)
outstanding_req_addr.io.enq.bits.addrindex := request_input.bits.addr & 0x1F.U
outstanding_req_addr.io.enq.bits.tag := sendtag
dmem.a.valid := fire_req.fire(dmem.a.ready)
request_input.ready := fire_req.fire(request_input.valid)
outstanding_req_addr.io.enq.valid := fire_req.fire(outstanding_req_addr.io.enq.ready)
tags_for_issue_Q.io.deq.ready := fire_req.fire(tags_for_issue_Q.io.deq.valid)
when (dmem.a.fire) {
when (request_input.bits.cmd === M_XRD) {
logger.logInfo(printInfo + " L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n",
request_input.bits.addr,
tlb.io.resp.paddr,
request_input.bits.size,
global_memop_sent,
sendtag)
}
when (request_input.bits.cmd === M_XWR) {
logger.logCritical(printInfo + " L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n",
request_input.bits.addr,
tlb.io.resp.paddr,
request_input.bits.size,
request_input.bits.data,
global_memop_sent,
sendtag)
if (printWriteBytes) {
for (i <- 0 until 32) {
when (i.U < (1.U << request_input.bits.size)) {
logger.logInfo("WRITE_BYTE ADDR: 0x%x BYTE: 0x%x " + printInfo + "\n", request_input.bits.addr + i.U, (request_input.bits.data >> (i*8).U)(7, 0))
}
}
}
}
}
val selectQready = tl_resp_queues(dmem.d.bits.source).enq.ready
val fire_actual_mem_resp = DecoupledHelper(
selectQready,
dmem.d.valid,
tags_for_issue_Q.io.enq.ready
)
when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready)) {
tags_for_issue_Q.io.enq.valid := true.B
tags_for_issue_Q.io.enq.bits := dmem.d.bits.source
}
when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready) &&
tags_for_issue_Q.io.enq.valid) {
logger.logInfo(printInfo + " tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits)
}
dmem.d.ready := fire_actual_mem_resp.fire(dmem.d.valid)
for (i <- 0 until outer.numOutstandingRequestsAllowed) {
tl_resp_queues(i).enq.valid := fire_actual_mem_resp.fire(selectQready) && (dmem.d.bits.source === i.U)
tl_resp_queues(i).enq.bits.data := dmem.d.bits.data
}
val currentQueue = tl_resp_queues(outstanding_req_addr.io.deq.bits.tag)
val queueValid = currentQueue.deq.valid
val fire_user_resp = DecoupledHelper(
queueValid,
response_output.ready,
outstanding_req_addr.io.deq.valid
)
val resultdata = currentQueue.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3)
response_output.bits.data := resultdata
response_output.valid := fire_user_resp.fire(response_output.ready)
outstanding_req_addr.io.deq.ready := fire_user_resp.fire(outstanding_req_addr.io.deq.valid)
for (i <- 0 until outer.numOutstandingRequestsAllowed) {
tl_resp_queues(i).deq.ready := fire_user_resp.fire(queueValid) && (outstanding_req_addr.io.deq.bits.tag === i.U)
}
when (dmem.d.fire) {
when (edge.hasData(dmem.d.bits)) {
logger.logInfo(printInfo + " L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n",
dmem.d.bits.data,
global_memop_ackd,
dmem.d.bits.source)
} .otherwise {
logger.logInfo(printInfo + " L2IF: resp(write) opnum: %d, gettag: %d\n",
global_memop_ackd,
dmem.d.bits.source)
}
}
when (response_output.fire) {
logger.logInfo(printInfo + " L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n",
resultdata,
global_memop_resp_to_user,
outstanding_req_addr.io.deq.bits.tag)
}
when (dmem.d.fire) {
global_memop_ackd := global_memop_ackd + 1.U
}
when (response_output.fire) {
global_memop_resp_to_user := global_memop_resp_to_user + 1.U
}
}
| module L2MemHelper( // @[L2MemHelper.scala:63:7]
input clock, // @[L2MemHelper.scala:63:7]
input reset, // @[L2MemHelper.scala:63:7]
input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_userif_req_ready, // @[L2MemHelper.scala:69:14]
input io_userif_req_valid, // @[L2MemHelper.scala:69:14]
input [70:0] io_userif_req_bits_addr, // @[L2MemHelper.scala:69:14]
input io_userif_resp_ready, // @[L2MemHelper.scala:69:14]
output io_userif_resp_valid, // @[L2MemHelper.scala:69:14]
output [255:0] io_userif_resp_bits_data, // @[L2MemHelper.scala:69:14]
output io_userif_no_memops_inflight, // @[L2MemHelper.scala:69:14]
input io_sfence, // @[L2MemHelper.scala:69:14]
input io_ptw_req_ready, // @[L2MemHelper.scala:69:14]
output io_ptw_req_valid, // @[L2MemHelper.scala:69:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelper.scala:69:14]
output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_valid, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_ae_ptw, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_ae_final, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pf, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_gf, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_hr, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_hw, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_hx, // @[L2MemHelper.scala:69:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelper.scala:69:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pte_d, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pte_a, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pte_g, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pte_u, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pte_x, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pte_w, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pte_r, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_pte_v, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_resp_bits_level, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_homogeneous, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_gpa_valid, // @[L2MemHelper.scala:69:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelper.scala:69:14]
input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelper.scala:69:14]
input [3:0] io_ptw_ptbr_mode, // @[L2MemHelper.scala:69:14]
input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelper.scala:69:14]
input io_ptw_status_debug, // @[L2MemHelper.scala:69:14]
input io_ptw_status_cease, // @[L2MemHelper.scala:69:14]
input io_ptw_status_wfi, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_status_isa, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_status_dprv, // @[L2MemHelper.scala:69:14]
input io_ptw_status_dv, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_status_prv, // @[L2MemHelper.scala:69:14]
input io_ptw_status_v, // @[L2MemHelper.scala:69:14]
input io_ptw_status_mpv, // @[L2MemHelper.scala:69:14]
input io_ptw_status_gva, // @[L2MemHelper.scala:69:14]
input io_ptw_status_tsr, // @[L2MemHelper.scala:69:14]
input io_ptw_status_tw, // @[L2MemHelper.scala:69:14]
input io_ptw_status_tvm, // @[L2MemHelper.scala:69:14]
input io_ptw_status_mxr, // @[L2MemHelper.scala:69:14]
input io_ptw_status_sum, // @[L2MemHelper.scala:69:14]
input io_ptw_status_mprv, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_status_fs, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_status_mpp, // @[L2MemHelper.scala:69:14]
input io_ptw_status_spp, // @[L2MemHelper.scala:69:14]
input io_ptw_status_mpie, // @[L2MemHelper.scala:69:14]
input io_ptw_status_spie, // @[L2MemHelper.scala:69:14]
input io_ptw_status_mie, // @[L2MemHelper.scala:69:14]
input io_ptw_status_sie, // @[L2MemHelper.scala:69:14]
input io_ptw_hstatus_spvp, // @[L2MemHelper.scala:69:14]
input io_ptw_hstatus_spv, // @[L2MemHelper.scala:69:14]
input io_ptw_hstatus_gva, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_debug, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_cease, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_wfi, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_gstatus_isa, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_dv, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_gstatus_prv, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_v, // @[L2MemHelper.scala:69:14]
input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_mpv, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_gva, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_mbe, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_sbe, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelper.scala:69:14]
input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_tsr, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_tw, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_tvm, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_mxr, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_sum, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_mprv, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_gstatus_fs, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_gstatus_vs, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_spp, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_mpie, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_ube, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_spie, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_upie, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_mie, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_hie, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_sie, // @[L2MemHelper.scala:69:14]
input io_ptw_gstatus_uie, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_0_cfg_l, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_0_cfg_x, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_0_cfg_w, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_0_cfg_r, // @[L2MemHelper.scala:69:14]
input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_1_cfg_l, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_1_cfg_x, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_1_cfg_w, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_1_cfg_r, // @[L2MemHelper.scala:69:14]
input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_2_cfg_l, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_2_cfg_x, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_2_cfg_w, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_2_cfg_r, // @[L2MemHelper.scala:69:14]
input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_3_cfg_l, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_3_cfg_x, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_3_cfg_w, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_3_cfg_r, // @[L2MemHelper.scala:69:14]
input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_4_cfg_l, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_4_cfg_x, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_4_cfg_w, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_4_cfg_r, // @[L2MemHelper.scala:69:14]
input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_5_cfg_l, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_5_cfg_x, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_5_cfg_w, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_5_cfg_r, // @[L2MemHelper.scala:69:14]
input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_6_cfg_l, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_6_cfg_x, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_6_cfg_w, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_6_cfg_r, // @[L2MemHelper.scala:69:14]
input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_7_cfg_l, // @[L2MemHelper.scala:69:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_7_cfg_x, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_7_cfg_w, // @[L2MemHelper.scala:69:14]
input io_ptw_pmp_7_cfg_r, // @[L2MemHelper.scala:69:14]
input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelper.scala:69:14]
input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelper.scala:69:14]
input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelper.scala:69:14]
input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelper.scala:69:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelper.scala:69:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelper.scala:69:14]
input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelper.scala:69:14]
input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelper.scala:69:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelper.scala:69:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelper.scala:69:14]
input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelper.scala:69:14]
input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelper.scala:69:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelper.scala:69:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelper.scala:69:14]
input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelper.scala:69:14]
input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelper.scala:69:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelper.scala:69:14]
input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelper.scala:69:14]
input io_status_valid, // @[L2MemHelper.scala:69:14]
input io_status_bits_debug, // @[L2MemHelper.scala:69:14]
input io_status_bits_cease, // @[L2MemHelper.scala:69:14]
input io_status_bits_wfi, // @[L2MemHelper.scala:69:14]
input [31:0] io_status_bits_isa, // @[L2MemHelper.scala:69:14]
input [1:0] io_status_bits_dprv, // @[L2MemHelper.scala:69:14]
input io_status_bits_dv, // @[L2MemHelper.scala:69:14]
input [1:0] io_status_bits_prv, // @[L2MemHelper.scala:69:14]
input io_status_bits_v, // @[L2MemHelper.scala:69:14]
input io_status_bits_sd, // @[L2MemHelper.scala:69:14]
input [22:0] io_status_bits_zero2, // @[L2MemHelper.scala:69:14]
input io_status_bits_mpv, // @[L2MemHelper.scala:69:14]
input io_status_bits_gva, // @[L2MemHelper.scala:69:14]
input io_status_bits_mbe, // @[L2MemHelper.scala:69:14]
input io_status_bits_sbe, // @[L2MemHelper.scala:69:14]
input [1:0] io_status_bits_sxl, // @[L2MemHelper.scala:69:14]
input [1:0] io_status_bits_uxl, // @[L2MemHelper.scala:69:14]
input io_status_bits_sd_rv32, // @[L2MemHelper.scala:69:14]
input [7:0] io_status_bits_zero1, // @[L2MemHelper.scala:69:14]
input io_status_bits_tsr, // @[L2MemHelper.scala:69:14]
input io_status_bits_tw, // @[L2MemHelper.scala:69:14]
input io_status_bits_tvm, // @[L2MemHelper.scala:69:14]
input io_status_bits_mxr, // @[L2MemHelper.scala:69:14]
input io_status_bits_sum, // @[L2MemHelper.scala:69:14]
input io_status_bits_mprv, // @[L2MemHelper.scala:69:14]
input [1:0] io_status_bits_xs, // @[L2MemHelper.scala:69:14]
input [1:0] io_status_bits_fs, // @[L2MemHelper.scala:69:14]
input [1:0] io_status_bits_mpp, // @[L2MemHelper.scala:69:14]
input [1:0] io_status_bits_vs, // @[L2MemHelper.scala:69:14]
input io_status_bits_spp, // @[L2MemHelper.scala:69:14]
input io_status_bits_mpie, // @[L2MemHelper.scala:69:14]
input io_status_bits_ube, // @[L2MemHelper.scala:69:14]
input io_status_bits_spie, // @[L2MemHelper.scala:69:14]
input io_status_bits_upie, // @[L2MemHelper.scala:69:14]
input io_status_bits_mie, // @[L2MemHelper.scala:69:14]
input io_status_bits_hie, // @[L2MemHelper.scala:69:14]
input io_status_bits_sie, // @[L2MemHelper.scala:69:14]
input io_status_bits_uie // @[L2MemHelper.scala:69:14]
);
wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelper.scala:128:32]
wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelper.scala:128:32]
wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelper.scala:128:32]
wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelper.scala:125:36]
wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelper.scala:125:36]
wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelper.scala:125:36]
wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelper.scala:125:36]
wire _tlb_io_req_ready; // @[L2MemHelper.scala:103:19]
wire _tlb_io_resp_miss; // @[L2MemHelper.scala:103:19]
wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelper.scala:103:19]
wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelper.scala:63:7]
wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelper.scala:63:7]
wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelper.scala:63:7]
wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelper.scala:63:7]
wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelper.scala:63:7]
wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelper.scala:63:7]
wire [4:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelper.scala:63:7]
wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelper.scala:63:7]
wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelper.scala:63:7]
wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelper.scala:63:7]
wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelper.scala:63:7]
wire [70:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelper.scala:63:7]
wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelper.scala:63:7]
wire io_sfence_0 = io_sfence; // @[L2MemHelper.scala:63:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelper.scala:63:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelper.scala:63:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelper.scala:63:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelper.scala:63:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelper.scala:63:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelper.scala:63:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelper.scala:63:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelper.scala:63:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelper.scala:63:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelper.scala:63:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelper.scala:63:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelper.scala:63:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelper.scala:63:7]
wire io_status_valid_0 = io_status_valid; // @[L2MemHelper.scala:63:7]
wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelper.scala:63:7]
wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelper.scala:63:7]
wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelper.scala:63:7]
wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelper.scala:63:7]
wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelper.scala:63:7]
wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelper.scala:63:7]
wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelper.scala:63:7]
wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelper.scala:63:7]
wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelper.scala:63:7]
wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelper.scala:63:7]
wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelper.scala:63:7]
wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelper.scala:63:7]
wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelper.scala:63:7]
wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelper.scala:63:7]
wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelper.scala:63:7]
wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelper.scala:63:7]
wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelper.scala:63:7]
wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelper.scala:63:7]
wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelper.scala:63:7]
wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelper.scala:63:7]
wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelper.scala:63:7]
wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelper.scala:63:7]
wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelper.scala:63:7]
wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelper.scala:63:7]
wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelper.scala:63:7]
wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelper.scala:63:7]
wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelper.scala:63:7]
wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelper.scala:63:7]
wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelper.scala:63:7]
wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelper.scala:63:7]
wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelper.scala:63:7]
wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelper.scala:63:7]
wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelper.scala:63:7]
wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelper.scala:63:7]
wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelper.scala:63:7]
wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelper.scala:63:7]
wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelper.scala:63:7]
wire auto_master_out_a_bits_corrupt = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_userif_req_bits_cmd = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_mbe = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_sbe = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_ube = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_upie = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_hie = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_uie = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelper.scala:63:7]
wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29]
wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54]
wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelper.scala:63:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelper.scala:63:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelper.scala:63:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelper.scala:63:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelper.scala:63:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelper.scala:63:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelper.scala:63:7]
wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelper.scala:63:7]
wire io_ptw_status_sd = 1'h1; // @[L2MemHelper.scala:63:7]
wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelper.scala:63:7]
wire _legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28]
wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38]
wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33]
wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29]
wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelper.scala:63:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelper.scala:63:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelper.scala:63:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelper.scala:63:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelper.scala:63:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelper.scala:63:7]
wire [2:0] auto_master_out_a_bits_param = 3'h0; // @[L2MemHelper.scala:63:7]
wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] io_userif_req_bits_size = 3'h5; // @[L2MemHelper.scala:63:7]
wire [255:0] io_userif_req_bits_data = 256'h0; // @[L2MemHelper.scala:63:7]
wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelper.scala:63:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelper.scala:63:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelper.scala:63:7]
wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17]
wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[L2MemHelper.scala:63:7]
wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[L2MemHelper.scala:63:7]
wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[L2MemHelper.scala:63:7]
wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[L2MemHelper.scala:63:7]
wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[L2MemHelper.scala:63:7]
wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[L2MemHelper.scala:63:7]
wire [4:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[L2MemHelper.scala:63:7]
wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[L2MemHelper.scala:63:7]
wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[L2MemHelper.scala:63:7]
wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[L2MemHelper.scala:63:7]
wire _io_userif_no_memops_inflight_T; // @[L2MemHelper.scala:163:57]
wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelper.scala:63:7]
wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelper.scala:63:7]
wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelper.scala:63:7]
wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelper.scala:63:7]
wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelper.scala:63:7]
wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelper.scala:63:7]
wire auto_master_out_a_valid_0; // @[L2MemHelper.scala:63:7]
wire auto_master_out_d_ready_0; // @[L2MemHelper.scala:63:7]
wire io_userif_req_ready_0; // @[L2MemHelper.scala:63:7]
wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelper.scala:63:7]
wire io_userif_resp_valid_0; // @[L2MemHelper.scala:63:7]
wire io_userif_no_memops_inflight_0; // @[L2MemHelper.scala:63:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelper.scala:63:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelper.scala:63:7]
wire io_ptw_req_valid_0; // @[L2MemHelper.scala:63:7]
wire _masterNodeOut_a_valid_T_4; // @[Misc.scala:26:53]
assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[L2MemHelper.scala:63:7]
assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[L2MemHelper.scala:63:7]
assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[L2MemHelper.scala:63:7]
assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[L2MemHelper.scala:63:7]
assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[L2MemHelper.scala:63:7]
assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[L2MemHelper.scala:63:7]
assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[L2MemHelper.scala:63:7]
wire _masterNodeOut_d_ready_T; // @[Misc.scala:26:53]
assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[L2MemHelper.scala:63:7]
wire [255:0] tl_resp_queues_0_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_1_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_2_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_3_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_4_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_5_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_6_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_7_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_8_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_9_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_10_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_11_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_12_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_13_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_14_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_15_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_16_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_17_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_18_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_19_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_20_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_21_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_22_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_23_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_24_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_25_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_26_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_27_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_28_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_29_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_30_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_31_enq_bits_data = masterNodeOut_d_bits_data; // @[L2MemHelper.scala:196:73]
wire _request_input_ready_T_4; // @[Misc.scala:26:53]
wire [70:0] request_input_bits_addr; // @[L2MemHelper.scala:79:27]
wire [2:0] request_input_bits_size; // @[L2MemHelper.scala:79:27]
wire [255:0] request_input_bits_data; // @[L2MemHelper.scala:79:27]
wire request_input_bits_cmd; // @[L2MemHelper.scala:79:27]
wire request_input_ready; // @[L2MemHelper.scala:79:27]
wire request_input_valid; // @[L2MemHelper.scala:79:27]
wire _response_output_valid_T; // @[Misc.scala:26:53]
wire [255:0] resultdata; // @[L2MemHelper.scala:281:47]
wire [255:0] response_output_bits_data; // @[L2MemHelper.scala:88:29]
wire response_output_ready; // @[L2MemHelper.scala:88:29]
wire response_output_valid; // @[L2MemHelper.scala:88:29]
reg status_debug; // @[L2MemHelper.scala:97:19]
reg status_cease; // @[L2MemHelper.scala:97:19]
reg status_wfi; // @[L2MemHelper.scala:97:19]
reg [31:0] status_isa; // @[L2MemHelper.scala:97:19]
reg [1:0] status_dprv; // @[L2MemHelper.scala:97:19]
reg status_dv; // @[L2MemHelper.scala:97:19]
reg [1:0] status_prv; // @[L2MemHelper.scala:97:19]
reg status_v; // @[L2MemHelper.scala:97:19]
reg status_sd; // @[L2MemHelper.scala:97:19]
reg [22:0] status_zero2; // @[L2MemHelper.scala:97:19]
reg status_mpv; // @[L2MemHelper.scala:97:19]
reg status_gva; // @[L2MemHelper.scala:97:19]
reg status_mbe; // @[L2MemHelper.scala:97:19]
reg status_sbe; // @[L2MemHelper.scala:97:19]
reg [1:0] status_sxl; // @[L2MemHelper.scala:97:19]
reg [1:0] status_uxl; // @[L2MemHelper.scala:97:19]
reg status_sd_rv32; // @[L2MemHelper.scala:97:19]
reg [7:0] status_zero1; // @[L2MemHelper.scala:97:19]
reg status_tsr; // @[L2MemHelper.scala:97:19]
reg status_tw; // @[L2MemHelper.scala:97:19]
reg status_tvm; // @[L2MemHelper.scala:97:19]
reg status_mxr; // @[L2MemHelper.scala:97:19]
reg status_sum; // @[L2MemHelper.scala:97:19]
reg status_mprv; // @[L2MemHelper.scala:97:19]
reg [1:0] status_xs; // @[L2MemHelper.scala:97:19]
reg [1:0] status_fs; // @[L2MemHelper.scala:97:19]
reg [1:0] status_mpp; // @[L2MemHelper.scala:97:19]
reg [1:0] status_vs; // @[L2MemHelper.scala:97:19]
reg status_spp; // @[L2MemHelper.scala:97:19]
reg status_mpie; // @[L2MemHelper.scala:97:19]
reg status_ube; // @[L2MemHelper.scala:97:19]
reg status_spie; // @[L2MemHelper.scala:97:19]
reg status_upie; // @[L2MemHelper.scala:97:19]
reg status_mie; // @[L2MemHelper.scala:97:19]
reg status_hie; // @[L2MemHelper.scala:97:19]
reg status_sie; // @[L2MemHelper.scala:97:19]
reg status_uie; // @[L2MemHelper.scala:97:19]
reg [63:0] allargs_0; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T = {1'h0, allargs_0} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Logger.scala:38:38]
wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelper.scala:103:19, :109:39]
wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelper.scala:103:19, :109:{36,39}]
reg [5:0] tags_init_reg; // @[L2MemHelper.scala:133:30]
wire _T_2 = tags_init_reg != 6'h20; // @[L2MemHelper.scala:133:30, :134:23]
wire _GEN = tags_init_reg == 6'h20; // @[L2MemHelper.scala:131:32, :133:30, :134:{23,68}, :135:34]
reg [63:0] allargs_0_1; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, allargs_0_1} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Logger.scala:38:38]
wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelper.scala:133:30, :139:38]
wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelper.scala:139:38]
wire [70:0] _addr_mask_check_T = 71'h1 << request_input_bits_size; // @[L2MemHelper.scala:79:27, :143:36]
wire [71:0] _addr_mask_check_T_1 = {1'h0, _addr_mask_check_T} - 72'h1; // @[L2MemHelper.scala:143:{36,64}]
wire [70:0] addr_mask_check = _addr_mask_check_T_1[70:0]; // @[L2MemHelper.scala:143:64]
wire _assertcheck_T = ~request_input_valid; // @[L2MemHelper.scala:79:27, :144:30]
wire [70:0] _assertcheck_T_1 = request_input_bits_addr & addr_mask_check; // @[L2MemHelper.scala:79:27, :143:64, :144:81]
wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelper.scala:143:64, :144:{81,100}]
wire _assertcheck_T_3 = _assertcheck_T | _assertcheck_T_2; // @[L2MemHelper.scala:144:{30,52,100}]
reg assertcheck; // @[L2MemHelper.scala:144:28]
reg [63:0] allargs_0_2; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, allargs_0_2} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Logger.scala:38:38]
reg [63:0] global_memop_accepted; // @[L2MemHelper.scala:152:38]
wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelper.scala:152:38, :154:52]
wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelper.scala:154:52]
reg [63:0] global_memop_sent; // @[L2MemHelper.scala:157:34]
reg [63:0] global_memop_ackd; // @[L2MemHelper.scala:159:34]
reg [63:0] global_memop_resp_to_user; // @[L2MemHelper.scala:161:42]
assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelper.scala:152:38, :159:34, :163:57]
assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelper.scala:63:7, :163:57]
wire [64:0] _GEN_0 = {1'h0, global_memop_sent}; // @[L2MemHelper.scala:157:34, :165:54]
wire [64:0] _GEN_1 = {1'h0, global_memop_ackd}; // @[L2MemHelper.scala:159:34, :165:54]
wire [64:0] _GEN_2 = _GEN_0 - _GEN_1; // @[L2MemHelper.scala:165:54]
wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelper.scala:165:54]
assign _free_outstanding_op_slots_T = _GEN_2; // @[L2MemHelper.scala:165:54]
wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelper.scala:166:61]
assign _assert_free_outstanding_op_slots_T = _GEN_2; // @[L2MemHelper.scala:165:54, :166:61]
wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelper.scala:165:54]
wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelper.scala:165:{54,75}]
wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelper.scala:166:61]
wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelper.scala:166:{61,82}]
reg [63:0] allargs_0_3; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, allargs_0_3} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Logger.scala:38:38]
wire [64:0] _global_memop_sent_T = _GEN_0 + 65'h1; // @[L2MemHelper.scala:165:54, :175:44]
wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelper.scala:175:44]
wire [31:0] _GEN_3 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_4; // @[Parameters.scala:137:31]
assign _legal_T_4 = _GEN_3; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_67; // @[Parameters.scala:137:31]
assign _legal_T_67 = _GEN_3; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46]
wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54]
wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _GEN_4 = request_input_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _legal_T_11; // @[Parameters.scala:92:38]
assign _legal_T_11 = _GEN_4; // @[Parameters.scala:92:38]
wire _legal_T_74; // @[Parameters.scala:92:38]
assign _legal_T_74 = _GEN_4; // @[Parameters.scala:92:38]
wire _legal_T_12 = _legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _legal_T_13 = _legal_T_12; // @[Parameters.scala:684:29]
wire [31:0] _legal_T_14; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46]
wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_19; // @[Parameters.scala:137:31]
assign _legal_T_19 = _GEN_5; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_24; // @[Parameters.scala:137:31]
assign _legal_T_24 = _GEN_5; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_126; // @[Parameters.scala:137:31]
assign _legal_T_126 = _GEN_5; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46]
wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46]
wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_29; // @[Parameters.scala:137:31]
assign _legal_T_29 = _GEN_6; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_87; // @[Parameters.scala:137:31]
assign _legal_T_87 = _GEN_6; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46]
wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_7 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_34; // @[Parameters.scala:137:31]
assign _legal_T_34 = _GEN_7; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_39; // @[Parameters.scala:137:31]
assign _legal_T_39 = _GEN_7; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_97; // @[Parameters.scala:137:31]
assign _legal_T_97 = _GEN_7; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_102; // @[Parameters.scala:137:31]
assign _legal_T_102 = _GEN_7; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46]
wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46]
wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_8 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_44; // @[Parameters.scala:137:31]
assign _legal_T_44 = _GEN_8; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_107; // @[Parameters.scala:137:31]
assign _legal_T_107 = _GEN_8; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46]
wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_9 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_49; // @[Parameters.scala:137:31]
assign _legal_T_49 = _GEN_9; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_112; // @[Parameters.scala:137:31]
assign _legal_T_112 = _GEN_9; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46]
wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_54 = _legal_T_18 | _legal_T_23; // @[Parameters.scala:685:42]
wire _legal_T_55 = _legal_T_54 | _legal_T_28; // @[Parameters.scala:685:42]
wire _legal_T_56 = _legal_T_55 | _legal_T_33; // @[Parameters.scala:685:42]
wire _legal_T_57 = _legal_T_56 | _legal_T_38; // @[Parameters.scala:685:42]
wire _legal_T_58 = _legal_T_57 | _legal_T_43; // @[Parameters.scala:685:42]
wire _legal_T_59 = _legal_T_58 | _legal_T_48; // @[Parameters.scala:685:42]
wire _legal_T_60 = _legal_T_59 | _legal_T_53; // @[Parameters.scala:685:42]
wire _legal_T_61 = _legal_T_13 & _legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42]
wire legal = _legal_T_62 | _legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire [31:0] _a_mask_T; // @[Misc.scala:222:10]
wire [3:0] bundle_size; // @[Edges.scala:460:17]
wire [4:0] bundle_source; // @[Edges.scala:460:17]
wire [31:0] bundle_address; // @[Edges.scala:460:17]
wire [31:0] bundle_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_10 = {1'h0, request_input_bits_size}; // @[Edges.scala:463:15]
assign bundle_size = _GEN_10; // @[Edges.scala:460:17, :463:15]
wire [3:0] bundle_1_size; // @[Edges.scala:480:17]
assign bundle_1_size = _GEN_10; // @[Edges.scala:463:15, :480:17]
wire [4:0] _GEN_11 = {2'h0, request_input_bits_size}; // @[Misc.scala:202:34]
wire [4:0] _a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _a_mask_sizeOH_T = _GEN_11; // @[Misc.scala:202:34]
wire [4:0] _a_mask_sizeOH_T_3; // @[Misc.scala:202:34]
assign _a_mask_sizeOH_T_3 = _GEN_11; // @[Misc.scala:202:34]
wire [4:0] _a_mask_sizeOH_shiftAmount_T = _a_mask_sizeOH_T; // @[OneHot.scala:64:31]
wire [2:0] a_mask_sizeOH_shiftAmount = _a_mask_sizeOH_shiftAmount_T[2:0]; // @[OneHot.scala:64:{31,49}]
wire [7:0] _a_mask_sizeOH_T_1 = 8'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [4:0] _a_mask_sizeOH_T_2 = _a_mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}]
wire [4:0] a_mask_sizeOH = {_a_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27]
wire _GEN_12 = request_input_bits_size > 3'h4; // @[Misc.scala:206:21]
wire a_mask_sub_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21]
assign a_mask_sub_sub_sub_sub_sub_0_1 = _GEN_12; // @[Misc.scala:206:21]
wire a_mask_sub_sub_sub_sub_sub_0_1_1; // @[Misc.scala:206:21]
assign a_mask_sub_sub_sub_sub_sub_0_1_1 = _GEN_12; // @[Misc.scala:206:21]
wire a_mask_sub_sub_sub_sub_size = a_mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_sub_acc_T = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _a_mask_sub_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire a_mask_sub_sub_sub_size = a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_acc_T = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_2_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_3_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_size = a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_size & a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_0_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_size & a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_1_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_2 = a_mask_sub_sub_size & a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_2_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_3 = a_mask_sub_sub_size & a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_3_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_4 = a_mask_sub_sub_size & a_mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_4_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_5 = a_mask_sub_sub_size & a_mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_5_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_6 = a_mask_sub_sub_size & a_mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_6_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_7 = a_mask_sub_sub_size & a_mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_7_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_size = a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26]
wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26]
wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T = a_mask_sub_size & a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_0_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_1 = a_mask_sub_size & a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_1_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_2 = a_mask_sub_size & a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_2_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_3 = a_mask_sub_size & a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_3_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_4 = a_mask_sub_size & a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_4_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_5 = a_mask_sub_size & a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_5_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_6 = a_mask_sub_size & a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_6_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_7 = a_mask_sub_size & a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_7_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_8 = a_mask_sub_size & a_mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_8_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_9 = a_mask_sub_size & a_mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_9_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_10 = a_mask_sub_size & a_mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_10_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_11 = a_mask_sub_size & a_mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_11_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_12 = a_mask_sub_size & a_mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_12_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_13 = a_mask_sub_size & a_mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_13_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_14 = a_mask_sub_size & a_mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_14_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_15 = a_mask_sub_size & a_mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_15_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire a_mask_size = a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26]
wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26]
wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T = a_mask_size & a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc = a_mask_sub_0_1 | _a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_1 = a_mask_size & a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_1 = a_mask_sub_0_1 | _a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_2 = a_mask_size & a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_2 = a_mask_sub_1_1 | _a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_3 = a_mask_size & a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_3 = a_mask_sub_1_1 | _a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_4 = a_mask_size & a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_4 = a_mask_sub_2_1 | _a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_5 = a_mask_size & a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_5 = a_mask_sub_2_1 | _a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_6 = a_mask_size & a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_6 = a_mask_sub_3_1 | _a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_7 = a_mask_size & a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_7 = a_mask_sub_3_1 | _a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_8 = a_mask_size & a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_8 = a_mask_sub_4_1 | _a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_9 = a_mask_size & a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_9 = a_mask_sub_4_1 | _a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_10 = a_mask_size & a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_10 = a_mask_sub_5_1 | _a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_11 = a_mask_size & a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_11 = a_mask_sub_5_1 | _a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_12 = a_mask_size & a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_12 = a_mask_sub_6_1 | _a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_13 = a_mask_size & a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_13 = a_mask_sub_6_1 | _a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_14 = a_mask_size & a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_14 = a_mask_sub_7_1 | _a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_15 = a_mask_size & a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_15 = a_mask_sub_7_1 | _a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_16 = a_mask_size & a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_16 = a_mask_sub_8_1 | _a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_17 = a_mask_size & a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_17 = a_mask_sub_8_1 | _a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_18 = a_mask_size & a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_18 = a_mask_sub_9_1 | _a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_19 = a_mask_size & a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_19 = a_mask_sub_9_1 | _a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_20 = a_mask_size & a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_20 = a_mask_sub_10_1 | _a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_21 = a_mask_size & a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_21 = a_mask_sub_10_1 | _a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_22 = a_mask_size & a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_22 = a_mask_sub_11_1 | _a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_23 = a_mask_size & a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_23 = a_mask_sub_11_1 | _a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_24 = a_mask_size & a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_24 = a_mask_sub_12_1 | _a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_25 = a_mask_size & a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_25 = a_mask_sub_12_1 | _a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_26 = a_mask_size & a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_26 = a_mask_sub_13_1 | _a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_27 = a_mask_size & a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_27 = a_mask_sub_13_1 | _a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_28 = a_mask_size & a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_28 = a_mask_sub_14_1 | _a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_29 = a_mask_size & a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_29 = a_mask_sub_14_1 | _a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_30 = a_mask_size & a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_30 = a_mask_sub_15_1 | _a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_31 = a_mask_size & a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_31 = a_mask_sub_15_1 | _a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] a_mask_lo_lo_lo_lo = {a_mask_acc_1, a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_lo_lo_hi = {a_mask_acc_3, a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_lo_lo = {a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_lo_hi_lo = {a_mask_acc_5, a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_lo_hi_hi = {a_mask_acc_7, a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_lo_hi = {a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] a_mask_lo_lo = {a_mask_lo_lo_hi, a_mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_hi_lo_lo = {a_mask_acc_9, a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_hi_lo_hi = {a_mask_acc_11, a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_hi_lo = {a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_hi_hi_lo = {a_mask_acc_13, a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_hi_hi_hi = {a_mask_acc_15, a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_hi_hi = {a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] a_mask_lo_hi = {a_mask_lo_hi_hi, a_mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] a_mask_lo = {a_mask_lo_hi, a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_lo_lo_lo = {a_mask_acc_17, a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_lo_lo_hi = {a_mask_acc_19, a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_lo_lo = {a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_lo_hi_lo = {a_mask_acc_21, a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_lo_hi_hi = {a_mask_acc_23, a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_lo_hi = {a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] a_mask_hi_lo = {a_mask_hi_lo_hi, a_mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_hi_lo_lo = {a_mask_acc_25, a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_hi_lo_hi = {a_mask_acc_27, a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_hi_lo = {a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_hi_hi_lo = {a_mask_acc_29, a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_hi_hi_hi = {a_mask_acc_31, a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_hi_hi = {a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] a_mask_hi_hi = {a_mask_hi_hi_hi, a_mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] a_mask_hi = {a_mask_hi_hi, a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _a_mask_T = {a_mask_hi, a_mask_lo}; // @[Misc.scala:222:10]
assign bundle_mask = _a_mask_T; // @[Misc.scala:222:10]
wire [510:0] _T_23 = {255'h0, request_input_bits_data} << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelper.scala:79:27, :189:{58,86}]
wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46]
wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54]
wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26]
wire _legal_T_75 = _legal_T_74; // @[Parameters.scala:92:{33,38}]
wire _legal_T_76 = _legal_T_75; // @[Parameters.scala:684:29]
wire [31:0] _legal_T_77; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46]
wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46]
wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46]
wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46]
wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46]
wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46]
wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46]
wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46]
wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_117 = _legal_T_81 | _legal_T_86; // @[Parameters.scala:685:42]
wire _legal_T_118 = _legal_T_117 | _legal_T_91; // @[Parameters.scala:685:42]
wire _legal_T_119 = _legal_T_118 | _legal_T_96; // @[Parameters.scala:685:42]
wire _legal_T_120 = _legal_T_119 | _legal_T_101; // @[Parameters.scala:685:42]
wire _legal_T_121 = _legal_T_120 | _legal_T_106; // @[Parameters.scala:685:42]
wire _legal_T_122 = _legal_T_121 | _legal_T_111; // @[Parameters.scala:685:42]
wire _legal_T_123 = _legal_T_122 | _legal_T_116; // @[Parameters.scala:685:42]
wire _legal_T_124 = _legal_T_76 & _legal_T_123; // @[Parameters.scala:684:{29,54}, :685:42]
wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46]
wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_133 = _legal_T_132 | _legal_T_124; // @[Parameters.scala:684:54, :686:26]
wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26]
wire [31:0] _a_mask_T_1; // @[Misc.scala:222:10]
wire [4:0] bundle_1_source; // @[Edges.scala:480:17]
wire [31:0] bundle_1_address; // @[Edges.scala:480:17]
wire [31:0] bundle_1_mask; // @[Edges.scala:480:17]
wire [255:0] bundle_1_data; // @[Edges.scala:480:17]
wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = _a_mask_sizeOH_T_3; // @[OneHot.scala:64:31]
wire [2:0] a_mask_sizeOH_shiftAmount_1 = _a_mask_sizeOH_shiftAmount_T_1[2:0]; // @[OneHot.scala:64:{31,49}]
wire [7:0] _a_mask_sizeOH_T_4 = 8'h1 << a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [4:0] _a_mask_sizeOH_T_5 = _a_mask_sizeOH_T_4[4:0]; // @[OneHot.scala:65:{12,27}]
wire [4:0] a_mask_sizeOH_1 = {_a_mask_sizeOH_T_5[4:1], 1'h1}; // @[OneHot.scala:65:27]
wire a_mask_sub_sub_sub_sub_size_1 = a_mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _a_mask_sub_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire a_mask_sub_sub_sub_size_1 = a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_acc_T_4 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_sub_acc_T_5 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_acc_T_6 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_2_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_sub_acc_T_7 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_3_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_size_1 = a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_8 = a_mask_sub_sub_size_1 & a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_0_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_9 = a_mask_sub_sub_size_1 & a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_1_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_10 = a_mask_sub_sub_size_1 & a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_2_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_11 = a_mask_sub_sub_size_1 & a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_3_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_12 = a_mask_sub_sub_size_1 & a_mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_4_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_13 = a_mask_sub_sub_size_1 & a_mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_5_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_14 = a_mask_sub_sub_size_1 & a_mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_6_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_15 = a_mask_sub_sub_size_1 & a_mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_7_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_size_1 = a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_16 = a_mask_sub_size_1 & a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_0_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_17 = a_mask_sub_size_1 & a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_1_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_18 = a_mask_sub_size_1 & a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_2_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_19 = a_mask_sub_size_1 & a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_3_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_20 = a_mask_sub_size_1 & a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_4_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_21 = a_mask_sub_size_1 & a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_5_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_22 = a_mask_sub_size_1 & a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_6_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_23 = a_mask_sub_size_1 & a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_7_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_24 = a_mask_sub_size_1 & a_mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_8_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_25 = a_mask_sub_size_1 & a_mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_9_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_26 = a_mask_sub_size_1 & a_mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_10_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_27 = a_mask_sub_size_1 & a_mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_11_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_28 = a_mask_sub_size_1 & a_mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_12_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_29 = a_mask_sub_size_1 & a_mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_13_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_30 = a_mask_sub_size_1 & a_mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_14_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_31 = a_mask_sub_size_1 & a_mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_15_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire a_mask_size_1 = a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_32 = a_mask_size_1 & a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_32 = a_mask_sub_0_1_1 | _a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_33 = a_mask_size_1 & a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_33 = a_mask_sub_0_1_1 | _a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_34 = a_mask_size_1 & a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_34 = a_mask_sub_1_1_1 | _a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_35 = a_mask_size_1 & a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_35 = a_mask_sub_1_1_1 | _a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_36 = a_mask_size_1 & a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_36 = a_mask_sub_2_1_1 | _a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_37 = a_mask_size_1 & a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_37 = a_mask_sub_2_1_1 | _a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_38 = a_mask_size_1 & a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_38 = a_mask_sub_3_1_1 | _a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_39 = a_mask_size_1 & a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_39 = a_mask_sub_3_1_1 | _a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_40 = a_mask_size_1 & a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_40 = a_mask_sub_4_1_1 | _a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_41 = a_mask_size_1 & a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_41 = a_mask_sub_4_1_1 | _a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_42 = a_mask_size_1 & a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_42 = a_mask_sub_5_1_1 | _a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_43 = a_mask_size_1 & a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_43 = a_mask_sub_5_1_1 | _a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_44 = a_mask_size_1 & a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_44 = a_mask_sub_6_1_1 | _a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_45 = a_mask_size_1 & a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_45 = a_mask_sub_6_1_1 | _a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_46 = a_mask_size_1 & a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_46 = a_mask_sub_7_1_1 | _a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_47 = a_mask_size_1 & a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_47 = a_mask_sub_7_1_1 | _a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_48 = a_mask_size_1 & a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_48 = a_mask_sub_8_1_1 | _a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_49 = a_mask_size_1 & a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_49 = a_mask_sub_8_1_1 | _a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_50 = a_mask_size_1 & a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_50 = a_mask_sub_9_1_1 | _a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_51 = a_mask_size_1 & a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_51 = a_mask_sub_9_1_1 | _a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_52 = a_mask_size_1 & a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_52 = a_mask_sub_10_1_1 | _a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_53 = a_mask_size_1 & a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_53 = a_mask_sub_10_1_1 | _a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_54 = a_mask_size_1 & a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_54 = a_mask_sub_11_1_1 | _a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_55 = a_mask_size_1 & a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_55 = a_mask_sub_11_1_1 | _a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_56 = a_mask_size_1 & a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_56 = a_mask_sub_12_1_1 | _a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_57 = a_mask_size_1 & a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_57 = a_mask_sub_12_1_1 | _a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_58 = a_mask_size_1 & a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_58 = a_mask_sub_13_1_1 | _a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_59 = a_mask_size_1 & a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_59 = a_mask_sub_13_1_1 | _a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_60 = a_mask_size_1 & a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_60 = a_mask_sub_14_1_1 | _a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_61 = a_mask_size_1 & a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_61 = a_mask_sub_14_1_1 | _a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_62 = a_mask_size_1 & a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_62 = a_mask_sub_15_1_1 | _a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_63 = a_mask_size_1 & a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_63 = a_mask_sub_15_1_1 | _a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] a_mask_lo_lo_lo_lo_1 = {a_mask_acc_33, a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_lo_lo_hi_1 = {a_mask_acc_35, a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_lo_lo_1 = {a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_lo_hi_lo_1 = {a_mask_acc_37, a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_lo_hi_hi_1 = {a_mask_acc_39, a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_lo_hi_1 = {a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] a_mask_lo_lo_1 = {a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_hi_lo_lo_1 = {a_mask_acc_41, a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_hi_lo_hi_1 = {a_mask_acc_43, a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_hi_lo_1 = {a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_hi_hi_lo_1 = {a_mask_acc_45, a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_hi_hi_hi_1 = {a_mask_acc_47, a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_hi_hi_1 = {a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] a_mask_lo_hi_1 = {a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10]
wire [15:0] a_mask_lo_1 = {a_mask_lo_hi_1, a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_lo_lo_lo_1 = {a_mask_acc_49, a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_lo_lo_hi_1 = {a_mask_acc_51, a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_lo_lo_1 = {a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_lo_hi_lo_1 = {a_mask_acc_53, a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_lo_hi_hi_1 = {a_mask_acc_55, a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_lo_hi_1 = {a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] a_mask_hi_lo_1 = {a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_hi_lo_lo_1 = {a_mask_acc_57, a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_hi_lo_hi_1 = {a_mask_acc_59, a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_hi_lo_1 = {a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_hi_hi_lo_1 = {a_mask_acc_61, a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_hi_hi_hi_1 = {a_mask_acc_63, a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_hi_hi_1 = {a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] a_mask_hi_hi_1 = {a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10]
wire [15:0] a_mask_hi_1 = {a_mask_hi_hi_1, a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _a_mask_T_1 = {a_mask_hi_1, a_mask_lo_1}; // @[Misc.scala:222:10]
assign bundle_1_mask = _a_mask_T_1; // @[Misc.scala:222:10]
assign bundle_1_data = _T_23[255:0]; // @[Edges.scala:480:17, :489:15]
assign masterNodeOut_a_bits_opcode = {~request_input_bits_cmd, 2'h0}; // @[L2MemHelper.scala:79:27, :180:{32,43}, :184:17, :185:50]
assign masterNodeOut_a_bits_size = request_input_bits_cmd ? bundle_1_size : bundle_size; // @[Edges.scala:460:17, :480:17]
assign masterNodeOut_a_bits_source = request_input_bits_cmd ? bundle_1_source : bundle_source; // @[Edges.scala:460:17, :480:17]
assign masterNodeOut_a_bits_address = request_input_bits_cmd ? bundle_1_address : bundle_address; // @[Edges.scala:460:17, :480:17]
assign masterNodeOut_a_bits_mask = request_input_bits_cmd ? bundle_1_mask : bundle_mask; // @[Edges.scala:460:17, :480:17]
assign masterNodeOut_a_bits_data = request_input_bits_cmd ? bundle_1_data : 256'h0; // @[Edges.scala:480:17]
reg [63:0] allargs_0_4; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, allargs_0_4} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Logger.scala:38:38]
wire _tl_resp_queues_0_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_0_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_1_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_1_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_2_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_2_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_3_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_3_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_4_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_4_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_5_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_5_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_6_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_6_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_7_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_7_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_8_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_8_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_9_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_9_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_10_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_10_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_11_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_11_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_12_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_12_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_13_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_13_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_14_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_14_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_15_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_15_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_16_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_16_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_17_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_17_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_18_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_18_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_19_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_19_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_20_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_20_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_21_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_21_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_22_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_22_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_23_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_23_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_24_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_24_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_25_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_25_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_26_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_26_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_27_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_27_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_28_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_28_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_29_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_29_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_30_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_30_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire _tl_resp_queues_31_enq_valid_T_2; // @[L2MemHelper.scala:268:76]
wire _tl_resp_queues_31_deq_ready_T_2; // @[L2MemHelper.scala:289:68]
wire tl_resp_queues_0_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_0_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_0_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_0_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_0_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_0_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_1_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_1_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_1_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_1_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_1_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_1_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_2_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_2_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_2_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_2_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_2_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_2_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_3_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_3_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_3_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_3_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_3_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_3_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_4_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_4_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_4_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_4_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_4_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_4_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_5_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_5_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_5_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_5_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_5_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_5_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_6_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_6_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_6_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_6_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_6_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_6_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_7_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_7_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_7_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_7_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_7_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_7_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_8_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_8_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_8_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_8_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_8_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_8_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_9_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_9_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_9_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_9_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_9_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_9_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_10_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_10_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_10_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_10_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_10_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_10_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_11_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_11_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_11_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_11_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_11_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_11_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_12_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_12_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_12_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_12_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_12_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_12_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_13_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_13_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_13_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_13_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_13_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_13_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_14_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_14_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_14_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_14_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_14_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_14_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_15_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_15_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_15_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_15_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_15_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_15_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_16_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_16_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_16_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_16_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_16_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_16_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_17_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_17_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_17_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_17_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_17_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_17_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_18_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_18_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_18_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_18_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_18_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_18_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_19_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_19_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_19_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_19_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_19_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_19_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_20_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_20_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_20_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_20_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_20_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_20_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_21_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_21_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_21_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_21_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_21_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_21_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_22_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_22_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_22_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_22_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_22_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_22_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_23_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_23_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_23_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_23_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_23_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_23_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_24_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_24_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_24_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_24_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_24_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_24_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_25_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_25_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_25_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_25_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_25_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_25_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_26_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_26_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_26_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_26_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_26_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_26_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_27_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_27_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_27_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_27_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_27_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_27_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_28_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_28_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_28_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_28_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_28_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_28_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_29_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_29_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_29_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_29_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_29_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_29_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_30_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_30_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_30_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_30_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_30_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_30_count; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_31_enq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_31_enq_valid; // @[L2MemHelper.scala:196:73]
wire [255:0] tl_resp_queues_31_deq_bits_data; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_31_deq_ready; // @[L2MemHelper.scala:196:73]
wire tl_resp_queues_31_deq_valid; // @[L2MemHelper.scala:196:73]
wire [2:0] tl_resp_queues_31_count; // @[L2MemHelper.scala:196:73]
wire [70:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {66'h0, request_input_bits_addr[4:0]}; // @[L2MemHelper.scala:79:27, :211:73]
wire _masterNodeOut_a_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53]
wire _masterNodeOut_a_valid_T_1 = _masterNodeOut_a_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53]
wire _masterNodeOut_a_valid_T_2 = _masterNodeOut_a_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53]
wire _masterNodeOut_a_valid_T_3 = _masterNodeOut_a_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53]
wire [31:0] _GEN_13 = {{tl_resp_queues_31_enq_ready}, {tl_resp_queues_30_enq_ready}, {tl_resp_queues_29_enq_ready}, {tl_resp_queues_28_enq_ready}, {tl_resp_queues_27_enq_ready}, {tl_resp_queues_26_enq_ready}, {tl_resp_queues_25_enq_ready}, {tl_resp_queues_24_enq_ready}, {tl_resp_queues_23_enq_ready}, {tl_resp_queues_22_enq_ready}, {tl_resp_queues_21_enq_ready}, {tl_resp_queues_20_enq_ready}, {tl_resp_queues_19_enq_ready}, {tl_resp_queues_18_enq_ready}, {tl_resp_queues_17_enq_ready}, {tl_resp_queues_16_enq_ready}, {tl_resp_queues_15_enq_ready}, {tl_resp_queues_14_enq_ready}, {tl_resp_queues_13_enq_ready}, {tl_resp_queues_12_enq_ready}, {tl_resp_queues_11_enq_ready}, {tl_resp_queues_10_enq_ready}, {tl_resp_queues_9_enq_ready}, {tl_resp_queues_8_enq_ready}, {tl_resp_queues_7_enq_ready}, {tl_resp_queues_6_enq_ready}, {tl_resp_queues_5_enq_ready}, {tl_resp_queues_4_enq_ready}, {tl_resp_queues_3_enq_ready}, {tl_resp_queues_2_enq_ready}, {tl_resp_queues_1_enq_ready}, {tl_resp_queues_0_enq_ready}}; // @[Misc.scala:26:53]
wire _GEN_14 = _GEN_13[_tags_for_issue_Q_io_deq_bits]; // @[Misc.scala:26:53]
assign _masterNodeOut_a_valid_T_4 = _masterNodeOut_a_valid_T_3 & _GEN_14; // @[Misc.scala:26:53]
assign masterNodeOut_a_valid = _masterNodeOut_a_valid_T_4; // @[Misc.scala:26:53]
wire _request_input_ready_T = masterNodeOut_a_ready & tlb_ready; // @[Misc.scala:26:53]
wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53]
wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53]
wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53]
assign _request_input_ready_T_4 = _request_input_ready_T_3 & _GEN_14; // @[Misc.scala:26:53]
assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53]
wire _GEN_15 = request_input_valid & masterNodeOut_a_ready; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53]
assign _outstanding_req_addr_io_enq_valid_T = _GEN_15; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53]
assign _tags_for_issue_Q_io_deq_ready_T = _GEN_15; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & _GEN_14; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & _GEN_14; // @[Misc.scala:26:53]
reg [63:0] allargs_0_5; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, allargs_0_5} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_6; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, allargs_0_6} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Logger.scala:38:38]
wire _T_37 = _GEN_13[masterNodeOut_d_bits_source] & masterNodeOut_d_valid; // @[Misc.scala:26:53]
wire tags_for_issue_Q_io_enq_valid = _T_37 | _T_2; // @[Misc.scala:26:53]
wire [4:0] tags_for_issue_Q_io_enq_bits = _T_37 ? masterNodeOut_d_bits_source : _GEN ? 5'h0 : tags_init_reg[4:0]; // @[Misc.scala:26:53]
reg [63:0] allargs_0_7; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, allargs_0_7} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Logger.scala:38:38]
assign _masterNodeOut_d_ready_T = _GEN_13[masterNodeOut_d_bits_source] & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53]
assign masterNodeOut_d_ready = _masterNodeOut_d_ready_T; // @[Misc.scala:26:53]
wire _GEN_16 = masterNodeOut_d_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53]
wire _tl_resp_queues_0_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_0_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_1_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_1_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_2_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_2_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_3_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_3_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_4_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_4_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_5_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_5_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_6_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_6_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_7_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_7_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_8_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_8_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_9_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_9_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_10_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_10_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_11_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_11_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_12_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_12_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_13_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_13_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_14_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_14_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_15_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_15_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_16_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_16_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_17_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_17_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_18_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_18_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_19_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_19_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_20_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_20_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_21_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_21_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_22_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_22_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_23_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_23_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_24_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_24_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_25_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_25_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_26_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_26_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_27_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_27_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_28_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_28_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_29_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_29_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_30_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_30_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_31_enq_valid_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_31_enq_valid_T = _GEN_16; // @[Misc.scala:26:53]
wire _tl_resp_queues_0_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h0; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_0_enq_valid_T_2 = _tl_resp_queues_0_enq_valid_T & _tl_resp_queues_0_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_0_enq_valid = _tl_resp_queues_0_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_1_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h1; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_1_enq_valid_T_2 = _tl_resp_queues_1_enq_valid_T & _tl_resp_queues_1_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_1_enq_valid = _tl_resp_queues_1_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_2_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h2; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_2_enq_valid_T_2 = _tl_resp_queues_2_enq_valid_T & _tl_resp_queues_2_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_2_enq_valid = _tl_resp_queues_2_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_3_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h3; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_3_enq_valid_T_2 = _tl_resp_queues_3_enq_valid_T & _tl_resp_queues_3_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_3_enq_valid = _tl_resp_queues_3_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_4_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h4; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_4_enq_valid_T_2 = _tl_resp_queues_4_enq_valid_T & _tl_resp_queues_4_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_4_enq_valid = _tl_resp_queues_4_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_5_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h5; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_5_enq_valid_T_2 = _tl_resp_queues_5_enq_valid_T & _tl_resp_queues_5_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_5_enq_valid = _tl_resp_queues_5_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_6_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h6; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_6_enq_valid_T_2 = _tl_resp_queues_6_enq_valid_T & _tl_resp_queues_6_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_6_enq_valid = _tl_resp_queues_6_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_7_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h7; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_7_enq_valid_T_2 = _tl_resp_queues_7_enq_valid_T & _tl_resp_queues_7_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_7_enq_valid = _tl_resp_queues_7_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_8_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h8; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_8_enq_valid_T_2 = _tl_resp_queues_8_enq_valid_T & _tl_resp_queues_8_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_8_enq_valid = _tl_resp_queues_8_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_9_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h9; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_9_enq_valid_T_2 = _tl_resp_queues_9_enq_valid_T & _tl_resp_queues_9_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_9_enq_valid = _tl_resp_queues_9_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_10_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'hA; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_10_enq_valid_T_2 = _tl_resp_queues_10_enq_valid_T & _tl_resp_queues_10_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_10_enq_valid = _tl_resp_queues_10_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_11_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'hB; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_11_enq_valid_T_2 = _tl_resp_queues_11_enq_valid_T & _tl_resp_queues_11_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_11_enq_valid = _tl_resp_queues_11_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_12_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'hC; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_12_enq_valid_T_2 = _tl_resp_queues_12_enq_valid_T & _tl_resp_queues_12_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_12_enq_valid = _tl_resp_queues_12_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_13_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'hD; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_13_enq_valid_T_2 = _tl_resp_queues_13_enq_valid_T & _tl_resp_queues_13_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_13_enq_valid = _tl_resp_queues_13_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_14_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'hE; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_14_enq_valid_T_2 = _tl_resp_queues_14_enq_valid_T & _tl_resp_queues_14_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_14_enq_valid = _tl_resp_queues_14_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_15_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'hF; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_15_enq_valid_T_2 = _tl_resp_queues_15_enq_valid_T & _tl_resp_queues_15_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_15_enq_valid = _tl_resp_queues_15_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_16_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h10; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_16_enq_valid_T_2 = _tl_resp_queues_16_enq_valid_T & _tl_resp_queues_16_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_16_enq_valid = _tl_resp_queues_16_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_17_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h11; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_17_enq_valid_T_2 = _tl_resp_queues_17_enq_valid_T & _tl_resp_queues_17_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_17_enq_valid = _tl_resp_queues_17_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_18_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h12; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_18_enq_valid_T_2 = _tl_resp_queues_18_enq_valid_T & _tl_resp_queues_18_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_18_enq_valid = _tl_resp_queues_18_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_19_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h13; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_19_enq_valid_T_2 = _tl_resp_queues_19_enq_valid_T & _tl_resp_queues_19_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_19_enq_valid = _tl_resp_queues_19_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_20_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h14; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_20_enq_valid_T_2 = _tl_resp_queues_20_enq_valid_T & _tl_resp_queues_20_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_20_enq_valid = _tl_resp_queues_20_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_21_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h15; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_21_enq_valid_T_2 = _tl_resp_queues_21_enq_valid_T & _tl_resp_queues_21_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_21_enq_valid = _tl_resp_queues_21_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_22_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h16; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_22_enq_valid_T_2 = _tl_resp_queues_22_enq_valid_T & _tl_resp_queues_22_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_22_enq_valid = _tl_resp_queues_22_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_23_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h17; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_23_enq_valid_T_2 = _tl_resp_queues_23_enq_valid_T & _tl_resp_queues_23_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_23_enq_valid = _tl_resp_queues_23_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_24_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h18; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_24_enq_valid_T_2 = _tl_resp_queues_24_enq_valid_T & _tl_resp_queues_24_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_24_enq_valid = _tl_resp_queues_24_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_25_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h19; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_25_enq_valid_T_2 = _tl_resp_queues_25_enq_valid_T & _tl_resp_queues_25_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_25_enq_valid = _tl_resp_queues_25_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_26_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h1A; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_26_enq_valid_T_2 = _tl_resp_queues_26_enq_valid_T & _tl_resp_queues_26_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_26_enq_valid = _tl_resp_queues_26_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_27_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h1B; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_27_enq_valid_T_2 = _tl_resp_queues_27_enq_valid_T & _tl_resp_queues_27_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_27_enq_valid = _tl_resp_queues_27_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_28_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h1C; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_28_enq_valid_T_2 = _tl_resp_queues_28_enq_valid_T & _tl_resp_queues_28_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_28_enq_valid = _tl_resp_queues_28_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_29_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h1D; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_29_enq_valid_T_2 = _tl_resp_queues_29_enq_valid_T & _tl_resp_queues_29_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_29_enq_valid = _tl_resp_queues_29_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_30_enq_valid_T_1 = masterNodeOut_d_bits_source == 5'h1E; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_30_enq_valid_T_2 = _tl_resp_queues_30_enq_valid_T & _tl_resp_queues_30_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_30_enq_valid = _tl_resp_queues_30_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire _tl_resp_queues_31_enq_valid_T_1 = &masterNodeOut_d_bits_source; // @[L2MemHelper.scala:268:99]
assign _tl_resp_queues_31_enq_valid_T_2 = _tl_resp_queues_31_enq_valid_T & _tl_resp_queues_31_enq_valid_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_31_enq_valid = _tl_resp_queues_31_enq_valid_T_2; // @[L2MemHelper.scala:196:73, :268:76]
wire [4:0] _currentQueue_T;
wire [4:0] _currentQueue_T_1 = _currentQueue_T;
wire [7:0] _resultdata_T = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelper.scala:125:36, :281:94]
wire [31:0] _GEN_17 = {{tl_resp_queues_31_deq_valid}, {tl_resp_queues_30_deq_valid}, {tl_resp_queues_29_deq_valid}, {tl_resp_queues_28_deq_valid}, {tl_resp_queues_27_deq_valid}, {tl_resp_queues_26_deq_valid}, {tl_resp_queues_25_deq_valid}, {tl_resp_queues_24_deq_valid}, {tl_resp_queues_23_deq_valid}, {tl_resp_queues_22_deq_valid}, {tl_resp_queues_21_deq_valid}, {tl_resp_queues_20_deq_valid}, {tl_resp_queues_19_deq_valid}, {tl_resp_queues_18_deq_valid}, {tl_resp_queues_17_deq_valid}, {tl_resp_queues_16_deq_valid}, {tl_resp_queues_15_deq_valid}, {tl_resp_queues_14_deq_valid}, {tl_resp_queues_13_deq_valid}, {tl_resp_queues_12_deq_valid}, {tl_resp_queues_11_deq_valid}, {tl_resp_queues_10_deq_valid}, {tl_resp_queues_9_deq_valid}, {tl_resp_queues_8_deq_valid}, {tl_resp_queues_7_deq_valid}, {tl_resp_queues_6_deq_valid}, {tl_resp_queues_5_deq_valid}, {tl_resp_queues_4_deq_valid}, {tl_resp_queues_3_deq_valid}, {tl_resp_queues_2_deq_valid}, {tl_resp_queues_1_deq_valid}, {tl_resp_queues_0_deq_valid}}; // @[L2MemHelper.scala:196:73, :281:47]
wire [31:0][255:0] _GEN_18 = {{tl_resp_queues_31_deq_bits_data}, {tl_resp_queues_30_deq_bits_data}, {tl_resp_queues_29_deq_bits_data}, {tl_resp_queues_28_deq_bits_data}, {tl_resp_queues_27_deq_bits_data}, {tl_resp_queues_26_deq_bits_data}, {tl_resp_queues_25_deq_bits_data}, {tl_resp_queues_24_deq_bits_data}, {tl_resp_queues_23_deq_bits_data}, {tl_resp_queues_22_deq_bits_data}, {tl_resp_queues_21_deq_bits_data}, {tl_resp_queues_20_deq_bits_data}, {tl_resp_queues_19_deq_bits_data}, {tl_resp_queues_18_deq_bits_data}, {tl_resp_queues_17_deq_bits_data}, {tl_resp_queues_16_deq_bits_data}, {tl_resp_queues_15_deq_bits_data}, {tl_resp_queues_14_deq_bits_data}, {tl_resp_queues_13_deq_bits_data}, {tl_resp_queues_12_deq_bits_data}, {tl_resp_queues_11_deq_bits_data}, {tl_resp_queues_10_deq_bits_data}, {tl_resp_queues_9_deq_bits_data}, {tl_resp_queues_8_deq_bits_data}, {tl_resp_queues_7_deq_bits_data}, {tl_resp_queues_6_deq_bits_data}, {tl_resp_queues_5_deq_bits_data}, {tl_resp_queues_4_deq_bits_data}, {tl_resp_queues_3_deq_bits_data}, {tl_resp_queues_2_deq_bits_data}, {tl_resp_queues_1_deq_bits_data}, {tl_resp_queues_0_deq_bits_data}}; // @[L2MemHelper.scala:196:73, :281:47]
assign resultdata = _GEN_18[_currentQueue_T_1] >> _resultdata_T; // @[L2MemHelper.scala:281:{47,94}]
assign response_output_bits_data = resultdata; // @[L2MemHelper.scala:88:29, :281:47]
assign _response_output_valid_T = _GEN_17[_currentQueue_T_1] & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53]
assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_deq_ready_T = _GEN_17[_currentQueue_T_1] & response_output_ready; // @[Misc.scala:26:53]
wire _GEN_19 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53]
wire _tl_resp_queues_0_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_0_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_1_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_1_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_2_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_2_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_3_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_3_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_4_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_4_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_5_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_5_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_6_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_6_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_7_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_7_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_8_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_8_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_9_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_9_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_10_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_10_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_11_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_11_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_12_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_12_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_13_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_13_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_14_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_14_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_15_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_15_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_16_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_16_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_17_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_17_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_18_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_18_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_19_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_19_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_20_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_20_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_21_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_21_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_22_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_22_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_23_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_23_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_24_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_24_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_25_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_25_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_26_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_26_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_27_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_27_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_28_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_28_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_29_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_29_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_30_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_30_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_31_deq_ready_T; // @[Misc.scala:26:53]
assign _tl_resp_queues_31_deq_ready_T = _GEN_19; // @[Misc.scala:26:53]
wire _tl_resp_queues_0_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_0_deq_ready_T_2 = _tl_resp_queues_0_deq_ready_T & _tl_resp_queues_0_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_0_deq_ready = _tl_resp_queues_0_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_1_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_1_deq_ready_T_2 = _tl_resp_queues_1_deq_ready_T & _tl_resp_queues_1_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_1_deq_ready = _tl_resp_queues_1_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_2_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_2_deq_ready_T_2 = _tl_resp_queues_2_deq_ready_T & _tl_resp_queues_2_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_2_deq_ready = _tl_resp_queues_2_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_3_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_3_deq_ready_T_2 = _tl_resp_queues_3_deq_ready_T & _tl_resp_queues_3_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_3_deq_ready = _tl_resp_queues_3_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_4_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_4_deq_ready_T_2 = _tl_resp_queues_4_deq_ready_T & _tl_resp_queues_4_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_4_deq_ready = _tl_resp_queues_4_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_5_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_5_deq_ready_T_2 = _tl_resp_queues_5_deq_ready_T & _tl_resp_queues_5_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_5_deq_ready = _tl_resp_queues_5_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_6_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_6_deq_ready_T_2 = _tl_resp_queues_6_deq_ready_T & _tl_resp_queues_6_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_6_deq_ready = _tl_resp_queues_6_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_7_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_7_deq_ready_T_2 = _tl_resp_queues_7_deq_ready_T & _tl_resp_queues_7_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_7_deq_ready = _tl_resp_queues_7_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_8_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_8_deq_ready_T_2 = _tl_resp_queues_8_deq_ready_T & _tl_resp_queues_8_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_8_deq_ready = _tl_resp_queues_8_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_9_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_9_deq_ready_T_2 = _tl_resp_queues_9_deq_ready_T & _tl_resp_queues_9_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_9_deq_ready = _tl_resp_queues_9_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_10_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_10_deq_ready_T_2 = _tl_resp_queues_10_deq_ready_T & _tl_resp_queues_10_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_10_deq_ready = _tl_resp_queues_10_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_11_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_11_deq_ready_T_2 = _tl_resp_queues_11_deq_ready_T & _tl_resp_queues_11_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_11_deq_ready = _tl_resp_queues_11_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_12_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_12_deq_ready_T_2 = _tl_resp_queues_12_deq_ready_T & _tl_resp_queues_12_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_12_deq_ready = _tl_resp_queues_12_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_13_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_13_deq_ready_T_2 = _tl_resp_queues_13_deq_ready_T & _tl_resp_queues_13_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_13_deq_ready = _tl_resp_queues_13_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_14_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_14_deq_ready_T_2 = _tl_resp_queues_14_deq_ready_T & _tl_resp_queues_14_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_14_deq_ready = _tl_resp_queues_14_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_15_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_15_deq_ready_T_2 = _tl_resp_queues_15_deq_ready_T & _tl_resp_queues_15_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_15_deq_ready = _tl_resp_queues_15_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_16_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_16_deq_ready_T_2 = _tl_resp_queues_16_deq_ready_T & _tl_resp_queues_16_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_16_deq_ready = _tl_resp_queues_16_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_17_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_17_deq_ready_T_2 = _tl_resp_queues_17_deq_ready_T & _tl_resp_queues_17_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_17_deq_ready = _tl_resp_queues_17_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_18_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_18_deq_ready_T_2 = _tl_resp_queues_18_deq_ready_T & _tl_resp_queues_18_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_18_deq_ready = _tl_resp_queues_18_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_19_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_19_deq_ready_T_2 = _tl_resp_queues_19_deq_ready_T & _tl_resp_queues_19_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_19_deq_ready = _tl_resp_queues_19_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_20_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_20_deq_ready_T_2 = _tl_resp_queues_20_deq_ready_T & _tl_resp_queues_20_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_20_deq_ready = _tl_resp_queues_20_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_21_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_21_deq_ready_T_2 = _tl_resp_queues_21_deq_ready_T & _tl_resp_queues_21_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_21_deq_ready = _tl_resp_queues_21_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_22_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_22_deq_ready_T_2 = _tl_resp_queues_22_deq_ready_T & _tl_resp_queues_22_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_22_deq_ready = _tl_resp_queues_22_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_23_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_23_deq_ready_T_2 = _tl_resp_queues_23_deq_ready_T & _tl_resp_queues_23_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_23_deq_ready = _tl_resp_queues_23_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_24_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_24_deq_ready_T_2 = _tl_resp_queues_24_deq_ready_T & _tl_resp_queues_24_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_24_deq_ready = _tl_resp_queues_24_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_25_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_25_deq_ready_T_2 = _tl_resp_queues_25_deq_ready_T & _tl_resp_queues_25_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_25_deq_ready = _tl_resp_queues_25_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_26_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_26_deq_ready_T_2 = _tl_resp_queues_26_deq_ready_T & _tl_resp_queues_26_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_26_deq_ready = _tl_resp_queues_26_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_27_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_27_deq_ready_T_2 = _tl_resp_queues_27_deq_ready_T & _tl_resp_queues_27_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_27_deq_ready = _tl_resp_queues_27_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_28_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_28_deq_ready_T_2 = _tl_resp_queues_28_deq_ready_T & _tl_resp_queues_28_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_28_deq_ready = _tl_resp_queues_28_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_29_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_29_deq_ready_T_2 = _tl_resp_queues_29_deq_ready_T & _tl_resp_queues_29_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_29_deq_ready = _tl_resp_queues_29_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_30_deq_ready_T_1 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_30_deq_ready_T_2 = _tl_resp_queues_30_deq_ready_T & _tl_resp_queues_30_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_30_deq_ready = _tl_resp_queues_30_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _tl_resp_queues_31_deq_ready_T_1 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelper.scala:125:36, :289:109]
assign _tl_resp_queues_31_deq_ready_T_2 = _tl_resp_queues_31_deq_ready_T & _tl_resp_queues_31_deq_ready_T_1; // @[Misc.scala:26:53]
assign tl_resp_queues_31_deq_ready = _tl_resp_queues_31_deq_ready_T_2; // @[L2MemHelper.scala:196:73, :289:68]
wire _T_49 = masterNodeOut_d_ready & masterNodeOut_d_valid; // @[Decoupled.scala:51:35]
wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
reg [63:0] allargs_0_8; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, allargs_0_8} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Logger.scala:38:38]
reg [63:0] allargs_0_9; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, allargs_0_9} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Logger.scala:38:38]
wire _T_50 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35]
reg [63:0] allargs_0_10; // @[Logger.scala:37:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, allargs_0_10} + 65'h1; // @[Logger.scala:37:33, :38:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Logger.scala:38:38] |
Generate the Verilog code corresponding to the following Chisel files.
File IterativeTrapCheck.scala:
package saturn.frontend
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._
import saturn.common._
class IndexMaskAccess(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val in = Input(Bool())
val inst = Input(new VectorIssueInst)
val index_access = Flipped(new VectorIndexAccessIO)
val mask_access = Flipped(new VectorMaskAccessIO)
val access = new Bundle {
val ready = Output(Bool())
val eidx = Input(UInt(log2Ceil(maxVLMax).W))
val index = Output(UInt(64.W))
val mask = Output(Bool())
}
val pop = Input(Valid(UInt(log2Ceil(maxVLMax).W)))
val flush = Input(Bool())
})
val valid = RegInit(false.B)
val eidx = Reg(UInt(log2Ceil(maxVLMax).W))
// This all works only with pow2 buffers and eidx starting at 0
val valids = Reg(Vec(4, Bool()))
val indices = Reg(Vec(4, UInt(64.W)))
val masks = Reg(Vec(4, Bool()))
when (io.in) {
assert(!valid)
valid := true.B
eidx := 0.U
valids.foreach(_ := false.B)
}
val needs_index = io.inst.mop.isOneOf(mopOrdered, mopUnordered)
val needs_mask = !io.inst.vm
val index_ready = io.index_access.ready || !needs_index
val mask_ready = io.mask_access.ready || !needs_mask
io.index_access.valid := valid && needs_index && !valids(eidx(1,0))
io.mask_access.valid := valid && needs_mask && !valids(eidx(1,0))
io.index_access.vrs := io.inst.rs2
io.index_access.eidx := eidx
io.index_access.eew := io.inst.mem_idx_size
io.mask_access.eidx := eidx
when (valid && index_ready && mask_ready && !valids(eidx(1,0))) {
val next_eidx = eidx +& 1.U
eidx := eidx + 1.U
when (next_eidx === io.inst.vconfig.vl) {
valid := false.B
}
valids(eidx(1,0)) := true.B
indices(eidx(1,0)) := io.index_access.idx
masks(eidx(1,0)) := io.mask_access.mask
}
io.access.ready := valids(io.access.eidx(1,0))
io.access.index := indices(io.access.eidx(1,0))
io.access.mask := masks(io.access.eidx(1,0))
when (io.pop.fire) {
valids(io.pop.bits(1,0)) := false.B
}
when (io.flush) {
valid := false.B
}
}
class IterativeTrapCheck(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val status = Input(new MStatus)
val in = Input(Valid(new VectorIssueInst))
val busy = Output(Bool())
val s0_tlb_req = Valid(new TLBReq(3))
val s1_tlb_req = Valid(new TLBReq(3))
val tlb_resp = Input(new TLBResp)
val retire = Output(Bool())
val pc = Output(UInt(vaddrBitsExtended.W))
val vstart = Valid(UInt(log2Ceil(maxVLMax).W))
val vconfig = Valid(new VConfig)
val xcpt = Valid(new Bundle {
val cause = UInt(xLen.W)
val tval = UInt(coreMaxAddrBits.W)
})
val inst = Output(new VectorIssueInst)
val issue = Decoupled(new VectorIssueInst)
val index_access = Flipped(new VectorIndexAccessIO)
val mask_access = Flipped(new VectorMaskAccessIO)
})
val replay_kill = WireInit(false.B)
def nextPage(addr: UInt) = ((addr + (1 << pgIdxBits).U) >> pgIdxBits) << pgIdxBits
val valid = RegInit(false.B)
val seg_hi = Reg(Bool())
val inst = Reg(new VectorIssueInst)
val eidx = Reg(UInt(log2Ceil(maxVLMax).W))
val addr = Reg(UInt(vaddrBitsExtended.W))
val tlb_backoff = RegInit(0.U(2.W))
when (tlb_backoff =/= 0.U) { tlb_backoff := tlb_backoff - 1.U }
val im_access = Module(new IndexMaskAccess)
im_access.io.in := io.in.valid
im_access.io.inst := inst
im_access.io.index_access <> io.index_access
im_access.io.mask_access <> io.mask_access
when (io.in.valid) {
assert(!valid)
valid := true.B
seg_hi := false.B
inst := io.in.bits
eidx := 0.U
addr := io.in.bits.rs1_data
}
val stride = MuxLookup(inst.mop, 0.U)(Seq(
(mopUnit -> ((inst.seg_nf +& 1.U) << inst.mem_elem_size)),
(mopStrided -> inst.rs2_data)
))
val indexed = inst.mop.isOneOf(mopOrdered, mopUnordered)
val index_ready = !indexed || im_access.io.access.ready
val mask_ready = inst.vm || im_access.io.access.ready
val index = Mux(indexed, im_access.io.access.index & eewBitMask(inst.mem_idx_size), 0.U)
val base = Mux(indexed, inst.rs1_data, addr)
val indexaddr = base + index
val tlb_addr = Mux(seg_hi, nextPage(indexaddr), indexaddr)
val seg_nf_consumed = ((1 << pgIdxBits).U - Mux(seg_hi, indexaddr, tlb_addr)(pgIdxBits-1,0)) >> inst.mem_elem_size
val seg_single_page = seg_nf_consumed >= (inst.seg_nf +& 1.U)
val masked = !im_access.io.access.mask && !inst.vm
val tlb_valid = eidx < inst.vconfig.vl && eidx >= inst.vstart && !masked
val ff = inst.umop === lumopFF && inst.mop === mopUnit
io.busy := valid
io.inst := inst
im_access.io.access.eidx := eidx
io.s0_tlb_req.valid := tlb_valid && tlb_backoff === 0.U && index_ready && mask_ready
io.s0_tlb_req.bits.vaddr := tlb_addr
io.s0_tlb_req.bits.passthrough := false.B
io.s0_tlb_req.bits.size := inst.mem_elem_size
io.s0_tlb_req.bits.cmd := Mux(inst.opcode(5), M_XWR, M_XRD)
io.s0_tlb_req.bits.prv := io.status.prv
io.s0_tlb_req.bits.v := io.status.v
io.s1_tlb_req.valid := RegEnable(io.s0_tlb_req.valid, false.B, valid)
io.s1_tlb_req.bits := RegEnable(io.s0_tlb_req.bits, valid)
val replay_fire = valid && eidx < inst.vconfig.vl && tlb_backoff === 0.U && index_ready && mask_ready
when (replay_fire) {
when (seg_hi || seg_single_page || inst.seg_nf === 0.U) {
eidx := eidx + 1.U
addr := addr + stride
seg_hi := false.B
} .otherwise {
seg_hi := true.B
}
}
val s1_valid = RegNext(replay_fire && !replay_kill, false.B)
val s1_eidx = RegEnable(eidx, valid)
val s1_masked = RegEnable(masked, valid)
val s1_seg_hi = RegEnable(seg_hi, valid)
val s1_base = RegEnable(base, valid)
val s1_tlb_valid = RegEnable(tlb_valid, valid)
val s1_tlb_addr = RegEnable(tlb_addr, valid)
val s1_seg_nf_consumed = RegEnable(seg_nf_consumed, valid)
val s1_seg_single_page = RegEnable(seg_single_page, valid)
when (io.tlb_resp.miss && s1_valid && tlb_backoff === 0.U) { tlb_backoff := 3.U }
val tlb_resp = WireInit(io.tlb_resp)
when (!s1_tlb_valid) {
tlb_resp.miss := false.B
}
val xcpts = Seq(
(tlb_resp.pf.st, Causes.store_page_fault.U),
(tlb_resp.pf.ld, Causes.load_page_fault.U),
(tlb_resp.gf.st, Causes.store_guest_page_fault.U),
(tlb_resp.gf.ld, Causes.load_guest_page_fault.U),
(tlb_resp.ae.st, Causes.store_access.U),
(tlb_resp.ae.ld, Causes.load_access.U),
(tlb_resp.ma.st, Causes.misaligned_store.U),
(tlb_resp.ma.ld, Causes.misaligned_load.U)
)
val xcpt = xcpts.map(_._1).orR && s1_eidx >= inst.vstart && !s1_masked
val cause = PriorityMux(xcpts)
io.issue.valid := false.B
io.issue.bits := inst
io.issue.bits.vstart := s1_eidx
io.issue.bits.vconfig.vl := s1_eidx +& 1.U
io.issue.bits.segend := inst.seg_nf
io.issue.bits.segstart := 0.U
io.issue.bits.page := tlb_resp.paddr >> pgIdxBits
io.xcpt.valid := false.B
io.pc := inst.pc
io.xcpt.bits.cause := cause
io.xcpt.bits.tval := s1_tlb_addr
io.vstart.valid := false.B
io.vstart.bits := s1_eidx
io.retire := false.B
io.vconfig.valid := false.B
io.vconfig.bits := inst.vconfig
io.vconfig.bits.vl := s1_eidx
im_access.io.pop.valid := false.B
im_access.io.pop.bits := s1_eidx
im_access.io.flush := false.B
when (s1_valid) {
io.issue.valid := !tlb_resp.miss && !xcpt && s1_eidx >= inst.vstart && !s1_masked
when (inst.seg_nf =/= 0.U && !s1_seg_single_page) {
when (!s1_seg_hi) {
io.issue.bits.segend := s1_seg_nf_consumed - 1.U
} .otherwise {
io.issue.bits.segstart := s1_seg_nf_consumed
}
}
when (s1_seg_hi || s1_seg_single_page || inst.seg_nf === 0.U) {
im_access.io.pop.valid := true.B
}
when (tlb_resp.miss || !io.issue.ready) {
tlb_backoff := 3.U
replay_kill := true.B
eidx := s1_eidx
addr := s1_base
seg_hi := s1_seg_hi
im_access.io.pop.valid := false.B
} .elsewhen (xcpt) {
val ff_nofault = ff && s1_eidx =/= 0.U
valid := false.B
replay_kill := true.B
io.retire := ff_nofault
io.xcpt.valid := !ff_nofault
io.vstart.valid := !ff_nofault
io.vconfig.valid := ff_nofault
im_access.io.flush := true.B
} .elsewhen ((s1_eidx +& 1.U) === inst.vconfig.vl && (s1_seg_hi || s1_seg_single_page || inst.seg_nf === 0.U)) {
valid := false.B
replay_kill := true.B
io.retire := true.B
io.vstart.valid := true.B
io.vstart.bits := 0.U
im_access.io.flush := true.B
}
}
}
| module IndexMaskAccess( // @[IterativeTrapCheck.scala:14:7]
input clock, // @[IterativeTrapCheck.scala:14:7]
input reset, // @[IterativeTrapCheck.scala:14:7]
input io_in, // @[IterativeTrapCheck.scala:15:14]
input [31:0] io_inst_bits, // @[IterativeTrapCheck.scala:15:14]
input [6:0] io_inst_vconfig_vl, // @[IterativeTrapCheck.scala:15:14]
input [1:0] io_inst_mop, // @[IterativeTrapCheck.scala:15:14]
input io_index_access_ready, // @[IterativeTrapCheck.scala:15:14]
output io_index_access_valid, // @[IterativeTrapCheck.scala:15:14]
output [4:0] io_index_access_vrs, // @[IterativeTrapCheck.scala:15:14]
output [6:0] io_index_access_eidx, // @[IterativeTrapCheck.scala:15:14]
output [1:0] io_index_access_eew, // @[IterativeTrapCheck.scala:15:14]
input [63:0] io_index_access_idx, // @[IterativeTrapCheck.scala:15:14]
input io_mask_access_ready, // @[IterativeTrapCheck.scala:15:14]
output io_mask_access_valid, // @[IterativeTrapCheck.scala:15:14]
output [6:0] io_mask_access_eidx, // @[IterativeTrapCheck.scala:15:14]
input io_mask_access_mask, // @[IterativeTrapCheck.scala:15:14]
output io_access_ready, // @[IterativeTrapCheck.scala:15:14]
input [5:0] io_access_eidx, // @[IterativeTrapCheck.scala:15:14]
output [63:0] io_access_index, // @[IterativeTrapCheck.scala:15:14]
output io_access_mask, // @[IterativeTrapCheck.scala:15:14]
input io_pop_valid, // @[IterativeTrapCheck.scala:15:14]
input [5:0] io_pop_bits, // @[IterativeTrapCheck.scala:15:14]
input io_flush // @[IterativeTrapCheck.scala:15:14]
);
reg valid; // @[IterativeTrapCheck.scala:33:22]
reg [5:0] eidx; // @[IterativeTrapCheck.scala:34:17]
reg valids_0; // @[IterativeTrapCheck.scala:36:19]
reg valids_1; // @[IterativeTrapCheck.scala:36:19]
reg valids_2; // @[IterativeTrapCheck.scala:36:19]
reg valids_3; // @[IterativeTrapCheck.scala:36:19]
reg [63:0] indices_0; // @[IterativeTrapCheck.scala:37:20]
reg [63:0] indices_1; // @[IterativeTrapCheck.scala:37:20]
reg [63:0] indices_2; // @[IterativeTrapCheck.scala:37:20]
reg [63:0] indices_3; // @[IterativeTrapCheck.scala:37:20]
reg masks_0; // @[IterativeTrapCheck.scala:38:18]
reg masks_1; // @[IterativeTrapCheck.scala:38:18]
reg masks_2; // @[IterativeTrapCheck.scala:38:18]
reg masks_3; // @[IterativeTrapCheck.scala:38:18] |
Generate the Verilog code corresponding to the following Chisel files.
File ListBuffer.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
}
| module data_33x47( // @[ListBuffer.scala:52:18]
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [46:0] R0_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [46:0] W0_data
);
reg [46:0] Memory[0:32]; // @[ListBuffer.scala:52:18]
always @(posedge W0_clk) begin // @[ListBuffer.scala:52:18]
if (W0_en & 1'h1) // @[ListBuffer.scala:52:18]
Memory[W0_addr] <= W0_data; // @[ListBuffer.scala:52:18]
always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 47'bx; // @[ListBuffer.scala:52:18]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_237( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_493 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_92( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Nodes.scala:
package constellation.channel
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
case class EmptyParams()
case class ChannelEdgeParams(cp: ChannelParams, p: Parameters)
object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {
def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
ChannelEdgeParams(pu, p)
}
def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)
def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString)
}
override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {
val monitor = Module(new NoCMonitor(edge.cp)(edge.p))
monitor.io.in := bundle
}
// TODO: Add nodepath stuff? override def mixO, override def mixI
}
case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))
case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))
case class ChannelAdapterNode(
slaveFn: ChannelParams => ChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)
case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()
case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()
case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)
case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)
object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {
def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
IngressChannelEdgeParams(pu, p)
}
def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)
def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString)
}
}
object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {
def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
EgressChannelEdgeParams(pu, p)
}
def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)
def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString)
}
}
case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))
case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))
case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))
case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))
case class IngressChannelAdapterNode(
slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)
case class EgressChannelAdapterNode(
slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)
case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()
case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()
case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()
case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()
File Router.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{RoutingRelation}
import constellation.noc.{HasNoCParams}
case class UserRouterParams(
// Payload width. Must match payload width on all channels attached to this routing node
payloadBits: Int = 64,
// Combines SA and ST stages (removes pipeline register)
combineSAST: Boolean = false,
// Combines RC and VA stages (removes pipeline register)
combineRCVA: Boolean = false,
// Adds combinational path from SA to VA
coupleSAVA: Boolean = false,
vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)
)
case class RouterParams(
nodeId: Int,
nIngress: Int,
nEgress: Int,
user: UserRouterParams
)
trait HasRouterOutputParams {
def outParams: Seq[ChannelParams]
def egressParams: Seq[EgressChannelParams]
def allOutParams = outParams ++ egressParams
def nOutputs = outParams.size
def nEgress = egressParams.size
def nAllOutputs = allOutParams.size
}
trait HasRouterInputParams {
def inParams: Seq[ChannelParams]
def ingressParams: Seq[IngressChannelParams]
def allInParams = inParams ++ ingressParams
def nInputs = inParams.size
def nIngress = ingressParams.size
def nAllInputs = allInParams.size
}
trait HasRouterParams
{
def routerParams: RouterParams
def nodeId = routerParams.nodeId
def payloadBits = routerParams.user.payloadBits
}
class DebugBundle(val nIn: Int) extends Bundle {
val va_stall = Vec(nIn, UInt())
val sa_stall = Vec(nIn, UInt())
}
class Router(
val routerParams: RouterParams,
preDiplomaticInParams: Seq[ChannelParams],
preDiplomaticIngressParams: Seq[IngressChannelParams],
outDests: Seq[Int],
egressIds: Seq[Int]
)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {
val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams
val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))
val sourceNodes = outDests.map(u => ChannelSourceNode(u))
val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))
val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))
val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))
val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None
def inParams = module.inParams
def outParams = module.outParams
def ingressParams = module.ingressParams
def egressParams = module.egressParams
lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {
val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip
val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip
val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip
val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip
val io_debug = debugNode.out(0)._1
val inParams = edgesIn.map(_.cp)
val outParams = edgesOut.map(_.cp)
val ingressParams = edgesIngress.map(_.cp)
val egressParams = edgesEgress.map(_.cp)
allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))
allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))
require(nIngress == routerParams.nIngress)
require(nEgress == routerParams.nEgress)
require(nAllInputs >= 1)
require(nAllOutputs >= 1)
require(nodeId < (1 << nodeIdBits))
val input_units = inParams.zipWithIndex.map { case (u,i) =>
Module(new InputUnit(u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"input_unit_${i}_from_${u.srcId}") }
val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>
Module(new IngressUnit(i, u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") }
val all_input_units = input_units ++ ingress_units
val output_units = outParams.zipWithIndex.map { case (u,i) =>
Module(new OutputUnit(inParams, ingressParams, u))
.suggestName(s"output_unit_${i}_to_${u.destId}")}
val egress_units = egressParams.zipWithIndex.map { case (u,i) =>
Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,
routerParams.user.combineSAST,
inParams, ingressParams, u))
.suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")}
val all_output_units = output_units ++ egress_units
val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))
val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))
val vc_allocator = Module(routerParams.user.vcAllocator(
VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)
)(p))
val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))
val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))
dontTouch(fires_count)
(io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }
(io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }
(output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }
(egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }
(route_computer.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.router_req }
(all_input_units zip route_computer.io.resp).foreach {
case (u,o) => u.io.router_resp <> o }
(vc_allocator.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.vcalloc_req }
(all_input_units zip vc_allocator.io.resp).foreach {
case (u,o) => u.io.vcalloc_resp <> o }
(all_output_units zip vc_allocator.io.out_allocs).foreach {
case (u,a) => u.io.allocs <> a }
(vc_allocator.io.channel_status zip all_output_units).foreach {
case (a,u) => a := u.io.channel_status }
all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>
in.io.out_credit_available(outIdx) := out.io.credit_available
})
(all_input_units zip switch_allocator.io.req).foreach {
case (u,r) => r <> u.io.salloc_req }
(all_output_units zip switch_allocator.io.credit_alloc).foreach {
case (u,a) => u.io.credit_alloc := a }
(switch.io.in zip all_input_units).foreach {
case (i,u) => i <> u.io.out }
(all_output_units zip switch.io.out).foreach {
case (u,o) => u.io.in <> o }
switch.io.sel := (if (routerParams.user.combineSAST) {
switch_allocator.io.switch_sel
} else {
RegNext(switch_allocator.io.switch_sel)
})
if (hasCtrl) {
val io_ctrl = ctrlNode.get.out(0)._1
val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))
io_ctrl <> ctrl.io.ctrl
(all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }
(all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }
} else {
input_units.foreach(_.io.block := false.B)
ingress_units.foreach(_.io.block := false.B)
}
(io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }
(io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }
val debug_tsc = RegInit(0.U(64.W))
debug_tsc := debug_tsc + 1.U
val debug_sample = RegInit(0.U(64.W))
debug_sample := debug_sample + 1.U
val sample_rate = PlusArg("noc_util_sample_rate", width=20)
when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }
def sample(fire: Bool, s: String) = {
val util_ctr = RegInit(0.U(64.W))
val fired = RegInit(false.B)
util_ctr := util_ctr + fire
fired := fired || fire
when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {
val fmtStr = s"nocsample %d $s %d\n"
printf(fmtStr, debug_tsc, util_ctr);
fired := fire
}
}
destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>
sample(f.fire, s"${edge.cp.srcId} $nodeId")
} }
ingressNodes.map(_.in(0)).foreach { case (in, edge) =>
sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId")
}
egressNodes.map(_.out(0)).foreach { case (out, edge) =>
sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}")
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module Router_5( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [4:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_va_stall_5, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_debug_out_sa_stall_5, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_4_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_4_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_4_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_4_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_3_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_3_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_3_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_3_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_3_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_4_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_4_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_4_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_4_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_4_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_ingress_nodes_in_4_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_3_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_3_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_3_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_3_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_3_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_ingress_nodes_in_3_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _vc_allocator_io_req_5_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_10; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_11; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_12; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_13; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_14; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_15; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_16; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_17; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_18; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_19; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_20; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_21; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_10; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_11; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_12; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_13; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_14; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_15; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_16; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_17; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_18; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_19; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_20; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_21; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_8; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_9; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_10; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_11; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_12; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_13; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_14; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_15; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_16; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_17; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_18; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_19; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_20; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_21; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_5_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_4_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_8_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_9_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_12_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_13_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_16_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_17_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_20_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_21_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_5_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_5_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_5_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_4_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_4_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_8_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_9_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_12_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_13_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_16_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_17_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_20_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_21_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_io_out_5_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_5_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_5_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_5_0_bits_payload; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_5_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_5_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_4_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_4_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_4_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_4_0_bits_payload; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_4_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_4_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [5:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_5_to_49_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_5_to_49_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_5_to_49_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_4_to_48_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_4_to_48_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_4_to_48_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_3_to_47_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_47_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_47_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_2_to_7_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_7_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_7_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_6_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_6_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_6_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_26_io_credit_available_8; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_9; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_12; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_13; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_16; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_17; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_20; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_credit_available_21; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_8_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_9_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_12_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_13_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_16_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_17_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_20_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_26_io_channel_status_21_occupied; // @[Router.scala:122:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_10; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_11; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_14; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_15; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_16; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_17; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_18; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_19; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_5_from_54_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_5_from_54_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [5:0] _ingress_unit_5_from_54_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_5_from_54_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [5:0] _ingress_unit_5_from_54_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_5_from_54_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_5_from_54_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_5_from_54_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_10; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_11; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_14; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_15; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_16; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_17; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_18; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_19; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_4_from_53_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_4_from_53_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [5:0] _ingress_unit_4_from_53_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_4_from_53_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [5:0] _ingress_unit_4_from_53_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_4_from_53_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_4_from_53_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_4_from_53_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_10; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_11; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_12; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_13; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_14; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_15; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_16; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_17; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_18; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_19; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_20; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_vcalloc_req_bits_vc_sel_0_21; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_8; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_9; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_10; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_11; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_12; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_13; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_14; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_15; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_16; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_17; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_18; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_19; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_20; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_vc_sel_0_21; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_9_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_9_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [5:0] _ingress_unit_1_from_9_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_9_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [5:0] _ingress_unit_1_from_9_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_9_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_1_from_9_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_9_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_0_from_26_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_26_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_26_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [5:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_26_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_9_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_26_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_53_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_5_ready & _ingress_unit_5_from_54_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35]
reg REG_5_0_5_0; // @[Router.scala:178:14]
reg REG_5_0_4_0; // @[Router.scala:178:14]
reg REG_5_0_3_0; // @[Router.scala:178:14]
reg REG_5_0_2_0; // @[Router.scala:178:14]
reg REG_5_0_1_0; // @[Router.scala:178:14]
reg REG_5_0_0_0; // @[Router.scala:178:14]
reg REG_4_0_5_0; // @[Router.scala:178:14]
reg REG_4_0_4_0; // @[Router.scala:178:14]
reg REG_4_0_3_0; // @[Router.scala:178:14]
reg REG_4_0_2_0; // @[Router.scala:178:14]
reg REG_4_0_1_0; // @[Router.scala:178:14]
reg REG_4_0_0_0; // @[Router.scala:178:14]
reg REG_3_0_5_0; // @[Router.scala:178:14]
reg REG_3_0_4_0; // @[Router.scala:178:14]
reg REG_3_0_3_0; // @[Router.scala:178:14]
reg REG_3_0_2_0; // @[Router.scala:178:14]
reg REG_3_0_1_0; // @[Router.scala:178:14]
reg REG_3_0_0_0; // @[Router.scala:178:14]
reg REG_2_0_5_0; // @[Router.scala:178:14]
reg REG_2_0_4_0; // @[Router.scala:178:14]
reg REG_2_0_3_0; // @[Router.scala:178:14]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_5_0; // @[Router.scala:178:14]
reg REG_1_0_4_0; // @[Router.scala:178:14]
reg REG_1_0_3_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_5_0; // @[Router.scala:178:14]
reg REG_0_0_4_0; // @[Router.scala:178:14]
reg REG_0_0_3_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_6; // @[Router.scala:203:29]
reg fired_6; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_6; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_7; // @[Router.scala:203:29]
reg fired_7; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_7; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_8; // @[Router.scala:203:29]
reg fired_8; // @[Router.scala:204:26]
wire _GEN_7 = _GEN_0 & fired_8; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_9; // @[Router.scala:203:29]
reg fired_9; // @[Router.scala:204:26]
wire _GEN_8 = _GEN_0 & fired_9; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_10; // @[Router.scala:203:29]
reg fired_10; // @[Router.scala:204:26]
wire _GEN_9 = _GEN_0 & fired_10; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_4( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_5_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_4_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_5_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_4_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_5_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_4_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'h2; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_37 = io_in_bits_egress_id == 4'h1; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'h0; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 4'hC; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 4'h5; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 4'hB; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = io_in_bits_egress_id == 4'h3; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = io_in_bits_egress_id == 4'hA; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = io_in_bits_egress_id == 4'h9; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = io_in_bits_egress_id == 4'h7; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_29 = {2'h0, {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_1}}} | {4{_route_buffer_io_enq_bits_flow_egress_node_id_T_4}}; // @[Mux.scala:30:73]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_32 = {_route_buffer_io_enq_bits_flow_egress_node_T_29[3], _route_buffer_io_enq_bits_flow_egress_node_T_29[2:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_5, 2'h0}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'hE : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hB : 4'h0); // @[Mux.scala:30:73]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_37 = (_route_buffer_io_enq_bits_flow_egress_node_id_T_10 ? 4'hD : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_11 ? 4'hC : 4'h0) | {_route_buffer_io_enq_bits_flow_egress_node_T_32[3] | _route_buffer_io_enq_bits_flow_egress_node_id_T_12, {_route_buffer_io_enq_bits_flow_egress_node_T_32[2], _route_buffer_io_enq_bits_flow_egress_node_T_32[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_8, 1'h0}} | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_9}}}; // @[Mux.scala:30:73]
wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_37}; // @[IngressUnit.scala:30:72, :45:50]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & ~(|_route_buffer_io_enq_bits_flow_egress_node_T_37); // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & (|_route_buffer_io_enq_bits_flow_egress_node_T_37); // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
| module MulAddRecFNPipe_l2_e11_s53_1( // @[FPU.scala:633:7]
input clock, // @[FPU.scala:633:7]
input reset, // @[FPU.scala:633:7]
input io_validin, // @[FPU.scala:638:16]
input [1:0] io_op, // @[FPU.scala:638:16]
input [64:0] io_a, // @[FPU.scala:638:16]
input [64:0] io_b, // @[FPU.scala:638:16]
input [64:0] io_c, // @[FPU.scala:638:16]
input [2:0] io_roundingMode, // @[FPU.scala:638:16]
output [64:0] io_out, // @[FPU.scala:638:16]
output [4:0] io_exceptionFlags, // @[FPU.scala:638:16]
output io_validout // @[FPU.scala:638:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42]
wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42]
wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42]
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41]
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41]
wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41]
wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41]
wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41]
wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41]
wire io_validin_0 = io_validin; // @[FPU.scala:633:7]
wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7]
wire [64:0] io_a_0 = io_a; // @[FPU.scala:633:7]
wire [64:0] io_b_0 = io_b; // @[FPU.scala:633:7]
wire [64:0] io_c_0 = io_c; // @[FPU.scala:633:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7]
wire io_detectTininess = 1'h1; // @[FPU.scala:633:7]
wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37]
wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21]
wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_0; // @[FPU.scala:633:7]
wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7]
wire io_validout_0; // @[FPU.scala:633:7]
wire [105:0] _mulAddResult_T = {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45]
wire [106:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50]
wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
wire valid_stage0; // @[FPU.scala:667:28]
wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26]
reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26]
wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26]
reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26]
wire [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26]
reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26]
wire [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26]
wire [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24]
wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26]
assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26]
assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24]
wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg valid_stage0_pipe_v; // @[Valid.scala:141:24]
assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26]
reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26]
wire [12:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26]
reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26]
wire [55:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26]
reg io_validout_pipe_v; // @[Valid.scala:141:24]
assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24]
assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:633:7]
if (reset) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
end
if (io_validin_0) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
end
if (valid_stage0) begin // @[FPU.scala:667:28]
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26]
end
roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
always @(posedge)
MulAddRecFNToRaw_preMul_e11_s53_1 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41]
.io_op (io_op_0), // @[FPU.scala:633:7]
.io_a (io_a_0), // @[FPU.scala:633:7]
.io_b (io_b_0), // @[FPU.scala:633:7]
.io_c (io_c_0), // @[FPU.scala:633:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[FPU.scala:654:41]
MulAddRecFNToRaw_postMul_e11_s53_1 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42]
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21]
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21]
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21]
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21]
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21]
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21]
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21]
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21]
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21]
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21]
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21]
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21]
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[FPU.scala:655:42]
RoundRawFNToRecFN_e11_s53_2 roundRawFNToRecFN ( // @[FPU.scala:682:35]
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21]
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21]
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21]
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21]
.io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21]
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21]
.io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21]
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[FPU.scala:682:35]
assign io_out = io_out_0; // @[FPU.scala:633:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7]
assign io_validout = io_validout_0; // @[FPU.scala:633:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_157( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Pipeline.scala:
package gemmini
import chisel3._
import chisel3.util._
class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module {
val io = IO(new Bundle {
val in = Flipped(Decoupled(gen))
val out = Decoupled(gen)
val busy = Output(Bool())
})
require(comb.size == latency+1, "length of combinational is incorrect")
if (latency == 0) {
io.in.ready := io.out.ready
io.out.valid := io.in.valid
io.out.bits := comb.head(io.in.bits)
io.busy := io.in.valid
} else {
val stages = Reg(Vec(latency, gen))
val valids = RegInit(VecInit(Seq.fill(latency)(false.B)))
val stalling = VecInit(Seq.fill(latency)(false.B))
io.busy := io.in.valid || valids.reduce(_||_)
// Stall signals
io.in.ready := !stalling.head
stalling.last := valids.last && !io.out.ready
(stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) =>
s1 := v1 && s2
}
// Valid signals
// When the pipeline stage ahead of you isn't stalling, then make yourself invalid
io.out.valid := valids.last
when(io.out.ready) {
valids.last := false.B
}
(valids.init, stalling.tail).zipped.foreach { case (v1, s2) =>
when(!s2) {
v1 := false.B
}
}
// When the pipeline stage behind you is valid then become true
when(io.in.fire) {
valids.head := true.B
}
(valids.tail, valids.init).zipped.foreach { case (v2, v1) =>
when(v1) {
v2 := true.B
}
}
// Stages
when(io.in.fire) {
stages.head := comb.head(io.in.bits)
}
io.out.bits := comb.last(stages.last)
((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) =>
when(!s2) {
st2 := c1(st1)
}
}
}
}
object Pipeline {
def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = {
val p = Module(new Pipeline(in.bits.cloneType, latency)(comb))
p.io.in <> in
p.io.out
}
def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = {
val p = Module(new Pipeline(in.bits.cloneType, latency)())
p.io.in <> in
p.io.out
}
}
| module Pipeline_10( // @[Pipeline.scala:6:7]
input clock, // @[Pipeline.scala:6:7]
input reset, // @[Pipeline.scala:6:7]
output io_in_ready, // @[Pipeline.scala:7:14]
input io_in_valid, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_data_0_0_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_data_1_0_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_data_2_0_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_data_3_0_bits, // @[Pipeline.scala:7:14]
input io_in_bits_resp_fromDMA, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_scale_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_igelu_qb_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_igelu_qc_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_iexp_qln2_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_resp_iexp_qln2_inv_bits, // @[Pipeline.scala:7:14]
input [2:0] io_in_bits_resp_act, // @[Pipeline.scala:7:14]
input [1:0] io_in_bits_resp_acc_bank_id, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_full_data_0_0_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_full_data_1_0_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_full_data_2_0_bits, // @[Pipeline.scala:7:14]
input [31:0] io_in_bits_full_data_3_0_bits, // @[Pipeline.scala:7:14]
input io_out_ready, // @[Pipeline.scala:7:14]
output io_out_valid, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_resp_data_0_0_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_resp_data_1_0_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_resp_data_2_0_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_resp_data_3_0_bits, // @[Pipeline.scala:7:14]
output io_out_bits_resp_fromDMA, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_resp_acc_bank_id, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_full_data_0_0_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_full_data_1_0_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_full_data_2_0_bits, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_full_data_3_0_bits // @[Pipeline.scala:7:14]
);
wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_data_0_0_bits_0 = io_in_bits_resp_data_0_0_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_data_1_0_bits_0 = io_in_bits_resp_data_1_0_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_data_2_0_bits_0 = io_in_bits_resp_data_2_0_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_data_3_0_bits_0 = io_in_bits_resp_data_3_0_bits; // @[Pipeline.scala:6:7]
wire io_in_bits_resp_fromDMA_0 = io_in_bits_resp_fromDMA; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_scale_bits_0 = io_in_bits_resp_scale_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_igelu_qb_bits_0 = io_in_bits_resp_igelu_qb_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_igelu_qc_bits_0 = io_in_bits_resp_igelu_qc_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_iexp_qln2_bits_0 = io_in_bits_resp_iexp_qln2_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_resp_iexp_qln2_inv_bits_0 = io_in_bits_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:6:7]
wire [2:0] io_in_bits_resp_act_0 = io_in_bits_resp_act; // @[Pipeline.scala:6:7]
wire [1:0] io_in_bits_resp_acc_bank_id_0 = io_in_bits_resp_acc_bank_id; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_full_data_0_0_bits_0 = io_in_bits_full_data_0_0_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_full_data_1_0_bits_0 = io_in_bits_full_data_1_0_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_full_data_2_0_bits_0 = io_in_bits_full_data_2_0_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_in_bits_full_data_3_0_bits_0 = io_in_bits_full_data_3_0_bits; // @[Pipeline.scala:6:7]
wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7]
wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_2 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_3 = 1'h0; // @[Pipeline.scala:22:33]
wire _io_in_ready_T; // @[Pipeline.scala:27:20]
wire _io_busy_T_3; // @[Pipeline.scala:24:28]
wire io_in_ready_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_data_0_0_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_data_1_0_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_data_2_0_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_data_3_0_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_scale_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_igelu_qb_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_igelu_qc_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_iexp_qln2_bits; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:6:7]
wire io_out_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7]
wire [2:0] io_out_bits_resp_act; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_full_data_0_0_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_full_data_1_0_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_full_data_2_0_bits_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_full_data_3_0_bits_0; // @[Pipeline.scala:6:7]
wire io_out_valid_0; // @[Pipeline.scala:6:7]
wire io_busy; // @[Pipeline.scala:6:7]
reg [31:0] stages_0_resp_data_0_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_resp_data_1_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_resp_data_2_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_resp_data_3_0_bits; // @[Pipeline.scala:21:21]
reg stages_0_resp_fromDMA; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_resp_scale_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_resp_igelu_qb_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_resp_igelu_qc_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_resp_iexp_qln2_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:21:21]
reg [2:0] stages_0_resp_act; // @[Pipeline.scala:21:21]
reg [1:0] stages_0_resp_acc_bank_id; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_full_data_0_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_full_data_1_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_full_data_2_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_0_full_data_3_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_data_0_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_data_1_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_data_2_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_data_3_0_bits; // @[Pipeline.scala:21:21]
reg stages_1_resp_fromDMA; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_scale_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_igelu_qb_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_igelu_qc_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_iexp_qln2_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:21:21]
reg [2:0] stages_1_resp_act; // @[Pipeline.scala:21:21]
reg [1:0] stages_1_resp_acc_bank_id; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_full_data_0_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_full_data_1_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_full_data_2_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_1_full_data_3_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_data_0_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_data_1_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_data_2_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_data_3_0_bits; // @[Pipeline.scala:21:21]
reg stages_2_resp_fromDMA; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_scale_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_igelu_qb_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_igelu_qc_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_iexp_qln2_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:21:21]
reg [2:0] stages_2_resp_act; // @[Pipeline.scala:21:21]
reg [1:0] stages_2_resp_acc_bank_id; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_full_data_0_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_full_data_1_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_full_data_2_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_2_full_data_3_0_bits; // @[Pipeline.scala:21:21]
reg [31:0] stages_3_resp_data_0_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_data_0_0_bits_0 = stages_3_resp_data_0_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_resp_data_1_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_data_1_0_bits_0 = stages_3_resp_data_1_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_resp_data_2_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_data_2_0_bits_0 = stages_3_resp_data_2_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_resp_data_3_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_data_3_0_bits_0 = stages_3_resp_data_3_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg stages_3_resp_fromDMA; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_fromDMA_0 = stages_3_resp_fromDMA; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_resp_scale_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_scale_bits = stages_3_resp_scale_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_resp_igelu_qb_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_igelu_qb_bits = stages_3_resp_igelu_qb_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_resp_igelu_qc_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_igelu_qc_bits = stages_3_resp_igelu_qc_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_resp_iexp_qln2_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_iexp_qln2_bits = stages_3_resp_iexp_qln2_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_iexp_qln2_inv_bits = stages_3_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:6:7, :21:21]
reg [2:0] stages_3_resp_act; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_act = stages_3_resp_act; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_3_resp_acc_bank_id; // @[Pipeline.scala:21:21]
assign io_out_bits_resp_acc_bank_id_0 = stages_3_resp_acc_bank_id; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_full_data_0_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_full_data_0_0_bits_0 = stages_3_full_data_0_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_full_data_1_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_full_data_1_0_bits_0 = stages_3_full_data_1_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_full_data_2_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_full_data_2_0_bits_0 = stages_3_full_data_2_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_3_full_data_3_0_bits; // @[Pipeline.scala:21:21]
assign io_out_bits_full_data_3_0_bits_0 = stages_3_full_data_3_0_bits; // @[Pipeline.scala:6:7, :21:21]
reg valids_0; // @[Pipeline.scala:22:25]
reg valids_1; // @[Pipeline.scala:22:25]
reg valids_2; // @[Pipeline.scala:22:25]
reg valids_3; // @[Pipeline.scala:22:25]
assign io_out_valid_0 = valids_3; // @[Pipeline.scala:6:7, :22:25]
wire _stalling_0_T; // @[Pipeline.scala:30:16]
wire _stalling_1_T; // @[Pipeline.scala:30:16]
wire _stalling_2_T; // @[Pipeline.scala:30:16]
wire _stalling_3_T_1; // @[Pipeline.scala:28:34]
wire stalling_0; // @[Pipeline.scala:23:27]
wire stalling_1; // @[Pipeline.scala:23:27]
wire stalling_2; // @[Pipeline.scala:23:27]
wire stalling_3; // @[Pipeline.scala:23:27]
wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46]
wire _io_busy_T_1 = _io_busy_T | valids_2; // @[Pipeline.scala:22:25, :24:46]
wire _io_busy_T_2 = _io_busy_T_1 | valids_3; // @[Pipeline.scala:22:25, :24:46]
assign _io_busy_T_3 = io_in_valid_0 | _io_busy_T_2; // @[Pipeline.scala:6:7, :24:{28,46}]
assign io_busy = _io_busy_T_3; // @[Pipeline.scala:6:7, :24:28]
assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20]
assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20]
wire _stalling_3_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37]
assign _stalling_3_T_1 = valids_3 & _stalling_3_T; // @[Pipeline.scala:22:25, :28:{34,37}]
assign stalling_3 = _stalling_3_T_1; // @[Pipeline.scala:23:27, :28:34]
assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16]
assign _stalling_1_T = valids_1 & stalling_2; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_1 = _stalling_1_T; // @[Pipeline.scala:23:27, :30:16]
assign _stalling_2_T = valids_2 & stalling_3; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_2 = _stalling_2_T; // @[Pipeline.scala:23:27, :30:16]
wire _T_4 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Pipeline.scala:6:7]
if (_T_4) begin // @[Decoupled.scala:51:35]
stages_0_resp_data_0_0_bits <= io_in_bits_resp_data_0_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_data_1_0_bits <= io_in_bits_resp_data_1_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_data_2_0_bits <= io_in_bits_resp_data_2_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_data_3_0_bits <= io_in_bits_resp_data_3_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_fromDMA <= io_in_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_scale_bits <= io_in_bits_resp_scale_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_igelu_qb_bits <= io_in_bits_resp_igelu_qb_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_igelu_qc_bits <= io_in_bits_resp_igelu_qc_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_iexp_qln2_bits <= io_in_bits_resp_iexp_qln2_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_iexp_qln2_inv_bits <= io_in_bits_resp_iexp_qln2_inv_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_act <= io_in_bits_resp_act_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_resp_acc_bank_id <= io_in_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_full_data_0_0_bits <= io_in_bits_full_data_0_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_full_data_1_0_bits <= io_in_bits_full_data_1_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_full_data_2_0_bits <= io_in_bits_full_data_2_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_full_data_3_0_bits <= io_in_bits_full_data_3_0_bits_0; // @[Pipeline.scala:6:7, :21:21]
end
if (stalling_1) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_1_resp_data_0_0_bits <= stages_0_resp_data_0_0_bits; // @[Pipeline.scala:21:21]
stages_1_resp_data_1_0_bits <= stages_0_resp_data_1_0_bits; // @[Pipeline.scala:21:21]
stages_1_resp_data_2_0_bits <= stages_0_resp_data_2_0_bits; // @[Pipeline.scala:21:21]
stages_1_resp_data_3_0_bits <= stages_0_resp_data_3_0_bits; // @[Pipeline.scala:21:21]
stages_1_resp_fromDMA <= stages_0_resp_fromDMA; // @[Pipeline.scala:21:21]
stages_1_resp_scale_bits <= stages_0_resp_scale_bits; // @[Pipeline.scala:21:21]
stages_1_resp_igelu_qb_bits <= stages_0_resp_igelu_qb_bits; // @[Pipeline.scala:21:21]
stages_1_resp_igelu_qc_bits <= stages_0_resp_igelu_qc_bits; // @[Pipeline.scala:21:21]
stages_1_resp_iexp_qln2_bits <= stages_0_resp_iexp_qln2_bits; // @[Pipeline.scala:21:21]
stages_1_resp_iexp_qln2_inv_bits <= stages_0_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:21:21]
stages_1_resp_act <= stages_0_resp_act; // @[Pipeline.scala:21:21]
stages_1_resp_acc_bank_id <= stages_0_resp_acc_bank_id; // @[Pipeline.scala:21:21]
stages_1_full_data_0_0_bits <= stages_0_full_data_0_0_bits; // @[Pipeline.scala:21:21]
stages_1_full_data_1_0_bits <= stages_0_full_data_1_0_bits; // @[Pipeline.scala:21:21]
stages_1_full_data_2_0_bits <= stages_0_full_data_2_0_bits; // @[Pipeline.scala:21:21]
stages_1_full_data_3_0_bits <= stages_0_full_data_3_0_bits; // @[Pipeline.scala:21:21]
end
if (stalling_2) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_2_resp_data_0_0_bits <= stages_1_resp_data_0_0_bits; // @[Pipeline.scala:21:21]
stages_2_resp_data_1_0_bits <= stages_1_resp_data_1_0_bits; // @[Pipeline.scala:21:21]
stages_2_resp_data_2_0_bits <= stages_1_resp_data_2_0_bits; // @[Pipeline.scala:21:21]
stages_2_resp_data_3_0_bits <= stages_1_resp_data_3_0_bits; // @[Pipeline.scala:21:21]
stages_2_resp_fromDMA <= stages_1_resp_fromDMA; // @[Pipeline.scala:21:21]
stages_2_resp_scale_bits <= stages_1_resp_scale_bits; // @[Pipeline.scala:21:21]
stages_2_resp_igelu_qb_bits <= stages_1_resp_igelu_qb_bits; // @[Pipeline.scala:21:21]
stages_2_resp_igelu_qc_bits <= stages_1_resp_igelu_qc_bits; // @[Pipeline.scala:21:21]
stages_2_resp_iexp_qln2_bits <= stages_1_resp_iexp_qln2_bits; // @[Pipeline.scala:21:21]
stages_2_resp_iexp_qln2_inv_bits <= stages_1_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:21:21]
stages_2_resp_act <= stages_1_resp_act; // @[Pipeline.scala:21:21]
stages_2_resp_acc_bank_id <= stages_1_resp_acc_bank_id; // @[Pipeline.scala:21:21]
stages_2_full_data_0_0_bits <= stages_1_full_data_0_0_bits; // @[Pipeline.scala:21:21]
stages_2_full_data_1_0_bits <= stages_1_full_data_1_0_bits; // @[Pipeline.scala:21:21]
stages_2_full_data_2_0_bits <= stages_1_full_data_2_0_bits; // @[Pipeline.scala:21:21]
stages_2_full_data_3_0_bits <= stages_1_full_data_3_0_bits; // @[Pipeline.scala:21:21]
end
if (stalling_3) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_3_resp_data_0_0_bits <= stages_2_resp_data_0_0_bits; // @[Pipeline.scala:21:21]
stages_3_resp_data_1_0_bits <= stages_2_resp_data_1_0_bits; // @[Pipeline.scala:21:21]
stages_3_resp_data_2_0_bits <= stages_2_resp_data_2_0_bits; // @[Pipeline.scala:21:21]
stages_3_resp_data_3_0_bits <= stages_2_resp_data_3_0_bits; // @[Pipeline.scala:21:21]
stages_3_resp_fromDMA <= stages_2_resp_fromDMA; // @[Pipeline.scala:21:21]
stages_3_resp_scale_bits <= stages_2_resp_scale_bits; // @[Pipeline.scala:21:21]
stages_3_resp_igelu_qb_bits <= stages_2_resp_igelu_qb_bits; // @[Pipeline.scala:21:21]
stages_3_resp_igelu_qc_bits <= stages_2_resp_igelu_qc_bits; // @[Pipeline.scala:21:21]
stages_3_resp_iexp_qln2_bits <= stages_2_resp_iexp_qln2_bits; // @[Pipeline.scala:21:21]
stages_3_resp_iexp_qln2_inv_bits <= stages_2_resp_iexp_qln2_inv_bits; // @[Pipeline.scala:21:21]
stages_3_resp_act <= stages_2_resp_act; // @[Pipeline.scala:21:21]
stages_3_resp_acc_bank_id <= stages_2_resp_acc_bank_id; // @[Pipeline.scala:21:21]
stages_3_full_data_0_0_bits <= stages_2_full_data_0_0_bits; // @[Pipeline.scala:21:21]
stages_3_full_data_1_0_bits <= stages_2_full_data_1_0_bits; // @[Pipeline.scala:21:21]
stages_3_full_data_2_0_bits <= stages_2_full_data_2_0_bits; // @[Pipeline.scala:21:21]
stages_3_full_data_3_0_bits <= stages_2_full_data_3_0_bits; // @[Pipeline.scala:21:21]
end
if (reset) begin // @[Pipeline.scala:6:7]
valids_0 <= 1'h0; // @[Pipeline.scala:22:25]
valids_1 <= 1'h0; // @[Pipeline.scala:22:25]
valids_2 <= 1'h0; // @[Pipeline.scala:22:25]
valids_3 <= 1'h0; // @[Pipeline.scala:22:25]
end
else begin // @[Pipeline.scala:6:7]
valids_0 <= _T_4 | stalling_1 & valids_0; // @[Decoupled.scala:51:35]
valids_1 <= valids_0 | stalling_2 & valids_1; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12]
valids_2 <= valids_1 | stalling_3 & valids_2; // @[Pipeline.scala:22:25, :23:27, :40:17, :41:12, :49:16, :50:12]
valids_3 <= valids_2 | ~io_out_ready_0 & valids_3; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12]
end
always @(posedge)
assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7]
assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7]
assign io_out_bits_resp_data_0_0_bits = io_out_bits_resp_data_0_0_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_resp_data_1_0_bits = io_out_bits_resp_data_1_0_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_resp_data_2_0_bits = io_out_bits_resp_data_2_0_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_resp_data_3_0_bits = io_out_bits_resp_data_3_0_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_resp_fromDMA = io_out_bits_resp_fromDMA_0; // @[Pipeline.scala:6:7]
assign io_out_bits_resp_acc_bank_id = io_out_bits_resp_acc_bank_id_0; // @[Pipeline.scala:6:7]
assign io_out_bits_full_data_0_0_bits = io_out_bits_full_data_0_0_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_full_data_1_0_bits = io_out_bits_full_data_1_0_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_full_data_2_0_bits = io_out_bits_full_data_2_0_bits_0; // @[Pipeline.scala:6:7]
assign io_out_bits_full_data_3_0_bits = io_out_bits_full_data_3_0_bits_0; // @[Pipeline.scala:6:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_178( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_314 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_119( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_22( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ppred = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [7:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? 4'h0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
| module EgressUnit_29( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [36:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [36:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30] |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module rockettile_dcache_tag_array_2( // @[DescribedSRAM.scala:17:26]
input [5:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [175:0] RW0_wdata,
output [175:0] RW0_rdata,
input [7:0] RW0_wmask
);
rockettile_dcache_tag_array_ext rockettile_dcache_tag_array_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_62( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output io_debug_va_stall, // @[InputUnit.scala:170:14]
output io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [1:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_3_0; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_1_0; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File UserYanker.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Queue, QueueIO, UIntToOH}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.BundleMap
/** This adapter prunes all user bit fields of the echo type from request messages,
* storing them in queues and echoing them back when matching response messages are received.
*
* It also optionally rate limits the number of transactions that can be in flight simultaneously
* per FIFO domain / A[W|R]ID.
*
* @param capMaxFlight is an optional maximum number of transactions that can be in flight per A[W|R]ID.
*/
class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule
{
val node = AXI4AdapterNode(
masterFn = { mp => mp.copy(
masters = mp.masters.map { m => m.copy(
maxFlight = (m.maxFlight, capMaxFlight) match {
case (Some(x), Some(y)) => Some(x min y)
case (Some(x), None) => Some(x)
case (None, Some(y)) => Some(y)
case (None, None) => None })},
echoFields = Nil)},
slaveFn = { sp => sp })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// Which fields are we stripping?
val echoFields = edgeIn.master.echoFields
val need_bypass = edgeOut.slave.minLatency < 1
edgeOut.master.masters.foreach { m =>
require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID")
}
def queue(id: Int) = {
val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0)
if (depth == 0) {
Wire(new QueueIO(BundleMap(echoFields), 1)) // unused ID => undefined value
} else {
Module(new Queue(BundleMap(echoFields), depth, flow=need_bypass)).io
}
}
val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) }
val arid = in.ar.bits.id
val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid)
in .ar.ready := out.ar.ready && ar_ready
out.ar.valid := in .ar.valid && ar_ready
Connectable.waiveUnmatched(out.ar.bits, in.ar.bits) match {
case (lhs, rhs) => lhs :<= rhs
}
val rid = out.r.bits.id
val r_valid = VecInit(rqueues.map(_.deq.valid))(rid)
val r_bits = VecInit(rqueues.map(_.deq.bits))(rid)
assert (!out.r.valid || r_valid) // Q must be ready faster than the response
Connectable.waiveUnmatched(in.r, out.r) match {
case (lhs, rhs) => lhs :<>= rhs
}
in.r.bits.echo :<= r_bits
val arsel = UIntToOH(arid, edgeIn.master.endId).asBools
val rsel = UIntToOH(rid, edgeIn.master.endId).asBools
(rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) =>
q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last
q.deq.valid := DontCare
q.deq.bits := DontCare
q.enq.valid := in .ar.valid && out.ar.ready && ar
q.enq.ready := DontCare
q.enq.bits :<>= in.ar.bits.echo
q.count := DontCare
}
val awid = in.aw.bits.id
val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid)
in .aw.ready := out.aw.ready && aw_ready
out.aw.valid := in .aw.valid && aw_ready
Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match {
case (lhs, rhs) => lhs :<>= rhs
}
val bid = out.b.bits.id
val b_valid = VecInit(wqueues.map(_.deq.valid))(bid)
val b_bits = VecInit(wqueues.map(_.deq.bits))(bid)
assert (!out.b.valid || b_valid) // Q must be ready faster than the response
Connectable.waiveUnmatched(in.b, out.b) match {
case (lhs, rhs) => lhs :<>= rhs
}
in.b.bits.echo :<>= b_bits
val awsel = UIntToOH(awid, edgeIn.master.endId).asBools
val bsel = UIntToOH(bid, edgeIn.master.endId).asBools
(wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) =>
q.deq.ready := out.b .valid && in .b .ready && b
q.deq.valid := DontCare
q.deq.bits := DontCare
q.enq.valid := in .aw.valid && out.aw.ready && aw
q.enq.ready := DontCare
q.enq.bits :<>= in.aw.bits.echo
q.count := DontCare
}
out.w :<>= in.w
}
}
}
object AXI4UserYanker
{
def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node =
{
val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight))
axi4yank.node
}
}
| module AXI4UserYanker_1( // @[UserYanker.scala:36:9]
input clock, // @[UserYanker.scala:36:9]
input reset, // @[UserYanker.scala:36:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[UserYanker.scala:36:9]
wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[UserYanker.scala:36:9]
wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[UserYanker.scala:36:9]
wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[UserYanker.scala:36:9]
wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[UserYanker.scala:36:9]
wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[UserYanker.scala:36:9]
wire auto_in_aw_bits_echo_real_last_0 = auto_in_aw_bits_echo_real_last; // @[UserYanker.scala:36:9]
wire auto_in_w_valid_0 = auto_in_w_valid; // @[UserYanker.scala:36:9]
wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[UserYanker.scala:36:9]
wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[UserYanker.scala:36:9]
wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[UserYanker.scala:36:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[UserYanker.scala:36:9]
wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[UserYanker.scala:36:9]
wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[UserYanker.scala:36:9]
wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[UserYanker.scala:36:9]
wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[UserYanker.scala:36:9]
wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[UserYanker.scala:36:9]
wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[UserYanker.scala:36:9]
wire auto_in_ar_bits_echo_real_last_0 = auto_in_ar_bits_echo_real_last; // @[UserYanker.scala:36:9]
wire auto_in_r_ready_0 = auto_in_r_ready; // @[UserYanker.scala:36:9]
wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[UserYanker.scala:36:9]
wire auto_out_w_ready_0 = auto_out_w_ready; // @[UserYanker.scala:36:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[UserYanker.scala:36:9]
wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[UserYanker.scala:36:9]
wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[UserYanker.scala:36:9]
wire auto_out_r_valid_0 = auto_out_r_valid; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[UserYanker.scala:36:9]
wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[UserYanker.scala:36:9]
wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[UserYanker.scala:36:9]
wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[UserYanker.scala:36:9]
wire nodeIn_aw_ready; // @[MixedNode.scala:551:17]
wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[UserYanker.scala:36:9]
wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[UserYanker.scala:36:9]
wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[UserYanker.scala:36:9]
wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[UserYanker.scala:36:9]
wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[UserYanker.scala:36:9]
wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[UserYanker.scala:36:9]
wire nodeIn_aw_bits_echo_real_last = auto_in_aw_bits_echo_real_last_0; // @[UserYanker.scala:36:9]
wire nodeIn_w_ready; // @[MixedNode.scala:551:17]
wire nodeIn_w_valid = auto_in_w_valid_0; // @[UserYanker.scala:36:9]
wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[UserYanker.scala:36:9]
wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[UserYanker.scala:36:9]
wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[UserYanker.scala:36:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[UserYanker.scala:36:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_echo_real_last; // @[MixedNode.scala:551:17]
wire nodeIn_ar_ready; // @[MixedNode.scala:551:17]
wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[UserYanker.scala:36:9]
wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[UserYanker.scala:36:9]
wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[UserYanker.scala:36:9]
wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[UserYanker.scala:36:9]
wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[UserYanker.scala:36:9]
wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[UserYanker.scala:36:9]
wire nodeIn_ar_bits_echo_real_last = auto_in_ar_bits_echo_real_last_0; // @[UserYanker.scala:36:9]
wire nodeIn_r_ready = auto_in_r_ready_0; // @[UserYanker.scala:36:9]
wire nodeIn_r_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_echo_real_last; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17]
wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[UserYanker.scala:36:9]
wire nodeOut_aw_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17]
wire nodeOut_w_ready = auto_out_w_ready_0; // @[UserYanker.scala:36:9]
wire nodeOut_w_valid; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17]
wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[UserYanker.scala:36:9]
wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[UserYanker.scala:36:9]
wire nodeOut_ar_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17]
wire nodeOut_r_ready; // @[MixedNode.scala:542:17]
wire nodeOut_r_valid = auto_out_r_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[UserYanker.scala:36:9]
wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[UserYanker.scala:36:9]
wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[UserYanker.scala:36:9]
wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[UserYanker.scala:36:9]
wire auto_in_aw_ready_0; // @[UserYanker.scala:36:9]
wire auto_in_w_ready_0; // @[UserYanker.scala:36:9]
wire auto_in_b_bits_echo_real_last_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_b_bits_id_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_b_bits_resp_0; // @[UserYanker.scala:36:9]
wire auto_in_b_valid_0; // @[UserYanker.scala:36:9]
wire auto_in_ar_ready_0; // @[UserYanker.scala:36:9]
wire auto_in_r_bits_echo_real_last_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_in_r_bits_id_0; // @[UserYanker.scala:36:9]
wire [63:0] auto_in_r_bits_data_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_in_r_bits_resp_0; // @[UserYanker.scala:36:9]
wire auto_in_r_bits_last_0; // @[UserYanker.scala:36:9]
wire auto_in_r_valid_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_aw_bits_id_0; // @[UserYanker.scala:36:9]
wire [31:0] auto_out_aw_bits_addr_0; // @[UserYanker.scala:36:9]
wire [7:0] auto_out_aw_bits_len_0; // @[UserYanker.scala:36:9]
wire [2:0] auto_out_aw_bits_size_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_out_aw_bits_burst_0; // @[UserYanker.scala:36:9]
wire auto_out_aw_bits_lock_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_aw_bits_cache_0; // @[UserYanker.scala:36:9]
wire [2:0] auto_out_aw_bits_prot_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_aw_bits_qos_0; // @[UserYanker.scala:36:9]
wire auto_out_aw_valid_0; // @[UserYanker.scala:36:9]
wire [63:0] auto_out_w_bits_data_0; // @[UserYanker.scala:36:9]
wire [7:0] auto_out_w_bits_strb_0; // @[UserYanker.scala:36:9]
wire auto_out_w_bits_last_0; // @[UserYanker.scala:36:9]
wire auto_out_w_valid_0; // @[UserYanker.scala:36:9]
wire auto_out_b_ready_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_ar_bits_id_0; // @[UserYanker.scala:36:9]
wire [31:0] auto_out_ar_bits_addr_0; // @[UserYanker.scala:36:9]
wire [7:0] auto_out_ar_bits_len_0; // @[UserYanker.scala:36:9]
wire [2:0] auto_out_ar_bits_size_0; // @[UserYanker.scala:36:9]
wire [1:0] auto_out_ar_bits_burst_0; // @[UserYanker.scala:36:9]
wire auto_out_ar_bits_lock_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_ar_bits_cache_0; // @[UserYanker.scala:36:9]
wire [2:0] auto_out_ar_bits_prot_0; // @[UserYanker.scala:36:9]
wire [3:0] auto_out_ar_bits_qos_0; // @[UserYanker.scala:36:9]
wire auto_out_ar_valid_0; // @[UserYanker.scala:36:9]
wire auto_out_r_ready_0; // @[UserYanker.scala:36:9]
wire _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36]
assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[UserYanker.scala:36:9]
assign nodeOut_aw_bits_id = nodeIn_aw_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] awsel_shiftAmount = nodeIn_aw_bits_id; // @[OneHot.scala:64:49]
assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_w_ready_0 = nodeIn_w_ready; // @[UserYanker.scala:36:9]
assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[UserYanker.scala:36:9]
assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[UserYanker.scala:36:9]
assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[UserYanker.scala:36:9]
assign auto_in_b_bits_echo_real_last_0 = nodeIn_b_bits_echo_real_last; // @[UserYanker.scala:36:9]
wire _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36]
assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[UserYanker.scala:36:9]
assign nodeOut_ar_bits_id = nodeIn_ar_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] arsel_shiftAmount = nodeIn_ar_bits_id; // @[OneHot.scala:64:49]
assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_r_valid_0 = nodeIn_r_valid; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_echo_real_last_0 = nodeIn_r_bits_echo_real_last; // @[UserYanker.scala:36:9]
assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[UserYanker.scala:36:9]
wire _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36]
assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[UserYanker.scala:36:9]
assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[UserYanker.scala:36:9]
assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_w_valid_0 = nodeOut_w_valid; // @[UserYanker.scala:36:9]
assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[UserYanker.scala:36:9]
assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[UserYanker.scala:36:9]
assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[UserYanker.scala:36:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[UserYanker.scala:36:9]
assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] bsel_shiftAmount = nodeOut_b_bits_id; // @[OneHot.scala:64:49]
assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17]
wire _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36]
assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[UserYanker.scala:36:9]
assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[UserYanker.scala:36:9]
assign auto_out_r_ready_0 = nodeOut_r_ready; // @[UserYanker.scala:36:9]
assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] rsel_shiftAmount = nodeOut_r_bits_id; // @[OneHot.scala:64:49]
assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17]
wire _ar_ready_WIRE_0; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_1; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_2; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_3; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_4; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_5; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_6; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_7; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_8; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_9; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_10; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_11; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_12; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_13; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_14; // @[UserYanker.scala:59:29]
wire _ar_ready_WIRE_15; // @[UserYanker.scala:59:29]
wire [15:0] _GEN = {{_ar_ready_WIRE_15}, {_ar_ready_WIRE_14}, {_ar_ready_WIRE_13}, {_ar_ready_WIRE_12}, {_ar_ready_WIRE_11}, {_ar_ready_WIRE_10}, {_ar_ready_WIRE_9}, {_ar_ready_WIRE_8}, {_ar_ready_WIRE_7}, {_ar_ready_WIRE_6}, {_ar_ready_WIRE_5}, {_ar_ready_WIRE_4}, {_ar_ready_WIRE_3}, {_ar_ready_WIRE_2}, {_ar_ready_WIRE_1}, {_ar_ready_WIRE_0}}; // @[UserYanker.scala:59:29, :60:36]
assign _nodeIn_ar_ready_T = nodeOut_ar_ready & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36]
assign nodeIn_ar_ready = _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36]
assign _nodeOut_ar_valid_T = nodeIn_ar_valid & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36, :61:36]
assign nodeOut_ar_valid = _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36]
wire _r_bits_WIRE_0_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_1_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_2_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_3_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_4_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_5_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_6_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_7_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_8_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_9_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_10_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_11_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_12_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_13_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_14_real_last; // @[UserYanker.scala:68:27]
wire _r_bits_WIRE_15_real_last; // @[UserYanker.scala:68:27]
wire [15:0] _GEN_0 = {{_r_bits_WIRE_15_real_last}, {_r_bits_WIRE_14_real_last}, {_r_bits_WIRE_13_real_last}, {_r_bits_WIRE_12_real_last}, {_r_bits_WIRE_11_real_last}, {_r_bits_WIRE_10_real_last}, {_r_bits_WIRE_9_real_last}, {_r_bits_WIRE_8_real_last}, {_r_bits_WIRE_7_real_last}, {_r_bits_WIRE_6_real_last}, {_r_bits_WIRE_5_real_last}, {_r_bits_WIRE_4_real_last}, {_r_bits_WIRE_3_real_last}, {_r_bits_WIRE_2_real_last}, {_r_bits_WIRE_1_real_last}, {_r_bits_WIRE_0_real_last}}; // @[UserYanker.scala:68:27, :73:22]
assign nodeIn_r_bits_echo_real_last = _GEN_0[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22]
wire [15:0] _arsel_T = 16'h1 << arsel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [15:0] _arsel_T_1 = _arsel_T; // @[OneHot.scala:65:{12,27}]
wire arsel_0 = _arsel_T_1[0]; // @[OneHot.scala:65:27]
wire arsel_1 = _arsel_T_1[1]; // @[OneHot.scala:65:27]
wire arsel_2 = _arsel_T_1[2]; // @[OneHot.scala:65:27]
wire arsel_3 = _arsel_T_1[3]; // @[OneHot.scala:65:27]
wire arsel_4 = _arsel_T_1[4]; // @[OneHot.scala:65:27]
wire arsel_5 = _arsel_T_1[5]; // @[OneHot.scala:65:27]
wire arsel_6 = _arsel_T_1[6]; // @[OneHot.scala:65:27]
wire arsel_7 = _arsel_T_1[7]; // @[OneHot.scala:65:27]
wire arsel_8 = _arsel_T_1[8]; // @[OneHot.scala:65:27]
wire arsel_9 = _arsel_T_1[9]; // @[OneHot.scala:65:27]
wire arsel_10 = _arsel_T_1[10]; // @[OneHot.scala:65:27]
wire arsel_11 = _arsel_T_1[11]; // @[OneHot.scala:65:27]
wire arsel_12 = _arsel_T_1[12]; // @[OneHot.scala:65:27]
wire arsel_13 = _arsel_T_1[13]; // @[OneHot.scala:65:27]
wire arsel_14 = _arsel_T_1[14]; // @[OneHot.scala:65:27]
wire arsel_15 = _arsel_T_1[15]; // @[OneHot.scala:65:27]
wire [15:0] _rsel_T = 16'h1 << rsel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [15:0] _rsel_T_1 = _rsel_T; // @[OneHot.scala:65:{12,27}]
wire rsel_0 = _rsel_T_1[0]; // @[OneHot.scala:65:27]
wire rsel_1 = _rsel_T_1[1]; // @[OneHot.scala:65:27]
wire rsel_2 = _rsel_T_1[2]; // @[OneHot.scala:65:27]
wire rsel_3 = _rsel_T_1[3]; // @[OneHot.scala:65:27]
wire rsel_4 = _rsel_T_1[4]; // @[OneHot.scala:65:27]
wire rsel_5 = _rsel_T_1[5]; // @[OneHot.scala:65:27]
wire rsel_6 = _rsel_T_1[6]; // @[OneHot.scala:65:27]
wire rsel_7 = _rsel_T_1[7]; // @[OneHot.scala:65:27]
wire rsel_8 = _rsel_T_1[8]; // @[OneHot.scala:65:27]
wire rsel_9 = _rsel_T_1[9]; // @[OneHot.scala:65:27]
wire rsel_10 = _rsel_T_1[10]; // @[OneHot.scala:65:27]
wire rsel_11 = _rsel_T_1[11]; // @[OneHot.scala:65:27]
wire rsel_12 = _rsel_T_1[12]; // @[OneHot.scala:65:27]
wire rsel_13 = _rsel_T_1[13]; // @[OneHot.scala:65:27]
wire rsel_14 = _rsel_T_1[14]; // @[OneHot.scala:65:27]
wire rsel_15 = _rsel_T_1[15]; // @[OneHot.scala:65:27]
wire _T_80 = nodeOut_r_valid & nodeIn_r_ready; // @[UserYanker.scala:78:37]
wire _T_83 = nodeIn_ar_valid & nodeOut_ar_ready; // @[UserYanker.scala:81:37]
wire _aw_ready_WIRE_0; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_1; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_2; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_3; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_4; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_5; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_6; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_7; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_8; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_9; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_10; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_11; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_12; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_13; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_14; // @[UserYanker.scala:88:29]
wire _aw_ready_WIRE_15; // @[UserYanker.scala:88:29]
wire [15:0] _GEN_1 = {{_aw_ready_WIRE_15}, {_aw_ready_WIRE_14}, {_aw_ready_WIRE_13}, {_aw_ready_WIRE_12}, {_aw_ready_WIRE_11}, {_aw_ready_WIRE_10}, {_aw_ready_WIRE_9}, {_aw_ready_WIRE_8}, {_aw_ready_WIRE_7}, {_aw_ready_WIRE_6}, {_aw_ready_WIRE_5}, {_aw_ready_WIRE_4}, {_aw_ready_WIRE_3}, {_aw_ready_WIRE_2}, {_aw_ready_WIRE_1}, {_aw_ready_WIRE_0}}; // @[UserYanker.scala:88:29, :89:36]
assign _nodeIn_aw_ready_T = nodeOut_aw_ready & _GEN_1[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36]
assign nodeIn_aw_ready = _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36]
assign _nodeOut_aw_valid_T = nodeIn_aw_valid & _GEN_1[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36, :90:36]
assign nodeOut_aw_valid = _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36]
wire _r_valid_WIRE_0; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_1; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_2; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_3; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_4; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_5; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_6; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_7; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_8; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_9; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_10; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_11; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_12; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_13; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_14; // @[UserYanker.scala:67:28]
wire _r_valid_WIRE_15; // @[UserYanker.scala:67:28]
wire _b_valid_WIRE_0; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_1; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_2; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_3; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_4; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_5; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_6; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_7; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_8; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_9; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_10; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_11; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_12; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_13; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_14; // @[UserYanker.scala:96:28]
wire _b_valid_WIRE_15; // @[UserYanker.scala:96:28] |
Generate the Verilog code corresponding to the following Chisel files.
File loop.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomLoopPredictorParams(
nWays: Int = 4,
threshold: Int = 7
)
class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tagSz = 10
override val nSets = 16
class LoopMeta extends Bundle {
val s_cnt = UInt(10.W)
}
class LoopEntry extends Bundle {
val tag = UInt(tagSz.W)
val conf = UInt(3.W)
val age = UInt(3.W)
val p_cnt = UInt(10.W)
val s_cnt = UInt(10.W)
}
class LoopBranchPredictorColumn extends Module {
val io = IO(new Bundle {
val f2_req_valid = Input(Bool())
val f2_req_idx = Input(UInt())
val f3_req_fire = Input(Bool())
val f3_pred_in = Input(Bool())
val f3_pred = Output(Bool())
val f3_meta = Output(new LoopMeta)
val update_mispredict = Input(Bool())
val update_repair = Input(Bool())
val update_idx = Input(UInt())
val update_resolve_dir = Input(Bool())
val update_meta = Input(new LoopMeta)
})
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val entries = Reg(Vec(nSets, new LoopEntry))
val f2_entry = WireInit(entries(io.f2_req_idx))
when (io.update_repair && io.update_idx === io.f2_req_idx) {
f2_entry.s_cnt := io.update_meta.s_cnt
} .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) {
f2_entry.s_cnt := 0.U
}
val f3_entry = RegNext(f2_entry)
val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx),
io.update_meta.s_cnt,
f3_entry.s_cnt)
val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)))
io.f3_pred := io.f3_pred_in
io.f3_meta.s_cnt := f3_scnt
when (f3_entry.tag === f3_tag) {
when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) {
io.f3_pred := !io.f3_pred_in
}
}
val f4_fire = RegNext(io.f3_req_fire)
val f4_entry = RegNext(f3_entry)
val f4_tag = RegNext(f3_tag)
val f4_scnt = RegNext(f3_scnt)
val f4_idx = RegNext(RegNext(io.f2_req_idx))
when (f4_fire) {
when (f4_entry.tag === f4_tag) {
when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) {
entries(f4_idx).age := 7.U
entries(f4_idx).s_cnt := 0.U
} .otherwise {
entries(f4_idx).s_cnt := f4_scnt + 1.U
entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U)
}
}
}
val entry = entries(io.update_idx)
val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))
val tag_match = entry.tag === tag
val ctr_match = entry.p_cnt === io.update_meta.s_cnt
val wentry = WireInit(entry)
when (io.update_mispredict && !doing_reset) {
// Learned, tag match -> decrement confidence
when (entry.conf === 7.U && tag_match) {
wentry.s_cnt := 0.U
wentry.conf := entry.conf - 1.U
// Learned, no tag match -> do nothing? Don't evict super-confident entries?
} .elsewhen (entry.conf === 7.U && !tag_match) {
// Confident, tag match, ctr_match -> increment confidence, reset counter
} .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) {
wentry.conf := entry.conf + 1.U
wentry.s_cnt := 0.U
// Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter
} .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) {
wentry.conf := 0.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
// Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong
} .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) {
wentry.tag := tag
wentry.conf := 1.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
// Confident, no tag match, age > 0 -> decrement age
} .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) {
wentry.age := entry.age - 1.U
// Unconfident, tag match, ctr match -> increment confidence
} .elsewhen (entry.conf === 0.U && tag_match && ctr_match) {
wentry.conf := 1.U
wentry.age := 7.U
wentry.s_cnt := 0.U
// Unconfident, tag match, no ctr match -> set previous counter
} .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) {
wentry.p_cnt := io.update_meta.s_cnt
wentry.age := 7.U
wentry.s_cnt := 0.U
// Unconfident, no tag match -> set previous counter and tag
} .elsewhen (entry.conf === 0.U && !tag_match) {
wentry.tag := tag
wentry.conf := 1.U
wentry.age := 7.U
wentry.s_cnt := 0.U
wentry.p_cnt := io.update_meta.s_cnt
}
entries(io.update_idx) := wentry
} .elsewhen (io.update_repair && !doing_reset) {
when (tag_match && !(f4_fire && io.update_idx === f4_idx)) {
wentry.s_cnt := io.update_meta.s_cnt
entries(io.update_idx) := wentry
}
}
when (doing_reset) {
entries(reset_idx) := (0.U).asTypeOf(new LoopEntry)
}
}
val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) }
val mems = Nil // TODO fix
val f3_meta = Wire(Vec(bankWidth, new LoopMeta))
override val metaSz = f3_meta.asUInt.getWidth
val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta))
for (w <- 0 until bankWidth) {
columns(w).io.f2_req_valid := s2_valid
columns(w).io.f2_req_idx := s2_idx
columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire &&
RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br))
columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken
io.resp.f3(w).taken := columns(w).io.f3_pred
columns(w).io.update_mispredict := (s1_update.valid &&
s1_update.bits.br_mask(w) &&
s1_update.bits.is_mispredict_update &&
s1_update.bits.cfi_mispredicted)
columns(w).io.update_repair := (s1_update.valid &&
s1_update.bits.br_mask(w) &&
s1_update.bits.is_repair_update)
columns(w).io.update_idx := s1_update_idx
columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken
columns(w).io.update_meta := update_meta(w)
f3_meta(w) := columns(w).io.f3_meta
}
io.f3_meta := f3_meta.asUInt
}
| module LoopBranchPredictorColumn( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [36:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [36:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [36:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [36:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [36:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [36:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [36:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [36:0] f4_idx_REG; // @[loop.scala:92:35]
reg [36:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire [3:0] _GEN_4 = {1'h0, _GEN_0[_entry_T_1]}; // @[loop.scala:66:28, :110:31, :119:36]
wire [3:0] _wentry_conf_T = _GEN_4 - 4'h1; // @[loop.scala:119:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:119:36]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T_2 = _GEN_4 + 4'h1; // @[loop.scala:102:80, :119:36, :126:36]
wire [2:0] _wentry_conf_T_3 = _wentry_conf_T_2[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_5 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_6 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_6 | ~(_T_39 | ~(_T_44 | _GEN_5 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? _wentry_conf_T_1 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_3 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:{22,36}, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_7 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_8 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_8 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_7 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_8 | ~(_T_44 | _T_47 | ~_GEN_7)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_6 | _T_39 | ~(_T_44 | ~(_GEN_5 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_9 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_19( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [583:0] c_sizes_set = 584'h0; // @[Monitor.scala:741:34]
wire [291:0] c_opcodes_set = 292'h0; // @[Monitor.scala:740:34]
wire [72:0] c_set = 73'h0; // @[Monitor.scala:738:34]
wire [72:0] c_set_wo_ready = 73'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_52 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_53 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_72 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_67 = _source_ok_T_66 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_73 = _source_ok_T_72 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_77; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_78 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_84 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_90 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_79 = _source_ok_T_78 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_85 = _source_ok_T_84 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_91 = _source_ok_T_90 == 4'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_94 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_7 = _source_ok_T_95; // @[Parameters.scala:1138:31]
wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_97; // @[Parameters.scala:1138:31]
wire _source_ok_T_98 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_105 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1811 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1811; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1811; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1884 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1884; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1884; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1884; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [72:0] inflight; // @[Monitor.scala:614:27]
reg [291:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [583:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [72:0] a_set; // @[Monitor.scala:626:34]
wire [72:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [291:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [583:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [291:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [291:0] _a_opcode_lookup_T_6 = {288'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [291:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[291:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [583:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [583:0] _a_size_lookup_T_6 = {576'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [583:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[583:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire _T_1737 = _T_1811 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1737 ? _a_set_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1737 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1737 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1737 ? _a_opcodes_set_T_1[291:0] : 292'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1737 ? _a_sizes_set_T_1[583:0] : 584'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [72:0] d_clr; // @[Monitor.scala:664:34]
wire [72:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [291:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [583:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1783 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1783 & ~d_release_ack ? _d_clr_wo_ready_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire _T_1752 = _T_1884 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1752 ? _d_clr_T[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1752 ? _d_opcodes_clr_T_5[291:0] : 292'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1752 ? _d_sizes_clr_T_5[583:0] : 584'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [72:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [72:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [72:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [291:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [291:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [291:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [583:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [583:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [583:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [72:0] inflight_1; // @[Monitor.scala:726:35]
wire [72:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [291:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [291:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [583:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [583:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [291:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [291:0] _c_opcode_lookup_T_6 = {288'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [291:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[291:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [583:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [583:0] _c_size_lookup_T_6 = {576'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [583:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[583:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [72:0] d_clr_1; // @[Monitor.scala:774:34]
wire [72:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [291:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [583:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1855 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1855 & d_release_ack_1 ? _d_clr_wo_ready_T_1[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire _T_1837 = _T_1884 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1837 ? _d_clr_T_1[72:0] : 73'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1837 ? _d_opcodes_clr_T_11[291:0] : 292'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1837 ? _d_sizes_clr_T_11[583:0] : 584'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [72:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [72:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [291:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [291:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [583:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [583:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TLFragmenter( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [14:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [14:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30]
wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [9:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [28:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [3:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
reg [3:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire [4:0] _dsizeOH1_T = 5'h3 << auto_anon_out_d_bits_size; // @[package.scala:243:71]
wire [3:0] _GEN = ~(auto_anon_out_d_bits_source[3:0]); // @[package.scala:241:49]
wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[3:1] & {1'h1, _GEN[3:2]}; // @[OneHot.scala:30:18]
wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | {auto_anon_out_d_bits_source[0], ~(_dsizeOH1_T[1:0])} & {_GEN[1:0], _dsizeOH1_T[1]}; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[3:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}]
wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}]
wire [2:0] anonIn_d_bits_size = (|acknum) ? dOrig : dFirst_size; // @[OneHot.scala:32:10]
reg r_denied; // @[Fragmenter.scala:242:29]
wire d_denied = (|acknum) & r_denied | auto_anon_out_d_bits_denied; // @[Fragmenter.scala:201:29, :205:29, :242:29, :243:{35,48}]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
reg [3:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 4'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [3:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:2]) : gennum - 4'h1; // @[package.scala:243:{46,71,76}]
reg aToggle_r; // @[Fragmenter.scala:309:54] |
Generate the Verilog code corresponding to the following Chisel files.
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
| module Repeater_TLBundleA_a29d64s8k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [28:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [28:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [28:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [28:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [28:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [7:0] saved_source; // @[Repeater.scala:21:18]
reg [28:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_67( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
| module BranchKillableQueue_15( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [33:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [1:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [33:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [1:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
output io_empty // @[util.scala:463:14]
);
wire _out_valid_T_12; // @[util.scala:496:38]
wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22]
wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22]
wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22]
wire _main_io_deq_bits_is_hella; // @[util.scala:476:22]
wire _main_io_deq_bits_tag_match; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22]
wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22]
wire _main_io_empty; // @[util.scala:476:22]
wire [3:0] _main_io_count; // @[util.scala:476:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27]
wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27]
wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7]
wire io_flush = 1'h0; // @[util.scala:458:7]
wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59]
wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61]
wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94]
wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59]
wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61]
wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire _io_empty_T_1; // @[util.scala:484:31]
wire [3:0] _io_count_T_1; // @[util.scala:485:31]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count; // @[util.scala:458:7]
reg [31:0] out_reg_uop_inst; // @[util.scala:477:22]
reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22]
reg out_reg_uop_is_rvc; // @[util.scala:477:22]
reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22]
reg out_reg_uop_iq_type_0; // @[util.scala:477:22]
reg out_reg_uop_iq_type_1; // @[util.scala:477:22]
reg out_reg_uop_iq_type_2; // @[util.scala:477:22]
reg out_reg_uop_iq_type_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_0; // @[util.scala:477:22]
reg out_reg_uop_fu_code_1; // @[util.scala:477:22]
reg out_reg_uop_fu_code_2; // @[util.scala:477:22]
reg out_reg_uop_fu_code_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_4; // @[util.scala:477:22]
reg out_reg_uop_fu_code_5; // @[util.scala:477:22]
reg out_reg_uop_fu_code_6; // @[util.scala:477:22]
reg out_reg_uop_fu_code_7; // @[util.scala:477:22]
reg out_reg_uop_fu_code_8; // @[util.scala:477:22]
reg out_reg_uop_fu_code_9; // @[util.scala:477:22]
reg out_reg_uop_iw_issued; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_dis_col_sel; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22]
reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22]
reg out_reg_uop_is_sfb; // @[util.scala:477:22]
reg out_reg_uop_is_fence; // @[util.scala:477:22]
reg out_reg_uop_is_fencei; // @[util.scala:477:22]
reg out_reg_uop_is_sfence; // @[util.scala:477:22]
reg out_reg_uop_is_amo; // @[util.scala:477:22]
reg out_reg_uop_is_eret; // @[util.scala:477:22]
reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22]
reg out_reg_uop_is_rocc; // @[util.scala:477:22]
reg out_reg_uop_is_mov; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22]
reg out_reg_uop_edge_inst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22]
reg out_reg_uop_taken; // @[util.scala:477:22]
reg out_reg_uop_imm_rename; // @[util.scala:477:22]
reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22]
reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22]
reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22]
reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22]
reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22]
reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22]
reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22]
reg out_reg_uop_prs1_busy; // @[util.scala:477:22]
reg out_reg_uop_prs2_busy; // @[util.scala:477:22]
reg out_reg_uop_prs3_busy; // @[util.scala:477:22]
reg out_reg_uop_ppred_busy; // @[util.scala:477:22]
reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22]
reg out_reg_uop_exception; // @[util.scala:477:22]
reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22]
reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22]
reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22]
reg out_reg_uop_mem_signed; // @[util.scala:477:22]
reg out_reg_uop_uses_ldq; // @[util.scala:477:22]
reg out_reg_uop_uses_stq; // @[util.scala:477:22]
reg out_reg_uop_is_unique; // @[util.scala:477:22]
reg out_reg_uop_flush_on_commit; // @[util.scala:477:22]
reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22]
reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22]
reg out_reg_uop_frs3_en; // @[util.scala:477:22]
reg out_reg_uop_fcn_dw; // @[util.scala:477:22]
reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22]
reg out_reg_uop_fp_val; // @[util.scala:477:22]
reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22]
reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22]
reg out_reg_uop_bp_debug_if; // @[util.scala:477:22]
reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22]
reg [33:0] out_reg_addr; // @[util.scala:477:22]
assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22]
reg [63:0] out_reg_data; // @[util.scala:477:22]
assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22]
reg out_reg_is_hella; // @[util.scala:477:22]
assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22]
reg out_reg_tag_match; // @[util.scala:477:22]
assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22]
assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22]
reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22]
assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_way_en; // @[util.scala:477:22]
assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22]
reg [4:0] out_reg_sdq_id; // @[util.scala:477:22]
assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22]
reg out_valid; // @[util.scala:478:28]
assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28]
wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28]
reg [31:0] out_uop_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22]
reg [31:0] out_uop_debug_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22]
reg out_uop_is_rvc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22]
reg [33:0] out_uop_debug_pc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22]
wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_0; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_1; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_2; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_3; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_0; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_1; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_2; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_3; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_4; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_5; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_6; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_7; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_8; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_9; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_dis_col_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22]
wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_mask; // @[util.scala:479:22]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22]
wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22]
reg [1:0] out_uop_br_tag; // @[util.scala:479:22]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_type; // @[util.scala:479:22]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfb; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22]
reg out_uop_is_fence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22]
reg out_uop_is_fencei; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22]
reg out_uop_is_amo; // @[util.scala:479:22]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22]
reg out_uop_is_eret; // @[util.scala:479:22]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22]
reg out_uop_is_sys_pc2epc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22]
reg out_uop_is_rocc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22]
reg out_uop_is_mov; // @[util.scala:479:22]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22]
reg out_uop_edge_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22]
wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pc_lob; // @[util.scala:479:22]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22]
reg out_uop_taken; // @[util.scala:479:22]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22]
wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22]
reg out_uop_imm_rename; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22]
wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_imm_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_pimm; // @[util.scala:479:22]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22]
reg [19:0] out_uop_imm_packed; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22]
wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_op1_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_op2_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wen; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_toint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fma; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_div; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_vec; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_rob_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_stq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs1; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs2; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs3; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ppred; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22]
reg out_uop_prs1_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs2_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs3_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22]
reg out_uop_ppred_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22]
reg out_uop_exception; // @[util.scala:479:22]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22]
wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22]
reg [63:0] out_uop_exc_cause; // @[util.scala:479:22]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22]
wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_mem_size; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22]
reg out_uop_mem_signed; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22]
wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22]
reg out_uop_uses_ldq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22]
reg out_uop_uses_stq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22]
reg out_uop_is_unique; // @[util.scala:479:22]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22]
reg out_uop_flush_on_commit; // @[util.scala:479:22]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22]
wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22]
reg out_uop_ldst_is_rs1; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22]
wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs1; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs2; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs3; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22]
reg out_uop_frs3_en; // @[util.scala:479:22]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22]
wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22]
reg out_uop_fcn_dw; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22]
wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_fcn_op; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22]
reg out_uop_fp_val; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_fp_rm; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_typ; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_pf_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ae_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ma_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_debug_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_xcpt_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22]
wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34]
assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31]
wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31]
assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31]
assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31]
wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23]
assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}]
wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35]
wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}]
wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25]
wire out_uop_out_1_iq_type_0; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_1; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_2; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_0; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_1; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_2; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_4; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_5; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_6; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_7; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_8; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_9; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23]
wire out_uop_out_1_is_rvc; // @[util.scala:104:23]
wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23]
wire out_uop_out_1_is_sfb; // @[util.scala:104:23]
wire out_uop_out_1_is_fence; // @[util.scala:104:23]
wire out_uop_out_1_is_fencei; // @[util.scala:104:23]
wire out_uop_out_1_is_sfence; // @[util.scala:104:23]
wire out_uop_out_1_is_amo; // @[util.scala:104:23]
wire out_uop_out_1_is_eret; // @[util.scala:104:23]
wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23]
wire out_uop_out_1_is_rocc; // @[util.scala:104:23]
wire out_uop_out_1_is_mov; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23]
wire out_uop_out_1_edge_inst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23]
wire out_uop_out_1_taken; // @[util.scala:104:23]
wire out_uop_out_1_imm_rename; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23]
wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23]
wire out_uop_out_1_prs1_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs2_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs3_busy; // @[util.scala:104:23]
wire out_uop_out_1_ppred_busy; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23]
wire out_uop_out_1_exception; // @[util.scala:104:23]
wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23]
wire out_uop_out_1_mem_signed; // @[util.scala:104:23]
wire out_uop_out_1_uses_ldq; // @[util.scala:104:23]
wire out_uop_out_1_uses_stq; // @[util.scala:104:23]
wire out_uop_out_1_is_unique; // @[util.scala:104:23]
wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23]
wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23]
wire out_uop_out_1_frs3_en; // @[util.scala:104:23]
wire out_uop_out_1_fcn_dw; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23]
wire out_uop_out_1_fp_val; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23]
assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
always @(posedge clock) begin // @[util.scala:458:7]
if (main_io_deq_ready) begin // @[util.scala:495:23]
out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22]
out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22]
out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22]
out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22]
out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22]
out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22]
out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22]
out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22]
out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22]
out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22]
out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22]
out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22]
out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22]
out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22]
out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22]
out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22]
out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22]
out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22]
out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22]
out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22]
out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22]
end
out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
if (reset) // @[util.scala:458:7]
out_valid <= 1'h0; // @[util.scala:478:28]
else // @[util.scala:458:7]
out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}]
always @(posedge)
BranchKillableQueue_14 main ( // @[util.scala:476:22]
.clock (clock),
.reset (reset),
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[util.scala:458:7]
.io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7]
.io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7]
.io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7]
.io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7]
.io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7]
.io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7]
.io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7]
.io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7]
.io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7]
.io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7]
.io_deq_ready (main_io_deq_ready), // @[util.scala:495:23]
.io_deq_valid (_out_valid_T_12),
.io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst),
.io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst),
.io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc),
.io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc),
.io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0),
.io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1),
.io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2),
.io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3),
.io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0),
.io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1),
.io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2),
.io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3),
.io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4),
.io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5),
.io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6),
.io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7),
.io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8),
.io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9),
.io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued),
.io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen),
.io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen),
.io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child),
.io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child),
.io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint),
.io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint),
.io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint),
.io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel),
.io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag),
.io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type),
.io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb),
.io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence),
.io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei),
.io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence),
.io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret),
.io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc),
.io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc),
.io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov),
.io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx),
.io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst),
.io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob),
.io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken),
.io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename),
.io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel),
.io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm),
.io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed),
.io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel),
.io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel),
.io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst),
.io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen),
.io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1),
.io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2),
.io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3),
.io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12),
.io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23),
.io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn),
.io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut),
.io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint),
.io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint),
.io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe),
.io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma),
.io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div),
.io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt),
.io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags),
.io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec),
.io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx),
.io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx),
.io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst),
.io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1),
.io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2),
.io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3),
.io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred),
.io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy),
.io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy),
.io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy),
.io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy),
.io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst),
.io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception),
.io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause),
.io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd),
.io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size),
.io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed),
.io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq),
.io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique),
.io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit),
.io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd),
.io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1),
.io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst),
.io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1),
.io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2),
.io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3),
.io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype),
.io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype),
.io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en),
.io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw),
.io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op),
.io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val),
.io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm),
.io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ),
.io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if),
.io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if),
.io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if),
.io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if),
.io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if),
.io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc),
.io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc),
.io_deq_bits_addr (_main_io_deq_bits_addr),
.io_deq_bits_data (_main_io_deq_bits_data),
.io_deq_bits_is_hella (_main_io_deq_bits_is_hella),
.io_deq_bits_tag_match (_main_io_deq_bits_tag_match),
.io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state),
.io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag),
.io_deq_bits_way_en (_main_io_deq_bits_way_en),
.io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id),
.io_empty (_main_io_empty),
.io_count (_main_io_count)
); // @[util.scala:476:22]
assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22]
assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_243( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File ClockGroupCombiner.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
object ClockGroupCombiner {
def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = {
LazyModule(new ClockGroupCombiner()).node
}
}
case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil)
// All clock groups with a name containing any substring in names will be combined into a single clock group
class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])*) extends Config((site, here, up) => {
case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) =>
(grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n)))
}
})
/** This node combines sets of clock groups according to functions provided in the ClockGroupCombinerKey
* The ClockGroupCombinersKey contains a list of tuples of:
* - The name of the combined group
* - A function on the ClockSinkParameters, returning True if the associated clock group should be grouped by this node
* This node will fail if
* - Multiple grouping functions match a single clock group
* - A grouping function matches zero clock groups
* - A grouping function matches clock groups with different requested frequncies
*/
class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule {
val combiners = p(ClockGroupCombinerKey)
val sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m }
val sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { u =>
var i = 0
val (grouped, rest) = combiners.map(_._2).foldLeft((Seq[ClockSinkParameters](), u.members)) { case ((grouped, rest), c) =>
val (g, r) = rest.partition(c(_))
val name = combiners(i)._1
i = i + 1
require(g.size >= 1)
val names = g.map(_.name.getOrElse("unamed"))
val takes = g.map(_.take).flatten
require(takes.distinct.size <= 1,
s"Clock group '$name' has non-homogeneous requested ClockParameters ${names.zip(takes)}")
require(takes.size > 0,
s"Clock group '$name' has no inheritable frequencies")
(grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r)
}
ClockGroupSinkParameters(
name = u.name,
members = grouped ++ rest
)
}
val node = ClockGroupAdapterNode(sourceFn, sinkFn)
lazy val module = new LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((o, oe), (i, ie)) =>
{
val inMap = (i.member.data zip ie.sink.members).map { case (id, im) =>
im.name.get -> id
}.toMap
(o.member.data zip oe.sink.members).map { case (od, om) =>
val matches = combiners.filter(c => c._2(om))
require(matches.size <= 1)
if (matches.size == 0) {
od := inMap(om.name.get)
} else {
od := inMap(matches(0)._1)
}
}
}
}
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module ClockGroupCombiner( // @[ClockGroupCombiner.scala:68:25]
input auto_clock_group_combiner_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_group_combiner_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_5_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_5_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_4_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_4_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_3_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_3_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_group_combiner_out_member_allClocks_sbus_0_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_clock_group_combiner_in_member_allClocks_uncore_clock_0 = auto_clock_group_combiner_in_member_allClocks_uncore_clock; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_in_member_allClocks_uncore_reset_0 = auto_clock_group_combiner_in_member_allClocks_uncore_reset; // @[ClockGroupCombiner.scala:68:25]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroupCombinerIn_member_allClocks_uncore_clock = auto_clock_group_combiner_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17]
wire clockGroupCombinerIn_member_allClocks_uncore_reset = auto_clock_group_combiner_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17]
wire clockGroupCombinerOut_member_allClocks_sbus_5_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_5_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_4_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_4_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_3_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_3_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_2_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_2_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
wire clockGroupCombinerOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
wire auto_clock_group_combiner_out_member_allClocks_sbus_5_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_5_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_4_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_4_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_3_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_3_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_2_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_2_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_1_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_1_reset_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
wire auto_clock_group_combiner_out_member_allClocks_sbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign clockGroupCombinerOut_member_allClocks_sbus_5_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_4_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_3_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_2_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_1_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_0_clock = clockGroupCombinerIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_5_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_4_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_3_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_2_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_1_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockGroupCombinerOut_member_allClocks_sbus_0_reset = clockGroupCombinerIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_5_clock_0 = clockGroupCombinerOut_member_allClocks_sbus_5_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_5_reset_0 = clockGroupCombinerOut_member_allClocks_sbus_5_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_4_clock_0 = clockGroupCombinerOut_member_allClocks_sbus_4_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_4_reset_0 = clockGroupCombinerOut_member_allClocks_sbus_4_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_3_clock_0 = clockGroupCombinerOut_member_allClocks_sbus_3_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_3_reset_0 = clockGroupCombinerOut_member_allClocks_sbus_3_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_2_clock_0 = clockGroupCombinerOut_member_allClocks_sbus_2_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_2_reset_0 = clockGroupCombinerOut_member_allClocks_sbus_2_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_1_clock_0 = clockGroupCombinerOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_1_reset_0 = clockGroupCombinerOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_0_clock_0 = clockGroupCombinerOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_0_reset_0 = clockGroupCombinerOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
assign auto_clock_group_combiner_out_member_allClocks_sbus_5_clock = auto_clock_group_combiner_out_member_allClocks_sbus_5_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_5_reset = auto_clock_group_combiner_out_member_allClocks_sbus_5_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_4_clock = auto_clock_group_combiner_out_member_allClocks_sbus_4_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_4_reset = auto_clock_group_combiner_out_member_allClocks_sbus_4_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_3_clock = auto_clock_group_combiner_out_member_allClocks_sbus_3_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_3_reset = auto_clock_group_combiner_out_member_allClocks_sbus_3_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_2_clock = auto_clock_group_combiner_out_member_allClocks_sbus_2_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_2_reset = auto_clock_group_combiner_out_member_allClocks_sbus_2_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_1_clock = auto_clock_group_combiner_out_member_allClocks_sbus_1_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_1_reset = auto_clock_group_combiner_out_member_allClocks_sbus_1_reset_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_0_clock = auto_clock_group_combiner_out_member_allClocks_sbus_0_clock_0; // @[ClockGroupCombiner.scala:68:25]
assign auto_clock_group_combiner_out_member_allClocks_sbus_0_reset = auto_clock_group_combiner_out_member_allClocks_sbus_0_reset_0; // @[ClockGroupCombiner.scala:68:25]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Debug.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBFanout, APBToTL}
import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule}
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError}
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode}
import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.rocket.{CSRs, Instructions}
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}
import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
import freechips.rocketchip.util.SeqBoolBitwiseOps
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.BooleanToAugmentedBoolean
object DsbBusConsts {
def sbAddrWidth = 12
def sbIdWidth = 10
}
object DsbRegAddrs{
// These are used by the ROM.
def HALTED = 0x100
def GOING = 0x104
def RESUMING = 0x108
def EXCEPTION = 0x10C
def WHERETO = 0x300
// This needs to be aligned for up to lq/sq
// This shows up in HartInfo, and needs to be aligned
// to enable up to LQ/SQ instructions.
def DATA = 0x380
// We want DATA to immediately follow PROGBUF so that we can
// use them interchangeably. Leave another slot if there is an
// implicit ebreak.
def PROGBUF(cfg:DebugModuleParams) = {
val tmp = DATA - (cfg.nProgramBufferWords * 4)
if (cfg.hasImplicitEbreak) (tmp - 4) else tmp
}
// This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF.
def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 }
// We want abstract to be immediately before PROGBUF
// because we auto-generate 2 (or 5) instructions.
def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4)
def FLAGS = 0x400
def ROMBASE = 0x800
}
/** Enumerations used both in the hardware
* and in the configuration specification.
*/
object DebugModuleAccessType extends scala.Enumeration {
type DebugModuleAccessType = Value
val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value
}
object DebugAbstractCommandError extends scala.Enumeration {
type DebugAbstractCommandError = Value
val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value
}
object DebugAbstractCommandType extends scala.Enumeration {
type DebugAbstractCommandType = Value
val AccessRegister, QuickAccess = Value
}
/** Parameters exposed to the top-level design, set based on
* external requirements, etc.
*
* This object checks that the parameters conform to the
* full specification. The implementation which receives this
* object can perform more checks on what that implementation
* actually supports.
* @param nComponents Number of components to support debugging.
* @param baseAddress Base offest for debugEntry and debugException
* @param nDMIAddrSize Size of the Debug Bus Address
* @param nAbstractDataWords Number of 32-bit words for Abstract Commands
* @param nProgamBufferWords Number of 32-bit words for Program Buffer
* @param hasBusMaster Whether or not a bus master should be included
* @param clockGate Whether or not to use dmactive as the clockgate for debug module
* @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic.
* @param supportQuickAccess Whether or not to support the quick access command.
* @param supportHartArray Whether or not to implement the hart array register (if >1 hart).
* @param nHaltGroups Number of halt groups
* @param nExtTriggers Number of external triggers
* @param hasHartResets Feature to reset all the currently selected harts
* @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak
* @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset.
*/
case class DebugModuleParams (
baseAddress : BigInt = BigInt(0),
nDMIAddrSize : Int = 7,
nProgramBufferWords: Int = 16,
nAbstractDataWords : Int = 4,
nScratch : Int = 1,
hasBusMaster : Boolean = false,
clockGate : Boolean = true,
maxSupportedSBAccess : Int = 32,
supportQuickAccess : Boolean = false,
supportHartArray : Boolean = true,
nHaltGroups : Int = 1,
nExtTriggers : Int = 0,
hasHartResets : Boolean = false,
hasImplicitEbreak : Boolean = false,
hasAuthentication : Boolean = false,
crossingHasSafeReset : Boolean = true
) {
require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}")
require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}")
require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}")
require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}")
require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}")
if (supportQuickAccess) {
// TODO: Check that quick access requirements are met.
}
def address = AddressSet(baseAddress, 0xFFF)
/** the base address of DM */
def atzero = (baseAddress == 0)
/** The number of generated instructions
*
* When the base address is not zero, we need more instruction also,
* more dscratch registers) to load/store memory mapped data register
* because they may no longer be directly addressible with x0 + 12-bit imm
*/
def nAbstractInstructions = if (atzero) 2 else 5
def debugEntry: BigInt = baseAddress + 0x800
def debugException: BigInt = baseAddress + 0x808
def nDscratch: Int = if (atzero) 1 else 2
}
object DefaultDebugModuleParams {
def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = {
new DebugModuleParams().copy(
nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4),
maxSupportedSBAccess = xlen
)
}
}
case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams()))
/** Functional parameters exposed to the design configuration.
*
* hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping.
* hartSelToHartId: Provide inverse mapping of the above
*/
case class DebugModuleHartSelFuncs (
hartIdToHartSel : (UInt) => UInt = (x:UInt) => x,
hartSelToHartId : (UInt) => UInt = (x:UInt) => x
)
case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs())
class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle {
val req = Output(UInt(nExtTriggers.W))
val ack = Input(UInt(nExtTriggers.W))
}
class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle {
val req = Input(UInt(nExtTriggers.W))
val ack = Output(UInt(nExtTriggers.W))
}
class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {
val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers)
val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers)
}
class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {
val dmactive = Output(Bool())
val dmAuthWrite = Output(Bool())
val dmAuthRead = Output(Bool())
val dmAuthWdata = Output(UInt(32.W))
val dmAuthBusy = Input(Bool())
val dmAuthRdata = Input(UInt(32.W))
val dmAuthenticated = Input(Bool())
}
// *****************************************
// Module Interfaces
//
// *****************************************
/** Control signals for Inner, generated in Outer
* {{{
* run control: resumreq, ackhavereset, halt-on-reset mask
* hart select: hasel, hartsel and the hart array mask
* }}}
*/
class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
/** resume request */
val resumereq = Bool()
/** hart select */
val hartsel = UInt(10.W)
/** reset acknowledge */
val ackhavereset = Bool()
/** hart array enable */
val hasel = Bool()
/** hart array mask */
val hamask = Vec(nComponents, Bool())
/** halt-on-reset mask */
val hrmask = Vec(nComponents, Bool())
}
/** structure for top-level Debug Module signals which aren't the bus interfaces. */
class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
/** debug availability status for all harts */
val debugUnavail = Input(Vec(nComponents, Bool()))
/** reset signal
*
* for every part of the hardware platform,
* including every hart, except for the DM and any
* logic required to access the DM
*/
val ndreset = Output(Bool())
/** reset signal for the DM itself */
val dmactive = Output(Bool())
/** dmactive acknowlege */
val dmactiveAck = Input(Bool())
}
// *****************************************
// Debug Module
//
// *****************************************
/** Parameterized version of the Debug Module defined in the
* RISC-V Debug Specification
*
* DebugModule is a slave to two asynchronous masters:
* The Debug Bus (DMI) -- This is driven by an external debugger
*
* The System Bus -- This services requests from the cores. Generally
* this interface should only be active at the request
* of the debugger, but the Debug Module may also
* provide the default MTVEC since it is mapped
* to address 0x0.
*
* DebugModule is responsible for control registers and RAM, and
* Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and
* the TL clock. Therefore, it is divided into "Outer" portion (running
* off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset).
* This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive,
* and ndreset to be modified even while the Core is in reset or not being clocked.
* Not all reads from the Debugger to the Debug Module will actually complete
* in these scenarios either, they will just block until tl_clock and tl_reset
* allow them to complete. This is not strictly necessary for
* proper debugger functionality.
*/
// Local reg mapper function : Notify when written, but give the value as well.
object WNotifyWire {
def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = {
RegField(n, 0.U, RegWriteFn((valid, data) => {
set := valid
value := data
true.B
}), Some(RegFieldDesc(name = name, desc = desc,
access = RegFieldAccessType.W)))
}
}
// Local reg mapper function : Notify when accessed either as read or write.
object RWNotify {
def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = {
RegField(n,
RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}),
RegWriteFn((valid, data) => {
wNotify := valid
when (valid) {wVal := data}
true.B
}
), desc)
}
}
// Local reg mapper function : Notify with value when written, take read input as presented.
// This allows checking or correcting the write value before storing it in the register field.
object WNotifyVal {
def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = {
RegField(n, rVal, RegWriteFn((valid, data) => {
wNotify := valid
wVal := data
true.B
}
), desc)
}
}
class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule {
// For Shorter Register Names
import DMI_RegAddrs._
val cfg = p(DebugModuleKey).get
val intnode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false)
val dmiNode = TLRegisterNode (
address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++
AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOW << 2, 4),
device = device,
beatBytes = 4,
executable = false
)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts")
val nComponents = intnode.out.size
def getNComponents = () => nComponents
val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart
val io = IO(new Bundle {
/** structure for top-level Debug Module signals which aren't the bus interfaces. */
val ctrl = (new DebugCtrlBundle(nComponents))
/** control signals for Inner, generated in Outer */
val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents))
/** debug interruption from Inner to Outer
*
* contains 2 type of debug interruption causes:
* - halt group
* - halt-on-reset
*/
val hgDebugInt = Input(Vec(nComponents, Bool()))
/** hart reset request to core */
val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** authentication support */
val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool()))
})
val omRegMap = withReset(reset.asAsyncReset) {
// FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available)
val dmAuthenticated = io.dmAuthenticated.map( dma =>
ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B)
//----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it
// can be written even if 'Inner' is not being clocked or is in reset. This allows halting
// harts while the rest of the system is in reset. It doesn't really allow any other
// register accesses, which will keep returning 'busy' to the debugger interface.
val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg")
val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U
val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val dmactiveWrEn = WireInit(false.B)
val ndmresetWrEn = WireInit(false.B)
val clrresethaltreqWrEn = WireInit(false.B)
val setresethaltreqWrEn = WireInit(false.B)
val hartselloWrEn = WireInit(false.B)
val haselWrEn = WireInit(false.B)
val ackhaveresetWrEn = WireInit(false.B)
val hartresetWrEn = WireInit(false.B)
val resumereqWrEn = WireInit(false.B)
val haltreqWrEn = WireInit(false.B)
val dmactive = DMCONTROLReg.dmactive
DMCONTROLNxt := DMCONTROLReg
when (~dmactive) {
DMCONTROLNxt := DMCONTROLReset
} .otherwise {
when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset }
when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask}
when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel }
when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset }
when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq }
}
// Put this last to override its own effects.
when (dmactiveWrEn) {
DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive
}
//----HARTINFO
// DATA registers are mapped to memory. The dataaddr field of HARTINFO has only
// 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0
// (implying nonexistence according to the Debug Spec).
val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields()))
if (cfg.atzero) when (dmAuthenticated) {
HARTINFORdData.dataaccess := true.B
HARTINFORdData.datasize := cfg.nAbstractDataWords.U
HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U
HARTINFORdData.nscratch := cfg.nScratch.U
}
//--------------------------------------------------------------
// Hart array mask and window
// hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello
// HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW
//--------------------------------------------------------------
val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
def haWindowSize = 32
// The following need to be declared even if supportHartArray is false due to reference
// at compile time by dmiNode.regmap
val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
val HAWINDOWSELWrEn = WireInit(false.B)
val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAWINDOWWrEn = WireInit(false.B)
/** whether the hart is selected */
def hartSelected(hart: Int): Bool = {
((io.innerCtrl.bits.hartsel === hart.U) ||
(if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B))
}
val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt))
if (supportHartArray) {
val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
HAWINDOWSELNxt := HAWINDOWSELReg
when (~dmactive || ~dmAuthenticated) {
HAWINDOWSELNxt := HAWINDOWSELReset
} .otherwise {
when (HAWINDOWSELWrEn) {
// Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window
if (nComponents > haWindowSize) {
HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U
} else {
HAWINDOWSELNxt.hawindowsel := 0.U
}
}
}
val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1
HAWINDOWRdData.maskdata := 0.U // default, overridden below
// for each slice,use a hamaskReg to store the selection info
for (ii <- 0 until numHAMASKSlices) {
val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist
else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice
val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt))
when (ii.U === HAWINDOWSELReg.hawindowsel) {
HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U
}
HAMASKNxt.maskdata := HAMASKReg.asUInt
when (~dmactive || ~dmAuthenticated) {
HAMASKNxt := HAMASKRst
}.otherwise {
when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {
HAMASKNxt.maskdata := HAWINDOWWrData.maskdata
}
}
// drive each slice of hamask with stored HAMASKReg or with new value being written
for (jj <- 0 until haWindowSize) {
if (((ii*haWindowSize) + jj) < nComponents) {
val tempWrData = HAWINDOWWrData.maskdata.asBools
val tempMaskReg = HAMASKReg.asUInt.asBools
when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {
hamask(ii*haWindowSize + jj) := tempWrData(jj)
}.otherwise {
hamask(ii*haWindowSize + jj) := tempMaskReg(jj)
}
}
}
}
}
//--------------------------------------------------------------
// Halt-on-reset
// hrmaskReg is current set of harts that should halt-on-reset
// Reset state (dmactive=0) is all zeroes
// Bits are set by writing 1 to DMCONTROL.setresethaltreq
// Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq
// Spec says if both are 1, then clrresethaltreq is executed
// hrmask is the halt-on-reset mask which will be sent to inner
//--------------------------------------------------------------
val hrmask = Wire(Vec(nComponents, Bool()))
val hrmaskNxt = Wire(Vec(nComponents, Bool()))
val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg")
hrmaskNxt := hrmaskReg
for (component <- 0 until nComponents) {
when (~dmactive || ~dmAuthenticated) {
hrmaskNxt(component) := false.B
}.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) {
hrmaskNxt(component) := false.B
}.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) {
hrmaskNxt(component) := true.B
}
}
hrmask := hrmaskNxt
val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq(
WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn,
RegFieldDesc("dmactive", "debug module active", reset=Some(0))),
WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn,
RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))),
WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn,
RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)),
WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn,
RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)),
RegField(12),
if (nComponents > 1) WNotifyVal(p(MaxHartIdBits),
DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn,
RegFieldDesc("hartsello", "hart select low", reset=Some(0)))
else RegField(1),
if (nComponents > 1) RegField(10-p(MaxHartIdBits))
else RegField(9),
if (supportHartArray)
WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn,
RegFieldDesc("hasel", "hart array select", reset=Some(0)))
else RegField(1),
RegField(1),
WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn,
RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)),
if (cfg.hasHartResets)
WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn,
RegFieldDesc("hartreset", "hart reset request", reset=Some(0)))
else RegField(1),
WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn,
RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)),
WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior
RegFieldDesc("haltreq", "halt request", reset=Some(0)))
))
val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq(
RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))),
RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))),
RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))),
RegField(3),
RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0)))
))
//--------------------------------------------------------------
// DMI register decoder for Outer
//--------------------------------------------------------------
// regmap addresses are byte offsets from lowest address
def DMI_DMCONTROL_OFFSET = 0
def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2)
def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2)
def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2)
val omRegMap = dmiNode.regmap(
DMI_DMCONTROL_OFFSET -> dmControlRegFields,
DMI_HARTINFO_OFFSET -> hartinfoRegFields,
DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq(
WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn,
RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil),
DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq(
WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn,
RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil)
)
//--------------------------------------------------------------
// Interrupt Registers
//--------------------------------------------------------------
val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs")
debugIntNxt := debugIntRegs
val (intnode_out, _) = intnode.out.unzip
for (component <- 0 until nComponents) {
intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component)
}
// sends debug interruption to Core when dmcs.haltreq is set,
for (component <- 0 until nComponents) {
when (~dmactive || ~dmAuthenticated) {
debugIntNxt(component) := false.B
}. otherwise {
when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U)
|| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) {
debugIntNxt(component) := DMCONTROLWrData.haltreq
}
}
}
// Halt request registers are set & cleared by writes to DMCONTROL.haltreq
// resumereq also causes the core to execute a 'dret',
// so resumereq is passed through to Inner.
// hartsel/hasel/hamask must also be used by the DebugModule state machine,
// so it is passed to Inner.
// These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together.
// If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received.
// Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent.
// Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received.
val innerCtrlValid = Wire(Bool())
val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg")
val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg")
val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg")
innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn |
(HAWINDOWWrEn & supportHartArray.B)
innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it
innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted
innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted
io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg
io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello)
io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg
io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg
io.innerCtrl.bits.hrmask := hrmask
if (supportHartArray) {
io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel)
io.innerCtrl.bits.hamask := hamask
} else {
io.innerCtrl.bits.hasel := DontCare
io.innerCtrl.bits.hamask := DontCare
}
io.ctrl.ndreset := DMCONTROLReg.ndmreset
io.ctrl.dmactive := DMCONTROLReg.dmactive
// hart reset mechanism implementation
if (cfg.hasHartResets) {
val hartResetNxt = Wire(Vec(nComponents, Bool()))
val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt))
for (component <- 0 until nComponents) {
hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component)
io.hartResetReq.get(component) := hartResetReg(component)
}
}
omRegMap // FIXME: Remove this when withReset is removed
}}
}
// wrap a Outer with a DMIToTL, derived by dmi clock & reset
class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule {
val cfg = p(DebugModuleKey).get
val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar")))
val dmi2tlOpt = (!p(ExportDebug).apb).option({
val dmi2tl = LazyModule(new DMIToTL())
dmiXbar.node := dmi2tl.node
dmi2tl
})
val apbNodeOpt = p(ExportDebug).apb.option({
val apb2tl = LazyModule(new APBToTL())
val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe))
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4)
val tlError = LazyModule(new TLError(tlErrorParams, buffer=false))
val apbXbar = LazyModule(new APBFanout())
val apbRegs = LazyModule(new APBDebugRegisters())
apbRegs.node := apbXbar.node
apb2tl.node := apbXbar.node
apb2tlBuffer.node := apb2tl.node
dmiXbar.node := apb2tlBuffer.node
tlError.node := dmiXbar.node
apbXbar.node
})
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode = IntSyncIdentityNode()
intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4))
val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node
dmOuter.dmiNode := dmiXbar.node
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val nComponents = dmOuter.intnode.edges.out.size
val io = IO(new Bundle {
val dmi_clock = Input(Clock())
val dmi_reset = Input(Reset())
/** Debug Module Interface bewteen DM and DTM
*
* The DTM provides access to one or more Debug Modules (DMs) using DMI
*/
val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p)))
// Optional APB Interface is fully diplomatic so is not listed here.
val ctrl = new DebugCtrlBundle(nComponents)
/** conrol signals for Inner, generated in Outer */
val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))
/** debug interruption generated in Inner */
val hgDebugInt = Input(Vec(nComponents, Bool()))
/** hart reset request to core */
val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** Authentication signal from core */
val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool()))
})
val rf_reset = IO(Input(Reset())) // RF transform
childClock := io.dmi_clock
childReset := io.dmi_reset
override def provideImplicitClockToLazyChildren = true
withClockAndReset(childClock, childReset) {
dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get }
val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync"))
dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck
io.ctrl <> dmOuter.module.io.ctrl
dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter
io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))
dmOuter.module.io.hgDebugInt := io.hgDebugInt
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}}
}
}
}
class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// For Shorter Register Names
import DMI_RegAddrs._
val cfg = p(DebugModuleKey).get
def getCfg = () => cfg
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
/** dmiNode address set */
val dmiNode = TLRegisterNode(
// Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer
address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++
AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))),
device = device,
beatBytes = 4,
executable = false
)
val tlNode = TLRegisterNode(
address=Seq(cfg.address),
device=device,
beatBytes=beatBytes,
executable=true
)
val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL()))
// If we want to support custom registers read through Abstract Commands,
// provide a place to bring them into the debug module. What this connects
// to is up to the implementation.
val customNode = new DebugCustomSink()
lazy val module = new Impl
class Impl extends LazyModuleImp(this){
val nComponents = getNComponents()
Annotated.params(this, cfg)
val supportHartArray = cfg.supportHartArray & (nComponents > 1)
val nExtTriggers = cfg.nExtTriggers
val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups
else 0 // no halt groups possible if single hart with no external triggers
val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs(
hartIdToHartSel = (x) => 0.U,
hartSelToHartId = (x) => x
)
val io = IO(new Bundle {
/** dm reset signal passed in from Outer */
val dmactive = Input(Bool())
/** conrol signals for Inner
*
* it's generated by Outer and comes in
*/
val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents)))
/** debug unavail signal passed in from Outer*/
val debugUnavail = Input(Vec(nComponents, Bool()))
/** debug interruption from Inner to Outer
*
* contain 2 type of debug interruption causes:
* - halt group
* - halt-on-reset
*/
val hgDebugInt = Output(Vec(nComponents, Bool()))
/** interface for trigger */
val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(nComponents, Bool()))
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
/** Debug Authentication signals from core */
val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO())
})
sb2tlOpt.map { sb =>
sb.module.clock := io.tl_clock
sb.module.reset := io.tl_reset
sb.module.rf_reset := io.tl_reset
}
//--------------------------------------------------------------
// Import constants for shorter variable names
//--------------------------------------------------------------
import DMI_RegAddrs._
import DsbRegAddrs._
import DsbBusConsts._
//--------------------------------------------------------------
// Sanity Check Configuration For this implementation.
//--------------------------------------------------------------
require (cfg.supportQuickAccess == false, "No Quick Access support yet")
require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group")
//--------------------------------------------------------------
// Register & Wire Declarations (which need to be pre-declared)
//--------------------------------------------------------------
// run control regs: tracking all the harts
// implements: see implementation-specific bits part
/** all harts halted status */
val haltedBitRegs = Reg(UInt(nComponents.W))
/** all harts resume request status */
val resumeReqRegs = Reg(UInt(nComponents.W))
/** all harts have reset status */
val haveResetBitRegs = Reg(UInt(nComponents.W))
// default is 1,after resume, resumeAcks get 0
/** all harts resume ack status */
val resumeAcks = Wire(UInt(nComponents.W))
// --- regmapper outputs
// hart state Id and En
// in Hart Bus Access ROM
val hartHaltedWrEn = Wire(Bool())
val hartHaltedId = Wire(UInt(sbIdWidth.W))
val hartGoingWrEn = Wire(Bool())
val hartGoingId = Wire(UInt(sbIdWidth.W))
val hartResumingWrEn = Wire(Bool())
val hartResumingId = Wire(UInt(sbIdWidth.W))
val hartExceptionWrEn = Wire(Bool())
val hartExceptionId = Wire(UInt(sbIdWidth.W))
// progbuf and abstract data: byte-addressable control logic
// AccessLegal is set only when state = waiting
// RdEn and WrEnMaybe : contrl signal drived by DMI bus
val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
val dmiProgramBufferAccessLegal = WireInit(false.B)
val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
val dmiAbstractDataAccessLegal = WireInit(false.B)
val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
//--------------------------------------------------------------
// Registers coming from 'CONTROL' in Outer
//--------------------------------------------------------------
val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B)
val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W))
// hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true
val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
if (nComponents > 1) {
when (~io.dmactive) {
selectedHartReg := 0.U
}.elsewhen (io.innerCtrl.fire){
selectedHartReg := io.innerCtrl.bits.hartsel
}
}
if (supportHartArray) {
val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
val hamaskReg = Reg(Vec(nComponents, Bool()))
when (~io.dmactive || ~dmAuthenticated) {
hamaskReg := hamaskZero
}.elsewhen (io.innerCtrl.fire){
hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero)
}
hamaskFull := hamaskReg
}
// Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello,
// so append it here
when (selectedHartReg < nComponents.U) {
hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B
}
io.innerCtrl.ready := true.B
// Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write
// A hart may be selected by hartsel field or by hart array
val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
for (component <- 0 until nComponents ) {
hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) ||
(if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B))
}
//-------------------------------------
// Halt-on-reset logic
// hrmask is set in dmOuter and passed in
// Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set
// Debug interrupt is maintained until the hart enters halted state
//-------------------------------------
val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } ))
val hrDebugInt = Wire(Vec(nComponents, Bool()))
val hrmaskReg = RegInit(hrReset)
val hartIsInResetSync = Wire(Vec(nComponents, Bool()))
for (component <- 0 until nComponents) {
hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component"))
}
when (~io.dmactive || ~dmAuthenticated) {
hrmaskReg := hrReset
}.elsewhen (io.innerCtrl.fire){
hrmaskReg := io.innerCtrl.bits.hrmask
}
withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge
val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } ))
when (~io.dmactive || ~dmAuthenticated) {
hrDebugIntReg := hrReset
}.otherwise {
hrDebugIntReg := hrmaskReg &
(hartIsInResetSync | // set debugInt during reset
(hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts
}
hrDebugInt := hrDebugIntReg
}
//--------------------------------------------------------------
// DMI Registers
//--------------------------------------------------------------
//----DMSTATUS
val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields()))
DMSTATUSRdData.authenticated := dmAuthenticated
DMSTATUSRdData.version := 2.U // Version 0.13
io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy)
val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq
when (dmAuthenticated) {
DMSTATUSRdData.hasresethaltreq := true.B
DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent
// all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array
DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _))
when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false
DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _)
when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set
DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _)
}
}
//TODO
DMSTATUSRdData.confstrptrvalid := false.B
DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B
}
when(~io.dmactive || ~dmAuthenticated) {
haveResetBitRegs := 0.U
}.otherwise {
when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) {
haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt
}.otherwise {
haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt
}
}
//----DMCS2 (Halt Groups)
val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields()))
val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields()))
val hgselectWrEn = WireInit(false.B)
val hgwriteWrEn = WireInit(false.B)
val haltgroupWrEn = WireInit(false.B)
val exttriggerWrEn = WireInit(false.B)
val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup
val hgBits = log2Up(nHaltGroups)
// hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned.
val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W))))
val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil
// assign group index to current seledcted harts
for (component <- 0 until nComponents) {
when (~io.dmactive || ~dmAuthenticated) {
hgParticipateHart(component) := 0.U
}.otherwise {
when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect &
hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {
hgParticipateHart(component) := DMCS2WrData.haltgroup
}
}
}
DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
if (nExtTriggers > 0) {
val hgSelect = Reg(Bool())
when (~io.dmactive || ~dmAuthenticated) {
hgSelect := false.B
}.otherwise {
when (hgselectWrEn) {
hgSelect := DMCS2WrData.hgselect
}
}
// assign group index to trigger
for (trigger <- 0 until nExtTriggers) {
when (~io.dmactive || ~dmAuthenticated) {
hgParticipateTrig(trigger) := 0.U
}.otherwise {
when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect &
(DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {
hgParticipateTrig(trigger) := DMCS2WrData.haltgroup
}
}
}
DMCS2RdData.hgselect := hgSelect
when (hgSelect) {
DMCS2RdData.haltgroup := hgParticipateTrig(0)
}
// If there is only 1 ext trigger, then the exttrigger field is fixed at 0
// Otherwise, instantiate a register with only the number of bits required
if (nExtTriggers > 1) {
val trigBits = log2Up(nExtTriggers-1)
val hgExtTrigger = Reg(UInt(trigBits.W))
when (~io.dmactive || ~dmAuthenticated) {
hgExtTrigger := 0.U
}.otherwise {
when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) {
hgExtTrigger := DMCS2WrData.exttrigger
}
}
DMCS2RdData.exttrigger := hgExtTrigger
when (hgSelect) {
DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger)
}
}
}
// Halt group state machine
// IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0
// or when any trigin assigned to this hg occurs
// FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs
// and all trig out in this hg have been acknowledged
val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} ))
val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting
val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in
val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted
val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked
io.extTrigger.foreach {extTrigger =>
val extTriggerInReq = Wire(Vec(nExtTriggers, Bool()))
val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool()))
extTriggerInReq := extTrigger.in.req.asBools
extTriggerOutAck := extTrigger.out.ack.asBools
val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync"))
val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync"))
for (hg <- 1 to nHaltGroups) {
hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _)
hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _)
}
extTrigger.in.ack := trigInReq.asUInt
}
for (hg <- 1 to nHaltGroups) {
hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U)
hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _)
when (~io.dmactive || ~dmAuthenticated) {
hgFired(hg) := false.B
}.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) {
hgFired(hg) := true.B
}.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) {
hgFired(hg) := false.B
}
}
// For each hg that has fired, assert debug interrupt to each hart in that hg
for (component <- 0 until nComponents) {
hgDebugInt(component) := hgFired(hgParticipateHart(component))
}
// For each hg that has fired, assert trigger out for all external triggers in that hg
io.extTrigger.foreach {extTrigger =>
val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} ))
for (trig <- 0 until nExtTriggers) {
extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig))
}
extTrigger.out.req := extTriggerOutReq.asUInt
}
}
io.hgDebugInt := hgDebugInt | hrDebugInt
//----HALTSUM*
val numHaltedStatus = ((nComponents - 1) / 32) + 1
val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W)))
for (ii <- 0 until numHaltedStatus) {
when (dmAuthenticated) {
haltedStatus(ii) := haltedBitRegs >> (ii*32)
}.otherwise {
haltedStatus(ii) := 0.U
}
}
val haltedSummary = Cat(haltedStatus.map(_.orR).reverse)
val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields())
val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5))
val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields())
// Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3
//----ABSTRACTCS
val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))
ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U
ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U
val ABSTRACTCSReg = Reg(new ABSTRACTCSFields())
val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))
val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg)
val ABSTRACTCSRdEn = WireInit(false.B)
val ABSTRACTCSWrEnMaybe = WireInit(false.B)
val ABSTRACTCSWrEnLegal = WireInit(false.B)
val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal
// multiple error types
// find implement in the state machine part
val errorBusy = WireInit(false.B)
val errorException = WireInit(false.B)
val errorUnsupported = WireInit(false.B)
val errorHaltResume = WireInit(false.B)
when (~io.dmactive || ~dmAuthenticated) {
ABSTRACTCSReg := ABSTRACTCSReset
}.otherwise {
when (errorBusy){
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U
}.elsewhen (errorException) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U
}.elsewhen (errorUnsupported) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U
}.elsewhen (errorHaltResume) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U
}.otherwise {
//W1C
when (ABSTRACTCSWrEn){
ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr);
}
}
}
// For busy, see below state machine.
val abstractCommandBusy = WireInit(true.B)
ABSTRACTCSRdData.busy := abstractCommandBusy
when (~dmAuthenticated) { // read value must be 0 when not authenticated
ABSTRACTCSRdData.datacount := 0.U
ABSTRACTCSRdData.progbufsize := 0.U
}
//---- ABSTRACTAUTO
// It is a mask indicating whether datai/probufi have the autoexcution permisson
// this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec
// first two specify which reg supports autoexec
// autoexec is a control signal, meaning there is at least one enabled autoexec reg
// when autoexec is set, generate instructions using COMMAND register
val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))
val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields())
val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))
val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg)
val ABSTRACTAUTORdEn = WireInit(false.B)
val autoexecdataWrEnMaybe = WireInit(false.B)
val autoexecprogbufWrEnMaybe = WireInit(false.B)
val ABSTRACTAUTOWrEnLegal = WireInit(false.B)
when (~io.dmactive || ~dmAuthenticated) {
ABSTRACTAUTOReg := ABSTRACTAUTOReset
}.otherwise {
when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) {
ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U
}
when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) {
ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U
}
}
// Abstract Data access vector(byte-addressable)
val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w}
// Program Buffer access vector(byte-addressable)
val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w}
// at least one word access
val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ )
val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _)
// This will take the shorter of the lists, which is what we want.
val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} ))
val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} ))
(autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 }
(autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2}
val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _)
//---- COMMAND
val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields()))
val COMMANDReg = Reg(new COMMANDFields())
val COMMANDWrDataVal = WireInit(0.U(32.W))
val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields()))
val COMMANDWrEnMaybe = WireInit(false.B)
val COMMANDWrEnLegal = WireInit(false.B)
val COMMANDRdEn = WireInit(false.B)
val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal
val COMMANDRdData = COMMANDReg
when (~io.dmactive || ~dmAuthenticated) {
COMMANDReg := COMMANDReset
}.otherwise {
when (COMMANDWrEn) {
COMMANDReg := COMMANDWrData
}
}
// --- Abstract Data
// These are byte addressible, s.t. the Processor can use
// byte-addressible instructions to store to them.
val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W)))
val abstractDataNxt = WireInit(abstractDataMem)
// --- Program Buffer
// byte-addressible mem
val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W)))
val programBufferNxt = WireInit(programBufferMem)
//--------------------------------------------------------------
// These bits are implementation-specific bits set
// by harts executing code.
//--------------------------------------------------------------
// Run control logic
when (~io.dmactive || ~dmAuthenticated) {
haltedBitRegs := 0.U
resumeReqRegs := 0.U
}.otherwise {
//remove those harts in reset
resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt)
val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId))
val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId))
val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel)
when (hartHaltedWrEn) {
// add those harts halting and remove those in reset
haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt)
}.elsewhen (hartResumingWrEn) {
// remove those harts in reset and those in resume
haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)
}.otherwise {
// remove those harts in reset
haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt)
}
when (hartResumingWrEn) {
// remove those harts in resume and those in reset
resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)
}
when (resumereq) {
// set all sleceted harts to resumeReq, remove those in reset
resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt)
}
}
when (resumereq) {
// next cycle resumeAcls will be the negation of next cycle resumeReqRegs
resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt))
}.otherwise {
resumeAcks := ~resumeReqRegs
}
//---- AUTHDATA
val authRdEnMaybe = WireInit(false.B)
val authWrEnMaybe = WireInit(false.B)
io.auth.map { a =>
a.dmactive := io.dmactive
a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy
a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy
}
val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq(
RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))),
RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))),
RegField(2),
RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0)))
))
val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq(
WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn,
RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)),
WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn,
RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)),
WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn,
RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)),
if (nExtTriggers > 1)
WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn,
RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true))
else RegField(4)
))
val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq(
RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))),
RegField(4),
WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe,
RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),
RegField(1),
RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))),
RegField(11),
RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords)))
))
val (sbcsFields, sbAddrFields, sbDataFields):
(Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl =>
SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p)
}.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField])))
//--------------------------------------------------------------
// Program Buffer Access (DMI ... System Bus can override)
//--------------------------------------------------------------
val omRegMap = dmiNode.regmap(
(DMI_DMSTATUS << 2) -> dmstatusRegFields,
//TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields,
(DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil),
(DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"),
Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))),
(DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"),
Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))),
(DMI_ABSTRACTCS << 2) -> abstractcsRegFields,
(DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq(
WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe,
RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))),
RegField(16-cfg.nAbstractDataWords),
WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe,
RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))),
(DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"),
Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe,
Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))),
(DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) =>
RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i),
dmiAbstractDataRdEn(i),
dmiAbstractDataWrEnMaybe(i),
Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false),
(DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) =>
RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i),
dmiProgramBufferRdEn(i),
dmiProgramBufferWrEnMaybe(i),
Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false),
(DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"),
Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe,
Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil),
(DMI_SBCS << 2) -> sbcsFields,
(DMI_SBDATA0 << 2) -> sbDataFields(0),
(DMI_SBDATA1 << 2) -> sbDataFields(1),
(DMI_SBDATA2 << 2) -> sbDataFields(2),
(DMI_SBDATA3 << 2) -> sbDataFields(3),
(DMI_SBADDRESS0 << 2) -> sbAddrFields(0),
(DMI_SBADDRESS1 << 2) -> sbAddrFields(1),
(DMI_SBADDRESS2 << 2) -> sbAddrFields(2),
(DMI_SBADDRESS3 << 2) -> sbAddrFields(3)
)
// Abstract data mem is written by both the tile link interface and DMI...
abstractDataMem.zipWithIndex.foreach { case (x, i) =>
when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) {
x := abstractDataNxt(i)
}
}
// ... and also by custom register read (if implemented)
val (customs, customParams) = customNode.in.unzip
val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0)
def getNeedCustom = () => needCustom
if (needCustom) {
val (custom, customP) = customNode.in.head
require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}")
val custom_data = custom.data.asBools
val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt}
when (custom.ready && custom.valid) {
(abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) =>
a := b
}
}
}
programBufferMem.zipWithIndex.foreach { case (x, i) =>
when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) {
x := programBufferNxt(i)
}
}
//--------------------------------------------------------------
// "Variable" ROM Generation
//--------------------------------------------------------------
val goReg = Reg(Bool())
val goAbstract = WireInit(false.B)
val goCustom = WireInit(false.B)
val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ()))
jalAbstract.setImm(ABSTRACT(cfg) - WHERETO)
when (~io.dmactive){
goReg := false.B
}.otherwise {
when (goAbstract) {
goReg := true.B
}.elsewhen (hartGoingWrEn){
assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U)
goReg := false.B
}
}
class flagBundle extends Bundle {
val reserved = UInt(6.W)
val resume = Bool()
val go = Bool()
}
val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} ))
assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U),
s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.")
flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg
for (component <- 0 until nComponents) {
val componentSel = WireInit(component.U)
flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component)
}
//----------------------------
// Abstract Command Decoding & Generation
//----------------------------
val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields()))
/** real COMMAND*/
val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields()))
// TODO: Quick Access
class GeneratedI extends Bundle {
val imm = UInt(12.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedS extends Bundle {
val immhi = UInt(7.W)
val rs2 = UInt(5.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val immlo = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedCSR extends Bundle {
val imm = UInt(12.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedUJ extends Bundle {
val imm3 = UInt(1.W)
val imm0 = UInt(10.W)
val imm1 = UInt(1.W)
val imm2 = UInt(8.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
def setImm(imm: Int) : Unit = {
// TODO: Check bounds of imm.
require(imm % 2 == 0, "Immediate must be even for UJ encoding.")
val immWire = WireInit(imm.S(21.W))
val immBits = WireInit(VecInit(immWire.asBools))
imm0 := immBits.slice(1, 1 + 10).asUInt
imm1 := immBits.slice(11, 11 + 11).asUInt
imm2 := immBits.slice(12, 12 + 8).asUInt
imm3 := immBits.slice(20, 20 + 1).asUInt
}
}
require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5),
"Mismatch between DebugModuleParams atzero and nAbstractInstructions")
val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W))))
def abstractGeneratedI(cfg: DebugModuleParams): UInt = {
val inst = Wire(new GeneratedI())
val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF
val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)
inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode
inst.rd := (accessRegisterCommandReg.regno & 0x1F.U)
inst.funct3 := accessRegisterCommandReg.size
inst.rs1 := base
inst.imm := offset.U
inst.asUInt
}
def abstractGeneratedS(cfg: DebugModuleParams): UInt = {
val inst = Wire(new GeneratedS())
val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF
val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)
inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode
inst.immlo := (offset & 0x1F).U
inst.funct3 := accessRegisterCommandReg.size
inst.rs1 := base
inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U)
inst.immhi := (offset >> 5).U
inst.asUInt
}
def abstractGeneratedCSR: UInt = {
val inst = Wire(new GeneratedCSR())
val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs
inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR()))
inst.imm := CSRs.dscratch1.U
inst.rs1 := base
inst.rd := base
inst.asUInt
}
val nop = Wire(new GeneratedI())
nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI())
nop.rd := 0.U
nop.rs1 := 0.U
nop.imm := 0.U
val isa = Wire(new GeneratedI())
isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI())
isa.rd := 0.U
isa.rs1 := 0.U
isa.imm := 0.U
when (goAbstract) {
if (cfg.nAbstractInstructions == 2) {
// ABSTRACT(0): Transfer: LW or SW, else NOP
// ABSTRACT(1): Postexec: NOP else EBREAK
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),
nop.asUInt
)
abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec,
nop.asUInt,
Instructions.EBREAK.value.U)
} else {
// Entry: All regs in GPRs, dscratch1=offset 0x800 in DM
// ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64)
// ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0
// ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP
// ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0
// ABSTRACT(4): Postexec: NOP else EBREAK
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt)
abstractGeneratedMem(1) := abstractGeneratedCSR
abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),
nop.asUInt
)
abstractGeneratedMem(3) := abstractGeneratedCSR
abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec,
nop.asUInt,
Instructions.EBREAK.value.U)
}
}
//--------------------------------------------------------------
// Drive Custom Access
//--------------------------------------------------------------
if (needCustom) {
val (custom, customP) = customNode.in.head
custom.addr := accessRegisterCommandReg.regno
custom.valid := goCustom
}
//--------------------------------------------------------------
// Hart Bus Access
//--------------------------------------------------------------
tlNode.regmap(
// This memory is writable.
HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn,
"debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")),
GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn,
"debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")),
RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn,
"debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")),
EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn,
"debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")),
DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"),
abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}),
PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"),
programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}),
// These sections are read-only.
IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U,
RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil},
WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))),
ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"),
abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}),
FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"),
if (nComponents == 1) {
Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) }
} else {
flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))}
}),
ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"),
(if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) =>
RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
)
// Override System Bus accesses with dmactive reset.
when (~io.dmactive){
abstractDataMem.foreach {x => x := 0.U}
programBufferMem.foreach {x => x := 0.U}
}
//--------------------------------------------------------------
// Abstract Command State Machine
//--------------------------------------------------------------
object CtrlState extends scala.Enumeration {
type CtrlState = Value
val Waiting, CheckGenerate, Exec, Custom = Value
def apply( t : Value) : UInt = {
t.id.U(log2Up(values.size).W)
}
}
import CtrlState._
// This is not an initialization!
val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting)))
val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
val ctrlStateNxt = WireInit(ctrlStateReg)
//------------------------
// DMI Register Control and Status
abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting))
ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting))
dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting))
errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) ||
(autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||
(autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||
(COMMANDWrEnMaybe && ~COMMANDWrEnLegal) ||
(dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) ||
(dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal)
// TODO: Maybe Quick Access
val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)
val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)
val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister
val commandRegIsUnsupported = WireInit(true.B)
val commandRegBadHaltResume = WireInit(false.B)
// We only support abstract commands for GPRs and any custom registers, if specified.
val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U)
val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize
val accessRegIsCustom = if (needCustom) {
val (custom, customP) = customNode.in.head
customP.addrs.foldLeft(false.B){
(result, current) => result || (current.U === accessRegisterCommandReg.regno)}
} else false.B
when (commandRegIsAccessRegister) {
when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) {
commandRegIsUnsupported := false.B
}.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) {
commandRegIsUnsupported := false.B
commandRegBadHaltResume := ~hartHalted
}
}
val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)
val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)
//------------------------
// Variable ROM STATE MACHINE
// -----------------------
when (ctrlStateReg === CtrlState(Waiting)){
when (wrAccessRegisterCommand || regAccessRegisterCommand) {
ctrlStateNxt := CtrlState(CheckGenerate)
}.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type.
errorUnsupported := true.B
}.elsewhen (autoexec && commandRegIsUnsupported) {
errorUnsupported := true.B
}
}.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){
// We use this state to ensure that the COMMAND has been
// registered by the time that we need to use it, to avoid
// generating it directly from the COMMANDWrData.
// This 'commandRegIsUnsupported' is really just checking the
// AccessRegisterCommand parameters (regno)
when (commandRegIsUnsupported) {
errorUnsupported := true.B
ctrlStateNxt := CtrlState(Waiting)
}.elsewhen (commandRegBadHaltResume){
errorHaltResume := true.B
ctrlStateNxt := CtrlState(Waiting)
}.otherwise {
when(accessRegIsCustom) {
ctrlStateNxt := CtrlState(Custom)
}.otherwise {
ctrlStateNxt := CtrlState(Exec)
goAbstract := true.B
}
}
}.elsewhen (ctrlStateReg === CtrlState(Exec)) {
// We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
ctrlStateNxt := CtrlState(Waiting)
}
when(hartExceptionWrEn) {
assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U)
ctrlStateNxt := CtrlState(Waiting)
errorException := true.B
}
}.elsewhen (ctrlStateReg === CtrlState(Custom)) {
assert(needCustom.B, "Should not be in custom state unless we need it.")
goCustom := true.B
val (custom, customP) = customNode.in.head
when (custom.ready && custom.valid) {
ctrlStateNxt := CtrlState(Waiting)
}
}
when (~io.dmactive || ~dmAuthenticated) {
ctrlStateReg := CtrlState(Waiting)
}.otherwise {
ctrlStateReg := ctrlStateNxt
}
assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),
"Unexpected EXCEPTION write: should only get it in Debug Module EXEC state")
}
}
// Wrapper around TL Debug Module Inner and an Async DMI Sink interface.
// Handles the synchronization of dmactive, which is used as a synchronous reset
// inside the Inner block.
// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.
class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{
val cfg = p(DebugModuleKey).get
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes))
val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))
val dmiNode = dmiXing.node
val tlNode = dmInner.tlNode
dmInner.dmiNode := dmiXing.node
// Require that there are no registers in TL interface, so that spurious
// processor accesses to the DM don't need to enable the clock. We don't
// require this property of the SBA, because the debugger is responsible for
// raising dmactive (hence enabling the clock) during these transactions.
require(dmInner.tlNode.concurrency == 0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
// Clock/reset domains:
// debug_clock / debug_reset = Debug inner domain
// tl_clock / tl_reset = tilelink domain (External: clock / reset)
//
val io = IO(new Bundle {
val debug_clock = Input(Clock())
val debug_reset = Input(Reset())
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
// These are all asynchronous and come from Outer
/** reset signal for DM */
val dmactive = Input(Bool())
/** conrol signals for Inner
*
* generated in Outer
*/
val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))
// This comes from tlClk domain.
/** debug available status */
val debugUnavail = Input(Vec(getNComponents(), Bool()))
/** debug interruption*/
val hgDebugInt = Output(Vec(getNComponents(), Bool()))
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(getNComponents(), Bool()))
/** Debug Authentication signals from core */
val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())
})
val rf_reset = IO(Input(Reset())) // RF transform
childClock := io.debug_clock
childReset := io.debug_reset
override def provideImplicitClockToLazyChildren = true
val dmactive_synced = withClockAndReset(childClock, childReset) {
val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync"))
dmInner.module.clock := io.debug_clock
dmInner.module.reset := io.debug_reset
dmInner.module.io.tl_clock := io.tl_clock
dmInner.module.io.tl_reset := io.tl_reset
dmInner.module.io.dmactive := dmactive_synced
dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl)
dmInner.module.io.debugUnavail := io.debugUnavail
io.hgDebugInt := dmInner.module.io.hgDebugInt
io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}
dmInner.module.io.hartIsInReset := io.hartIsInReset
io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
dmactive_synced
}
}
}
/** Create a version of the TLDebugModule which includes a synchronization interface
* internally for the DMI. This is no longer optional outside of this module
* because the Clock must run when tl_clock isn't running or tl_reset is asserted.
*/
class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val attach = Map(
"debug-attach" -> (
(if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++
(if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++
(if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++
(if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq())))
Description(name, mapping ++ attach)
}
}
val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p))
val node = dmInner.tlNode
val intnode = dmOuter.intnode
val apbNodeOpt = dmOuter.apbNodeOpt
dmInner.dmiNode := dmOuter.dmiInnerNode
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val nComponents = dmOuter.dmOuter.intnode.edges.out.size
// Clock/reset domains:
// tl_clock / tl_reset = tilelink domain
// debug_clock / debug_reset = Inner debug (synchronous to tl_clock)
// apb_clock / apb_reset = Outer debug with APB
// dmiClock / dmiReset = Outer debug without APB
//
val io = IO(new Bundle {
val debug_clock = Input(Clock())
val debug_reset = Input(Reset())
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
/** Debug control signals generated in Outer */
val ctrl = new DebugCtrlBundle(nComponents)
/** Debug Module Interface bewteen DM and DTM
*
* The DTM provides access to one or more Debug Modules (DMs) using DMI
*/
val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO()))
val apb_clock = p(ExportDebug).apb.option(Input(Clock()))
val apb_reset = p(ExportDebug).apb.option(Input(Reset()))
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(nComponents, Bool()))
/** hart reset request generated by hartreset-logic in Outer */
val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** Debug Authentication signals from core */
val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())
})
childClock := io.tl_clock
childReset := io.tl_reset
override def provideImplicitClockToLazyChildren = true
dmOuter.module.io.dmi.foreach { dmOuterDMI =>
dmOuterDMI <> io.dmi.get.dmi
dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset
dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock
dmOuter.module.rf_reset := io.dmi.get.dmiReset
}
(io.apb_clock zip io.apb_reset) foreach { case (c, r) =>
dmOuter.module.io.dmi_reset := r
dmOuter.module.io.dmi_clock := c
dmOuter.module.rf_reset := r
}
dmInner.module.rf_reset := io.debug_reset
dmInner.module.io.debug_clock := io.debug_clock
dmInner.module.io.debug_reset := io.debug_reset
dmInner.module.io.tl_clock := io.tl_clock
dmInner.module.io.tl_reset := io.tl_reset
dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt
io.ctrl <> dmOuter.module.io.ctrl
io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}
dmInner.module.io.hartIsInReset := io.hartIsInReset
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated }
io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File SBA.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug.systembusaccess
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.{AMBAProt, AMBAProtField}
import freechips.rocketchip.devices.debug.{DebugModuleKey, RWNotify, SBCSFields, WNotifyVal}
import freechips.rocketchip.diplomacy.TransferSizes
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType}
import freechips.rocketchip.tilelink.{TLClientNode, TLMasterParameters, TLMasterPortParameters}
import freechips.rocketchip.util.property
object SystemBusAccessState extends scala.Enumeration {
type SystemBusAccessState = Value
val Idle, SBReadRequest, SBWriteRequest, SBReadResponse, SBWriteResponse = Value
}
object SBErrorCode extends scala.Enumeration {
type SBErrorCode = Value
val NoError = Value(0)
val Timeout = Value(1)
val BadAddr = Value(2)
val AlgnError = Value(3)
val BadAccess = Value(4)
val OtherError = Value(7)
}
object SystemBusAccessModule
{
def apply(sb2tl: SBToTL, dmactive: Bool, dmAuthenticated: Bool)(implicit p: Parameters):
(Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) =
{
import SBErrorCode._
val cfg = p(DebugModuleKey).get
val anyAddressWrEn = WireInit(false.B).suggestName("anyAddressWrEn")
val anyDataRdEn = WireInit(false.B).suggestName("anyDataRdEn")
val anyDataWrEn = WireInit(false.B).suggestName("anyDataWrEn")
// --- SBCS Status Register ---
val SBCSFieldsReg = Reg(new SBCSFields()).suggestName("SBCSFieldsReg")
val SBCSFieldsRegReset = WireInit(0.U.asTypeOf(new SBCSFields()))
SBCSFieldsRegReset.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018
SBCSFieldsRegReset.sbbusy := (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U)
SBCSFieldsRegReset.sbaccess := 2.U
SBCSFieldsRegReset.sbasize := sb2tl.module.edge.bundle.addressBits.U
SBCSFieldsRegReset.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B
SBCSFieldsRegReset.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B
SBCSFieldsRegReset.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B
SBCSFieldsRegReset.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B
SBCSFieldsRegReset.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B
val SBCSRdData = WireInit(0.U.asTypeOf(new SBCSFields())).suggestName("SBCSRdData")
val SBCSWrDataVal = WireInit(0.U(32.W))
val SBCSWrData = WireInit(SBCSWrDataVal.asTypeOf(new SBCSFields()))
val sberrorWrEn = WireInit(false.B)
val sbreadondataWrEn = WireInit(false.B)
val sbautoincrementWrEn= WireInit(false.B)
val sbaccessWrEn = WireInit(false.B)
val sbreadonaddrWrEn = WireInit(false.B)
val sbbusyerrorWrEn = WireInit(false.B)
val sbcsfields = RegFieldGroup("sbcs", Some("system bus access control and status"), Seq(
RegField.r(1, SBCSRdData.sbaccess8, RegFieldDesc("sbaccess8", "8-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 8) 1 else 0))),
RegField.r(1, SBCSRdData.sbaccess16, RegFieldDesc("sbaccess16", "16-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 16) 1 else 0))),
RegField.r(1, SBCSRdData.sbaccess32, RegFieldDesc("sbaccess32", "32-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 32) 1 else 0))),
RegField.r(1, SBCSRdData.sbaccess64, RegFieldDesc("sbaccess64", "64-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess >= 64) 1 else 0))),
RegField.r(1, SBCSRdData.sbaccess128, RegFieldDesc("sbaccess128", "128-bit accesses supported", reset=Some(if (cfg.maxSupportedSBAccess == 128) 1 else 0))),
RegField.r(7, SBCSRdData.sbasize, RegFieldDesc("sbasize", "bits in address", reset=Some(sb2tl.module.edge.bundle.addressBits))),
WNotifyVal(3, SBCSRdData.sberror, SBCSWrData.sberror, sberrorWrEn,
RegFieldDesc("sberror", "system bus error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),
WNotifyVal(1, SBCSRdData.sbreadondata, SBCSWrData.sbreadondata, sbreadondataWrEn,
RegFieldDesc("sbreadondata", "system bus read on data", reset=Some(0))),
WNotifyVal(1, SBCSRdData.sbautoincrement, SBCSWrData.sbautoincrement, sbautoincrementWrEn,
RegFieldDesc("sbautoincrement", "system bus auto-increment address", reset=Some(0))),
WNotifyVal(3, SBCSRdData.sbaccess, SBCSWrData.sbaccess, sbaccessWrEn,
RegFieldDesc("sbaccess", "system bus access size", reset=Some(2))),
WNotifyVal(1, SBCSRdData.sbreadonaddr, SBCSWrData.sbreadonaddr, sbreadonaddrWrEn,
RegFieldDesc("sbreadonaddr", "system bus read on data", reset=Some(0))),
RegField.r(1, SBCSRdData.sbbusy, RegFieldDesc("sbbusy", "system bus access is busy", reset=Some(0))),
WNotifyVal(1, SBCSRdData.sbbusyerror, SBCSWrData.sbbusyerror, sbbusyerrorWrEn,
RegFieldDesc("sbbusyerror", "system bus busy error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),
RegField(6),
RegField.r(3, SBCSRdData.sbversion, RegFieldDesc("sbversion", "system bus access version", reset=Some(1))),
))
// --- System Bus Address Registers ---
// ADDR0 Register is required
// Instantiate ADDR1-3 registers as needed depending on system bus address width
val hasSBAddr1 = (sb2tl.module.edge.bundle.addressBits >= 33)
val hasSBAddr2 = (sb2tl.module.edge.bundle.addressBits >= 65)
val hasSBAddr3 = (sb2tl.module.edge.bundle.addressBits >= 97)
val hasAddr = Seq(true, hasSBAddr1, hasSBAddr2, hasSBAddr3)
val SBADDRESSFieldsReg = Reg(Vec(4, UInt(32.W)))
SBADDRESSFieldsReg.zipWithIndex.foreach { case(a,i) => a.suggestName("SBADDRESS"+i+"FieldsReg")}
val SBADDRESSWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} ))
val SBADDRESSRdEn = WireInit(VecInit(Seq.fill(4) {false.B} ))
val SBADDRESSWrEn = WireInit(VecInit(Seq.fill(4) {false.B} ))
val autoIncrementedAddr = WireInit(0.U(128.W))
autoIncrementedAddr := Cat(SBADDRESSFieldsReg.reverse) + (1.U << SBCSFieldsReg.sbaccess)
autoIncrementedAddr.suggestName("autoIncrementedAddr")
val sbaddrfields: Seq[Seq[RegField]] = SBADDRESSFieldsReg.zipWithIndex.map { case(a,i) =>
if(hasAddr(i)) {
when (~dmactive || ~dmAuthenticated) {
a := 0.U(32.W)
}.otherwise {
a := Mux(SBADDRESSWrEn(i) && !SBCSRdData.sberror && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror, SBADDRESSWrData(i),
Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && SBCSFieldsReg.sbautoincrement, autoIncrementedAddr(32*i+31,32*i), a))
}
RegFieldGroup("dmi_sbaddr"+i, Some("SBA Address Register"), Seq(RWNotify(32, a, SBADDRESSWrData(i), SBADDRESSRdEn(i), SBADDRESSWrEn(i),
Some(RegFieldDesc("dmi_sbaddr"+i, "SBA address register", reset=Some(0), volatile=true)))))
} else {
a := DontCare
Seq.empty[RegField]
}
}
sb2tl.module.io.addrIn := Mux(SBADDRESSWrEn(0),
Cat(Cat(SBADDRESSFieldsReg.drop(1).reverse), SBADDRESSWrData(0)),
Cat(SBADDRESSFieldsReg.reverse))
anyAddressWrEn := SBADDRESSWrEn.reduce(_ || _)
// --- System Bus Data Registers ---
// DATA0 Register is required
// DATA1-3 Registers may not be needed depending on implementation
val hasSBData1 = (cfg.maxSupportedSBAccess > 32)
val hasSBData2And3 = (cfg.maxSupportedSBAccess == 128)
val hasData = Seq(true, hasSBData1, hasSBData2And3, hasSBData2And3)
val SBDATAFieldsReg = Reg(Vec(4, Vec(4, UInt(8.W))))
SBDATAFieldsReg.zipWithIndex.foreach { case(d,i) => d.zipWithIndex.foreach { case(d,j) => d.suggestName("SBDATA"+i+"BYTE"+j) }}
val SBDATARdData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} ))
SBDATARdData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATARdData"+i) }
val SBDATAWrData = WireInit(VecInit(Seq.fill(4) {0.U(32.W)} ))
SBDATAWrData.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrData"+i) }
val SBDATARdEn = WireInit(VecInit(Seq.fill(4) {false.B} ))
val SBDATAWrEn = WireInit(VecInit(Seq.fill(4) {false.B} ))
SBDATAWrEn.zipWithIndex.foreach { case(d,i) => d.suggestName("SBDATAWrEn"+i) }
val sbdatafields: Seq[Seq[RegField]] = SBDATAFieldsReg.zipWithIndex.map { case(d,i) =>
if(hasData(i)) {
// For data registers, load enable per-byte
for (j <- 0 to 3) {
when (~dmactive || ~dmAuthenticated) {
d(j) := 0.U(8.W)
}.otherwise {
d(j) := Mux(SBDATAWrEn(i) && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror, SBDATAWrData(i)(8*j+7,8*j),
Mux(sb2tl.module.io.rdLoad(4*i+j), sb2tl.module.io.dataOut, d(j)))
}
}
SBDATARdData(i) := Cat(d.reverse)
RegFieldGroup("dmi_sbdata"+i, Some("SBA Data Register"), Seq(RWNotify(32, SBDATARdData(i), SBDATAWrData(i), SBDATARdEn(i), SBDATAWrEn(i),
Some(RegFieldDesc("dmi_sbdata"+i, "SBA data register", reset=Some(0), volatile=true)))))
} else {
for (j <- 0 to 3) { d(j) := DontCare }
Seq.empty[RegField]
}
}
sb2tl.module.io.dataIn := Mux(sb2tl.module.io.wrEn,Cat(SBDATAWrData.reverse),Cat(SBDATAFieldsReg.flatten.reverse))
anyDataRdEn := SBDATARdEn.reduce(_ || _)
anyDataWrEn := SBDATAWrEn.reduce(_ || _)
val tryWrEn = SBDATAWrEn(0)
val tryRdEn = (SBADDRESSWrEn(0) && SBCSFieldsReg.sbreadonaddr) || (SBDATARdEn(0) && SBCSFieldsReg.sbreadondata)
val sbAccessError = (SBCSFieldsReg.sbaccess === 0.U) && (SBCSFieldsReg.sbaccess8 =/= 1.U) ||
(SBCSFieldsReg.sbaccess === 1.U) && (SBCSFieldsReg.sbaccess16 =/= 1.U) ||
(SBCSFieldsReg.sbaccess === 2.U) && (SBCSFieldsReg.sbaccess32 =/= 1.U) ||
(SBCSFieldsReg.sbaccess === 3.U) && (SBCSFieldsReg.sbaccess64 =/= 1.U) ||
(SBCSFieldsReg.sbaccess === 4.U) && (SBCSFieldsReg.sbaccess128 =/= 1.U) || (SBCSFieldsReg.sbaccess > 4.U)
val compareAddr = Wire(UInt(32.W)) // Need use written or latched address to detect error case depending on how transaction is initiated
compareAddr := Mux(SBADDRESSWrEn(0),SBADDRESSWrData(0),SBADDRESSFieldsReg(0))
val sbAlignmentError = (SBCSFieldsReg.sbaccess === 1.U) && (compareAddr(0) =/= 0.U) ||
(SBCSFieldsReg.sbaccess === 2.U) && (compareAddr(1,0) =/= 0.U) ||
(SBCSFieldsReg.sbaccess === 3.U) && (compareAddr(2,0) =/= 0.U) ||
(SBCSFieldsReg.sbaccess === 4.U) && (compareAddr(3,0) =/= 0.U)
sbAccessError.suggestName("sbAccessError")
sbAlignmentError.suggestName("sbAlignmentError")
sb2tl.module.io.wrEn := dmAuthenticated && tryWrEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError
sb2tl.module.io.rdEn := dmAuthenticated && tryRdEn && !SBCSFieldsReg.sbbusy && !SBCSFieldsReg.sbbusyerror && !SBCSRdData.sberror && !sbAccessError && !sbAlignmentError
sb2tl.module.io.sizeIn := SBCSFieldsReg.sbaccess
val sbBusy = (sb2tl.module.io.sbStateOut =/= SystemBusAccessState.Idle.id.U)
when (~dmactive || ~dmAuthenticated) {
SBCSFieldsReg := SBCSFieldsRegReset
}.otherwise {
SBCSFieldsReg.sbbusyerror := Mux(sbbusyerrorWrEn && SBCSWrData.sbbusyerror, false.B, // W1C
Mux(anyAddressWrEn && sbBusy, true.B, // Set if a write to SBADDRESS occurs while busy
Mux((anyDataRdEn || anyDataWrEn) && sbBusy, true.B, SBCSFieldsReg.sbbusyerror))) // Set if any access to SBDATA occurs while busy
SBCSFieldsReg.sbreadonaddr := Mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr , SBCSFieldsReg.sbreadonaddr)
SBCSFieldsReg.sbautoincrement := Mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement)
SBCSFieldsReg.sbreadondata := Mux(sbreadondataWrEn, SBCSWrData.sbreadondata , SBCSFieldsReg.sbreadondata)
SBCSFieldsReg.sbaccess := Mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess)
SBCSFieldsReg.sbversion := 1.U(1.W) // This code implements a version of the spec after January 1, 2018
}
// sbErrorReg has a per-bit load enable since each bit can be individually cleared by writing a 1 to it
val sbErrorReg = Reg(Vec(4, UInt(1.W)))
when(~dmactive || ~dmAuthenticated) {
for (i <- 0 until 3)
sbErrorReg(i) := 0.U
}.otherwise {
for (i <- 0 until 3)
sbErrorReg(i) := Mux(sberrorWrEn && SBCSWrData.sberror(i) === 1.U, NoError.id.U.extract(i), // W1C
Mux((sb2tl.module.io.wrEn && !sb2tl.module.io.wrLegal) || (sb2tl.module.io.rdEn && !sb2tl.module.io.rdLegal), BadAddr.id.U.extract(i), // Bad address accessed
Mux((tryWrEn || tryRdEn) && sbAlignmentError, AlgnError.id.U.extract(i), // Address alignment error
Mux((tryWrEn || tryRdEn) && sbAccessError, BadAccess.id.U.extract(i), // Access size error
Mux((sb2tl.module.io.rdDone || sb2tl.module.io.wrDone) && sb2tl.module.io.respError, OtherError.id.U.extract(i), sbErrorReg(i)))))) // Response error from TL
}
SBCSRdData := SBCSFieldsReg
SBCSRdData.sbasize := sb2tl.module.edge.bundle.addressBits.U
SBCSRdData.sbaccess128 := (cfg.maxSupportedSBAccess == 128).B
SBCSRdData.sbaccess64 := (cfg.maxSupportedSBAccess >= 64).B
SBCSRdData.sbaccess32 := (cfg.maxSupportedSBAccess >= 32).B
SBCSRdData.sbaccess16 := (cfg.maxSupportedSBAccess >= 16).B
SBCSRdData.sbaccess8 := (cfg.maxSupportedSBAccess >= 8).B
SBCSRdData.sbbusy := sbBusy
SBCSRdData.sberror := sbErrorReg.asUInt
when (~dmAuthenticated) { // Read value must be 0 if not authenticated
SBCSRdData := 0.U.asTypeOf(new SBCSFields())
}
property.cover(SBCSFieldsReg.sbbusyerror, "SBCS Cover", "sberror set")
property.cover(SBCSFieldsReg.sbbusy === 3.U, "SBCS Cover", "sbbusyerror alignment error")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 0.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "8-bit access")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 1.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "16-bit access")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 2.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "32-bit access")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 3.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "64-bit access")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess === 4.U && !sbAccessError && !sbAlignmentError, "SBCS Cover", "128-bit access")
property.cover(SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access with autoincrement set")
property.cover(!SBCSFieldsReg.sbautoincrement && SBCSFieldsReg.sbbusy, "SBCS Cover", "Access without autoincrement set")
property.cover((sb2tl.module.io.wrEn || sb2tl.module.io.rdEn) && SBCSFieldsReg.sbaccess > 4.U, "SBCS Cover", "Invalid sbaccess value")
(sbcsfields, sbaddrfields, sbdatafields)
}
}
class SBToTL(implicit p: Parameters) extends LazyModule {
val cfg = p(DebugModuleKey).get
val node = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1("debug")),
requestFields = Seq(AMBAProtField()))))
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val rdEn = Input(Bool())
val wrEn = Input(Bool())
val addrIn = Input(UInt(128.W)) // TODO: Parameterize these widths
val dataIn = Input(UInt(128.W))
val sizeIn = Input(UInt(3.W))
val rdLegal = Output(Bool())
val wrLegal = Output(Bool())
val rdDone = Output(Bool())
val wrDone = Output(Bool())
val respError = Output(Bool())
val dataOut = Output(UInt(8.W))
val rdLoad = Output(Vec(cfg.maxSupportedSBAccess/8, Bool()))
val sbStateOut = Output(UInt(log2Ceil(SystemBusAccessState.maxId).W))
})
val rf_reset = IO(Input(Reset()))
import SystemBusAccessState._
val (tl, edge) = node.out(0)
val sbState = RegInit(0.U)
// --- Drive payloads on bus to TileLink ---
val d = Queue(tl.d, 2) // Add a small buffer since response could arrive on same cycle as request
d.ready := (sbState === SBReadResponse.id.U) || (sbState === SBWriteResponse.id.U)
val muxedData = WireInit(0.U(8.W))
val requestValid = tl.a.valid
val requestReady = tl.a.ready
val responseValid = d.valid
val responseReady = d.ready
val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W))
val vecData = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W)))
vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8*i+7,8*i) }
muxedData := vecData(counter(log2Ceil(vecData.size)-1,0))
// Need an additional check to determine if address is safe for Get/Put
val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8)))
val wrLegal_addr = edge.manager.supportsPutFullSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8)))
val (_, gbits) = edge.Get(0.U, io.addrIn, io.sizeIn)
val (_, pfbits) = edge.Put(0.U, io.addrIn, io.sizeIn, muxedData)
io.rdLegal := rdLegal_addr
io.wrLegal := wrLegal_addr
io.sbStateOut := sbState
when(sbState === SBReadRequest.id.U) { tl.a.bits := gbits }
.otherwise { tl.a.bits := pfbits }
tl.a.bits.user.lift(AMBAProt).foreach { x =>
x.bufferable := false.B
x.modifiable := false.B
x.readalloc := false.B
x.writealloc := false.B
x.privileged := true.B
x.secure := true.B
x.fetch := false.B
}
val respError = d.bits.denied || d.bits.corrupt
io.respError := respError
val wrTxValid = sbState === SBWriteRequest.id.U && requestValid && requestReady
val rdTxValid = sbState === SBReadResponse.id.U && responseValid && responseReady
val txLast = counter === ((1.U << io.sizeIn) - 1.U)
counter := Mux((wrTxValid || rdTxValid) && txLast, 0.U,
Mux((wrTxValid || rdTxValid) , counter+1.U, counter))
for (i <- 0 until (cfg.maxSupportedSBAccess/8)) {
io.rdLoad(i) := rdTxValid && (counter === i.U)
}
// --- State Machine to interface with TileLink ---
when (sbState === Idle.id.U){
sbState := Mux(io.rdEn && io.rdLegal, SBReadRequest.id.U,
Mux(io.wrEn && io.wrLegal, SBWriteRequest.id.U, sbState))
}.elsewhen (sbState === SBReadRequest.id.U){
sbState := Mux(requestValid && requestReady, SBReadResponse.id.U, sbState)
}.elsewhen (sbState === SBWriteRequest.id.U){
sbState := Mux(wrTxValid && txLast, SBWriteResponse.id.U, sbState)
}.elsewhen (sbState === SBReadResponse.id.U){
sbState := Mux(rdTxValid && txLast, Idle.id.U, sbState)
}.elsewhen (sbState === SBWriteResponse.id.U){
sbState := Mux(responseValid && responseReady, Idle.id.U, sbState)
}
io.rdDone := rdTxValid && txLast
io.wrDone := (sbState === SBWriteResponse.id.U) && responseValid && responseReady
io.dataOut := d.bits.data
tl.a.valid := (sbState === SBReadRequest.id.U) || (sbState === SBWriteRequest.id.U)
// Tie off unused channels
tl.b.ready := false.B
tl.c.valid := false.B
tl.e.valid := false.B
assert (sbState === Idle.id.U ||
sbState === SBReadRequest.id.U ||
sbState === SBWriteRequest.id.U ||
sbState === SBReadResponse.id.U ||
sbState === SBWriteResponse.id.U, "SBA state machine in undefined state")
property.cover (sbState === Idle.id.U, "SBA State Cover", "SBA Access Idle")
property.cover (sbState === SBReadRequest.id.U, "SBA State Cover", "SBA Access Read Req")
property.cover (sbState === SBWriteRequest.id.U, "SBA State Cover", "SBA Access Write Req")
property.cover (sbState === SBReadResponse.id.U, "SBA State Cover", "SBA Access Read Resp")
property.cover (sbState === SBWriteResponse.id.U, "SBA State Cover", "SBA Access Write Resp")
property.cover (io.rdEn && !io.rdLegal, "SB Legality Cover", "SBA Rd Address Illegal")
property.cover (io.wrEn && !io.wrLegal, "SB Legality Cover", "SBA Wr Address Illegal")
}
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLDebugModuleInner( // @[Debug.scala:790:9]
input clock, // @[Debug.scala:790:9]
input reset, // @[Debug.scala:790:9]
input auto_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmi_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmi_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dmi_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dmi_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_dmi_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_dmactive, // @[Debug.scala:803:16]
input io_innerCtrl_valid, // @[Debug.scala:803:16]
input io_innerCtrl_bits_resumereq, // @[Debug.scala:803:16]
input [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:803:16]
input io_innerCtrl_bits_ackhavereset, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hasel, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_0, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_1, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_2, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_3, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_4, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_5, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_6, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hamask_7, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_0, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_1, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_2, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_3, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_4, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_5, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_6, // @[Debug.scala:803:16]
input io_innerCtrl_bits_hrmask_7, // @[Debug.scala:803:16]
output io_hgDebugInt_0, // @[Debug.scala:803:16]
output io_hgDebugInt_1, // @[Debug.scala:803:16]
output io_hgDebugInt_2, // @[Debug.scala:803:16]
output io_hgDebugInt_3, // @[Debug.scala:803:16]
output io_hgDebugInt_4, // @[Debug.scala:803:16]
output io_hgDebugInt_5, // @[Debug.scala:803:16]
output io_hgDebugInt_6, // @[Debug.scala:803:16]
output io_hgDebugInt_7, // @[Debug.scala:803:16]
input io_hartIsInReset_0, // @[Debug.scala:803:16]
input io_hartIsInReset_1, // @[Debug.scala:803:16]
input io_hartIsInReset_2, // @[Debug.scala:803:16]
input io_hartIsInReset_3, // @[Debug.scala:803:16]
input io_hartIsInReset_4, // @[Debug.scala:803:16]
input io_hartIsInReset_5, // @[Debug.scala:803:16]
input io_hartIsInReset_6, // @[Debug.scala:803:16]
input io_hartIsInReset_7, // @[Debug.scala:803:16]
input io_tl_clock, // @[Debug.scala:803:16]
input io_tl_reset // @[Debug.scala:803:16]
);
wire out_front_1_valid; // @[RegisterRouter.scala:87:24]
wire out_front_1_ready; // @[RegisterRouter.scala:87:24]
wire out_1_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_1_bits_index; // @[RegisterRouter.scala:73:18]
wire in_1_bits_read; // @[RegisterRouter.scala:73:18]
wire [7:0] _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:71]
wire [2:0] _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:71]
wire [15:0] _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:71]
wire [7:0] _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:74]
wire [2:0] _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:74]
wire [15:0] _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:74]
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [6:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire SBDATAWrEn_0; // @[SBA.scala:150:35]
wire [31:0] SBDATARdData_1; // @[SBA.scala:145:35]
wire [31:0] SBDATARdData_0; // @[SBA.scala:145:35]
wire SBADDRESSWrEn_0; // @[SBA.scala:108:38]
wire [7:0] _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:65]
wire [23:0] _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:65]
wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41]
wire [31:0] _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48]
wire _sb2tlOpt_io_rdLegal; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_wrLegal; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdDone; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_wrDone; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_respError; // @[Debug.scala:782:52]
wire [7:0] _sb2tlOpt_io_dataOut; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_0; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_1; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_2; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_3; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_4; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_5; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_6; // @[Debug.scala:782:52]
wire _sb2tlOpt_io_rdLoad_7; // @[Debug.scala:782:52]
wire [2:0] _sb2tlOpt_io_sbStateOut; // @[Debug.scala:782:52]
wire auto_sb2tlOpt_out_a_ready_0 = auto_sb2tlOpt_out_a_ready; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_valid_0 = auto_sb2tlOpt_out_d_valid; // @[Debug.scala:790:9]
wire [2:0] auto_sb2tlOpt_out_d_bits_opcode_0 = auto_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:790:9]
wire [1:0] auto_sb2tlOpt_out_d_bits_param_0 = auto_sb2tlOpt_out_d_bits_param; // @[Debug.scala:790:9]
wire [3:0] auto_sb2tlOpt_out_d_bits_size_0 = auto_sb2tlOpt_out_d_bits_size; // @[Debug.scala:790:9]
wire [2:0] auto_sb2tlOpt_out_d_bits_sink_0 = auto_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_bits_denied_0 = auto_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:790:9]
wire [7:0] auto_sb2tlOpt_out_d_bits_data_0 = auto_sb2tlOpt_out_d_bits_data; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_bits_corrupt_0 = auto_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:790:9]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[Debug.scala:790:9]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[Debug.scala:790:9]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[Debug.scala:790:9]
wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[Debug.scala:790:9]
wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[Debug.scala:790:9]
wire [11:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[Debug.scala:790:9]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[Debug.scala:790:9]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[Debug.scala:790:9]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[Debug.scala:790:9]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[Debug.scala:790:9]
wire auto_dmi_in_a_valid_0 = auto_dmi_in_a_valid; // @[Debug.scala:790:9]
wire [2:0] auto_dmi_in_a_bits_opcode_0 = auto_dmi_in_a_bits_opcode; // @[Debug.scala:790:9]
wire [2:0] auto_dmi_in_a_bits_param_0 = auto_dmi_in_a_bits_param; // @[Debug.scala:790:9]
wire [1:0] auto_dmi_in_a_bits_size_0 = auto_dmi_in_a_bits_size; // @[Debug.scala:790:9]
wire auto_dmi_in_a_bits_source_0 = auto_dmi_in_a_bits_source; // @[Debug.scala:790:9]
wire [8:0] auto_dmi_in_a_bits_address_0 = auto_dmi_in_a_bits_address; // @[Debug.scala:790:9]
wire [3:0] auto_dmi_in_a_bits_mask_0 = auto_dmi_in_a_bits_mask; // @[Debug.scala:790:9]
wire [31:0] auto_dmi_in_a_bits_data_0 = auto_dmi_in_a_bits_data; // @[Debug.scala:790:9]
wire auto_dmi_in_a_bits_corrupt_0 = auto_dmi_in_a_bits_corrupt; // @[Debug.scala:790:9]
wire auto_dmi_in_d_ready_0 = auto_dmi_in_d_ready; // @[Debug.scala:790:9]
wire io_dmactive_0 = io_dmactive; // @[Debug.scala:790:9]
wire io_innerCtrl_valid_0 = io_innerCtrl_valid; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_resumereq_0 = io_innerCtrl_bits_resumereq; // @[Debug.scala:790:9]
wire [9:0] io_innerCtrl_bits_hartsel_0 = io_innerCtrl_bits_hartsel; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_ackhavereset_0 = io_innerCtrl_bits_ackhavereset; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hasel_0 = io_innerCtrl_bits_hasel; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_0_0 = io_innerCtrl_bits_hamask_0; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_1_0 = io_innerCtrl_bits_hamask_1; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_2_0 = io_innerCtrl_bits_hamask_2; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_3_0 = io_innerCtrl_bits_hamask_3; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_4_0 = io_innerCtrl_bits_hamask_4; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_5_0 = io_innerCtrl_bits_hamask_5; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_6_0 = io_innerCtrl_bits_hamask_6; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hamask_7_0 = io_innerCtrl_bits_hamask_7; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_0_0 = io_innerCtrl_bits_hrmask_0; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_1_0 = io_innerCtrl_bits_hrmask_1; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_2_0 = io_innerCtrl_bits_hrmask_2; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_3_0 = io_innerCtrl_bits_hrmask_3; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_4_0 = io_innerCtrl_bits_hrmask_4; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_5_0 = io_innerCtrl_bits_hrmask_5; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_6_0 = io_innerCtrl_bits_hrmask_6; // @[Debug.scala:790:9]
wire io_innerCtrl_bits_hrmask_7_0 = io_innerCtrl_bits_hrmask_7; // @[Debug.scala:790:9]
wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:790:9]
wire io_hartIsInReset_1_0 = io_hartIsInReset_1; // @[Debug.scala:790:9]
wire io_hartIsInReset_2_0 = io_hartIsInReset_2; // @[Debug.scala:790:9]
wire io_hartIsInReset_3_0 = io_hartIsInReset_3; // @[Debug.scala:790:9]
wire io_hartIsInReset_4_0 = io_hartIsInReset_4; // @[Debug.scala:790:9]
wire io_hartIsInReset_5_0 = io_hartIsInReset_5; // @[Debug.scala:790:9]
wire io_hartIsInReset_6_0 = io_hartIsInReset_6; // @[Debug.scala:790:9]
wire io_hartIsInReset_7_0 = io_hartIsInReset_7; // @[Debug.scala:790:9]
wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:790:9]
wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:790:9]
wire auto_custom_in_addr = 1'h0; // @[Debug.scala:790:9]
wire auto_custom_in_ready = 1'h0; // @[Debug.scala:790:9]
wire auto_custom_in_valid = 1'h0; // @[Debug.scala:790:9]
wire auto_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9]
wire auto_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_bits_sink = 1'h0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_bits_denied = 1'h0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_bits_corrupt = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_1 = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_2 = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_3 = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_4 = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_5 = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_6 = 1'h0; // @[Debug.scala:790:9]
wire io_debugUnavail_7 = 1'h0; // @[Debug.scala:790:9]
wire dmiNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire customNodeIn_addr = 1'h0; // @[MixedNode.scala:551:17]
wire customNodeIn_ready = 1'h0; // @[MixedNode.scala:551:17]
wire customNodeIn_valid = 1'h0; // @[MixedNode.scala:551:17]
wire _dmiProgramBufferRdEn_WIRE_0 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_1 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_2 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_3 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_4 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_5 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_6 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_7 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_8 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_9 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_10 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_11 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_12 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_13 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_14 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_15 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_16 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_17 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_18 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_19 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_20 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_21 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_22 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_23 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_24 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_25 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_26 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_27 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_28 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_29 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_30 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_31 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_32 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_33 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_34 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_35 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_36 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_37 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_38 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_39 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_40 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_41 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_42 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_43 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_44 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_45 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_46 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_47 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_48 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_49 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_50 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_51 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_52 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_53 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_54 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_55 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_56 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_57 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_58 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_59 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_60 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_61 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_62 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferRdEn_WIRE_63 = 1'h0; // @[Debug.scala:887:48]
wire _dmiProgramBufferWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_32 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_33 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_34 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_35 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_36 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_37 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_38 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_39 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_40 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_41 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_42 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_43 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_44 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_45 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_46 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_47 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_48 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_49 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_50 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_51 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_52 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_53 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_54 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_55 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_56 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_57 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_58 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_59 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_60 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_61 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_62 = 1'h0; // @[Debug.scala:889:53]
wire _dmiProgramBufferWrEnMaybe_WIRE_63 = 1'h0; // @[Debug.scala:889:53]
wire _dmiAbstractDataRdEn_WIRE_0 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_1 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_2 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_3 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_4 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_5 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_6 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_7 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_8 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_9 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_10 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_11 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_12 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_13 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_14 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_15 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_16 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_17 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_18 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_19 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_20 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_21 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_22 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_23 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_24 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_25 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_26 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_27 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_28 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_29 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_30 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataRdEn_WIRE_31 = 1'h0; // @[Debug.scala:891:47]
wire _dmiAbstractDataWrEnMaybe_WIRE_0 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_1 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_2 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_3 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_4 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_5 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_6 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_7 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_8 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_9 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_10 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_11 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_12 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_13 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_14 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_15 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_16 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_17 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_18 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_19 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_20 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_21 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_22 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_23 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_24 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_25 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_26 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_27 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_28 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_29 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_30 = 1'h0; // @[Debug.scala:893:52]
wire _dmiAbstractDataWrEnMaybe_WIRE_31 = 1'h0; // @[Debug.scala:893:52]
wire _hamaskFull_WIRE_0 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskFull_WIRE_1 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskFull_WIRE_2 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskFull_WIRE_3 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskFull_WIRE_4 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskFull_WIRE_5 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskFull_WIRE_6 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskFull_WIRE_7 = 1'h0; // @[Debug.scala:903:38]
wire _hamaskZero_WIRE_0 = 1'h0; // @[Debug.scala:914:40]
wire _hamaskZero_WIRE_1 = 1'h0; // @[Debug.scala:914:40]
wire _hamaskZero_WIRE_2 = 1'h0; // @[Debug.scala:914:40]
wire _hamaskZero_WIRE_3 = 1'h0; // @[Debug.scala:914:40]
wire _hamaskZero_WIRE_4 = 1'h0; // @[Debug.scala:914:40]
wire _hamaskZero_WIRE_5 = 1'h0; // @[Debug.scala:914:40]
wire _hamaskZero_WIRE_6 = 1'h0; // @[Debug.scala:914:40]
wire _hamaskZero_WIRE_7 = 1'h0; // @[Debug.scala:914:40]
wire hamaskZero_0 = 1'h0; // @[Debug.scala:914:32]
wire hamaskZero_1 = 1'h0; // @[Debug.scala:914:32]
wire hamaskZero_2 = 1'h0; // @[Debug.scala:914:32]
wire hamaskZero_3 = 1'h0; // @[Debug.scala:914:32]
wire hamaskZero_4 = 1'h0; // @[Debug.scala:914:32]
wire hamaskZero_5 = 1'h0; // @[Debug.scala:914:32]
wire hamaskZero_6 = 1'h0; // @[Debug.scala:914:32]
wire hamaskZero_7 = 1'h0; // @[Debug.scala:914:32]
wire _hamaskWrSel_WIRE_0 = 1'h0; // @[Debug.scala:933:39]
wire _hamaskWrSel_WIRE_1 = 1'h0; // @[Debug.scala:933:39]
wire _hamaskWrSel_WIRE_2 = 1'h0; // @[Debug.scala:933:39]
wire _hamaskWrSel_WIRE_3 = 1'h0; // @[Debug.scala:933:39]
wire _hamaskWrSel_WIRE_4 = 1'h0; // @[Debug.scala:933:39]
wire _hamaskWrSel_WIRE_5 = 1'h0; // @[Debug.scala:933:39]
wire _hamaskWrSel_WIRE_6 = 1'h0; // @[Debug.scala:933:39]
wire _hamaskWrSel_WIRE_7 = 1'h0; // @[Debug.scala:933:39]
wire _hrReset_WIRE_0 = 1'h0; // @[Debug.scala:945:38]
wire _hrReset_WIRE_1 = 1'h0; // @[Debug.scala:945:38]
wire _hrReset_WIRE_2 = 1'h0; // @[Debug.scala:945:38]
wire _hrReset_WIRE_3 = 1'h0; // @[Debug.scala:945:38]
wire _hrReset_WIRE_4 = 1'h0; // @[Debug.scala:945:38]
wire _hrReset_WIRE_5 = 1'h0; // @[Debug.scala:945:38]
wire _hrReset_WIRE_6 = 1'h0; // @[Debug.scala:945:38]
wire _hrReset_WIRE_7 = 1'h0; // @[Debug.scala:945:38]
wire hrReset_0 = 1'h0; // @[Debug.scala:945:30]
wire hrReset_1 = 1'h0; // @[Debug.scala:945:30]
wire hrReset_2 = 1'h0; // @[Debug.scala:945:30]
wire hrReset_3 = 1'h0; // @[Debug.scala:945:30]
wire hrReset_4 = 1'h0; // @[Debug.scala:945:30]
wire hrReset_5 = 1'h0; // @[Debug.scala:945:30]
wire hrReset_6 = 1'h0; // @[Debug.scala:945:30]
wire hrReset_7 = 1'h0; // @[Debug.scala:945:30]
wire _hrDebugIntReg_WIRE_0 = 1'h0; // @[Debug.scala:961:42]
wire _hrDebugIntReg_WIRE_1 = 1'h0; // @[Debug.scala:961:42]
wire _hrDebugIntReg_WIRE_2 = 1'h0; // @[Debug.scala:961:42]
wire _hrDebugIntReg_WIRE_3 = 1'h0; // @[Debug.scala:961:42]
wire _hrDebugIntReg_WIRE_4 = 1'h0; // @[Debug.scala:961:42]
wire _hrDebugIntReg_WIRE_5 = 1'h0; // @[Debug.scala:961:42]
wire _hrDebugIntReg_WIRE_6 = 1'h0; // @[Debug.scala:961:42]
wire _hrDebugIntReg_WIRE_7 = 1'h0; // @[Debug.scala:961:42]
wire _DMSTATUSRdData_WIRE_impebreak = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allhavereset = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyhavereset = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allresumeack = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyresumeack = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allnonexistent = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anynonexistent = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allunavail = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyunavail = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allrunning = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyrunning = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_allhalted = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_anyhalted = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_authenticated = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_authbusy = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_hasresethaltreq = 1'h0; // @[Debug.scala:978:47]
wire _DMSTATUSRdData_WIRE_confstrptrvalid = 1'h0; // @[Debug.scala:978:47]
wire DMSTATUSRdData_impebreak = 1'h0; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allnonexistent = 1'h0; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anynonexistent = 1'h0; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyunavail = 1'h0; // @[Debug.scala:978:34]
wire DMSTATUSRdData_authbusy = 1'h0; // @[Debug.scala:978:34]
wire DMSTATUSRdData_confstrptrvalid = 1'h0; // @[Debug.scala:978:34]
wire _DMSTATUSRdData_anynonexistent_T = 1'h0; // @[Debug.scala:988:57]
wire _DMSTATUSRdData_allnonexistent_T = 1'h0; // @[Debug.scala:991:57]
wire _DMSTATUSRdData_allnonexistent_T_9 = 1'h0; // @[Debug.scala:991:75]
wire _DMSTATUSRdData_anyunavail_T = 1'h0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyunavail_T_1 = 1'h0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyunavail_T_2 = 1'h0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyunavail_T_3 = 1'h0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyunavail_T_4 = 1'h0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyunavail_T_5 = 1'h0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyunavail_T_6 = 1'h0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyunavail_T_7 = 1'h0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyunavail_T_8 = 1'h0; // @[Debug.scala:994:81]
wire _DMSTATUSRdData_anyunavail_T_9 = 1'h0; // @[Debug.scala:994:81]
wire _DMSTATUSRdData_anyunavail_T_10 = 1'h0; // @[Debug.scala:994:81]
wire _DMSTATUSRdData_anyunavail_T_11 = 1'h0; // @[Debug.scala:994:81]
wire _DMSTATUSRdData_anyunavail_T_12 = 1'h0; // @[Debug.scala:994:81]
wire _DMSTATUSRdData_anyunavail_T_13 = 1'h0; // @[Debug.scala:994:81]
wire _DMSTATUSRdData_anyunavail_T_14 = 1'h0; // @[Debug.scala:994:81]
wire _DMCS2RdData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1025:47]
wire _DMCS2RdData_WIRE_hgselect = 1'h0; // @[Debug.scala:1025:47]
wire DMCS2RdData_hgwrite = 1'h0; // @[Debug.scala:1025:34]
wire DMCS2RdData_hgselect = 1'h0; // @[Debug.scala:1025:34]
wire _DMCS2WrData_WIRE_hgwrite = 1'h0; // @[Debug.scala:1026:47]
wire _DMCS2WrData_WIRE_hgselect = 1'h0; // @[Debug.scala:1026:47]
wire exttriggerWrEn = 1'h0; // @[Debug.scala:1030:34]
wire _hgDebugInt_WIRE_0 = 1'h0; // @[Debug.scala:1031:42]
wire _hgDebugInt_WIRE_1 = 1'h0; // @[Debug.scala:1031:42]
wire _hgDebugInt_WIRE_2 = 1'h0; // @[Debug.scala:1031:42]
wire _hgDebugInt_WIRE_3 = 1'h0; // @[Debug.scala:1031:42]
wire _hgDebugInt_WIRE_4 = 1'h0; // @[Debug.scala:1031:42]
wire _hgDebugInt_WIRE_5 = 1'h0; // @[Debug.scala:1031:42]
wire _hgDebugInt_WIRE_6 = 1'h0; // @[Debug.scala:1031:42]
wire _hgDebugInt_WIRE_7 = 1'h0; // @[Debug.scala:1031:42]
wire _hgParticipateHart_WIRE_0 = 1'h0; // @[Debug.scala:1036:46]
wire _hgParticipateHart_WIRE_1 = 1'h0; // @[Debug.scala:1036:46]
wire _hgParticipateHart_WIRE_2 = 1'h0; // @[Debug.scala:1036:46]
wire _hgParticipateHart_WIRE_3 = 1'h0; // @[Debug.scala:1036:46]
wire _hgParticipateHart_WIRE_4 = 1'h0; // @[Debug.scala:1036:46]
wire _hgParticipateHart_WIRE_5 = 1'h0; // @[Debug.scala:1036:46]
wire _hgParticipateHart_WIRE_6 = 1'h0; // @[Debug.scala:1036:46]
wire _hgParticipateHart_WIRE_7 = 1'h0; // @[Debug.scala:1036:46]
wire _hgFired_WIRE_0 = 1'h0; // @[Debug.scala:1107:46]
wire _hgFired_WIRE_1 = 1'h0; // @[Debug.scala:1107:46]
wire _hgHartFiring_WIRE_0 = 1'h0; // @[Debug.scala:1108:46]
wire _hgHartFiring_WIRE_1 = 1'h0; // @[Debug.scala:1108:46]
wire hgHartFiring_0 = 1'h0; // @[Debug.scala:1108:38]
wire _hgTrigFiring_WIRE_0 = 1'h0; // @[Debug.scala:1109:46]
wire _hgTrigFiring_WIRE_1 = 1'h0; // @[Debug.scala:1109:46]
wire hgTrigFiring_0 = 1'h0; // @[Debug.scala:1109:38]
wire hgTrigFiring_1 = 1'h0; // @[Debug.scala:1109:38]
wire _hgHartsAllHalted_WIRE_0 = 1'h0; // @[Debug.scala:1110:46]
wire _hgHartsAllHalted_WIRE_1 = 1'h0; // @[Debug.scala:1110:46]
wire hgHartsAllHalted_0 = 1'h0; // @[Debug.scala:1110:38]
wire _selectedHaltedStatus_T = 1'h0; // @[Debug.scala:1172:53]
wire _selectedHaltedStatus_T_1 = 1'h0; // @[Debug.scala:1172:59]
wire _selectedHaltedStatus_T_2 = 1'h0; // @[Debug.scala:1172:114]
wire _selectedHaltedStatus_WIRE = 1'h0;
wire _ABSTRACTCSReset_WIRE_busy = 1'h0; // @[Debug.scala:1179:48]
wire _ABSTRACTCSReset_WIRE_reserved2 = 1'h0; // @[Debug.scala:1179:48]
wire ABSTRACTCSReset_busy = 1'h0; // @[Debug.scala:1179:35]
wire ABSTRACTCSReset_reserved2 = 1'h0; // @[Debug.scala:1179:35]
wire _ABSTRACTCSWrData_WIRE_busy = 1'h0; // @[Debug.scala:1184:52]
wire _ABSTRACTCSWrData_WIRE_reserved2 = 1'h0; // @[Debug.scala:1184:52]
wire ABSTRACTCSWrData_busy = 1'h0; // @[Debug.scala:1184:39]
wire ABSTRACTCSWrData_reserved2 = 1'h0; // @[Debug.scala:1184:39]
wire ABSTRACTCSRdData_reserved2 = 1'h0; // @[Debug.scala:1185:39]
wire ABSTRACTCSRdEn = 1'h0; // @[Debug.scala:1187:34]
wire ABSTRACTAUTORdEn = 1'h0; // @[Debug.scala:1239:36]
wire _dmiAbstractDataAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiAbstractDataAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1257:53]
wire _dmiProgramBufferAccessVec_WIRE_0 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_1 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_2 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_3 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_4 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_5 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_6 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_7 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_8 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_9 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_10 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_11 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_12 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_13 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_14 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_15 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_16 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_17 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_18 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_19 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_20 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_21 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_22 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_23 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_24 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_25 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_26 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_27 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_28 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_29 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_30 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_31 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_32 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_33 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_34 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_35 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_36 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_37 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_38 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_39 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_40 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_41 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_42 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_43 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_44 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_45 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_46 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_47 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_48 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_49 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_50 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_51 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_52 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_53 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_54 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_55 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_56 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_57 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_58 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_59 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_60 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_61 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_62 = 1'h0; // @[Debug.scala:1260:54]
wire _dmiProgramBufferAccessVec_WIRE_63 = 1'h0; // @[Debug.scala:1260:54]
wire _autoexecData_WIRE_0 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_1 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_2 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_3 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_4 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_5 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_6 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecData_WIRE_7 = 1'h0; // @[Debug.scala:1267:41]
wire _autoexecProg_WIRE_0 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_1 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_2 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_3 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_4 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_5 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_6 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_7 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_8 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_9 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_10 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_11 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_12 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_13 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_14 = 1'h0; // @[Debug.scala:1268:41]
wire _autoexecProg_WIRE_15 = 1'h0; // @[Debug.scala:1268:41]
wire authRdEnMaybe = 1'h0; // @[Debug.scala:1356:33]
wire authWrEnMaybe = 1'h0; // @[Debug.scala:1357:33]
wire _SBCSFieldsRegReset_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbbusy = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbreadondata = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:49:51]
wire _SBCSFieldsRegReset_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:49:51]
wire SBCSFieldsRegReset_sbbusyerror = 1'h0; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbreadonaddr = 1'h0; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbautoincrement = 1'h0; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbreadondata = 1'h0; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbaccess128 = 1'h0; // @[SBA.scala:49:38]
wire _SBCSRdData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbbusy = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:60:51]
wire _SBCSRdData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:60:51]
wire SBCSRdData_sbaccess128 = 1'h0; // @[SBA.scala:60:38]
wire _SBCSWrData_WIRE_sbbusyerror = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbbusy = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbreadonaddr = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbautoincrement = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbreadondata = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess128 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess64 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess32 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess16 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_WIRE_sbaccess8 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_1 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_2 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_3 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_4 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_7 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_8 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_10 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_11 = 1'h0; // @[SBA.scala:63:61]
wire _SBCSWrData_T_12 = 1'h0; // @[SBA.scala:63:61]
wire SBCSWrData_sbbusy = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess128 = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess64 = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess32 = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess16 = 1'h0; // @[SBA.scala:63:38]
wire SBCSWrData_sbaccess8 = 1'h0; // @[SBA.scala:63:38]
wire _SBADDRESSRdEn_WIRE_0 = 1'h0; // @[SBA.scala:107:46]
wire _SBADDRESSRdEn_WIRE_1 = 1'h0; // @[SBA.scala:107:46]
wire _SBADDRESSRdEn_WIRE_2 = 1'h0; // @[SBA.scala:107:46]
wire _SBADDRESSRdEn_WIRE_3 = 1'h0; // @[SBA.scala:107:46]
wire SBADDRESSRdEn_1 = 1'h0; // @[SBA.scala:107:38]
wire SBADDRESSRdEn_2 = 1'h0; // @[SBA.scala:107:38]
wire SBADDRESSRdEn_3 = 1'h0; // @[SBA.scala:107:38]
wire _SBADDRESSWrEn_WIRE_0 = 1'h0; // @[SBA.scala:108:46]
wire _SBADDRESSWrEn_WIRE_1 = 1'h0; // @[SBA.scala:108:46]
wire _SBADDRESSWrEn_WIRE_2 = 1'h0; // @[SBA.scala:108:46]
wire _SBADDRESSWrEn_WIRE_3 = 1'h0; // @[SBA.scala:108:46]
wire SBADDRESSWrEn_1 = 1'h0; // @[SBA.scala:108:38]
wire SBADDRESSWrEn_2 = 1'h0; // @[SBA.scala:108:38]
wire SBADDRESSWrEn_3 = 1'h0; // @[SBA.scala:108:38]
wire _SBDATARdEn_WIRE_0 = 1'h0; // @[SBA.scala:149:43]
wire _SBDATARdEn_WIRE_1 = 1'h0; // @[SBA.scala:149:43]
wire _SBDATARdEn_WIRE_2 = 1'h0; // @[SBA.scala:149:43]
wire _SBDATARdEn_WIRE_3 = 1'h0; // @[SBA.scala:149:43]
wire SBDATARdEn_2 = 1'h0; // @[SBA.scala:149:35]
wire SBDATARdEn_3 = 1'h0; // @[SBA.scala:149:35]
wire _SBDATAWrEn_WIRE_0 = 1'h0; // @[SBA.scala:150:43]
wire _SBDATAWrEn_WIRE_1 = 1'h0; // @[SBA.scala:150:43]
wire _SBDATAWrEn_WIRE_2 = 1'h0; // @[SBA.scala:150:43]
wire _SBDATAWrEn_WIRE_3 = 1'h0; // @[SBA.scala:150:43]
wire SBDATAWrEn_2 = 1'h0; // @[SBA.scala:150:35]
wire SBDATAWrEn_3 = 1'h0; // @[SBA.scala:150:35]
wire _sbAccessError_T_1 = 1'h0; // @[SBA.scala:182:88]
wire _sbAccessError_T_2 = 1'h0; // @[SBA.scala:182:58]
wire _sbAccessError_T_4 = 1'h0; // @[SBA.scala:183:88]
wire _sbAccessError_T_5 = 1'h0; // @[SBA.scala:183:58]
wire _sbAccessError_T_6 = 1'h0; // @[SBA.scala:182:97]
wire _sbAccessError_T_8 = 1'h0; // @[SBA.scala:184:88]
wire _sbAccessError_T_9 = 1'h0; // @[SBA.scala:184:58]
wire _sbAccessError_T_10 = 1'h0; // @[SBA.scala:183:97]
wire _sbAccessError_T_12 = 1'h0; // @[SBA.scala:185:88]
wire _sbAccessError_T_13 = 1'h0; // @[SBA.scala:185:58]
wire _sbAccessError_T_14 = 1'h0; // @[SBA.scala:184:97]
wire _SBCSRdData_WIRE_1_sbbusyerror = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbbusy = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbreadonaddr = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbautoincrement = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbreadondata = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess128 = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess64 = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess32 = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess16 = 1'h0; // @[SBA.scala:243:33]
wire _SBCSRdData_WIRE_1_sbaccess8 = 1'h0; // @[SBA.scala:243:33]
wire _out_T_266 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_267 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_12 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_68 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_76 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_84 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_88 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_104 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_108 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_112 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_116 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_120 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_124 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_128 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_196 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_200 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_208 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_212 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_216 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_220 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_224 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_236 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_240 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_252 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_256 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_258 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_69 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_77 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_85 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_89 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_105 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_109 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_113 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_117 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_121 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_125 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_129 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_197 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_201 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_209 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_213 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_217 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_221 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_225 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_237 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_241 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_253 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_257 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_259 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire dmiNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire dmiNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire dmiNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire _jalAbstract_WIRE_imm3 = 1'h0; // @[Debug.scala:1497:66]
wire _jalAbstract_WIRE_imm1 = 1'h0; // @[Debug.scala:1497:66]
wire jalAbstract_imm3 = 1'h0; // @[Debug.scala:1497:32]
wire jalAbstract_imm1 = 1'h0; // @[Debug.scala:1497:32]
wire _immBits_T = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_1 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_2 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_6 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_7 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_8 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_9 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_10 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_11 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_12 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_13 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_14 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_15 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_16 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_17 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_18 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_19 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_T_20 = 1'h0; // @[Debug.scala:1575:48]
wire _immBits_WIRE_0 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_1 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_2 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_6 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_7 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_8 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_9 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_10 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_11 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_12 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_13 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_14 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_15 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_16 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_17 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_18 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_19 = 1'h0; // @[Debug.scala:1575:39]
wire _immBits_WIRE_20 = 1'h0; // @[Debug.scala:1575:39]
wire immBits_0 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_1 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_2 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_6 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_7 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_8 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_9 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_10 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_11 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_12 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_13 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_14 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_15 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_16 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_17 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_18 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_19 = 1'h0; // @[Debug.scala:1575:31]
wire immBits_20 = 1'h0; // @[Debug.scala:1575:31]
wire _flags_WIRE_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_1_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_1_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_2_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_2_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_3_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_3_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_4_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_4_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_5_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_5_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_6_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_6_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_7_resume = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_7_go = 1'h0; // @[Debug.scala:1517:87]
wire _flags_WIRE_8_0_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_0_go = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_1_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_1_go = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_2_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_2_go = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_3_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_3_go = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_4_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_4_go = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_5_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_5_go = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_6_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_6_go = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_7_resume = 1'h0; // @[Debug.scala:1517:33]
wire _flags_WIRE_8_7_go = 1'h0; // @[Debug.scala:1517:33]
wire componentSel = 1'h0; // @[Debug.scala:1523:34]
wire _out_rifireMux_T_271 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_275 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_279 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_283 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_287 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_291 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_295 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_299 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_303 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_395 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_647 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_675 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_679 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_683 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_687 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_691 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_695 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_699 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_703 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_707 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_711 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_715 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_719 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_723 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_819 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_823 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_827 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_831 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_835 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_839 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_843 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_847 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_851 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_855 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_859 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_863 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_867 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_871 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_875 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_879 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_883 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_887 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_891 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_895 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_899 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_903 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_907 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_911 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_915 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_919 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_923 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_927 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_931 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_935 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_939 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_943 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_947 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_951 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_955 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_959 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_963 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_967 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_971 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_975 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_979 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_983 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_987 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_991 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_995 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_999 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1003 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1007 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1011 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1015 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1019 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1023 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1027 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1031 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1035 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1039 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1043 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1047 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1051 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1055 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1059 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1063 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1067 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1071 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1075 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1079 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1083 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1087 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1091 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1095 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1099 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1103 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1107 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1111 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1115 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1119 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1123 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1127 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1131 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1135 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1139 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1143 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1147 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1151 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1155 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1159 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1163 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1167 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1171 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1175 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1179 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1183 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1187 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1191 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1195 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1199 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1203 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1207 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1211 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1215 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1219 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1223 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1227 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1231 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1235 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1239 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1243 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1247 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1251 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1255 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1259 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1263 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1267 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1271 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1275 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1279 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1283 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_273 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_277 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_281 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_285 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_289 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_293 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_297 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_301 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_305 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_397 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_649 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_677 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_681 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_685 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_689 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_693 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_697 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_701 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_705 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_709 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_713 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_717 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_721 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_725 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_821 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_825 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_829 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_833 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_837 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_841 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_845 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_849 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_853 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_857 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_861 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_865 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_869 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_873 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_877 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_881 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_885 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_889 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_893 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_897 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_901 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_905 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_909 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_913 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_917 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_921 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_925 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_929 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_933 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_937 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_941 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_945 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_949 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_953 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_957 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_961 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_965 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_969 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_973 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_977 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_981 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_985 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_989 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_993 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_997 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1001 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1005 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1009 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1013 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1017 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1021 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1025 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1029 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1033 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1037 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1041 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1045 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1049 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1053 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1057 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1061 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1065 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1069 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1073 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1077 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1081 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1085 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1089 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1093 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1097 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1101 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1105 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1109 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1113 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1117 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1121 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1125 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1129 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1133 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1137 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1141 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1145 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1149 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1153 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1157 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1161 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1165 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1169 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1173 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1177 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1181 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1185 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1189 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1193 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1197 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1201 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1205 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1209 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1213 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1217 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1221 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1225 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1229 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1233 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1237 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1241 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1245 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1249 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1253 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1257 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1261 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1265 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1269 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1273 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1277 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1281 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1285 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_271 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_275 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_279 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_283 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_287 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_291 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_295 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_299 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_303 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_307 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_311 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_315 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_319 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_323 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_327 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_331 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_335 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_339 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_343 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_347 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_351 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_355 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_359 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_363 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_367 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_371 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_375 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_379 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_383 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_387 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_395 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_399 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_403 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_407 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_411 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_415 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_471 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_475 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_479 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_483 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_487 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_491 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_495 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_499 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_503 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_507 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_511 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_515 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_523 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_527 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_531 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_535 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_539 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_543 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_547 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_551 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_555 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_559 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_563 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_567 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_571 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_575 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_579 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_583 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_587 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_591 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_595 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_599 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_603 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_607 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_611 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_615 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_619 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_623 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_627 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_631 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_635 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_639 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_643 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_647 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_651 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_655 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_659 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_663 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_667 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_671 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_675 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_679 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_683 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_687 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_691 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_695 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_699 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_703 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_707 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_711 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_715 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_719 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_723 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_727 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_731 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_735 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_739 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_743 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_747 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_751 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_755 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_759 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_763 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_767 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_771 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_819 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_823 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_827 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_831 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_835 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_839 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_843 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_847 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_851 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_855 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_859 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_863 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_867 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_871 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_875 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_879 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_883 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_887 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_891 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_895 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_899 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_903 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_907 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_911 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_915 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_919 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_923 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_927 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_931 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_935 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_939 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_943 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_947 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_951 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_955 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_959 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_963 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_967 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_971 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_975 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_979 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_983 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_987 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_991 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_995 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_999 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1003 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1007 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1011 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1015 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1019 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1023 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1027 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1031 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1035 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1039 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1043 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1047 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1051 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1055 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1059 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1063 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1067 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1071 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1075 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1079 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1083 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1087 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1091 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1095 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1099 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1103 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1107 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1111 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1115 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1119 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1123 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1127 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1131 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1135 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1139 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1143 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1147 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1151 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1155 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1159 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1163 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1167 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1171 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1175 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1179 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1183 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1187 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1191 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1195 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1199 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1203 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1207 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1211 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1215 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1219 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1223 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1227 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1231 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1235 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1239 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1243 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1247 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1251 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1255 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1259 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1263 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1267 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1271 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1275 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1279 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1283 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1285 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_273 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_277 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_281 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_285 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_289 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_293 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_297 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_301 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_305 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_309 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_313 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_317 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_321 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_325 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_329 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_333 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_337 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_341 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_345 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_349 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_353 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_357 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_361 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_365 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_369 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_373 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_377 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_381 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_385 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_389 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_397 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_401 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_405 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_409 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_413 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_417 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_473 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_477 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_481 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_485 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_489 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_493 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_497 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_501 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_505 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_509 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_513 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_517 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_525 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_529 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_533 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_537 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_541 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_545 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_549 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_553 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_557 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_561 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_565 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_569 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_573 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_577 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_581 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_585 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_589 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_593 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_597 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_601 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_605 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_609 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_613 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_617 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_621 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_625 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_629 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_633 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_637 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_641 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_645 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_649 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_653 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_657 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_661 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_665 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_669 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_673 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_677 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_681 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_685 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_689 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_693 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_697 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_701 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_705 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_709 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_713 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_717 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_721 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_725 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_729 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_733 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_737 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_741 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_745 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_749 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_753 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_757 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_761 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_765 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_769 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_773 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_821 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_825 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_829 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_833 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_837 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_841 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_845 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_849 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_853 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_857 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_861 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_865 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_869 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_873 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_877 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_881 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_885 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_889 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_893 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_897 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_901 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_905 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_909 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_913 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_917 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_921 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_925 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_929 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_933 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_937 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_941 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_945 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_949 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_953 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_957 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_961 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_965 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_969 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_973 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_977 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_981 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_985 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_989 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_993 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_997 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1001 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1005 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1009 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1013 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1017 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1021 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1025 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1029 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1033 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1037 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1041 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1045 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1049 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1053 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1057 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1061 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1065 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1069 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1073 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1077 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1081 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1085 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1089 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1093 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1097 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1101 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1105 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1109 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1113 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1117 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1121 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1125 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1129 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1133 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1137 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1141 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1145 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1149 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1153 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1157 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1161 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1165 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1169 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1173 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1177 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1181 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1185 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1189 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1193 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1197 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1201 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1205 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1209 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1213 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1217 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1221 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1225 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1229 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1233 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1237 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1241 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1245 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1249 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1253 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1257 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1261 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1265 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1269 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1273 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1277 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1281 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1285 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1287 = 1'h0; // @[MuxLiteral.scala:49:17]
wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] autoIncrementedAddr_hi = 64'h0; // @[SBA.scala:111:31]
wire [63:0] sb2tlOpt_io_addrIn_hi = 64'h0; // @[SBA.scala:132:14]
wire [63:0] sb2tlOpt_io_addrIn_hi_1 = 64'h0; // @[SBA.scala:133:10]
wire [63:0] sb2tlOpt_io_dataIn_hi = 64'h0; // @[SBA.scala:175:59]
wire [63:0] sb2tlOpt_io_dataIn_hi_1 = 64'h0; // @[SBA.scala:175:85]
wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire [2:0] auto_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:790:9]
wire [2:0] _ABSTRACTCSReset_WIRE_reserved0 = 3'h0; // @[Debug.scala:1179:48]
wire [2:0] _ABSTRACTCSReset_WIRE_cmderr = 3'h0; // @[Debug.scala:1179:48]
wire [2:0] ABSTRACTCSReset_reserved0 = 3'h0; // @[Debug.scala:1179:35]
wire [2:0] ABSTRACTCSReset_cmderr = 3'h0; // @[Debug.scala:1179:35]
wire [2:0] _ABSTRACTCSWrData_WIRE_reserved0 = 3'h0; // @[Debug.scala:1184:52]
wire [2:0] _ABSTRACTCSWrData_WIRE_cmderr = 3'h0; // @[Debug.scala:1184:52]
wire [2:0] ABSTRACTCSWrData_reserved0 = 3'h0; // @[Debug.scala:1184:39]
wire [2:0] ABSTRACTCSRdData_reserved0 = 3'h0; // @[Debug.scala:1185:39]
wire [2:0] _SBCSFieldsRegReset_WIRE_sbversion = 3'h0; // @[SBA.scala:49:51]
wire [2:0] _SBCSFieldsRegReset_WIRE_sbaccess = 3'h0; // @[SBA.scala:49:51]
wire [2:0] _SBCSFieldsRegReset_WIRE_sberror = 3'h0; // @[SBA.scala:49:51]
wire [2:0] SBCSFieldsRegReset_sberror = 3'h0; // @[SBA.scala:49:38]
wire [2:0] _SBCSRdData_WIRE_sbversion = 3'h0; // @[SBA.scala:60:51]
wire [2:0] _SBCSRdData_WIRE_sbaccess = 3'h0; // @[SBA.scala:60:51]
wire [2:0] _SBCSRdData_WIRE_sberror = 3'h0; // @[SBA.scala:60:51]
wire [2:0] _SBCSWrData_WIRE_sbversion = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_WIRE_sbaccess = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_WIRE_sberror = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_T_6 = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_T_9 = 3'h0; // @[SBA.scala:63:61]
wire [2:0] _SBCSWrData_T_14 = 3'h0; // @[SBA.scala:63:61]
wire [2:0] SBCSWrData_sbversion = 3'h0; // @[SBA.scala:63:38]
wire [2:0] _SBCSRdData_WIRE_1_sbversion = 3'h0; // @[SBA.scala:243:33]
wire [2:0] _SBCSRdData_WIRE_1_sbaccess = 3'h0; // @[SBA.scala:243:33]
wire [2:0] _SBCSRdData_WIRE_1_sberror = 3'h0; // @[SBA.scala:243:33]
wire [2:0] dmiNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [2:0] jalAbstract_imm0_hi_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] jalAbstract_imm1_lo_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] jalAbstract_imm1_hi_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] nop_funct3 = 3'h0; // @[Debug.scala:1623:19]
wire [2:0] _nop_WIRE_funct3 = 3'h0; // @[Debug.scala:1624:46]
wire [2:0] isa_funct3 = 3'h0; // @[Debug.scala:1629:19]
wire [2:0] _isa_WIRE_funct3 = 3'h0; // @[Debug.scala:1630:47]
wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire auto_sb2tlOpt_out_a_bits_mask = 1'h1; // @[Debug.scala:790:9]
wire io_innerCtrl_ready = 1'h1; // @[Debug.scala:790:9]
wire DMSTATUSRdData_authenticated = 1'h1; // @[Debug.scala:978:34]
wire DMSTATUSRdData_hasresethaltreq = 1'h1; // @[Debug.scala:978:34]
wire _DMSTATUSRdData_anyhalted_T = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyhalted_T_1 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyhalted_T_2 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyhalted_T_3 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyhalted_T_4 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyhalted_T_5 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyhalted_T_6 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyhalted_T_7 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_1 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_2 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_3 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_4 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_5 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_6 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_7 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_1 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_2 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_3 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_4 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_5 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_6 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_7 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_1 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_2 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_3 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_4 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_5 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_6 = 1'h1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_7 = 1'h1; // @[package.scala:79:37]
wire _hgTrigsAllAcked_WIRE_0 = 1'h1; // @[Debug.scala:1111:46]
wire _hgTrigsAllAcked_WIRE_1 = 1'h1; // @[Debug.scala:1111:46]
wire hgTrigsAllAcked_0 = 1'h1; // @[Debug.scala:1111:38]
wire hgTrigsAllAcked_1 = 1'h1; // @[Debug.scala:1111:38]
wire SBCSFieldsRegReset_sbaccess64 = 1'h1; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbaccess32 = 1'h1; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbaccess16 = 1'h1; // @[SBA.scala:49:38]
wire SBCSFieldsRegReset_sbaccess8 = 1'h1; // @[SBA.scala:49:38]
wire SBCSRdData_sbaccess64 = 1'h1; // @[SBA.scala:60:38]
wire SBCSRdData_sbaccess32 = 1'h1; // @[SBA.scala:60:38]
wire SBCSRdData_sbaccess16 = 1'h1; // @[SBA.scala:60:38]
wire SBCSRdData_sbaccess8 = 1'h1; // @[SBA.scala:60:38]
wire _sbAccessError_T_16 = 1'h1; // @[SBA.scala:186:88]
wire _out_T_480 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_T_481 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_19 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_20 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_21 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_22 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_23 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_24 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_25 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_26 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_27 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_28 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_29 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_30 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_31 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_32 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_33 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_34 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_35 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_36 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_37 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_38 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_39 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_40 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_41 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_42 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_43 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_44 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_45 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_46 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_47 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_48 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_49 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_50 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_51 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_52 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_53 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_54 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_55 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_56 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_57 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_58 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_59 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_60 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_61 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_62 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_63 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _immBits_T_3 = 1'h1; // @[Debug.scala:1575:48]
wire _immBits_T_4 = 1'h1; // @[Debug.scala:1575:48]
wire _immBits_T_5 = 1'h1; // @[Debug.scala:1575:48]
wire _immBits_WIRE_3 = 1'h1; // @[Debug.scala:1575:39]
wire _immBits_WIRE_4 = 1'h1; // @[Debug.scala:1575:39]
wire _immBits_WIRE_5 = 1'h1; // @[Debug.scala:1575:39]
wire immBits_3 = 1'h1; // @[Debug.scala:1575:31]
wire immBits_4 = 1'h1; // @[Debug.scala:1575:31]
wire immBits_5 = 1'h1; // @[Debug.scala:1575:31]
wire componentSel_1 = 1'h1; // @[Debug.scala:1523:34]
wire out_rifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_320 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_324 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_328 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_332 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_336 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_340 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_344 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_348 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_352 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_356 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_360 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_364 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_368 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_372 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_376 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_380 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_384 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_388 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_392 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_396 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_400 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_404 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_408 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_412 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_416 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_420 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_424 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_428 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_432 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_436 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_440 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_444 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_448 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_452 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_456 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_460 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_464 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_468 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_472 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_476 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_480 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_484 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_488 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_492 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_496 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_500 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_504 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_508 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_512 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_516 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_520 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_524 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_528 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_532 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_536 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_540 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_544 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_548 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_552 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_556 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_560 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_564 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_568 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_572 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_576 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_580 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_584 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_588 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_592 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_596 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_600 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_604 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_608 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_612 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_616 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_620 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_624 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_628 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_632 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_636 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_640 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_644 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_648 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_652 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_656 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_660 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_664 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_668 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_672 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_676 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_680 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_684 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_688 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_692 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_696 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_700 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_704 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_708 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_712 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_716 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_720 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_724 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_728 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_732 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_736 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_740 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_744 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_748 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_752 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_756 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_760 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_764 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_768 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_772 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_776 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_780 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_784 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_788 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_792 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_796 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_800 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_804 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_808 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_812 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_816 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_820 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_824 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_828 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_832 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_836 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_840 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_844 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_848 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_852 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_856 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_860 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_864 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_868 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_872 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_876 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_880 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_884 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_888 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_892 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_896 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_900 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_904 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_908 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_912 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_916 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_920 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_924 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_928 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_932 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_936 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_940 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_944 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_948 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_952 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_956 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_960 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_964 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_968 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_972 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_976 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_980 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_984 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_988 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_992 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_996 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1000 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1004 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1008 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1012 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1016 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1020 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1024 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1028 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1032 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1036 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1040 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1044 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1048 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1052 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1056 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1060 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1064 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1068 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1072 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1076 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1080 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1084 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1088 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1092 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1096 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out_64 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_65 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_66 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_67 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_68 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_69 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_70 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_71 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_72 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_73 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_74 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_75 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_76 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_77 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_78 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_322 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_79 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_326 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_80 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_330 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_81 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_334 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_82 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_338 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_83 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_342 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_84 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_346 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_85 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_350 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_86 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_354 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_87 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_358 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_88 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_362 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_89 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_366 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_90 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_370 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_91 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_374 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_92 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_378 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_93 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_382 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_94 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_386 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_95 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_390 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_96 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_394 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_97 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_398 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_98 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_402 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_99 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_406 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_100 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_410 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_101 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_414 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_418 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_103 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_422 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_104 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_426 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_105 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_430 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_434 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_107 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_438 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_108 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_442 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_109 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_446 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_450 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_111 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_454 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_112 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_458 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_113 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_462 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_466 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_115 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_470 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_116 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_474 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_117 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_478 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_482 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_119 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_486 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_120 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_490 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_121 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_494 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_498 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_123 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_502 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_124 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_506 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_125 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_510 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_514 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_127 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_518 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_128 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_522 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_129 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_526 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_530 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_131 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_534 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_132 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_538 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_133 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_542 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_546 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_135 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_550 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_136 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_554 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_137 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_558 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_562 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_139 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_566 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_140 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_570 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_141 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_574 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_578 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_143 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_582 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_144 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_586 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_145 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_590 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_594 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_147 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_598 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_148 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_602 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_149 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_606 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_610 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_151 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_614 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_152 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_618 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_153 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_622 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_626 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_155 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_630 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_156 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_634 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_157 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_638 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_642 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_159 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_646 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_160 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_650 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_161 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_654 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_658 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_163 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_662 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_164 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_666 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_165 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_670 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_674 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_167 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_678 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_168 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_682 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_169 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_686 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_690 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_171 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_694 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_172 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_698 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_173 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_702 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_706 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_175 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_710 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_176 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_714 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_177 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_718 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_722 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_179 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_726 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_180 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_730 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_181 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_734 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_738 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_183 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_742 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_184 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_746 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_185 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_750 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_754 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_187 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_758 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_188 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_762 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_189 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_766 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_770 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_191 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_774 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_192 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_778 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_193 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_782 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_786 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_195 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_790 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_196 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_794 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_197 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_798 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_802 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_199 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_806 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_200 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_810 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_201 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_814 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_818 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_203 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_822 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_204 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_826 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_205 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_830 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_834 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_207 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_838 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_208 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_842 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_209 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_846 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_850 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_211 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_854 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_212 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_858 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_213 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_862 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_866 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_215 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_870 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_216 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_874 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_217 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_878 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_882 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_219 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_886 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_220 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_890 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_221 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_894 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_898 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_223 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_902 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_224 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_906 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_225 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_910 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_914 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_227 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_918 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_228 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_922 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_229 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_926 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_930 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_231 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_934 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_232 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_938 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_233 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_942 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_946 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_235 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_950 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_236 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_954 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_237 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_958 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_962 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_239 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_966 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_240 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_970 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_241 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_974 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_978 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_243 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_982 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_244 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_986 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_245 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_990 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_994 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_247 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_998 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_248 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1002 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_249 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1006 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1010 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_251 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1014 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_252 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1018 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_253 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1022 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1026 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_255 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1030 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_256 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1034 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_257 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1038 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1042 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_259 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1046 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_260 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1050 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_261 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1054 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1058 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_263 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1062 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_264 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1066 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_265 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1070 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1074 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_267 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1078 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_268 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1082 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_269 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1086 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1090 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_271 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1094 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_272 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1098 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_273 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1102 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1106 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_275 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1110 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_276 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1114 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_277 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1118 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1122 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_279 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1126 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_280 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1130 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_281 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1134 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1138 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_283 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1142 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_284 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1146 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_285 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1150 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1154 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_287 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1158 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_288 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1162 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_289 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1166 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_290 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1170 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_291 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1174 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_292 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1178 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_293 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1182 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_294 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1186 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_295 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1190 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_296 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1194 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_297 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1198 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_298 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1202 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_299 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1206 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_300 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1210 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_301 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1214 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_302 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1218 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_303 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1222 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_304 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1226 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_305 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1230 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_306 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1234 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_307 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1238 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_308 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1242 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_309 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1246 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_310 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1250 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_311 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1254 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_312 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1258 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_313 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1262 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_314 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1266 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_315 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1270 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_316 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1274 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_317 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1278 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_318 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1282 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_319 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1286 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_1_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_4 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_5 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_6 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_7 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_8 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_9 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_10 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_11 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_12 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_13 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_14 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_15 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_16 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_17 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_18 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_19 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_20 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_21 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_22 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_23 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_24 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_25 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_26 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_27 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_28 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_29 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_30 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_31 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_32 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_33 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_34 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_35 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_36 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_37 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_38 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_39 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_40 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_41 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_42 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_43 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_44 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_45 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_46 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_47 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_48 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_49 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_50 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_51 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_52 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_53 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_54 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_55 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_56 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_57 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_58 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_59 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_60 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_61 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_62 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_63 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_64 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_65 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_66 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_67 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_68 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_69 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_70 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_71 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_72 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_73 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_74 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_75 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_76 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_77 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_78 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_79 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_80 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_81 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_82 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_83 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_84 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_85 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_86 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_87 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_88 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_89 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_90 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_91 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_92 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_93 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_94 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_95 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_96 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_97 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_98 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_99 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_100 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_101 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_102 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_103 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_104 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_105 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_106 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_107 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_108 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_109 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_110 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_111 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_112 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_113 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_114 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_115 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_116 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_117 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_118 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_119 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_120 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_121 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_122 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_123 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_124 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_125 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_126 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_127 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_128 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_129 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_130 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_131 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_132 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_133 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_134 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_135 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_136 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_137 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_138 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_139 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_140 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_141 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_142 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_143 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_144 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_145 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_146 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_147 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_148 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_149 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_150 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_151 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_152 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_153 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_154 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_155 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_156 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_157 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_158 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_159 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_160 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_161 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_162 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_163 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_164 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_165 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_166 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_167 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_168 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_169 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_170 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_171 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_172 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_173 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_174 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_175 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_176 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_177 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_178 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_179 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_180 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_181 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_182 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_183 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_184 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_185 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_186 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_187 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_188 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_189 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_190 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_191 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_192 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_193 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_194 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_195 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_196 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_197 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_198 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_199 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_200 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_201 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_202 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_203 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_204 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_205 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_206 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_207 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_208 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_209 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_210 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_211 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_212 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_213 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_214 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_215 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_216 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_217 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_218 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_219 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_220 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_221 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_222 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_223 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_224 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_225 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_226 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_227 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_228 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_229 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_230 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_231 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_232 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_233 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_234 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_235 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_236 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_237 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_238 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_239 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_240 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_241 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_242 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_243 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_244 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_245 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_246 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_247 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_248 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_249 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_250 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_251 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_252 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_253 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_254 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1_255 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux_1 = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire [31:0] SBCSWrDataVal = 32'h0; // @[SBA.scala:62:38]
wire [31:0] _SBCSWrData_WIRE_1 = 32'h0; // @[SBA.scala:63:61]
wire [31:0] _SBADDRESSWrData_WIRE_0 = 32'h0; // @[SBA.scala:106:46]
wire [31:0] _SBADDRESSWrData_WIRE_1 = 32'h0; // @[SBA.scala:106:46]
wire [31:0] _SBADDRESSWrData_WIRE_2 = 32'h0; // @[SBA.scala:106:46]
wire [31:0] _SBADDRESSWrData_WIRE_3 = 32'h0; // @[SBA.scala:106:46]
wire [31:0] SBADDRESSWrData_1 = 32'h0; // @[SBA.scala:106:38]
wire [31:0] SBADDRESSWrData_2 = 32'h0; // @[SBA.scala:106:38]
wire [31:0] SBADDRESSWrData_3 = 32'h0; // @[SBA.scala:106:38]
wire [31:0] _SBDATARdData_WIRE_0 = 32'h0; // @[SBA.scala:145:43]
wire [31:0] _SBDATARdData_WIRE_1 = 32'h0; // @[SBA.scala:145:43]
wire [31:0] _SBDATARdData_WIRE_2 = 32'h0; // @[SBA.scala:145:43]
wire [31:0] _SBDATARdData_WIRE_3 = 32'h0; // @[SBA.scala:145:43]
wire [31:0] SBDATARdData_2 = 32'h0; // @[SBA.scala:145:35]
wire [31:0] SBDATARdData_3 = 32'h0; // @[SBA.scala:145:35]
wire [31:0] _SBDATAWrData_WIRE_0 = 32'h0; // @[SBA.scala:147:43]
wire [31:0] _SBDATAWrData_WIRE_1 = 32'h0; // @[SBA.scala:147:43]
wire [31:0] _SBDATAWrData_WIRE_2 = 32'h0; // @[SBA.scala:147:43]
wire [31:0] _SBDATAWrData_WIRE_3 = 32'h0; // @[SBA.scala:147:43]
wire [31:0] SBDATAWrData_2 = 32'h0; // @[SBA.scala:147:35]
wire [31:0] SBDATAWrData_3 = 32'h0; // @[SBA.scala:147:35]
wire [31:0] sb2tlOpt_io_dataIn_hi_lo = 32'h0; // @[SBA.scala:175:85]
wire [31:0] sb2tlOpt_io_dataIn_hi_hi = 32'h0; // @[SBA.scala:175:85]
wire [31:0] _out_out_bits_data_WIRE_1_1 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_2 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_3 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_12 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_13 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_14 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_15 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_16 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_18 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_20 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_21 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_25 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_26 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_27 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_28 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_29 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_30 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_31 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_48 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_49 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_51 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_52 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_53 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_54 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_55 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_58 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_59 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_62 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_63 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] dmiNodeIn_d_bits_d_data = 32'h0; // @[Edges.scala:792:17]
wire [31:0] _out_prepend_T_220 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_252 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [5:0] _SBCSFieldsRegReset_WIRE_reserved0 = 6'h0; // @[SBA.scala:49:51]
wire [5:0] SBCSFieldsRegReset_reserved0 = 6'h0; // @[SBA.scala:49:38]
wire [5:0] _SBCSRdData_WIRE_reserved0 = 6'h0; // @[SBA.scala:60:51]
wire [5:0] SBCSRdData_reserved0 = 6'h0; // @[SBA.scala:60:38]
wire [5:0] _SBCSWrData_WIRE_reserved0 = 6'h0; // @[SBA.scala:63:61]
wire [5:0] _SBCSWrData_T_13 = 6'h0; // @[SBA.scala:63:61]
wire [5:0] SBCSWrData_reserved0 = 6'h0; // @[SBA.scala:63:38]
wire [5:0] _SBCSRdData_WIRE_1_reserved0 = 6'h0; // @[SBA.scala:243:33]
wire [5:0] _flags_WIRE_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_1_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_2_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_3_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_4_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_5_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_6_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_7_reserved = 6'h0; // @[Debug.scala:1517:87]
wire [5:0] _flags_WIRE_8_0_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] _flags_WIRE_8_1_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] _flags_WIRE_8_2_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] _flags_WIRE_8_3_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] _flags_WIRE_8_4_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] _flags_WIRE_8_5_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] _flags_WIRE_8_6_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] _flags_WIRE_8_7_reserved = 6'h0; // @[Debug.scala:1517:33]
wire [5:0] flags_0_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [5:0] flags_1_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [5:0] flags_2_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [5:0] flags_3_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [5:0] flags_4_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [5:0] flags_5_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [5:0] flags_6_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [5:0] flags_7_reserved = 6'h0; // @[Debug.scala:1517:25]
wire [3:0] _DMSTATUSRdData_WIRE_version = 4'h0; // @[Debug.scala:978:47]
wire [3:0] _DMCS2RdData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1025:47]
wire [3:0] DMCS2RdData_exttrigger = 4'h0; // @[Debug.scala:1025:34]
wire [3:0] _DMCS2WrData_WIRE_exttrigger = 4'h0; // @[Debug.scala:1026:47]
wire [3:0] DMCS2WrData_exttrigger = 4'h0; // @[Debug.scala:1026:34]
wire [3:0] _ABSTRACTCSReset_WIRE_reserved3 = 4'h0; // @[Debug.scala:1179:48]
wire [3:0] _ABSTRACTCSReset_WIRE_datacount = 4'h0; // @[Debug.scala:1179:48]
wire [3:0] ABSTRACTCSReset_reserved3 = 4'h0; // @[Debug.scala:1179:35]
wire [3:0] _ABSTRACTCSWrData_WIRE_reserved3 = 4'h0; // @[Debug.scala:1184:52]
wire [3:0] _ABSTRACTCSWrData_WIRE_datacount = 4'h0; // @[Debug.scala:1184:52]
wire [3:0] ABSTRACTCSWrData_reserved3 = 4'h0; // @[Debug.scala:1184:39]
wire [3:0] ABSTRACTCSWrData_datacount = 4'h0; // @[Debug.scala:1184:39]
wire [3:0] ABSTRACTCSRdData_reserved3 = 4'h0; // @[Debug.scala:1185:39]
wire [3:0] _ABSTRACTAUTOReset_WIRE_reserved0 = 4'h0; // @[Debug.scala:1234:54]
wire [3:0] ABSTRACTAUTOReset_reserved0 = 4'h0; // @[Debug.scala:1234:41]
wire [3:0] _ABSTRACTAUTOWrData_WIRE_reserved0 = 4'h0; // @[Debug.scala:1236:54]
wire [3:0] ABSTRACTAUTOWrData_reserved0 = 4'h0; // @[Debug.scala:1236:41]
wire [3:0] ABSTRACTAUTORdData_reserved0 = 4'h0; // @[Debug.scala:1237:41]
wire [3:0] jalAbstract_imm2_lo = 4'h0; // @[package.scala:45:27]
wire [3:0] jalAbstract_imm2_hi = 4'h0; // @[package.scala:45:27]
wire [7:0] _out_T_1265 = 8'h8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1266 = 8'h8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_89 = 8'h8; // @[RegisterRouter.scala:87:24]
wire [4:0] out_prepend_88 = 5'h8; // @[RegisterRouter.scala:87:24]
wire [3:0] ABSTRACTCSReset_datacount = 4'h8; // @[Debug.scala:1179:35]
wire [3:0] ABSTRACTCSRdData_datacount = 4'h8; // @[Debug.scala:1185:39]
wire [3:0] _out_T_1256 = 4'h8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_1257 = 4'h8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_prepend_T_88 = 4'h8; // @[RegisterRouter.scala:87:24]
wire [15:0] _ABSTRACTAUTOReset_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:54]
wire [15:0] ABSTRACTAUTOReset_autoexecprogbuf = 16'h0; // @[Debug.scala:1234:41]
wire [15:0] _ABSTRACTAUTOWrData_WIRE_autoexecprogbuf = 16'h0; // @[Debug.scala:1236:54]
wire [15:0] sb2tlOpt_io_dataIn_hi_lo_lo = 16'h0; // @[SBA.scala:175:85]
wire [15:0] sb2tlOpt_io_dataIn_hi_lo_hi = 16'h0; // @[SBA.scala:175:85]
wire [15:0] sb2tlOpt_io_dataIn_hi_hi_lo = 16'h0; // @[SBA.scala:175:85]
wire [15:0] sb2tlOpt_io_dataIn_hi_hi_hi = 16'h0; // @[SBA.scala:175:85]
wire [95:0] _sb2tlOpt_io_addrIn_T = 96'h0; // @[SBA.scala:132:14]
wire [2:0] SBCSFieldsRegReset_sbversion = 3'h1; // @[SBA.scala:49:38]
wire [2:0] SBCSRdData_sbversion = 3'h1; // @[SBA.scala:60:38]
wire [10:0] _ABSTRACTCSReset_WIRE_reserved1 = 11'h0; // @[Debug.scala:1179:48]
wire [10:0] ABSTRACTCSReset_reserved1 = 11'h0; // @[Debug.scala:1179:35]
wire [10:0] _ABSTRACTCSWrData_WIRE_reserved1 = 11'h0; // @[Debug.scala:1184:52]
wire [10:0] ABSTRACTCSWrData_reserved1 = 11'h0; // @[Debug.scala:1184:39]
wire [10:0] ABSTRACTCSRdData_reserved1 = 11'h0; // @[Debug.scala:1185:39]
wire [4:0] ABSTRACTCSReset_progbufsize = 5'h10; // @[Debug.scala:1179:35]
wire [4:0] ABSTRACTCSRdData_progbufsize = 5'h10; // @[Debug.scala:1185:39]
wire [7:0] _COMMANDReset_WIRE_cmdtype = 8'h0; // @[Debug.scala:1276:45]
wire [7:0] COMMANDReset_cmdtype = 8'h0; // @[Debug.scala:1276:32]
wire [7:0] _jalAbstract_WIRE_imm2 = 8'h0; // @[Debug.scala:1497:66]
wire [7:0] jalAbstract_imm2 = 8'h0; // @[Debug.scala:1497:32]
wire [7:0] _jalAbstract_imm2_T = 8'h0; // @[package.scala:45:27]
wire [6:0] SBCSFieldsRegReset_sbasize = 7'h20; // @[SBA.scala:49:38]
wire [6:0] SBCSRdData_sbasize = 7'h20; // @[SBA.scala:60:38]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Debug.scala:790:9]
wire [1:0] auto_dmi_in_d_bits_param = 2'h0; // @[Debug.scala:790:9]
wire [1:0] dmiNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] _DMSTATUSRdData_WIRE_reserved1 = 2'h0; // @[Debug.scala:978:47]
wire [1:0] DMSTATUSRdData_reserved1 = 2'h0; // @[Debug.scala:978:34]
wire [1:0] out_prepend_12 = 2'h0; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_275 = 2'h0; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_276 = 2'h0; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_prepend_T_13 = 2'h0; // @[RegisterRouter.scala:87:24]
wire [1:0] dmiNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire [1:0] jalAbstract_imm0_lo_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm0_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm0_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm1_lo_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm1_lo_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm1_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm1_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm2_lo_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm2_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm2_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] jalAbstract_imm2_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire [63:0] out_prepend_274 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3555 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3556 = 64'hF14024737B241073; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_273 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3546 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3547 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_274 = 56'h4024737B241073; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_272 = 48'h24737B241073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3537 = 48'h24737B241073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3538 = 48'h24737B241073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_273 = 48'h24737B241073; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_271 = 40'h737B241073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3528 = 40'h737B241073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3529 = 40'h737B241073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_272 = 40'h737B241073; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_270 = 32'h7B241073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3519 = 32'h7B241073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3520 = 32'h7B241073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_271 = 32'h7B241073; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_269 = 24'h241073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3510 = 24'h241073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3511 = 24'h241073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_270 = 24'h241073; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_268 = 16'h1073; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3501 = 16'h1073; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3502 = 16'h1073; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_269 = 16'h1073; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2113 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2114 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_150 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2593 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2594 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_192 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3260 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3261 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_249 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3492 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3493 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_268 = 8'h73; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_259 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3377 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3378 = 64'h7B20247310802423; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_258 = 56'h20247310802423; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3368 = 56'h20247310802423; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3369 = 56'h20247310802423; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_259 = 56'h20247310802423; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_257 = 48'h247310802423; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3359 = 48'h247310802423; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3360 = 48'h247310802423; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_258 = 48'h247310802423; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_256 = 40'h7310802423; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3350 = 40'h7310802423; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3351 = 40'h7310802423; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_257 = 40'h7310802423; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_255 = 32'h10802423; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3341 = 32'h10802423; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3342 = 32'h10802423; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_256 = 32'h10802423; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_254 = 24'h802423; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3332 = 24'h802423; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3333 = 24'h802423; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_255 = 24'h802423; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_253 = 16'h2423; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3323 = 16'h2423; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3324 = 16'h2423; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_254 = 16'h2423; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2185 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2186 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_157 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3314 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3315 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_253 = 8'h23; // @[RegisterRouter.scala:87:24]
wire [41:0] _out_T_2922 = 42'h0; // @[RegisterRouter.scala:87:24]
wire [41:0] _out_T_2923 = 42'h0; // @[RegisterRouter.scala:87:24]
wire [41:0] _out_T_3305 = 42'h0; // @[RegisterRouter.scala:87:24]
wire [41:0] _out_T_3306 = 42'h0; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_220 = 33'h0; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_252 = 33'h0; // @[RegisterRouter.scala:87:24]
wire [9:0] _jalAbstract_WIRE_imm0 = 10'h0; // @[Debug.scala:1497:66]
wire [9:0] _jalAbstract_imm1_T = 10'h0; // @[package.scala:45:27]
wire [9:0] _out_T_2913 = 10'h0; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_2914 = 10'h0; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_3296 = 10'h0; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_3297 = 10'h0; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_251 = 32'h100073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3287 = 32'h100073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3288 = 32'h100073; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_250 = 24'h100073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3278 = 24'h100073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3279 = 24'h100073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_251 = 24'h100073; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_150 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2122 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2123 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_151 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_249 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3269 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3270 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_250 = 16'h73; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_234 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3091 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3092 = 64'h380006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_233 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3082 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3083 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_234 = 56'h80006F00C0006F; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_232 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3073 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3074 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_233 = 48'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_231 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3064 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3065 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_232 = 40'h6F00C0006F; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_230 = 32'hC0006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3055 = 32'hC0006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3056 = 32'hC0006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_231 = 32'hC0006F; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_229 = 24'hC0006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3046 = 24'hC0006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3047 = 24'hC0006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_230 = 24'hC0006F; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_122 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1802 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1803 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_123 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_228 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3037 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3038 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_229 = 16'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1793 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1794 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_122 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3028 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3029 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_228 = 8'h6F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2931 = 32'h380006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2932 = 32'h380006F; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_219 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2904 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2905 = 64'hFE0408E300347413; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_218 = 56'h408E300347413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2895 = 56'h408E300347413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2896 = 56'h408E300347413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_219 = 56'h408E300347413; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_217 = 48'h8E300347413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2886 = 48'h8E300347413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2887 = 48'h8E300347413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_218 = 48'h8E300347413; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_216 = 40'hE300347413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2877 = 40'hE300347413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2878 = 40'hE300347413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_217 = 40'hE300347413; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_215 = 32'h347413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2868 = 32'h347413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2869 = 32'h347413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_216 = 32'h347413; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_214 = 24'h347413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2859 = 24'h347413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2860 = 24'h347413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_215 = 24'h347413; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_136 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1962 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1963 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_137 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_213 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2850 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2851 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_214 = 16'h7413; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1953 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1954 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_136 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2841 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2842 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_213 = 8'h13; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_198 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2656 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2657 = 64'h100022237B202473; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_197 = 56'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2647 = 56'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2648 = 56'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_198 = 56'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_196 = 48'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2638 = 48'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2639 = 48'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_197 = 48'h22237B202473; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_195 = 40'h237B202473; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2629 = 40'h237B202473; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2630 = 40'h237B202473; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_196 = 40'h237B202473; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_194 = 32'h7B202473; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2620 = 32'h7B202473; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2621 = 32'h7B202473; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_195 = 32'h7B202473; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_193 = 24'h202473; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2611 = 24'h202473; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2612 = 24'h202473; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_194 = 24'h202473; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_192 = 16'h2473; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2602 = 16'h2473; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2603 = 16'h2473; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_193 = 16'h2473; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_184 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2496 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2497 = 64'hF140247330000067; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_183 = 56'h40247330000067; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2487 = 56'h40247330000067; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2488 = 56'h40247330000067; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_184 = 56'h40247330000067; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_182 = 48'h247330000067; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2478 = 48'h247330000067; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2479 = 48'h247330000067; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_183 = 48'h247330000067; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_181 = 40'h7330000067; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2469 = 40'h7330000067; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2470 = 40'h7330000067; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_182 = 40'h7330000067; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_180 = 32'h30000067; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2460 = 32'h30000067; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2461 = 32'h30000067; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_181 = 32'h30000067; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_179 = 24'h67; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2451 = 24'h67; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2452 = 24'h67; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_180 = 24'h67; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_178 = 16'h67; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2442 = 16'h67; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2443 = 16'h67; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_179 = 16'h67; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2433 = 8'h67; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2434 = 8'h67; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_178 = 8'h67; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_163 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2248 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2249 = 64'h4004440310802023; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_162 = 56'h4440310802023; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2239 = 56'h4440310802023; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2240 = 56'h4440310802023; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_163 = 56'h4440310802023; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_161 = 48'h440310802023; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2230 = 48'h440310802023; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2231 = 48'h440310802023; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_162 = 48'h440310802023; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_160 = 40'h310802023; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2221 = 40'h310802023; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2222 = 40'h310802023; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_161 = 40'h310802023; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_159 = 32'h10802023; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2212 = 32'h10802023; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2213 = 32'h10802023; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_160 = 32'h10802023; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_158 = 24'h802023; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2203 = 24'h802023; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2204 = 24'h802023; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_159 = 24'h802023; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_157 = 16'h2023; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2194 = 16'h2023; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2195 = 16'h2023; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_158 = 16'h2023; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_156 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2176 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2177 = 64'h100026237B200073; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_155 = 56'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2167 = 56'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2168 = 56'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_156 = 56'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_154 = 48'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2158 = 48'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2159 = 48'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_155 = 48'h26237B200073; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_153 = 40'h237B200073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2149 = 40'h237B200073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2150 = 40'h237B200073; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_154 = 40'h237B200073; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_152 = 32'h7B200073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2140 = 32'h7B200073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2141 = 32'h7B200073; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_153 = 32'h7B200073; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_151 = 24'h200073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2131 = 24'h200073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2132 = 24'h200073; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_152 = 24'h200073; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_142 = 64'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2016 = 64'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2017 = 64'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_141 = 56'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2007 = 56'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2008 = 56'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_142 = 56'h4086300147413; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_140 = 48'h86300147413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1998 = 48'h86300147413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1999 = 48'h86300147413; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_141 = 48'h86300147413; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_139 = 40'h6300147413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1989 = 40'h6300147413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1990 = 40'h6300147413; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_140 = 40'h6300147413; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_138 = 32'h147413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1980 = 32'h147413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1981 = 32'h147413; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_139 = 32'h147413; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_137 = 24'h147413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1971 = 24'h147413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1972 = 24'h147413; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_138 = 24'h147413; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_128 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_1856 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_1857 = 64'hFF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_127 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_1847 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_1848 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_128 = 56'hF0000F0440006F; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_126 = 48'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1838 = 48'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1839 = 48'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_127 = 48'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_125 = 40'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1829 = 40'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1830 = 40'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_126 = 40'hF0440006F; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_124 = 32'h440006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1820 = 32'h440006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1821 = 32'h440006F; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_125 = 32'h440006F; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_123 = 24'h40006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1811 = 24'h40006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1812 = 24'h40006F; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_124 = 24'h40006F; // @[RegisterRouter.scala:87:24]
wire [8:0] out_maskMatch_1 = 9'h20; // @[RegisterRouter.scala:87:24]
wire [11:0] hi = 12'h38; // @[Debug.scala:1697:55]
wire [10:0] hi_hi = 11'h1C; // @[Debug.scala:1697:55]
wire [19:0] lo = 20'h6F; // @[Debug.scala:1697:55]
wire [12:0] lo_hi = 13'h0; // @[Debug.scala:1697:55]
wire [31:0] _abstractGeneratedMem_0_T_3 = 32'h13; // @[Debug.scala:1642:15]
wire [31:0] _abstractGeneratedMem_1_T = 32'h13; // @[Debug.scala:1645:15]
wire [19:0] abstractGeneratedMem_0_hi_2 = 20'h0; // @[Debug.scala:1642:15]
wire [19:0] abstractGeneratedMem_1_hi = 20'h0; // @[Debug.scala:1645:15]
wire [16:0] abstractGeneratedMem_0_hi_hi_2 = 17'h0; // @[Debug.scala:1642:15]
wire [16:0] abstractGeneratedMem_1_hi_hi = 17'h0; // @[Debug.scala:1645:15]
wire [11:0] abstractGeneratedMem_0_lo_2 = 12'h13; // @[Debug.scala:1642:15]
wire [11:0] abstractGeneratedMem_1_lo = 12'h13; // @[Debug.scala:1645:15]
wire [6:0] abstractGeneratedMem_0_inst_1_opcode = 7'h23; // @[Debug.scala:1601:22]
wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_opcode = 7'h23; // @[Debug.scala:1604:55]
wire [4:0] _DMCS2RdData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1025:47]
wire [4:0] _DMCS2WrData_WIRE_haltgroup = 5'h0; // @[Debug.scala:1026:47]
wire [4:0] _ABSTRACTCSReset_WIRE_progbufsize = 5'h0; // @[Debug.scala:1179:48]
wire [4:0] _ABSTRACTCSWrData_WIRE_progbufsize = 5'h0; // @[Debug.scala:1184:52]
wire [4:0] ABSTRACTCSWrData_progbufsize = 5'h0; // @[Debug.scala:1184:39]
wire [4:0] _jalAbstract_WIRE_rd = 5'h0; // @[Debug.scala:1497:66]
wire [4:0] jalAbstract_rd = 5'h0; // @[Debug.scala:1497:32]
wire [4:0] jalAbstract_imm0_hi = 5'h0; // @[package.scala:45:27]
wire [4:0] jalAbstract_imm1_lo = 5'h0; // @[package.scala:45:27]
wire [4:0] jalAbstract_imm1_hi = 5'h0; // @[package.scala:45:27]
wire [4:0] nop_rs1 = 5'h0; // @[Debug.scala:1623:19]
wire [4:0] nop_rd = 5'h0; // @[Debug.scala:1623:19]
wire [4:0] _nop_WIRE_rs1 = 5'h0; // @[Debug.scala:1624:46]
wire [4:0] _nop_WIRE_rd = 5'h0; // @[Debug.scala:1624:46]
wire [4:0] isa_rs1 = 5'h0; // @[Debug.scala:1629:19]
wire [4:0] isa_rd = 5'h0; // @[Debug.scala:1629:19]
wire [4:0] _isa_WIRE_rs1 = 5'h0; // @[Debug.scala:1630:47]
wire [4:0] _isa_WIRE_rd = 5'h0; // @[Debug.scala:1630:47]
wire [4:0] abstractGeneratedMem_0_inst_rs1 = 5'h0; // @[Debug.scala:1589:22]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rs1 = 5'h0; // @[Debug.scala:1592:55]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_rd = 5'h0; // @[Debug.scala:1592:55]
wire [4:0] abstractGeneratedMem_0_inst_1_rs1 = 5'h0; // @[Debug.scala:1601:22]
wire [4:0] abstractGeneratedMem_0_inst_1_immlo = 5'h0; // @[Debug.scala:1601:22]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs2 = 5'h0; // @[Debug.scala:1604:55]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_rs1 = 5'h0; // @[Debug.scala:1604:55]
wire [4:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immlo = 5'h0; // @[Debug.scala:1604:55]
wire [2:0] SBCSFieldsRegReset_sbaccess = 3'h2; // @[SBA.scala:49:38]
wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_funct3 = 3'h2; // @[Debug.scala:1592:55]
wire [2:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_funct3 = 3'h2; // @[Debug.scala:1604:55]
wire [6:0] _SBCSFieldsRegReset_WIRE_sbasize = 7'h0; // @[SBA.scala:49:51]
wire [6:0] _SBCSRdData_WIRE_sbasize = 7'h0; // @[SBA.scala:60:51]
wire [6:0] _SBCSWrData_WIRE_sbasize = 7'h0; // @[SBA.scala:63:61]
wire [6:0] _SBCSWrData_T_5 = 7'h0; // @[SBA.scala:63:61]
wire [6:0] SBCSWrData_sbasize = 7'h0; // @[SBA.scala:63:38]
wire [6:0] _SBCSRdData_WIRE_1_sbasize = 7'h0; // @[SBA.scala:243:33]
wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_1_immhi = 7'h0; // @[Debug.scala:1604:55]
wire [6:0] abstractGeneratedMem_0_inst_1_immhi = 7'h1C; // @[Debug.scala:1601:22]
wire [16:0] abstractGeneratedMem_0_hi_hi = 17'h7000; // @[Debug.scala:1597:12]
wire [6:0] abstractGeneratedMem_0_inst_opcode = 7'h3; // @[Debug.scala:1589:22]
wire [6:0] _abstractGeneratedMem_0_inst_opcode_WIRE_opcode = 7'h3; // @[Debug.scala:1592:55]
wire [11:0] _ABSTRACTAUTOReset_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1234:54]
wire [11:0] ABSTRACTAUTOReset_autoexecdata = 12'h0; // @[Debug.scala:1234:41]
wire [11:0] _ABSTRACTAUTOWrData_WIRE_autoexecdata = 12'h0; // @[Debug.scala:1236:54]
wire [11:0] nop_imm = 12'h0; // @[Debug.scala:1623:19]
wire [11:0] _nop_WIRE_imm = 12'h0; // @[Debug.scala:1624:46]
wire [11:0] isa_imm = 12'h0; // @[Debug.scala:1629:19]
wire [11:0] _isa_WIRE_imm = 12'h0; // @[Debug.scala:1630:47]
wire [11:0] _abstractGeneratedMem_0_inst_opcode_WIRE_imm = 12'h0; // @[Debug.scala:1592:55]
wire [11:0] abstractGeneratedMem_0_inst_imm = 12'h380; // @[Debug.scala:1589:22]
wire [6:0] isa_opcode = 7'h1B; // @[Debug.scala:1629:19]
wire [6:0] _isa_WIRE_opcode = 7'h1B; // @[Debug.scala:1630:47]
wire [6:0] nop_opcode = 7'h13; // @[Debug.scala:1623:19]
wire [6:0] _nop_WIRE_opcode = 7'h13; // @[Debug.scala:1624:46]
wire [2:0] out_prepend_28 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_498 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_499 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_prepend_T_29 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] jalAbstract_imm0_lo_hi = 3'h7; // @[package.scala:45:27]
wire [2:0] componentSel_7 = 3'h7; // @[Debug.scala:1523:34]
wire [2:0] componentSel_6 = 3'h6; // @[Debug.scala:1523:34]
wire [2:0] componentSel_5 = 3'h5; // @[Debug.scala:1523:34]
wire [2:0] componentSel_4 = 3'h4; // @[Debug.scala:1523:34]
wire [1:0] out_prepend_27 = 2'h3; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_489 = 2'h3; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_490 = 2'h3; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_prepend_T_28 = 2'h3; // @[RegisterRouter.scala:87:24]
wire [1:0] jalAbstract_imm0_lo_hi_hi = 2'h3; // @[package.scala:45:27]
wire [1:0] componentSel_3 = 2'h3; // @[Debug.scala:1523:34]
wire [1:0] componentSel_2 = 2'h2; // @[Debug.scala:1523:34]
wire [9:0] jalAbstract_imm0 = 10'h1C; // @[Debug.scala:1497:32]
wire [9:0] _jalAbstract_imm0_T = 10'h1C; // @[package.scala:45:27]
wire [4:0] jalAbstract_imm0_lo = 5'h1C; // @[package.scala:45:27]
wire [20:0] immWire = 21'h38; // @[Debug.scala:1574:31]
wire [6:0] _jalAbstract_WIRE_opcode = 7'h6F; // @[Debug.scala:1497:66]
wire [6:0] jalAbstract_opcode = 7'h6F; // @[Debug.scala:1497:32]
wire [7:0] out_prepend_67 = 8'hA2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1033 = 8'hA2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1034 = 8'hA2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_68 = 8'hA2; // @[RegisterRouter.scala:87:24]
wire [6:0] out_prepend_66 = 7'h22; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_1024 = 7'h22; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_1025 = 7'h22; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_prepend_T_67 = 7'h22; // @[RegisterRouter.scala:87:24]
wire [5:0] out_prepend_65 = 6'h22; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_T_1015 = 6'h22; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_T_1016 = 6'h22; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_prepend_T_66 = 6'h22; // @[RegisterRouter.scala:87:24]
wire [4:0] out_prepend_64 = 5'h2; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_1006 = 5'h2; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_1007 = 5'h2; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_prepend_T_65 = 5'h2; // @[RegisterRouter.scala:87:24]
wire [3:0] DMSTATUSRdData_version = 4'h2; // @[Debug.scala:978:34]
wire [3:0] _out_T_997 = 4'h2; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_998 = 4'h2; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_prepend_T_64 = 4'h2; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend_31 = 12'h40F; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_525 = 12'h40F; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_526 = 12'h40F; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_prepend_T_32 = 12'h40F; // @[RegisterRouter.scala:87:24]
wire [4:0] out_prepend_30 = 5'hF; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_516 = 5'hF; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_517 = 5'hF; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_prepend_T_31 = 5'hF; // @[RegisterRouter.scala:87:24]
wire [3:0] out_prepend_29 = 4'hF; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_507 = 4'hF; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_508 = 4'hF; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_prepend_T_30 = 4'hF; // @[RegisterRouter.scala:87:24]
wire [6:0] out_maskMatch = 7'h40; // @[RegisterRouter.scala:87:24]
wire [23:0] _COMMANDReset_WIRE_control = 24'h0; // @[Debug.scala:1276:45]
wire [23:0] COMMANDReset_control = 24'h0; // @[Debug.scala:1276:32]
wire [20:0] _DMCS2RdData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1025:47]
wire [20:0] DMCS2RdData_reserved0 = 21'h0; // @[Debug.scala:1025:34]
wire [20:0] _DMCS2WrData_WIRE_reserved0 = 21'h0; // @[Debug.scala:1026:47]
wire [20:0] DMCS2WrData_reserved0 = 21'h0; // @[Debug.scala:1026:34]
wire [8:0] _DMSTATUSRdData_WIRE_reserved0 = 9'h0; // @[Debug.scala:978:47]
wire [8:0] DMSTATUSRdData_reserved0 = 9'h0; // @[Debug.scala:978:34]
wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[Debug.scala:790:9]
wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[Debug.scala:790:9]
wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[Debug.scala:790:9]
wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[Debug.scala:790:9]
wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[Debug.scala:790:9]
wire [11:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[Debug.scala:790:9]
wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[Debug.scala:790:9]
wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[Debug.scala:790:9]
wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[Debug.scala:790:9]
wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[Debug.scala:790:9]
wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] tlNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire dmiNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire dmiNodeIn_a_valid = auto_dmi_in_a_valid_0; // @[Debug.scala:790:9]
wire [2:0] dmiNodeIn_a_bits_opcode = auto_dmi_in_a_bits_opcode_0; // @[Debug.scala:790:9]
wire [2:0] dmiNodeIn_a_bits_param = auto_dmi_in_a_bits_param_0; // @[Debug.scala:790:9]
wire [1:0] dmiNodeIn_a_bits_size = auto_dmi_in_a_bits_size_0; // @[Debug.scala:790:9]
wire dmiNodeIn_a_bits_source = auto_dmi_in_a_bits_source_0; // @[Debug.scala:790:9]
wire [8:0] dmiNodeIn_a_bits_address = auto_dmi_in_a_bits_address_0; // @[Debug.scala:790:9]
wire [3:0] dmiNodeIn_a_bits_mask = auto_dmi_in_a_bits_mask_0; // @[Debug.scala:790:9]
wire [31:0] dmiNodeIn_a_bits_data = auto_dmi_in_a_bits_data_0; // @[Debug.scala:790:9]
wire dmiNodeIn_a_bits_corrupt = auto_dmi_in_a_bits_corrupt_0; // @[Debug.scala:790:9]
wire dmiNodeIn_d_ready = auto_dmi_in_d_ready_0; // @[Debug.scala:790:9]
wire dmiNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] dmiNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] dmiNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] dmiNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire _resumereq_T = io_innerCtrl_valid_0; // @[Decoupled.scala:51:35]
wire [2:0] auto_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:790:9]
wire [3:0] auto_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:790:9]
wire [31:0] auto_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:790:9]
wire [7:0] auto_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_a_valid_0; // @[Debug.scala:790:9]
wire auto_sb2tlOpt_out_d_ready_0; // @[Debug.scala:790:9]
wire auto_tl_in_a_ready_0; // @[Debug.scala:790:9]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[Debug.scala:790:9]
wire [1:0] auto_tl_in_d_bits_size_0; // @[Debug.scala:790:9]
wire [10:0] auto_tl_in_d_bits_source_0; // @[Debug.scala:790:9]
wire [63:0] auto_tl_in_d_bits_data_0; // @[Debug.scala:790:9]
wire auto_tl_in_d_valid_0; // @[Debug.scala:790:9]
wire auto_dmi_in_a_ready_0; // @[Debug.scala:790:9]
wire [2:0] auto_dmi_in_d_bits_opcode_0; // @[Debug.scala:790:9]
wire [1:0] auto_dmi_in_d_bits_size_0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_bits_source_0; // @[Debug.scala:790:9]
wire [31:0] auto_dmi_in_d_bits_data_0; // @[Debug.scala:790:9]
wire auto_dmi_in_d_valid_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_0_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_1_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_2_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_3_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_4_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_5_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_6_0; // @[Debug.scala:790:9]
wire io_hgDebugInt_7_0; // @[Debug.scala:790:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_dmi_in_a_ready_0 = dmiNodeIn_a_ready; // @[Debug.scala:790:9]
wire in_valid = dmiNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = dmiNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire in_bits_extra_tlrr_extra_source = dmiNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [3:0] in_bits_mask = dmiNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [31:0] in_bits_data = dmiNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = dmiNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_dmi_in_d_valid_0 = dmiNodeIn_d_valid; // @[Debug.scala:790:9]
assign auto_dmi_in_d_bits_opcode_0 = dmiNodeIn_d_bits_opcode; // @[Debug.scala:790:9]
wire [1:0] dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_dmi_in_d_bits_size_0 = dmiNodeIn_d_bits_size; // @[Debug.scala:790:9]
wire dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_dmi_in_d_bits_source_0 = dmiNodeIn_d_bits_source; // @[Debug.scala:790:9]
wire [31:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_dmi_in_d_bits_data_0 = dmiNodeIn_d_bits_data; // @[Debug.scala:790:9]
wire in_1_ready; // @[RegisterRouter.scala:73:18]
assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[Debug.scala:790:9]
wire in_1_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_1_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_1_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_1_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_1_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_1_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_1_valid; // @[RegisterRouter.scala:87:24]
assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[Debug.scala:790:9]
assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[Debug.scala:790:9]
wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[Debug.scala:790:9]
wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[Debug.scala:790:9]
wire [63:0] out_1_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_tl_in_d_bits_data_0 = tlNodeIn_d_bits_data; // @[Debug.scala:790:9]
reg [7:0] haltedBitRegs; // @[Debug.scala:861:31]
wire [7:0] _haltedStatus_0_T = haltedBitRegs; // @[Debug.scala:861:31, :1163:43]
reg [7:0] resumeReqRegs; // @[Debug.scala:863:31]
reg [7:0] haveResetBitRegs; // @[Debug.scala:865:31]
wire [7:0] resumeAcks; // @[Debug.scala:869:32]
wire out_f_woready_309; // @[RegisterRouter.scala:87:24]
wire hartHaltedWrEn; // @[Debug.scala:875:36]
wire [9:0] _out_T_3289; // @[RegisterRouter.scala:87:24]
wire [9:0] hartHaltedId; // @[Debug.scala:876:36]
wire out_f_woready_310; // @[RegisterRouter.scala:87:24]
wire hartGoingWrEn; // @[Debug.scala:877:36]
wire [9:0] _out_T_3298; // @[RegisterRouter.scala:87:24]
wire [9:0] hartGoingId; // @[Debug.scala:878:36]
wire out_f_woready_270; // @[RegisterRouter.scala:87:24]
wire hartResumingWrEn; // @[Debug.scala:879:36]
wire [9:0] _out_T_2906; // @[RegisterRouter.scala:87:24]
wire [9:0] hartResumingId; // @[Debug.scala:880:36]
wire out_f_woready_271; // @[RegisterRouter.scala:87:24]
wire hartExceptionWrEn; // @[Debug.scala:881:36]
wire [9:0] _out_T_2915; // @[RegisterRouter.scala:87:24]
wire [9:0] hartExceptionId; // @[Debug.scala:882:36]
wire out_f_roready_105; // @[RegisterRouter.scala:87:24]
wire out_f_roready_106; // @[RegisterRouter.scala:87:24]
wire out_f_roready_107; // @[RegisterRouter.scala:87:24]
wire out_f_roready_108; // @[RegisterRouter.scala:87:24]
wire out_f_roready_77; // @[RegisterRouter.scala:87:24]
wire out_f_roready_78; // @[RegisterRouter.scala:87:24]
wire out_f_roready_79; // @[RegisterRouter.scala:87:24]
wire out_f_roready_80; // @[RegisterRouter.scala:87:24]
wire out_f_roready_109; // @[RegisterRouter.scala:87:24]
wire out_f_roready_110; // @[RegisterRouter.scala:87:24]
wire out_f_roready_111; // @[RegisterRouter.scala:87:24]
wire out_f_roready_112; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_16; // @[RegisterRouter.scala:87:24]
wire out_f_roready_145; // @[RegisterRouter.scala:87:24]
wire out_f_roready_146; // @[RegisterRouter.scala:87:24]
wire out_f_roready_147; // @[RegisterRouter.scala:87:24]
wire out_f_roready_148; // @[RegisterRouter.scala:87:24]
wire out_f_roready_59; // @[RegisterRouter.scala:87:24]
wire out_f_roready_60; // @[RegisterRouter.scala:87:24]
wire out_f_roready_61; // @[RegisterRouter.scala:87:24]
wire out_f_roready_62; // @[RegisterRouter.scala:87:24]
wire out_f_roready_73; // @[RegisterRouter.scala:87:24]
wire out_f_roready_74; // @[RegisterRouter.scala:87:24]
wire out_f_roready_75; // @[RegisterRouter.scala:87:24]
wire out_f_roready_76; // @[RegisterRouter.scala:87:24]
wire out_f_roready_128; // @[RegisterRouter.scala:87:24]
wire out_f_roready_129; // @[RegisterRouter.scala:87:24]
wire out_f_roready_130; // @[RegisterRouter.scala:87:24]
wire out_f_roready_131; // @[RegisterRouter.scala:87:24]
wire out_f_roready_140; // @[RegisterRouter.scala:87:24]
wire out_f_roready_141; // @[RegisterRouter.scala:87:24]
wire out_f_roready_142; // @[RegisterRouter.scala:87:24]
wire out_f_roready_143; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_roready_52; // @[RegisterRouter.scala:87:24]
wire out_f_roready_53; // @[RegisterRouter.scala:87:24]
wire out_f_roready_54; // @[RegisterRouter.scala:87:24]
wire out_f_roready_55; // @[RegisterRouter.scala:87:24]
wire out_f_roready_136; // @[RegisterRouter.scala:87:24]
wire out_f_roready_137; // @[RegisterRouter.scala:87:24]
wire out_f_roready_138; // @[RegisterRouter.scala:87:24]
wire out_f_roready_139; // @[RegisterRouter.scala:87:24]
wire out_f_roready_120; // @[RegisterRouter.scala:87:24]
wire out_f_roready_121; // @[RegisterRouter.scala:87:24]
wire out_f_roready_122; // @[RegisterRouter.scala:87:24]
wire out_f_roready_123; // @[RegisterRouter.scala:87:24]
wire out_f_roready_81; // @[RegisterRouter.scala:87:24]
wire out_f_roready_82; // @[RegisterRouter.scala:87:24]
wire out_f_roready_83; // @[RegisterRouter.scala:87:24]
wire out_f_roready_84; // @[RegisterRouter.scala:87:24]
wire out_f_roready_63; // @[RegisterRouter.scala:87:24]
wire out_f_roready_64; // @[RegisterRouter.scala:87:24]
wire out_f_roready_65; // @[RegisterRouter.scala:87:24]
wire out_f_roready_66; // @[RegisterRouter.scala:87:24]
wire out_f_roready_29; // @[RegisterRouter.scala:87:24]
wire out_f_roready_30; // @[RegisterRouter.scala:87:24]
wire out_f_roready_31; // @[RegisterRouter.scala:87:24]
wire out_f_roready_32; // @[RegisterRouter.scala:87:24]
wire dmiProgramBufferRdEn_0; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_1; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_2; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_3; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_4; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_5; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_6; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_7; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_8; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_9; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_10; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_11; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_12; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_13; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_14; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_15; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_16; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_17; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_18; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_19; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_20; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_21; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_22; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_23; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_24; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_25; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_26; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_27; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_28; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_29; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_30; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_31; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_32; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_33; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_34; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_35; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_36; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_37; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_38; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_39; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_40; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_41; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_42; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_43; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_44; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_45; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_46; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_47; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_48; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_49; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_50; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_51; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_52; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_53; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_54; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_55; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_56; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_57; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_58; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_59; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_60; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_61; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_62; // @[Debug.scala:887:40]
wire dmiProgramBufferRdEn_63; // @[Debug.scala:887:40]
wire _dmiProgramBufferAccessLegal_T; // @[Debug.scala:1746:50]
wire dmiProgramBufferAccessLegal; // @[Debug.scala:888:47]
wire out_f_woready_105; // @[RegisterRouter.scala:87:24]
wire out_f_woready_106; // @[RegisterRouter.scala:87:24]
wire out_f_woready_107; // @[RegisterRouter.scala:87:24]
wire out_f_woready_108; // @[RegisterRouter.scala:87:24]
wire out_f_woready_77; // @[RegisterRouter.scala:87:24]
wire out_f_woready_78; // @[RegisterRouter.scala:87:24]
wire out_f_woready_79; // @[RegisterRouter.scala:87:24]
wire out_f_woready_80; // @[RegisterRouter.scala:87:24]
wire out_f_woready_109; // @[RegisterRouter.scala:87:24]
wire out_f_woready_110; // @[RegisterRouter.scala:87:24]
wire out_f_woready_111; // @[RegisterRouter.scala:87:24]
wire out_f_woready_112; // @[RegisterRouter.scala:87:24]
wire out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_16; // @[RegisterRouter.scala:87:24]
wire out_f_woready_145; // @[RegisterRouter.scala:87:24]
wire out_f_woready_146; // @[RegisterRouter.scala:87:24]
wire out_f_woready_147; // @[RegisterRouter.scala:87:24]
wire out_f_woready_148; // @[RegisterRouter.scala:87:24]
wire out_f_woready_59; // @[RegisterRouter.scala:87:24]
wire out_f_woready_60; // @[RegisterRouter.scala:87:24]
wire out_f_woready_61; // @[RegisterRouter.scala:87:24]
wire out_f_woready_62; // @[RegisterRouter.scala:87:24]
wire out_f_woready_73; // @[RegisterRouter.scala:87:24]
wire out_f_woready_74; // @[RegisterRouter.scala:87:24]
wire out_f_woready_75; // @[RegisterRouter.scala:87:24]
wire out_f_woready_76; // @[RegisterRouter.scala:87:24]
wire out_f_woready_128; // @[RegisterRouter.scala:87:24]
wire out_f_woready_129; // @[RegisterRouter.scala:87:24]
wire out_f_woready_130; // @[RegisterRouter.scala:87:24]
wire out_f_woready_131; // @[RegisterRouter.scala:87:24]
wire out_f_woready_140; // @[RegisterRouter.scala:87:24]
wire out_f_woready_141; // @[RegisterRouter.scala:87:24]
wire out_f_woready_142; // @[RegisterRouter.scala:87:24]
wire out_f_woready_143; // @[RegisterRouter.scala:87:24]
wire out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire out_f_woready_52; // @[RegisterRouter.scala:87:24]
wire out_f_woready_53; // @[RegisterRouter.scala:87:24]
wire out_f_woready_54; // @[RegisterRouter.scala:87:24]
wire out_f_woready_55; // @[RegisterRouter.scala:87:24]
wire out_f_woready_136; // @[RegisterRouter.scala:87:24]
wire out_f_woready_137; // @[RegisterRouter.scala:87:24]
wire out_f_woready_138; // @[RegisterRouter.scala:87:24]
wire out_f_woready_139; // @[RegisterRouter.scala:87:24]
wire out_f_woready_120; // @[RegisterRouter.scala:87:24]
wire out_f_woready_121; // @[RegisterRouter.scala:87:24]
wire out_f_woready_122; // @[RegisterRouter.scala:87:24]
wire out_f_woready_123; // @[RegisterRouter.scala:87:24]
wire out_f_woready_81; // @[RegisterRouter.scala:87:24]
wire out_f_woready_82; // @[RegisterRouter.scala:87:24]
wire out_f_woready_83; // @[RegisterRouter.scala:87:24]
wire out_f_woready_84; // @[RegisterRouter.scala:87:24]
wire out_f_woready_63; // @[RegisterRouter.scala:87:24]
wire out_f_woready_64; // @[RegisterRouter.scala:87:24]
wire out_f_woready_65; // @[RegisterRouter.scala:87:24]
wire out_f_woready_66; // @[RegisterRouter.scala:87:24]
wire out_f_woready_29; // @[RegisterRouter.scala:87:24]
wire out_f_woready_30; // @[RegisterRouter.scala:87:24]
wire out_f_woready_31; // @[RegisterRouter.scala:87:24]
wire out_f_woready_32; // @[RegisterRouter.scala:87:24]
wire dmiProgramBufferWrEnMaybe_0; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_1; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_2; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_3; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_4; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_5; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_6; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_7; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_8; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_9; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_10; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_11; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_12; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_13; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_14; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_15; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_16; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_17; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_18; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_19; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_20; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_21; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_22; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_23; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_24; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_25; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_26; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_27; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_28; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_29; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_30; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_31; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_32; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_33; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_34; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_35; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_36; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_37; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_38; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_39; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_40; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_41; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_42; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_43; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_44; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_45; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_46; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_47; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_48; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_49; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_50; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_51; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_52; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_53; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_54; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_55; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_56; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_57; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_58; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_59; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_60; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_61; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_62; // @[Debug.scala:889:45]
wire dmiProgramBufferWrEnMaybe_63; // @[Debug.scala:889:45]
wire out_f_roready_25; // @[RegisterRouter.scala:87:24]
wire out_f_roready_26; // @[RegisterRouter.scala:87:24]
wire out_f_roready_27; // @[RegisterRouter.scala:87:24]
wire out_f_roready_28; // @[RegisterRouter.scala:87:24]
wire out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_68; // @[RegisterRouter.scala:87:24]
wire out_f_roready_69; // @[RegisterRouter.scala:87:24]
wire out_f_roready_70; // @[RegisterRouter.scala:87:24]
wire out_f_roready_71; // @[RegisterRouter.scala:87:24]
wire out_f_roready_124; // @[RegisterRouter.scala:87:24]
wire out_f_roready_125; // @[RegisterRouter.scala:87:24]
wire out_f_roready_126; // @[RegisterRouter.scala:87:24]
wire out_f_roready_127; // @[RegisterRouter.scala:87:24]
wire out_f_roready_21; // @[RegisterRouter.scala:87:24]
wire out_f_roready_22; // @[RegisterRouter.scala:87:24]
wire out_f_roready_23; // @[RegisterRouter.scala:87:24]
wire out_f_roready_24; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_33; // @[RegisterRouter.scala:87:24]
wire out_f_roready_34; // @[RegisterRouter.scala:87:24]
wire out_f_roready_35; // @[RegisterRouter.scala:87:24]
wire out_f_roready_36; // @[RegisterRouter.scala:87:24]
wire out_f_roready_132; // @[RegisterRouter.scala:87:24]
wire out_f_roready_133; // @[RegisterRouter.scala:87:24]
wire out_f_roready_134; // @[RegisterRouter.scala:87:24]
wire out_f_roready_135; // @[RegisterRouter.scala:87:24]
wire dmiAbstractDataRdEn_0; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_1; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_2; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_3; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_4; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_5; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_6; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_7; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_8; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_9; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_10; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_11; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_12; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_13; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_14; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_15; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_16; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_17; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_18; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_19; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_20; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_21; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_22; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_23; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_24; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_25; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_26; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_27; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_28; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_29; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_30; // @[Debug.scala:891:39]
wire dmiAbstractDataRdEn_31; // @[Debug.scala:891:39]
wire _dmiAbstractDataAccessLegal_T; // @[Debug.scala:1745:50]
wire dmiAbstractDataAccessLegal; // @[Debug.scala:892:46]
wire out_f_woready_25; // @[RegisterRouter.scala:87:24]
wire out_f_woready_26; // @[RegisterRouter.scala:87:24]
wire out_f_woready_27; // @[RegisterRouter.scala:87:24]
wire out_f_woready_28; // @[RegisterRouter.scala:87:24]
wire out_f_woready; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_68; // @[RegisterRouter.scala:87:24]
wire out_f_woready_69; // @[RegisterRouter.scala:87:24]
wire out_f_woready_70; // @[RegisterRouter.scala:87:24]
wire out_f_woready_71; // @[RegisterRouter.scala:87:24]
wire out_f_woready_124; // @[RegisterRouter.scala:87:24]
wire out_f_woready_125; // @[RegisterRouter.scala:87:24]
wire out_f_woready_126; // @[RegisterRouter.scala:87:24]
wire out_f_woready_127; // @[RegisterRouter.scala:87:24]
wire out_f_woready_21; // @[RegisterRouter.scala:87:24]
wire out_f_woready_22; // @[RegisterRouter.scala:87:24]
wire out_f_woready_23; // @[RegisterRouter.scala:87:24]
wire out_f_woready_24; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_33; // @[RegisterRouter.scala:87:24]
wire out_f_woready_34; // @[RegisterRouter.scala:87:24]
wire out_f_woready_35; // @[RegisterRouter.scala:87:24]
wire out_f_woready_36; // @[RegisterRouter.scala:87:24]
wire out_f_woready_132; // @[RegisterRouter.scala:87:24]
wire out_f_woready_133; // @[RegisterRouter.scala:87:24]
wire out_f_woready_134; // @[RegisterRouter.scala:87:24]
wire out_f_woready_135; // @[RegisterRouter.scala:87:24]
wire dmiAbstractDataWrEnMaybe_0; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_1; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_2; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_3; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_4; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_5; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_6; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_7; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_8; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_9; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_10; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_11; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_12; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_13; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_14; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_15; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_16; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_17; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_18; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_19; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_20; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_21; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_22; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_23; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_24; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_25; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_26; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_27; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_28; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_29; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_30; // @[Debug.scala:893:44]
wire dmiAbstractDataWrEnMaybe_31; // @[Debug.scala:893:44]
reg [2:0] selectedHartReg; // @[Debug.scala:901:30]
wire hamaskFull_0; // @[Debug.scala:903:30]
wire hamaskFull_1; // @[Debug.scala:903:30]
wire hamaskFull_2; // @[Debug.scala:903:30]
wire hamaskFull_3; // @[Debug.scala:903:30]
wire hamaskFull_4; // @[Debug.scala:903:30]
wire hamaskFull_5; // @[Debug.scala:903:30]
wire hamaskFull_6; // @[Debug.scala:903:30]
wire hamaskFull_7; // @[Debug.scala:903:30]
reg hamaskReg_0; // @[Debug.scala:915:26]
reg hamaskReg_1; // @[Debug.scala:915:26]
reg hamaskReg_2; // @[Debug.scala:915:26]
reg hamaskReg_3; // @[Debug.scala:915:26]
reg hamaskReg_4; // @[Debug.scala:915:26]
reg hamaskReg_5; // @[Debug.scala:915:26]
reg hamaskReg_6; // @[Debug.scala:915:26]
reg hamaskReg_7; // @[Debug.scala:915:26]
wire _GEN = selectedHartReg == 3'h0; // @[Debug.scala:901:30, :926:71]
assign hamaskFull_0 = _GEN | hamaskReg_0; // @[Debug.scala:903:30, :915:26, :921:18, :926:71]
wire _GEN_0 = selectedHartReg == 3'h1; // @[Debug.scala:901:30, :926:71]
assign hamaskFull_1 = _GEN_0 | hamaskReg_1; // @[Debug.scala:903:30, :915:26, :921:18, :926:71]
wire _GEN_1 = selectedHartReg == 3'h2; // @[Debug.scala:901:30, :926:71]
assign hamaskFull_2 = _GEN_1 | hamaskReg_2; // @[Debug.scala:903:30, :915:26, :921:18, :926:71]
wire _GEN_2 = selectedHartReg == 3'h3; // @[Debug.scala:901:30, :926:71]
assign hamaskFull_3 = _GEN_2 | hamaskReg_3; // @[Debug.scala:903:30, :915:26, :921:18, :926:71]
wire _GEN_3 = selectedHartReg == 3'h4; // @[Debug.scala:901:30, :926:71]
assign hamaskFull_4 = _GEN_3 | hamaskReg_4; // @[Debug.scala:903:30, :915:26, :921:18, :926:71]
wire _GEN_4 = selectedHartReg == 3'h5; // @[Debug.scala:901:30, :926:71]
assign hamaskFull_5 = _GEN_4 | hamaskReg_5; // @[Debug.scala:903:30, :915:26, :921:18, :926:71]
wire _GEN_5 = selectedHartReg == 3'h6; // @[Debug.scala:901:30, :926:71]
assign hamaskFull_6 = _GEN_5 | hamaskReg_6; // @[Debug.scala:903:30, :915:26, :921:18, :926:71]
assign hamaskFull_7 = (&selectedHartReg) | hamaskReg_7; // @[Debug.scala:901:30, :903:30, :915:26, :921:18, :926:71]
wire _hamaskWrSel_0_T_2; // @[Debug.scala:935:78]
wire _hamaskWrSel_1_T_2; // @[Debug.scala:935:78]
wire _hamaskWrSel_2_T_2; // @[Debug.scala:935:78]
wire _hamaskWrSel_3_T_2; // @[Debug.scala:935:78]
wire _hamaskWrSel_4_T_2; // @[Debug.scala:935:78]
wire _hamaskWrSel_5_T_2; // @[Debug.scala:935:78]
wire _hamaskWrSel_6_T_2; // @[Debug.scala:935:78]
wire _hamaskWrSel_7_T_2; // @[Debug.scala:935:78]
wire hamaskWrSel_0; // @[Debug.scala:933:31]
wire hamaskWrSel_1; // @[Debug.scala:933:31]
wire hamaskWrSel_2; // @[Debug.scala:933:31]
wire hamaskWrSel_3; // @[Debug.scala:933:31]
wire hamaskWrSel_4; // @[Debug.scala:933:31]
wire hamaskWrSel_5; // @[Debug.scala:933:31]
wire hamaskWrSel_6; // @[Debug.scala:933:31]
wire hamaskWrSel_7; // @[Debug.scala:933:31]
wire _hamaskWrSel_0_T = io_innerCtrl_bits_hartsel_0 == 10'h0; // @[Debug.scala:790:9, :935:61]
wire _hamaskWrSel_0_T_1 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_0_0; // @[Debug.scala:790:9, :936:56]
assign _hamaskWrSel_0_T_2 = _hamaskWrSel_0_T | _hamaskWrSel_0_T_1; // @[Debug.scala:935:{61,78}, :936:56]
assign hamaskWrSel_0 = _hamaskWrSel_0_T_2; // @[Debug.scala:933:31, :935:78]
wire _hamaskWrSel_1_T = io_innerCtrl_bits_hartsel_0 == 10'h1; // @[Debug.scala:790:9, :935:61]
wire _hamaskWrSel_1_T_1 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_1_0; // @[Debug.scala:790:9, :936:56]
assign _hamaskWrSel_1_T_2 = _hamaskWrSel_1_T | _hamaskWrSel_1_T_1; // @[Debug.scala:935:{61,78}, :936:56]
assign hamaskWrSel_1 = _hamaskWrSel_1_T_2; // @[Debug.scala:933:31, :935:78]
wire _hamaskWrSel_2_T = io_innerCtrl_bits_hartsel_0 == 10'h2; // @[Debug.scala:790:9, :935:61]
wire _hamaskWrSel_2_T_1 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_2_0; // @[Debug.scala:790:9, :936:56]
assign _hamaskWrSel_2_T_2 = _hamaskWrSel_2_T | _hamaskWrSel_2_T_1; // @[Debug.scala:935:{61,78}, :936:56]
assign hamaskWrSel_2 = _hamaskWrSel_2_T_2; // @[Debug.scala:933:31, :935:78]
wire _hamaskWrSel_3_T = io_innerCtrl_bits_hartsel_0 == 10'h3; // @[Debug.scala:790:9, :935:61]
wire _hamaskWrSel_3_T_1 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_3_0; // @[Debug.scala:790:9, :936:56]
assign _hamaskWrSel_3_T_2 = _hamaskWrSel_3_T | _hamaskWrSel_3_T_1; // @[Debug.scala:935:{61,78}, :936:56]
assign hamaskWrSel_3 = _hamaskWrSel_3_T_2; // @[Debug.scala:933:31, :935:78]
wire _hamaskWrSel_4_T = io_innerCtrl_bits_hartsel_0 == 10'h4; // @[Debug.scala:790:9, :935:61]
wire _hamaskWrSel_4_T_1 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_4_0; // @[Debug.scala:790:9, :936:56]
assign _hamaskWrSel_4_T_2 = _hamaskWrSel_4_T | _hamaskWrSel_4_T_1; // @[Debug.scala:935:{61,78}, :936:56]
assign hamaskWrSel_4 = _hamaskWrSel_4_T_2; // @[Debug.scala:933:31, :935:78]
wire _hamaskWrSel_5_T = io_innerCtrl_bits_hartsel_0 == 10'h5; // @[Debug.scala:790:9, :935:61]
wire _hamaskWrSel_5_T_1 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_5_0; // @[Debug.scala:790:9, :936:56]
assign _hamaskWrSel_5_T_2 = _hamaskWrSel_5_T | _hamaskWrSel_5_T_1; // @[Debug.scala:935:{61,78}, :936:56]
assign hamaskWrSel_5 = _hamaskWrSel_5_T_2; // @[Debug.scala:933:31, :935:78]
wire _hamaskWrSel_6_T = io_innerCtrl_bits_hartsel_0 == 10'h6; // @[Debug.scala:790:9, :935:61]
wire _hamaskWrSel_6_T_1 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_6_0; // @[Debug.scala:790:9, :936:56]
assign _hamaskWrSel_6_T_2 = _hamaskWrSel_6_T | _hamaskWrSel_6_T_1; // @[Debug.scala:935:{61,78}, :936:56]
assign hamaskWrSel_6 = _hamaskWrSel_6_T_2; // @[Debug.scala:933:31, :935:78]
wire _hamaskWrSel_7_T = io_innerCtrl_bits_hartsel_0 == 10'h7; // @[Debug.scala:790:9, :935:61]
wire _hamaskWrSel_7_T_1 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_7_0; // @[Debug.scala:790:9, :936:56]
assign _hamaskWrSel_7_T_2 = _hamaskWrSel_7_T | _hamaskWrSel_7_T_1; // @[Debug.scala:935:{61,78}, :936:56]
assign hamaskWrSel_7 = _hamaskWrSel_7_T_2; // @[Debug.scala:933:31, :935:78]
wire hrDebugInt_0; // @[Debug.scala:946:26]
wire hrDebugInt_1; // @[Debug.scala:946:26]
wire hrDebugInt_2; // @[Debug.scala:946:26]
wire hrDebugInt_3; // @[Debug.scala:946:26]
wire hrDebugInt_4; // @[Debug.scala:946:26]
wire hrDebugInt_5; // @[Debug.scala:946:26]
wire hrDebugInt_6; // @[Debug.scala:946:26]
wire hrDebugInt_7; // @[Debug.scala:946:26]
reg hrmaskReg_0; // @[Debug.scala:947:29]
reg hrmaskReg_1; // @[Debug.scala:947:29]
reg hrmaskReg_2; // @[Debug.scala:947:29]
reg hrmaskReg_3; // @[Debug.scala:947:29]
reg hrmaskReg_4; // @[Debug.scala:947:29]
reg hrmaskReg_5; // @[Debug.scala:947:29]
reg hrmaskReg_6; // @[Debug.scala:947:29]
reg hrmaskReg_7; // @[Debug.scala:947:29]
wire _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24]
wire _hartIsInResetSync_1_WIRE; // @[ShiftReg.scala:48:24]
wire _hartIsInResetSync_2_WIRE; // @[ShiftReg.scala:48:24]
wire _hartIsInResetSync_3_WIRE; // @[ShiftReg.scala:48:24]
wire _hartIsInResetSync_4_WIRE; // @[ShiftReg.scala:48:24]
wire _hartIsInResetSync_5_WIRE; // @[ShiftReg.scala:48:24]
wire _hartIsInResetSync_6_WIRE; // @[ShiftReg.scala:48:24]
wire _hartIsInResetSync_7_WIRE; // @[ShiftReg.scala:48:24]
wire hartIsInResetSync_0; // @[Debug.scala:948:33]
wire hartIsInResetSync_1; // @[Debug.scala:948:33]
wire hartIsInResetSync_2; // @[Debug.scala:948:33]
wire hartIsInResetSync_3; // @[Debug.scala:948:33]
wire hartIsInResetSync_4; // @[Debug.scala:948:33]
wire hartIsInResetSync_5; // @[Debug.scala:948:33]
wire hartIsInResetSync_6; // @[Debug.scala:948:33]
wire hartIsInResetSync_7; // @[Debug.scala:948:33]
assign hartIsInResetSync_0 = _hartIsInResetSync_0_WIRE; // @[ShiftReg.scala:48:24]
assign hartIsInResetSync_1 = _hartIsInResetSync_1_WIRE; // @[ShiftReg.scala:48:24]
assign hartIsInResetSync_2 = _hartIsInResetSync_2_WIRE; // @[ShiftReg.scala:48:24]
assign hartIsInResetSync_3 = _hartIsInResetSync_3_WIRE; // @[ShiftReg.scala:48:24]
assign hartIsInResetSync_4 = _hartIsInResetSync_4_WIRE; // @[ShiftReg.scala:48:24]
assign hartIsInResetSync_5 = _hartIsInResetSync_5_WIRE; // @[ShiftReg.scala:48:24]
assign hartIsInResetSync_6 = _hartIsInResetSync_6_WIRE; // @[ShiftReg.scala:48:24]
assign hartIsInResetSync_7 = _hartIsInResetSync_7_WIRE; // @[ShiftReg.scala:48:24]
reg hrDebugIntReg_0; // @[Debug.scala:961:34]
assign hrDebugInt_0 = hrDebugIntReg_0; // @[Debug.scala:946:26, :961:34]
reg hrDebugIntReg_1; // @[Debug.scala:961:34]
assign hrDebugInt_1 = hrDebugIntReg_1; // @[Debug.scala:946:26, :961:34]
reg hrDebugIntReg_2; // @[Debug.scala:961:34]
assign hrDebugInt_2 = hrDebugIntReg_2; // @[Debug.scala:946:26, :961:34]
reg hrDebugIntReg_3; // @[Debug.scala:961:34]
assign hrDebugInt_3 = hrDebugIntReg_3; // @[Debug.scala:946:26, :961:34]
reg hrDebugIntReg_4; // @[Debug.scala:961:34]
assign hrDebugInt_4 = hrDebugIntReg_4; // @[Debug.scala:946:26, :961:34]
reg hrDebugIntReg_5; // @[Debug.scala:961:34]
assign hrDebugInt_5 = hrDebugIntReg_5; // @[Debug.scala:946:26, :961:34]
reg hrDebugIntReg_6; // @[Debug.scala:961:34]
assign hrDebugInt_6 = hrDebugIntReg_6; // @[Debug.scala:946:26, :961:34]
reg hrDebugIntReg_7; // @[Debug.scala:961:34]
assign hrDebugInt_7 = hrDebugIntReg_7; // @[Debug.scala:946:26, :961:34]
wire _DMSTATUSRdData_allhavereset_T_30; // @[Debug.scala:1003:92]
wire _DMSTATUSRdData_anyhavereset_T_22; // @[Debug.scala:997:90]
wire _DMSTATUSRdData_allresumeack_T_30; // @[Debug.scala:1004:86]
wire _DMSTATUSRdData_anyresumeack_T_22; // @[Debug.scala:998:84]
wire _DMSTATUSRdData_allunavail_T_22; // @[Debug.scala:1000:83]
wire _DMSTATUSRdData_allrunning_T_54; // @[Debug.scala:1002:113]
wire _DMSTATUSRdData_anyrunning_T_46; // @[Debug.scala:996:111]
wire _DMSTATUSRdData_allhalted_T_46; // @[Debug.scala:1001:113]
wire _DMSTATUSRdData_anyhalted_T_38; // @[Debug.scala:995:111]
wire DMSTATUSRdData_allhavereset; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyhavereset; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allresumeack; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyresumeack; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allunavail; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allrunning; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyrunning; // @[Debug.scala:978:34]
wire DMSTATUSRdData_allhalted; // @[Debug.scala:978:34]
wire DMSTATUSRdData_anyhalted; // @[Debug.scala:978:34]
wire resumereq = _resumereq_T & io_innerCtrl_bits_resumereq_0; // @[Decoupled.scala:51:35]
wire _DMSTATUSRdData_allnonexistent_T_1 = hamaskFull_0 | hamaskFull_1; // @[Debug.scala:903:30, :991:99]
wire _DMSTATUSRdData_allnonexistent_T_2 = _DMSTATUSRdData_allnonexistent_T_1 | hamaskFull_2; // @[Debug.scala:903:30, :991:99]
wire _DMSTATUSRdData_allnonexistent_T_3 = _DMSTATUSRdData_allnonexistent_T_2 | hamaskFull_3; // @[Debug.scala:903:30, :991:99]
wire _DMSTATUSRdData_allnonexistent_T_4 = _DMSTATUSRdData_allnonexistent_T_3 | hamaskFull_4; // @[Debug.scala:903:30, :991:99]
wire _DMSTATUSRdData_allnonexistent_T_5 = _DMSTATUSRdData_allnonexistent_T_4 | hamaskFull_5; // @[Debug.scala:903:30, :991:99]
wire _DMSTATUSRdData_allnonexistent_T_6 = _DMSTATUSRdData_allnonexistent_T_5 | hamaskFull_6; // @[Debug.scala:903:30, :991:99]
wire _DMSTATUSRdData_allnonexistent_T_7 = _DMSTATUSRdData_allnonexistent_T_6 | hamaskFull_7; // @[Debug.scala:903:30, :991:99]
wire _DMSTATUSRdData_allnonexistent_T_8 = ~_DMSTATUSRdData_allnonexistent_T_7; // @[Debug.scala:991:{78,99}]
wire _DMSTATUSRdData_anyhalted_T_8 = haltedBitRegs[0]; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_8 = haltedBitRegs[0]; // @[Debug.scala:861:31, :995:77, :996:77]
wire _DMSTATUSRdData_allhalted_T_8 = haltedBitRegs[0]; // @[Debug.scala:861:31, :995:77, :1001:79]
wire _DMSTATUSRdData_allrunning_T_8 = haltedBitRegs[0]; // @[Debug.scala:861:31, :995:77, :1002:79]
wire _hgHartsAllHalted_1_T = haltedBitRegs[0]; // @[Debug.scala:861:31, :995:77, :1129:48]
wire _DMSTATUSRdData_anyhalted_T_16 = _DMSTATUSRdData_anyhalted_T_8; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_9 = haltedBitRegs[1]; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_9 = haltedBitRegs[1]; // @[Debug.scala:861:31, :995:77, :996:77]
wire _DMSTATUSRdData_allhalted_T_9 = haltedBitRegs[1]; // @[Debug.scala:861:31, :995:77, :1001:79]
wire _DMSTATUSRdData_allrunning_T_9 = haltedBitRegs[1]; // @[Debug.scala:861:31, :995:77, :1002:79]
wire _hgHartsAllHalted_1_T_1 = haltedBitRegs[1]; // @[Debug.scala:861:31, :995:77, :1129:48]
wire _DMSTATUSRdData_anyhalted_T_17 = _DMSTATUSRdData_anyhalted_T_9; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_10 = haltedBitRegs[2]; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_10 = haltedBitRegs[2]; // @[Debug.scala:861:31, :995:77, :996:77]
wire _DMSTATUSRdData_allhalted_T_10 = haltedBitRegs[2]; // @[Debug.scala:861:31, :995:77, :1001:79]
wire _DMSTATUSRdData_allrunning_T_10 = haltedBitRegs[2]; // @[Debug.scala:861:31, :995:77, :1002:79]
wire _hgHartsAllHalted_1_T_2 = haltedBitRegs[2]; // @[Debug.scala:861:31, :995:77, :1129:48]
wire _DMSTATUSRdData_anyhalted_T_18 = _DMSTATUSRdData_anyhalted_T_10; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_11 = haltedBitRegs[3]; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_11 = haltedBitRegs[3]; // @[Debug.scala:861:31, :995:77, :996:77]
wire _DMSTATUSRdData_allhalted_T_11 = haltedBitRegs[3]; // @[Debug.scala:861:31, :995:77, :1001:79]
wire _DMSTATUSRdData_allrunning_T_11 = haltedBitRegs[3]; // @[Debug.scala:861:31, :995:77, :1002:79]
wire _hgHartsAllHalted_1_T_3 = haltedBitRegs[3]; // @[Debug.scala:861:31, :995:77, :1129:48]
wire _DMSTATUSRdData_anyhalted_T_19 = _DMSTATUSRdData_anyhalted_T_11; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_12 = haltedBitRegs[4]; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_12 = haltedBitRegs[4]; // @[Debug.scala:861:31, :995:77, :996:77]
wire _DMSTATUSRdData_allhalted_T_12 = haltedBitRegs[4]; // @[Debug.scala:861:31, :995:77, :1001:79]
wire _DMSTATUSRdData_allrunning_T_12 = haltedBitRegs[4]; // @[Debug.scala:861:31, :995:77, :1002:79]
wire _hgHartsAllHalted_1_T_4 = haltedBitRegs[4]; // @[Debug.scala:861:31, :995:77, :1129:48]
wire _DMSTATUSRdData_anyhalted_T_20 = _DMSTATUSRdData_anyhalted_T_12; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_13 = haltedBitRegs[5]; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_13 = haltedBitRegs[5]; // @[Debug.scala:861:31, :995:77, :996:77]
wire _DMSTATUSRdData_allhalted_T_13 = haltedBitRegs[5]; // @[Debug.scala:861:31, :995:77, :1001:79]
wire _DMSTATUSRdData_allrunning_T_13 = haltedBitRegs[5]; // @[Debug.scala:861:31, :995:77, :1002:79]
wire _hgHartsAllHalted_1_T_5 = haltedBitRegs[5]; // @[Debug.scala:861:31, :995:77, :1129:48]
wire _DMSTATUSRdData_anyhalted_T_21 = _DMSTATUSRdData_anyhalted_T_13; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_14 = haltedBitRegs[6]; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_14 = haltedBitRegs[6]; // @[Debug.scala:861:31, :995:77, :996:77]
wire _DMSTATUSRdData_allhalted_T_14 = haltedBitRegs[6]; // @[Debug.scala:861:31, :995:77, :1001:79]
wire _DMSTATUSRdData_allrunning_T_14 = haltedBitRegs[6]; // @[Debug.scala:861:31, :995:77, :1002:79]
wire _hgHartsAllHalted_1_T_6 = haltedBitRegs[6]; // @[Debug.scala:861:31, :995:77, :1129:48]
wire _DMSTATUSRdData_anyhalted_T_22 = _DMSTATUSRdData_anyhalted_T_14; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_15 = haltedBitRegs[7]; // @[Debug.scala:861:31, :995:77]
wire _DMSTATUSRdData_anyrunning_T_15 = haltedBitRegs[7]; // @[Debug.scala:861:31, :995:77, :996:77]
wire _DMSTATUSRdData_allhalted_T_15 = haltedBitRegs[7]; // @[Debug.scala:861:31, :995:77, :1001:79]
wire _DMSTATUSRdData_allrunning_T_15 = haltedBitRegs[7]; // @[Debug.scala:861:31, :995:77, :1002:79]
wire _hgHartsAllHalted_1_T_7 = haltedBitRegs[7]; // @[Debug.scala:861:31, :995:77, :1129:48]
wire _DMSTATUSRdData_anyhalted_T_23 = _DMSTATUSRdData_anyhalted_T_15; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_24 = _DMSTATUSRdData_anyhalted_T_16 & hamaskFull_0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_25 = _DMSTATUSRdData_anyhalted_T_17 & hamaskFull_1; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_26 = _DMSTATUSRdData_anyhalted_T_18 & hamaskFull_2; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_27 = _DMSTATUSRdData_anyhalted_T_19 & hamaskFull_3; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_28 = _DMSTATUSRdData_anyhalted_T_20 & hamaskFull_4; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_29 = _DMSTATUSRdData_anyhalted_T_21 & hamaskFull_5; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_30 = _DMSTATUSRdData_anyhalted_T_22 & hamaskFull_6; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_31 = _DMSTATUSRdData_anyhalted_T_23 & hamaskFull_7; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_32 = _DMSTATUSRdData_anyhalted_T_24 | _DMSTATUSRdData_anyhalted_T_25; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_33 = _DMSTATUSRdData_anyhalted_T_32 | _DMSTATUSRdData_anyhalted_T_26; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_34 = _DMSTATUSRdData_anyhalted_T_33 | _DMSTATUSRdData_anyhalted_T_27; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_35 = _DMSTATUSRdData_anyhalted_T_34 | _DMSTATUSRdData_anyhalted_T_28; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_36 = _DMSTATUSRdData_anyhalted_T_35 | _DMSTATUSRdData_anyhalted_T_29; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhalted_T_37 = _DMSTATUSRdData_anyhalted_T_36 | _DMSTATUSRdData_anyhalted_T_30; // @[package.scala:74:72]
assign _DMSTATUSRdData_anyhalted_T_38 = _DMSTATUSRdData_anyhalted_T_37 | _DMSTATUSRdData_anyhalted_T_31; // @[package.scala:74:72]
assign DMSTATUSRdData_anyhalted = _DMSTATUSRdData_anyhalted_T_38; // @[Debug.scala:978:34, :995:111]
wire _DMSTATUSRdData_anyrunning_T_16 = ~_DMSTATUSRdData_anyrunning_T_8; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_24 = _DMSTATUSRdData_anyrunning_T_16; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_17 = ~_DMSTATUSRdData_anyrunning_T_9; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_25 = _DMSTATUSRdData_anyrunning_T_17; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_18 = ~_DMSTATUSRdData_anyrunning_T_10; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_26 = _DMSTATUSRdData_anyrunning_T_18; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_19 = ~_DMSTATUSRdData_anyrunning_T_11; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_27 = _DMSTATUSRdData_anyrunning_T_19; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_20 = ~_DMSTATUSRdData_anyrunning_T_12; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_28 = _DMSTATUSRdData_anyrunning_T_20; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_21 = ~_DMSTATUSRdData_anyrunning_T_13; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_29 = _DMSTATUSRdData_anyrunning_T_21; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_22 = ~_DMSTATUSRdData_anyrunning_T_14; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_30 = _DMSTATUSRdData_anyrunning_T_22; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_23 = ~_DMSTATUSRdData_anyrunning_T_15; // @[package.scala:79:37]
wire _DMSTATUSRdData_anyrunning_T_31 = _DMSTATUSRdData_anyrunning_T_23; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_anyrunning_T_32 = _DMSTATUSRdData_anyrunning_T_24 & hamaskFull_0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_33 = _DMSTATUSRdData_anyrunning_T_25 & hamaskFull_1; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_34 = _DMSTATUSRdData_anyrunning_T_26 & hamaskFull_2; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_35 = _DMSTATUSRdData_anyrunning_T_27 & hamaskFull_3; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_36 = _DMSTATUSRdData_anyrunning_T_28 & hamaskFull_4; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_37 = _DMSTATUSRdData_anyrunning_T_29 & hamaskFull_5; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_38 = _DMSTATUSRdData_anyrunning_T_30 & hamaskFull_6; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_39 = _DMSTATUSRdData_anyrunning_T_31 & hamaskFull_7; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_40 = _DMSTATUSRdData_anyrunning_T_32 | _DMSTATUSRdData_anyrunning_T_33; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_41 = _DMSTATUSRdData_anyrunning_T_40 | _DMSTATUSRdData_anyrunning_T_34; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_42 = _DMSTATUSRdData_anyrunning_T_41 | _DMSTATUSRdData_anyrunning_T_35; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_43 = _DMSTATUSRdData_anyrunning_T_42 | _DMSTATUSRdData_anyrunning_T_36; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_44 = _DMSTATUSRdData_anyrunning_T_43 | _DMSTATUSRdData_anyrunning_T_37; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyrunning_T_45 = _DMSTATUSRdData_anyrunning_T_44 | _DMSTATUSRdData_anyrunning_T_38; // @[package.scala:74:72]
assign _DMSTATUSRdData_anyrunning_T_46 = _DMSTATUSRdData_anyrunning_T_45 | _DMSTATUSRdData_anyrunning_T_39; // @[package.scala:74:72]
assign DMSTATUSRdData_anyrunning = _DMSTATUSRdData_anyrunning_T_46; // @[Debug.scala:978:34, :996:111]
wire _DMSTATUSRdData_anyhavereset_T = haveResetBitRegs[0]; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T = haveResetBitRegs[0]; // @[Debug.scala:865:31, :997:58, :1003:60]
wire _DMSTATUSRdData_anyhavereset_T_1 = haveResetBitRegs[1]; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T_1 = haveResetBitRegs[1]; // @[Debug.scala:865:31, :997:58, :1003:60]
wire _DMSTATUSRdData_anyhavereset_T_2 = haveResetBitRegs[2]; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T_2 = haveResetBitRegs[2]; // @[Debug.scala:865:31, :997:58, :1003:60]
wire _DMSTATUSRdData_anyhavereset_T_3 = haveResetBitRegs[3]; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T_3 = haveResetBitRegs[3]; // @[Debug.scala:865:31, :997:58, :1003:60]
wire _DMSTATUSRdData_anyhavereset_T_4 = haveResetBitRegs[4]; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T_4 = haveResetBitRegs[4]; // @[Debug.scala:865:31, :997:58, :1003:60]
wire _DMSTATUSRdData_anyhavereset_T_5 = haveResetBitRegs[5]; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T_5 = haveResetBitRegs[5]; // @[Debug.scala:865:31, :997:58, :1003:60]
wire _DMSTATUSRdData_anyhavereset_T_6 = haveResetBitRegs[6]; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T_6 = haveResetBitRegs[6]; // @[Debug.scala:865:31, :997:58, :1003:60]
wire _DMSTATUSRdData_anyhavereset_T_7 = haveResetBitRegs[7]; // @[Debug.scala:865:31, :997:58]
wire _DMSTATUSRdData_allhavereset_T_7 = haveResetBitRegs[7]; // @[Debug.scala:865:31, :997:58, :1003:60]
wire _DMSTATUSRdData_anyhavereset_T_8 = _DMSTATUSRdData_anyhavereset_T & hamaskFull_0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_9 = _DMSTATUSRdData_anyhavereset_T_1 & hamaskFull_1; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_10 = _DMSTATUSRdData_anyhavereset_T_2 & hamaskFull_2; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_11 = _DMSTATUSRdData_anyhavereset_T_3 & hamaskFull_3; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_12 = _DMSTATUSRdData_anyhavereset_T_4 & hamaskFull_4; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_13 = _DMSTATUSRdData_anyhavereset_T_5 & hamaskFull_5; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_14 = _DMSTATUSRdData_anyhavereset_T_6 & hamaskFull_6; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_15 = _DMSTATUSRdData_anyhavereset_T_7 & hamaskFull_7; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_16 = _DMSTATUSRdData_anyhavereset_T_8 | _DMSTATUSRdData_anyhavereset_T_9; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_17 = _DMSTATUSRdData_anyhavereset_T_16 | _DMSTATUSRdData_anyhavereset_T_10; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_18 = _DMSTATUSRdData_anyhavereset_T_17 | _DMSTATUSRdData_anyhavereset_T_11; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_19 = _DMSTATUSRdData_anyhavereset_T_18 | _DMSTATUSRdData_anyhavereset_T_12; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_20 = _DMSTATUSRdData_anyhavereset_T_19 | _DMSTATUSRdData_anyhavereset_T_13; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyhavereset_T_21 = _DMSTATUSRdData_anyhavereset_T_20 | _DMSTATUSRdData_anyhavereset_T_14; // @[package.scala:74:72]
assign _DMSTATUSRdData_anyhavereset_T_22 = _DMSTATUSRdData_anyhavereset_T_21 | _DMSTATUSRdData_anyhavereset_T_15; // @[package.scala:74:72]
assign DMSTATUSRdData_anyhavereset = _DMSTATUSRdData_anyhavereset_T_22; // @[Debug.scala:978:34, :997:90]
wire _DMSTATUSRdData_anyresumeack_T = resumeAcks[0]; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T = resumeAcks[0]; // @[Debug.scala:869:32, :998:52, :1004:54]
wire _DMSTATUSRdData_anyresumeack_T_1 = resumeAcks[1]; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T_1 = resumeAcks[1]; // @[Debug.scala:869:32, :998:52, :1004:54]
wire _DMSTATUSRdData_anyresumeack_T_2 = resumeAcks[2]; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T_2 = resumeAcks[2]; // @[Debug.scala:869:32, :998:52, :1004:54]
wire _DMSTATUSRdData_anyresumeack_T_3 = resumeAcks[3]; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T_3 = resumeAcks[3]; // @[Debug.scala:869:32, :998:52, :1004:54]
wire _DMSTATUSRdData_anyresumeack_T_4 = resumeAcks[4]; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T_4 = resumeAcks[4]; // @[Debug.scala:869:32, :998:52, :1004:54]
wire _DMSTATUSRdData_anyresumeack_T_5 = resumeAcks[5]; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T_5 = resumeAcks[5]; // @[Debug.scala:869:32, :998:52, :1004:54]
wire _DMSTATUSRdData_anyresumeack_T_6 = resumeAcks[6]; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T_6 = resumeAcks[6]; // @[Debug.scala:869:32, :998:52, :1004:54]
wire _DMSTATUSRdData_anyresumeack_T_7 = resumeAcks[7]; // @[Debug.scala:869:32, :998:52]
wire _DMSTATUSRdData_allresumeack_T_7 = resumeAcks[7]; // @[Debug.scala:869:32, :998:52, :1004:54]
wire _DMSTATUSRdData_anyresumeack_T_8 = _DMSTATUSRdData_anyresumeack_T & hamaskFull_0; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_9 = _DMSTATUSRdData_anyresumeack_T_1 & hamaskFull_1; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_10 = _DMSTATUSRdData_anyresumeack_T_2 & hamaskFull_2; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_11 = _DMSTATUSRdData_anyresumeack_T_3 & hamaskFull_3; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_12 = _DMSTATUSRdData_anyresumeack_T_4 & hamaskFull_4; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_13 = _DMSTATUSRdData_anyresumeack_T_5 & hamaskFull_5; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_14 = _DMSTATUSRdData_anyresumeack_T_6 & hamaskFull_6; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_15 = _DMSTATUSRdData_anyresumeack_T_7 & hamaskFull_7; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_16 = _DMSTATUSRdData_anyresumeack_T_8 | _DMSTATUSRdData_anyresumeack_T_9; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_17 = _DMSTATUSRdData_anyresumeack_T_16 | _DMSTATUSRdData_anyresumeack_T_10; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_18 = _DMSTATUSRdData_anyresumeack_T_17 | _DMSTATUSRdData_anyresumeack_T_11; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_19 = _DMSTATUSRdData_anyresumeack_T_18 | _DMSTATUSRdData_anyresumeack_T_12; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_20 = _DMSTATUSRdData_anyresumeack_T_19 | _DMSTATUSRdData_anyresumeack_T_13; // @[package.scala:74:72]
wire _DMSTATUSRdData_anyresumeack_T_21 = _DMSTATUSRdData_anyresumeack_T_20 | _DMSTATUSRdData_anyresumeack_T_14; // @[package.scala:74:72]
assign _DMSTATUSRdData_anyresumeack_T_22 = _DMSTATUSRdData_anyresumeack_T_21 | _DMSTATUSRdData_anyresumeack_T_15; // @[package.scala:74:72]
assign DMSTATUSRdData_anyresumeack = _DMSTATUSRdData_anyresumeack_T_22; // @[Debug.scala:978:34, :998:84]
wire _DMSTATUSRdData_allunavail_T = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_8 = _DMSTATUSRdData_allunavail_T; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allunavail_T_1 = ~hamaskFull_1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_9 = _DMSTATUSRdData_allunavail_T_1; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allunavail_T_2 = ~hamaskFull_2; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_10 = _DMSTATUSRdData_allunavail_T_2; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allunavail_T_3 = ~hamaskFull_3; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_11 = _DMSTATUSRdData_allunavail_T_3; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allunavail_T_4 = ~hamaskFull_4; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_12 = _DMSTATUSRdData_allunavail_T_4; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allunavail_T_5 = ~hamaskFull_5; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_13 = _DMSTATUSRdData_allunavail_T_5; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allunavail_T_6 = ~hamaskFull_6; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_14 = _DMSTATUSRdData_allunavail_T_6; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allunavail_T_7 = ~hamaskFull_7; // @[package.scala:79:37]
wire _DMSTATUSRdData_allunavail_T_15 = _DMSTATUSRdData_allunavail_T_7; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allunavail_T_16 = _DMSTATUSRdData_allunavail_T_8 & _DMSTATUSRdData_allunavail_T_9; // @[package.scala:75:75]
wire _DMSTATUSRdData_allunavail_T_17 = _DMSTATUSRdData_allunavail_T_16 & _DMSTATUSRdData_allunavail_T_10; // @[package.scala:75:75]
wire _DMSTATUSRdData_allunavail_T_18 = _DMSTATUSRdData_allunavail_T_17 & _DMSTATUSRdData_allunavail_T_11; // @[package.scala:75:75]
wire _DMSTATUSRdData_allunavail_T_19 = _DMSTATUSRdData_allunavail_T_18 & _DMSTATUSRdData_allunavail_T_12; // @[package.scala:75:75]
wire _DMSTATUSRdData_allunavail_T_20 = _DMSTATUSRdData_allunavail_T_19 & _DMSTATUSRdData_allunavail_T_13; // @[package.scala:75:75]
wire _DMSTATUSRdData_allunavail_T_21 = _DMSTATUSRdData_allunavail_T_20 & _DMSTATUSRdData_allunavail_T_14; // @[package.scala:75:75]
assign _DMSTATUSRdData_allunavail_T_22 = _DMSTATUSRdData_allunavail_T_21 & _DMSTATUSRdData_allunavail_T_15; // @[package.scala:75:75]
assign DMSTATUSRdData_allunavail = _DMSTATUSRdData_allunavail_T_22; // @[Debug.scala:978:34, :1000:83]
wire _DMSTATUSRdData_allhalted_T_16 = _DMSTATUSRdData_allhalted_T_8; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_17 = _DMSTATUSRdData_allhalted_T_9; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_18 = _DMSTATUSRdData_allhalted_T_10; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_19 = _DMSTATUSRdData_allhalted_T_11; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_20 = _DMSTATUSRdData_allhalted_T_12; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_21 = _DMSTATUSRdData_allhalted_T_13; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_22 = _DMSTATUSRdData_allhalted_T_14; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_23 = _DMSTATUSRdData_allhalted_T_15; // @[package.scala:74:72]
wire _DMSTATUSRdData_allhalted_T_24 = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_25 = ~hamaskFull_1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_26 = ~hamaskFull_2; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_27 = ~hamaskFull_3; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_28 = ~hamaskFull_4; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_29 = ~hamaskFull_5; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_30 = ~hamaskFull_6; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_31 = ~hamaskFull_7; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhalted_T_32 = _DMSTATUSRdData_allhalted_T_16 | _DMSTATUSRdData_allhalted_T_24; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allhalted_T_33 = _DMSTATUSRdData_allhalted_T_17 | _DMSTATUSRdData_allhalted_T_25; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allhalted_T_34 = _DMSTATUSRdData_allhalted_T_18 | _DMSTATUSRdData_allhalted_T_26; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allhalted_T_35 = _DMSTATUSRdData_allhalted_T_19 | _DMSTATUSRdData_allhalted_T_27; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allhalted_T_36 = _DMSTATUSRdData_allhalted_T_20 | _DMSTATUSRdData_allhalted_T_28; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allhalted_T_37 = _DMSTATUSRdData_allhalted_T_21 | _DMSTATUSRdData_allhalted_T_29; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allhalted_T_38 = _DMSTATUSRdData_allhalted_T_22 | _DMSTATUSRdData_allhalted_T_30; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allhalted_T_39 = _DMSTATUSRdData_allhalted_T_23 | _DMSTATUSRdData_allhalted_T_31; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allhalted_T_40 = _DMSTATUSRdData_allhalted_T_32 & _DMSTATUSRdData_allhalted_T_33; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhalted_T_41 = _DMSTATUSRdData_allhalted_T_40 & _DMSTATUSRdData_allhalted_T_34; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhalted_T_42 = _DMSTATUSRdData_allhalted_T_41 & _DMSTATUSRdData_allhalted_T_35; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhalted_T_43 = _DMSTATUSRdData_allhalted_T_42 & _DMSTATUSRdData_allhalted_T_36; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhalted_T_44 = _DMSTATUSRdData_allhalted_T_43 & _DMSTATUSRdData_allhalted_T_37; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhalted_T_45 = _DMSTATUSRdData_allhalted_T_44 & _DMSTATUSRdData_allhalted_T_38; // @[package.scala:75:75]
assign _DMSTATUSRdData_allhalted_T_46 = _DMSTATUSRdData_allhalted_T_45 & _DMSTATUSRdData_allhalted_T_39; // @[package.scala:75:75]
assign DMSTATUSRdData_allhalted = _DMSTATUSRdData_allhalted_T_46; // @[Debug.scala:978:34, :1001:113]
wire _DMSTATUSRdData_allrunning_T_16 = ~_DMSTATUSRdData_allrunning_T_8; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_24 = _DMSTATUSRdData_allrunning_T_16; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_17 = ~_DMSTATUSRdData_allrunning_T_9; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_25 = _DMSTATUSRdData_allrunning_T_17; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_18 = ~_DMSTATUSRdData_allrunning_T_10; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_26 = _DMSTATUSRdData_allrunning_T_18; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_19 = ~_DMSTATUSRdData_allrunning_T_11; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_27 = _DMSTATUSRdData_allrunning_T_19; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_20 = ~_DMSTATUSRdData_allrunning_T_12; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_28 = _DMSTATUSRdData_allrunning_T_20; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_21 = ~_DMSTATUSRdData_allrunning_T_13; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_29 = _DMSTATUSRdData_allrunning_T_21; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_22 = ~_DMSTATUSRdData_allrunning_T_14; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_30 = _DMSTATUSRdData_allrunning_T_22; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_23 = ~_DMSTATUSRdData_allrunning_T_15; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_31 = _DMSTATUSRdData_allrunning_T_23; // @[package.scala:74:72, :79:37]
wire _DMSTATUSRdData_allrunning_T_32 = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_33 = ~hamaskFull_1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_34 = ~hamaskFull_2; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_35 = ~hamaskFull_3; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_36 = ~hamaskFull_4; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_37 = ~hamaskFull_5; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_38 = ~hamaskFull_6; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_39 = ~hamaskFull_7; // @[package.scala:79:37]
wire _DMSTATUSRdData_allrunning_T_40 = _DMSTATUSRdData_allrunning_T_24 | _DMSTATUSRdData_allrunning_T_32; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allrunning_T_41 = _DMSTATUSRdData_allrunning_T_25 | _DMSTATUSRdData_allrunning_T_33; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allrunning_T_42 = _DMSTATUSRdData_allrunning_T_26 | _DMSTATUSRdData_allrunning_T_34; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allrunning_T_43 = _DMSTATUSRdData_allrunning_T_27 | _DMSTATUSRdData_allrunning_T_35; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allrunning_T_44 = _DMSTATUSRdData_allrunning_T_28 | _DMSTATUSRdData_allrunning_T_36; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allrunning_T_45 = _DMSTATUSRdData_allrunning_T_29 | _DMSTATUSRdData_allrunning_T_37; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allrunning_T_46 = _DMSTATUSRdData_allrunning_T_30 | _DMSTATUSRdData_allrunning_T_38; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allrunning_T_47 = _DMSTATUSRdData_allrunning_T_31 | _DMSTATUSRdData_allrunning_T_39; // @[package.scala:74:72, :75:75, :79:37]
wire _DMSTATUSRdData_allrunning_T_48 = _DMSTATUSRdData_allrunning_T_40 & _DMSTATUSRdData_allrunning_T_41; // @[package.scala:75:75]
wire _DMSTATUSRdData_allrunning_T_49 = _DMSTATUSRdData_allrunning_T_48 & _DMSTATUSRdData_allrunning_T_42; // @[package.scala:75:75]
wire _DMSTATUSRdData_allrunning_T_50 = _DMSTATUSRdData_allrunning_T_49 & _DMSTATUSRdData_allrunning_T_43; // @[package.scala:75:75]
wire _DMSTATUSRdData_allrunning_T_51 = _DMSTATUSRdData_allrunning_T_50 & _DMSTATUSRdData_allrunning_T_44; // @[package.scala:75:75]
wire _DMSTATUSRdData_allrunning_T_52 = _DMSTATUSRdData_allrunning_T_51 & _DMSTATUSRdData_allrunning_T_45; // @[package.scala:75:75]
wire _DMSTATUSRdData_allrunning_T_53 = _DMSTATUSRdData_allrunning_T_52 & _DMSTATUSRdData_allrunning_T_46; // @[package.scala:75:75]
assign _DMSTATUSRdData_allrunning_T_54 = _DMSTATUSRdData_allrunning_T_53 & _DMSTATUSRdData_allrunning_T_47; // @[package.scala:75:75]
assign DMSTATUSRdData_allrunning = _DMSTATUSRdData_allrunning_T_54; // @[Debug.scala:978:34, :1002:113]
wire _DMSTATUSRdData_allhavereset_T_8 = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_9 = ~hamaskFull_1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_10 = ~hamaskFull_2; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_11 = ~hamaskFull_3; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_12 = ~hamaskFull_4; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_13 = ~hamaskFull_5; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_14 = ~hamaskFull_6; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_15 = ~hamaskFull_7; // @[package.scala:79:37]
wire _DMSTATUSRdData_allhavereset_T_16 = _DMSTATUSRdData_allhavereset_T | _DMSTATUSRdData_allhavereset_T_8; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allhavereset_T_17 = _DMSTATUSRdData_allhavereset_T_1 | _DMSTATUSRdData_allhavereset_T_9; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allhavereset_T_18 = _DMSTATUSRdData_allhavereset_T_2 | _DMSTATUSRdData_allhavereset_T_10; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allhavereset_T_19 = _DMSTATUSRdData_allhavereset_T_3 | _DMSTATUSRdData_allhavereset_T_11; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allhavereset_T_20 = _DMSTATUSRdData_allhavereset_T_4 | _DMSTATUSRdData_allhavereset_T_12; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allhavereset_T_21 = _DMSTATUSRdData_allhavereset_T_5 | _DMSTATUSRdData_allhavereset_T_13; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allhavereset_T_22 = _DMSTATUSRdData_allhavereset_T_6 | _DMSTATUSRdData_allhavereset_T_14; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allhavereset_T_23 = _DMSTATUSRdData_allhavereset_T_7 | _DMSTATUSRdData_allhavereset_T_15; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allhavereset_T_24 = _DMSTATUSRdData_allhavereset_T_16 & _DMSTATUSRdData_allhavereset_T_17; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhavereset_T_25 = _DMSTATUSRdData_allhavereset_T_24 & _DMSTATUSRdData_allhavereset_T_18; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhavereset_T_26 = _DMSTATUSRdData_allhavereset_T_25 & _DMSTATUSRdData_allhavereset_T_19; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhavereset_T_27 = _DMSTATUSRdData_allhavereset_T_26 & _DMSTATUSRdData_allhavereset_T_20; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhavereset_T_28 = _DMSTATUSRdData_allhavereset_T_27 & _DMSTATUSRdData_allhavereset_T_21; // @[package.scala:75:75]
wire _DMSTATUSRdData_allhavereset_T_29 = _DMSTATUSRdData_allhavereset_T_28 & _DMSTATUSRdData_allhavereset_T_22; // @[package.scala:75:75]
assign _DMSTATUSRdData_allhavereset_T_30 = _DMSTATUSRdData_allhavereset_T_29 & _DMSTATUSRdData_allhavereset_T_23; // @[package.scala:75:75]
assign DMSTATUSRdData_allhavereset = _DMSTATUSRdData_allhavereset_T_30; // @[Debug.scala:978:34, :1003:92]
wire _DMSTATUSRdData_allresumeack_T_8 = ~hamaskFull_0; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_9 = ~hamaskFull_1; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_10 = ~hamaskFull_2; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_11 = ~hamaskFull_3; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_12 = ~hamaskFull_4; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_13 = ~hamaskFull_5; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_14 = ~hamaskFull_6; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_15 = ~hamaskFull_7; // @[package.scala:79:37]
wire _DMSTATUSRdData_allresumeack_T_16 = _DMSTATUSRdData_allresumeack_T | _DMSTATUSRdData_allresumeack_T_8; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allresumeack_T_17 = _DMSTATUSRdData_allresumeack_T_1 | _DMSTATUSRdData_allresumeack_T_9; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allresumeack_T_18 = _DMSTATUSRdData_allresumeack_T_2 | _DMSTATUSRdData_allresumeack_T_10; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allresumeack_T_19 = _DMSTATUSRdData_allresumeack_T_3 | _DMSTATUSRdData_allresumeack_T_11; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allresumeack_T_20 = _DMSTATUSRdData_allresumeack_T_4 | _DMSTATUSRdData_allresumeack_T_12; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allresumeack_T_21 = _DMSTATUSRdData_allresumeack_T_5 | _DMSTATUSRdData_allresumeack_T_13; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allresumeack_T_22 = _DMSTATUSRdData_allresumeack_T_6 | _DMSTATUSRdData_allresumeack_T_14; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allresumeack_T_23 = _DMSTATUSRdData_allresumeack_T_7 | _DMSTATUSRdData_allresumeack_T_15; // @[package.scala:75:75, :79:37]
wire _DMSTATUSRdData_allresumeack_T_24 = _DMSTATUSRdData_allresumeack_T_16 & _DMSTATUSRdData_allresumeack_T_17; // @[package.scala:75:75]
wire _DMSTATUSRdData_allresumeack_T_25 = _DMSTATUSRdData_allresumeack_T_24 & _DMSTATUSRdData_allresumeack_T_18; // @[package.scala:75:75]
wire _DMSTATUSRdData_allresumeack_T_26 = _DMSTATUSRdData_allresumeack_T_25 & _DMSTATUSRdData_allresumeack_T_19; // @[package.scala:75:75]
wire _DMSTATUSRdData_allresumeack_T_27 = _DMSTATUSRdData_allresumeack_T_26 & _DMSTATUSRdData_allresumeack_T_20; // @[package.scala:75:75]
wire _DMSTATUSRdData_allresumeack_T_28 = _DMSTATUSRdData_allresumeack_T_27 & _DMSTATUSRdData_allresumeack_T_21; // @[package.scala:75:75]
wire _DMSTATUSRdData_allresumeack_T_29 = _DMSTATUSRdData_allresumeack_T_28 & _DMSTATUSRdData_allresumeack_T_22; // @[package.scala:75:75]
assign _DMSTATUSRdData_allresumeack_T_30 = _DMSTATUSRdData_allresumeack_T_29 & _DMSTATUSRdData_allresumeack_T_23; // @[package.scala:75:75]
assign DMSTATUSRdData_allresumeack = _DMSTATUSRdData_allresumeack_T_30; // @[Debug.scala:978:34, :1004:86]
wire [1:0] _GEN_6 = {hamaskWrSel_1, hamaskWrSel_0}; // @[Debug.scala:933:31, :1017:64]
wire [1:0] haveResetBitRegs_lo_lo; // @[Debug.scala:1017:64]
assign haveResetBitRegs_lo_lo = _GEN_6; // @[Debug.scala:1017:64]
wire [1:0] resumeReqRegs_lo_lo_2; // @[Debug.scala:1342:57]
assign resumeReqRegs_lo_lo_2 = _GEN_6; // @[Debug.scala:1017:64, :1342:57]
wire [1:0] resumeAcks_lo_lo; // @[Debug.scala:1349:55]
assign resumeAcks_lo_lo = _GEN_6; // @[Debug.scala:1017:64, :1349:55]
wire [1:0] _GEN_7 = {hamaskWrSel_3, hamaskWrSel_2}; // @[Debug.scala:933:31, :1017:64]
wire [1:0] haveResetBitRegs_lo_hi; // @[Debug.scala:1017:64]
assign haveResetBitRegs_lo_hi = _GEN_7; // @[Debug.scala:1017:64]
wire [1:0] resumeReqRegs_lo_hi_2; // @[Debug.scala:1342:57]
assign resumeReqRegs_lo_hi_2 = _GEN_7; // @[Debug.scala:1017:64, :1342:57]
wire [1:0] resumeAcks_lo_hi; // @[Debug.scala:1349:55]
assign resumeAcks_lo_hi = _GEN_7; // @[Debug.scala:1017:64, :1349:55]
wire [3:0] haveResetBitRegs_lo = {haveResetBitRegs_lo_hi, haveResetBitRegs_lo_lo}; // @[Debug.scala:1017:64]
wire [1:0] _GEN_8 = {hamaskWrSel_5, hamaskWrSel_4}; // @[Debug.scala:933:31, :1017:64]
wire [1:0] haveResetBitRegs_hi_lo; // @[Debug.scala:1017:64]
assign haveResetBitRegs_hi_lo = _GEN_8; // @[Debug.scala:1017:64]
wire [1:0] resumeReqRegs_hi_lo_2; // @[Debug.scala:1342:57]
assign resumeReqRegs_hi_lo_2 = _GEN_8; // @[Debug.scala:1017:64, :1342:57]
wire [1:0] resumeAcks_hi_lo; // @[Debug.scala:1349:55]
assign resumeAcks_hi_lo = _GEN_8; // @[Debug.scala:1017:64, :1349:55]
wire [1:0] _GEN_9 = {hamaskWrSel_7, hamaskWrSel_6}; // @[Debug.scala:933:31, :1017:64]
wire [1:0] haveResetBitRegs_hi_hi; // @[Debug.scala:1017:64]
assign haveResetBitRegs_hi_hi = _GEN_9; // @[Debug.scala:1017:64]
wire [1:0] resumeReqRegs_hi_hi_2; // @[Debug.scala:1342:57]
assign resumeReqRegs_hi_hi_2 = _GEN_9; // @[Debug.scala:1017:64, :1342:57]
wire [1:0] resumeAcks_hi_hi; // @[Debug.scala:1349:55]
assign resumeAcks_hi_hi = _GEN_9; // @[Debug.scala:1017:64, :1349:55]
wire [3:0] haveResetBitRegs_hi = {haveResetBitRegs_hi_hi, haveResetBitRegs_hi_lo}; // @[Debug.scala:1017:64]
wire [7:0] _haveResetBitRegs_T = {haveResetBitRegs_hi, haveResetBitRegs_lo}; // @[Debug.scala:1017:64]
wire [7:0] _haveResetBitRegs_T_1 = ~_haveResetBitRegs_T; // @[Debug.scala:1017:{50,64}]
wire [7:0] _haveResetBitRegs_T_2 = haveResetBitRegs & _haveResetBitRegs_T_1; // @[Debug.scala:865:31, :1017:{47,50}]
wire [1:0] _GEN_10 = {hartIsInResetSync_1, hartIsInResetSync_0}; // @[Debug.scala:948:33, :1017:94]
wire [1:0] haveResetBitRegs_lo_lo_1; // @[Debug.scala:1017:94]
assign haveResetBitRegs_lo_lo_1 = _GEN_10; // @[Debug.scala:1017:94]
wire [1:0] haveResetBitRegs_lo_lo_2; // @[Debug.scala:1019:66]
assign haveResetBitRegs_lo_lo_2 = _GEN_10; // @[Debug.scala:1017:94, :1019:66]
wire [1:0] resumeReqRegs_lo_lo; // @[Debug.scala:1320:62]
assign resumeReqRegs_lo_lo = _GEN_10; // @[Debug.scala:1017:94, :1320:62]
wire [1:0] haltedBitRegs_lo_lo; // @[Debug.scala:1327:86]
assign haltedBitRegs_lo_lo = _GEN_10; // @[Debug.scala:1017:94, :1327:86]
wire [1:0] haltedBitRegs_lo_lo_1; // @[Debug.scala:1330:91]
assign haltedBitRegs_lo_lo_1 = _GEN_10; // @[Debug.scala:1017:94, :1330:91]
wire [1:0] haltedBitRegs_lo_lo_2; // @[Debug.scala:1333:64]
assign haltedBitRegs_lo_lo_2 = _GEN_10; // @[Debug.scala:1017:94, :1333:64]
wire [1:0] resumeReqRegs_lo_lo_1; // @[Debug.scala:1338:91]
assign resumeReqRegs_lo_lo_1 = _GEN_10; // @[Debug.scala:1017:94, :1338:91]
wire [1:0] resumeReqRegs_lo_lo_3; // @[Debug.scala:1342:87]
assign resumeReqRegs_lo_lo_3 = _GEN_10; // @[Debug.scala:1017:94, :1342:87]
wire [1:0] _GEN_11 = {hartIsInResetSync_3, hartIsInResetSync_2}; // @[Debug.scala:948:33, :1017:94]
wire [1:0] haveResetBitRegs_lo_hi_1; // @[Debug.scala:1017:94]
assign haveResetBitRegs_lo_hi_1 = _GEN_11; // @[Debug.scala:1017:94]
wire [1:0] haveResetBitRegs_lo_hi_2; // @[Debug.scala:1019:66]
assign haveResetBitRegs_lo_hi_2 = _GEN_11; // @[Debug.scala:1017:94, :1019:66]
wire [1:0] resumeReqRegs_lo_hi; // @[Debug.scala:1320:62]
assign resumeReqRegs_lo_hi = _GEN_11; // @[Debug.scala:1017:94, :1320:62]
wire [1:0] haltedBitRegs_lo_hi; // @[Debug.scala:1327:86]
assign haltedBitRegs_lo_hi = _GEN_11; // @[Debug.scala:1017:94, :1327:86]
wire [1:0] haltedBitRegs_lo_hi_1; // @[Debug.scala:1330:91]
assign haltedBitRegs_lo_hi_1 = _GEN_11; // @[Debug.scala:1017:94, :1330:91]
wire [1:0] haltedBitRegs_lo_hi_2; // @[Debug.scala:1333:64]
assign haltedBitRegs_lo_hi_2 = _GEN_11; // @[Debug.scala:1017:94, :1333:64]
wire [1:0] resumeReqRegs_lo_hi_1; // @[Debug.scala:1338:91]
assign resumeReqRegs_lo_hi_1 = _GEN_11; // @[Debug.scala:1017:94, :1338:91]
wire [1:0] resumeReqRegs_lo_hi_3; // @[Debug.scala:1342:87]
assign resumeReqRegs_lo_hi_3 = _GEN_11; // @[Debug.scala:1017:94, :1342:87]
wire [3:0] haveResetBitRegs_lo_1 = {haveResetBitRegs_lo_hi_1, haveResetBitRegs_lo_lo_1}; // @[Debug.scala:1017:94]
wire [1:0] _GEN_12 = {hartIsInResetSync_5, hartIsInResetSync_4}; // @[Debug.scala:948:33, :1017:94]
wire [1:0] haveResetBitRegs_hi_lo_1; // @[Debug.scala:1017:94]
assign haveResetBitRegs_hi_lo_1 = _GEN_12; // @[Debug.scala:1017:94]
wire [1:0] haveResetBitRegs_hi_lo_2; // @[Debug.scala:1019:66]
assign haveResetBitRegs_hi_lo_2 = _GEN_12; // @[Debug.scala:1017:94, :1019:66]
wire [1:0] resumeReqRegs_hi_lo; // @[Debug.scala:1320:62]
assign resumeReqRegs_hi_lo = _GEN_12; // @[Debug.scala:1017:94, :1320:62]
wire [1:0] haltedBitRegs_hi_lo; // @[Debug.scala:1327:86]
assign haltedBitRegs_hi_lo = _GEN_12; // @[Debug.scala:1017:94, :1327:86]
wire [1:0] haltedBitRegs_hi_lo_1; // @[Debug.scala:1330:91]
assign haltedBitRegs_hi_lo_1 = _GEN_12; // @[Debug.scala:1017:94, :1330:91]
wire [1:0] haltedBitRegs_hi_lo_2; // @[Debug.scala:1333:64]
assign haltedBitRegs_hi_lo_2 = _GEN_12; // @[Debug.scala:1017:94, :1333:64]
wire [1:0] resumeReqRegs_hi_lo_1; // @[Debug.scala:1338:91]
assign resumeReqRegs_hi_lo_1 = _GEN_12; // @[Debug.scala:1017:94, :1338:91]
wire [1:0] resumeReqRegs_hi_lo_3; // @[Debug.scala:1342:87]
assign resumeReqRegs_hi_lo_3 = _GEN_12; // @[Debug.scala:1017:94, :1342:87]
wire [1:0] _GEN_13 = {hartIsInResetSync_7, hartIsInResetSync_6}; // @[Debug.scala:948:33, :1017:94]
wire [1:0] haveResetBitRegs_hi_hi_1; // @[Debug.scala:1017:94]
assign haveResetBitRegs_hi_hi_1 = _GEN_13; // @[Debug.scala:1017:94]
wire [1:0] haveResetBitRegs_hi_hi_2; // @[Debug.scala:1019:66]
assign haveResetBitRegs_hi_hi_2 = _GEN_13; // @[Debug.scala:1017:94, :1019:66]
wire [1:0] resumeReqRegs_hi_hi; // @[Debug.scala:1320:62]
assign resumeReqRegs_hi_hi = _GEN_13; // @[Debug.scala:1017:94, :1320:62]
wire [1:0] haltedBitRegs_hi_hi; // @[Debug.scala:1327:86]
assign haltedBitRegs_hi_hi = _GEN_13; // @[Debug.scala:1017:94, :1327:86]
wire [1:0] haltedBitRegs_hi_hi_1; // @[Debug.scala:1330:91]
assign haltedBitRegs_hi_hi_1 = _GEN_13; // @[Debug.scala:1017:94, :1330:91]
wire [1:0] haltedBitRegs_hi_hi_2; // @[Debug.scala:1333:64]
assign haltedBitRegs_hi_hi_2 = _GEN_13; // @[Debug.scala:1017:94, :1333:64]
wire [1:0] resumeReqRegs_hi_hi_1; // @[Debug.scala:1338:91]
assign resumeReqRegs_hi_hi_1 = _GEN_13; // @[Debug.scala:1017:94, :1338:91]
wire [1:0] resumeReqRegs_hi_hi_3; // @[Debug.scala:1342:87]
assign resumeReqRegs_hi_hi_3 = _GEN_13; // @[Debug.scala:1017:94, :1342:87]
wire [3:0] haveResetBitRegs_hi_1 = {haveResetBitRegs_hi_hi_1, haveResetBitRegs_hi_lo_1}; // @[Debug.scala:1017:94]
wire [7:0] _haveResetBitRegs_T_3 = {haveResetBitRegs_hi_1, haveResetBitRegs_lo_1}; // @[Debug.scala:1017:94]
wire [7:0] _haveResetBitRegs_T_4 = _haveResetBitRegs_T_2 | _haveResetBitRegs_T_3; // @[Debug.scala:1017:{47,74,94}]
wire [3:0] haveResetBitRegs_lo_2 = {haveResetBitRegs_lo_hi_2, haveResetBitRegs_lo_lo_2}; // @[Debug.scala:1019:66]
wire [3:0] haveResetBitRegs_hi_2 = {haveResetBitRegs_hi_hi_2, haveResetBitRegs_hi_lo_2}; // @[Debug.scala:1019:66]
wire [7:0] _haveResetBitRegs_T_5 = {haveResetBitRegs_hi_2, haveResetBitRegs_lo_2}; // @[Debug.scala:1019:66]
wire [7:0] _haveResetBitRegs_T_6 = haveResetBitRegs | _haveResetBitRegs_T_5; // @[Debug.scala:865:31, :1019:{46,66}]
wire [4:0] DMCS2RdData_haltgroup; // @[Debug.scala:1025:34]
wire [4:0] _out_T_277; // @[RegisterRouter.scala:87:24]
wire _out_T_268; // @[RegisterRouter.scala:87:24]
wire _out_T_257; // @[RegisterRouter.scala:87:24]
wire [4:0] DMCS2WrData_haltgroup; // @[Debug.scala:1026:34]
wire DMCS2WrData_hgwrite; // @[Debug.scala:1026:34]
wire DMCS2WrData_hgselect; // @[Debug.scala:1026:34]
wire out_f_woready_17; // @[RegisterRouter.scala:87:24]
wire hgselectWrEn; // @[Debug.scala:1027:34]
wire out_f_woready_18; // @[RegisterRouter.scala:87:24]
wire hgwriteWrEn; // @[Debug.scala:1028:34]
wire out_f_woready_19; // @[RegisterRouter.scala:87:24]
wire haltgroupWrEn; // @[Debug.scala:1029:34]
wire hgDebugInt_0; // @[Debug.scala:1031:34]
wire hgDebugInt_1; // @[Debug.scala:1031:34]
wire hgDebugInt_2; // @[Debug.scala:1031:34]
wire hgDebugInt_3; // @[Debug.scala:1031:34]
wire hgDebugInt_4; // @[Debug.scala:1031:34]
wire hgDebugInt_5; // @[Debug.scala:1031:34]
wire hgDebugInt_6; // @[Debug.scala:1031:34]
wire hgDebugInt_7; // @[Debug.scala:1031:34]
reg hgParticipateHart_0; // @[Debug.scala:1036:38]
reg hgParticipateHart_1; // @[Debug.scala:1036:38]
reg hgParticipateHart_2; // @[Debug.scala:1036:38]
reg hgParticipateHart_3; // @[Debug.scala:1036:38]
reg hgParticipateHart_4; // @[Debug.scala:1036:38]
reg hgParticipateHart_5; // @[Debug.scala:1036:38]
reg hgParticipateHart_6; // @[Debug.scala:1036:38]
reg hgParticipateHart_7; // @[Debug.scala:1036:38]
wire [7:0] _GEN_14 = {{hgParticipateHart_7}, {hgParticipateHart_6}, {hgParticipateHart_5}, {hgParticipateHart_4}, {hgParticipateHart_3}, {hgParticipateHart_2}, {hgParticipateHart_1}, {hgParticipateHart_0}}; // @[Debug.scala:1036:38, :1050:29]
assign DMCS2RdData_haltgroup = {4'h0, _GEN_14[selectedHartReg]}; // @[Debug.scala:901:30, :1025:34, :1050:29]
reg hgFired_1; // @[Debug.scala:1107:38]
wire _hgHartFiring_1_T_6; // @[Debug.scala:1128:75]
wire hgHartFiring_1; // @[Debug.scala:1108:38]
wire _hgHartsAllHalted_1_T_30; // @[Debug.scala:1129:102]
wire hgHartsAllHalted_1; // @[Debug.scala:1110:38]
wire [9:0] _GEN_15 = {2'h0, haltedBitRegs} >> hartHaltedId; // @[Debug.scala:861:31, :876:36, :1128:60]
wire [7:0] _hgHartFiring_1_T = _GEN_15[7:0]; // @[Debug.scala:1128:60]
wire _hgHartFiring_1_T_1 = _hgHartFiring_1_T[0]; // @[Debug.scala:1128:60]
wire _hgHartFiring_1_T_2 = ~_hgHartFiring_1_T_1; // @[Debug.scala:1128:{46,60}]
wire _hgHartFiring_1_T_3 = hartHaltedWrEn & _hgHartFiring_1_T_2; // @[Debug.scala:875:36, :1128:{44,46}]
wire [2:0] _hgHartFiring_1_T_4 = hartHaltedId[2:0]; // @[Debug.scala:876:36]
wire _hgHartFiring_1_T_5 = _GEN_14[_hgHartFiring_1_T_4]; // @[Debug.scala:1050:29, :1128:140]
assign _hgHartFiring_1_T_6 = _hgHartFiring_1_T_3 & _hgHartFiring_1_T_5; // @[Debug.scala:1128:{44,75,140}]
assign hgHartFiring_1 = _hgHartFiring_1_T_6; // @[Debug.scala:1108:38, :1128:75]
wire _hgHartsAllHalted_1_T_8 = ~hgParticipateHart_0; // @[Debug.scala:1036:38, :1129:82]
wire _hgHartsAllHalted_1_T_9 = ~hgParticipateHart_1; // @[Debug.scala:1036:38, :1129:82]
wire _hgHartsAllHalted_1_T_10 = ~hgParticipateHart_2; // @[Debug.scala:1036:38, :1129:82]
wire _hgHartsAllHalted_1_T_11 = ~hgParticipateHart_3; // @[Debug.scala:1036:38, :1129:82]
wire _hgHartsAllHalted_1_T_12 = ~hgParticipateHart_4; // @[Debug.scala:1036:38, :1129:82]
wire _hgHartsAllHalted_1_T_13 = ~hgParticipateHart_5; // @[Debug.scala:1036:38, :1129:82]
wire _hgHartsAllHalted_1_T_14 = ~hgParticipateHart_6; // @[Debug.scala:1036:38, :1129:82]
wire _hgHartsAllHalted_1_T_15 = ~hgParticipateHart_7; // @[Debug.scala:1036:38, :1129:82]
wire _hgHartsAllHalted_1_T_16 = _hgHartsAllHalted_1_T | _hgHartsAllHalted_1_T_8; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_17 = _hgHartsAllHalted_1_T_1 | _hgHartsAllHalted_1_T_9; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_18 = _hgHartsAllHalted_1_T_2 | _hgHartsAllHalted_1_T_10; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_19 = _hgHartsAllHalted_1_T_3 | _hgHartsAllHalted_1_T_11; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_20 = _hgHartsAllHalted_1_T_4 | _hgHartsAllHalted_1_T_12; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_21 = _hgHartsAllHalted_1_T_5 | _hgHartsAllHalted_1_T_13; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_22 = _hgHartsAllHalted_1_T_6 | _hgHartsAllHalted_1_T_14; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_23 = _hgHartsAllHalted_1_T_7 | _hgHartsAllHalted_1_T_15; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_24 = _hgHartsAllHalted_1_T_16 & _hgHartsAllHalted_1_T_17; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_25 = _hgHartsAllHalted_1_T_24 & _hgHartsAllHalted_1_T_18; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_26 = _hgHartsAllHalted_1_T_25 & _hgHartsAllHalted_1_T_19; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_27 = _hgHartsAllHalted_1_T_26 & _hgHartsAllHalted_1_T_20; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_28 = _hgHartsAllHalted_1_T_27 & _hgHartsAllHalted_1_T_21; // @[package.scala:75:75]
wire _hgHartsAllHalted_1_T_29 = _hgHartsAllHalted_1_T_28 & _hgHartsAllHalted_1_T_22; // @[package.scala:75:75]
assign _hgHartsAllHalted_1_T_30 = _hgHartsAllHalted_1_T_29 & _hgHartsAllHalted_1_T_23; // @[package.scala:75:75]
assign hgHartsAllHalted_1 = _hgHartsAllHalted_1_T_30; // @[Debug.scala:1110:38, :1129:102]
assign hgDebugInt_0 = hgParticipateHart_0 & hgFired_1; // @[Debug.scala:1031:34, :1036:38, :1107:38, :1142:31]
assign hgDebugInt_1 = hgParticipateHart_1 & hgFired_1; // @[Debug.scala:1031:34, :1036:38, :1107:38, :1142:31]
assign hgDebugInt_2 = hgParticipateHart_2 & hgFired_1; // @[Debug.scala:1031:34, :1036:38, :1107:38, :1142:31]
assign hgDebugInt_3 = hgParticipateHart_3 & hgFired_1; // @[Debug.scala:1031:34, :1036:38, :1107:38, :1142:31]
assign hgDebugInt_4 = hgParticipateHart_4 & hgFired_1; // @[Debug.scala:1031:34, :1036:38, :1107:38, :1142:31]
assign hgDebugInt_5 = hgParticipateHart_5 & hgFired_1; // @[Debug.scala:1031:34, :1036:38, :1107:38, :1142:31]
assign hgDebugInt_6 = hgParticipateHart_6 & hgFired_1; // @[Debug.scala:1031:34, :1036:38, :1107:38, :1142:31]
assign hgDebugInt_7 = hgParticipateHart_7 & hgFired_1; // @[Debug.scala:1031:34, :1036:38, :1107:38, :1142:31]
assign io_hgDebugInt_0_0 = hgDebugInt_0 | hrDebugInt_0; // @[package.scala:75:75]
assign io_hgDebugInt_1_0 = hgDebugInt_1 | hrDebugInt_1; // @[package.scala:75:75]
assign io_hgDebugInt_2_0 = hgDebugInt_2 | hrDebugInt_2; // @[package.scala:75:75]
assign io_hgDebugInt_3_0 = hgDebugInt_3 | hrDebugInt_3; // @[package.scala:75:75]
assign io_hgDebugInt_4_0 = hgDebugInt_4 | hrDebugInt_4; // @[package.scala:75:75]
assign io_hgDebugInt_5_0 = hgDebugInt_5 | hrDebugInt_5; // @[package.scala:75:75]
assign io_hgDebugInt_6_0 = hgDebugInt_6 | hrDebugInt_6; // @[package.scala:75:75]
assign io_hgDebugInt_7_0 = hgDebugInt_7 | hrDebugInt_7; // @[package.scala:75:75]
wire [31:0] haltedStatus_0; // @[Debug.scala:1159:30]
wire [31:0] selectedHaltedStatus = haltedStatus_0; // @[Debug.scala:1159:30, :1172:35]
assign haltedStatus_0 = {24'h0, _haltedStatus_0_T}; // @[Debug.scala:1159:30, :1163:{26,43}]
wire haltedSummary = |haltedStatus_0; // @[Debug.scala:1159:30, :1169:48]
wire [31:0] _HALTSUM1RdData_T; // @[Debug.scala:1170:48]
wire [31:0] HALTSUM1RdData_haltsum1; // @[Debug.scala:1170:48]
wire [31:0] _out_T_1640 = HALTSUM1RdData_haltsum1; // @[RegisterRouter.scala:87:24]
assign _HALTSUM1RdData_T = _HALTSUM1RdData_WIRE; // @[Debug.scala:1170:48]
assign _HALTSUM1RdData_WIRE = {31'h0, haltedSummary}; // @[Debug.scala:1169:48, :1170:48]
assign HALTSUM1RdData_haltsum1 = _HALTSUM1RdData_T; // @[Debug.scala:1170:48]
wire [31:0] _HALTSUM0RdData_WIRE = selectedHaltedStatus; // @[Debug.scala:1172:35, :1173:55]
wire [31:0] _HALTSUM0RdData_T; // @[Debug.scala:1173:55]
wire [31:0] HALTSUM0RdData_haltsum0; // @[Debug.scala:1173:55]
wire [31:0] _out_T_988 = HALTSUM0RdData_haltsum0; // @[RegisterRouter.scala:87:24]
assign _HALTSUM0RdData_T = _HALTSUM0RdData_WIRE; // @[Debug.scala:1173:55]
assign HALTSUM0RdData_haltsum0 = _HALTSUM0RdData_T; // @[Debug.scala:1173:55]
reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34]
wire [2:0] ABSTRACTCSRdData_cmderr = ABSTRACTCSReg_cmderr; // @[Debug.scala:1183:34, :1185:39]
wire [2:0] _out_T_1267; // @[RegisterRouter.scala:87:24]
wire [2:0] ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39]
wire abstractCommandBusy; // @[Debug.scala:1220:39]
wire ABSTRACTCSRdData_busy; // @[Debug.scala:1185:39]
wire out_f_woready_115; // @[RegisterRouter.scala:87:24]
wire ABSTRACTCSWrEnMaybe; // @[Debug.scala:1188:39]
wire _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1742:44]
wire ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39]
wire ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe & ABSTRACTCSWrEnLegal; // @[Debug.scala:1188:39, :1190:39, :1191:51]
wire _errorBusy_T_16; // @[Debug.scala:1752:74]
wire errorBusy; // @[Debug.scala:1195:36]
wire errorException; // @[Debug.scala:1196:36]
wire errorUnsupported; // @[Debug.scala:1197:36]
wire errorHaltResume; // @[Debug.scala:1198:36]
wire [2:0] _ABSTRACTCSReg_cmderr_T = ~ABSTRACTCSWrData_cmderr; // @[Debug.scala:1184:39, :1214:58]
wire [2:0] _ABSTRACTCSReg_cmderr_T_1 = ABSTRACTCSReg_cmderr & _ABSTRACTCSReg_cmderr_T; // @[Debug.scala:1183:34, :1214:{56,58}]
wire _abstractCommandBusy_T; // @[Debug.scala:1740:42]
assign ABSTRACTCSRdData_busy = abstractCommandBusy; // @[Debug.scala:1185:39, :1220:39]
reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36]
wire [15:0] ABSTRACTAUTORdData_autoexecprogbuf = ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala:1235:36, :1237:41]
reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36]
wire [11:0] ABSTRACTAUTORdData_autoexecdata = ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala:1235:36, :1237:41]
wire [15:0] _out_T_684; // @[RegisterRouter.scala:87:24]
wire [15:0] _ABSTRACTAUTOReg_autoexecprogbuf_T = ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala:1236:41, :1249:79]
wire [11:0] ABSTRACTAUTOWrData_autoexecdata; // @[Debug.scala:1236:41]
wire [11:0] _out_T_673 = ABSTRACTAUTORdData_autoexecdata; // @[RegisterRouter.scala:87:24]
wire out_f_woready_56; // @[RegisterRouter.scala:87:24]
wire autoexecdataWrEnMaybe; // @[Debug.scala:1240:41]
wire out_f_woready_58; // @[RegisterRouter.scala:87:24]
wire autoexecprogbufWrEnMaybe; // @[Debug.scala:1241:44]
wire _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1744:44]
wire ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41]
wire [11:0] _ABSTRACTAUTOReg_autoexecdata_T = {4'h0, ABSTRACTAUTOWrData_autoexecdata[7:0]}; // @[Debug.scala:1236:41, :1252:73]
wire dmiAbstractDataAccessVec_0; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45]
wire dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45]
assign dmiAbstractDataAccessVec_0 = dmiAbstractDataWrEnMaybe_0 | dmiAbstractDataRdEn_0; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_1 = dmiAbstractDataWrEnMaybe_1 | dmiAbstractDataRdEn_1; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_2 = dmiAbstractDataWrEnMaybe_2 | dmiAbstractDataRdEn_2; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_3 = dmiAbstractDataWrEnMaybe_3 | dmiAbstractDataRdEn_3; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_4 = dmiAbstractDataWrEnMaybe_4 | dmiAbstractDataRdEn_4; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_5 = dmiAbstractDataWrEnMaybe_5 | dmiAbstractDataRdEn_5; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_6 = dmiAbstractDataWrEnMaybe_6 | dmiAbstractDataRdEn_6; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_7 = dmiAbstractDataWrEnMaybe_7 | dmiAbstractDataRdEn_7; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_8 = dmiAbstractDataWrEnMaybe_8 | dmiAbstractDataRdEn_8; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_9 = dmiAbstractDataWrEnMaybe_9 | dmiAbstractDataRdEn_9; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_10 = dmiAbstractDataWrEnMaybe_10 | dmiAbstractDataRdEn_10; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_11 = dmiAbstractDataWrEnMaybe_11 | dmiAbstractDataRdEn_11; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_12 = dmiAbstractDataWrEnMaybe_12 | dmiAbstractDataRdEn_12; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_13 = dmiAbstractDataWrEnMaybe_13 | dmiAbstractDataRdEn_13; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_14 = dmiAbstractDataWrEnMaybe_14 | dmiAbstractDataRdEn_14; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_15 = dmiAbstractDataWrEnMaybe_15 | dmiAbstractDataRdEn_15; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_16 = dmiAbstractDataWrEnMaybe_16 | dmiAbstractDataRdEn_16; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_17 = dmiAbstractDataWrEnMaybe_17 | dmiAbstractDataRdEn_17; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_18 = dmiAbstractDataWrEnMaybe_18 | dmiAbstractDataRdEn_18; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_19 = dmiAbstractDataWrEnMaybe_19 | dmiAbstractDataRdEn_19; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_20 = dmiAbstractDataWrEnMaybe_20 | dmiAbstractDataRdEn_20; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_21 = dmiAbstractDataWrEnMaybe_21 | dmiAbstractDataRdEn_21; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_22 = dmiAbstractDataWrEnMaybe_22 | dmiAbstractDataRdEn_22; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_23 = dmiAbstractDataWrEnMaybe_23 | dmiAbstractDataRdEn_23; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_24 = dmiAbstractDataWrEnMaybe_24 | dmiAbstractDataRdEn_24; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_25 = dmiAbstractDataWrEnMaybe_25 | dmiAbstractDataRdEn_25; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_26 = dmiAbstractDataWrEnMaybe_26 | dmiAbstractDataRdEn_26; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_27 = dmiAbstractDataWrEnMaybe_27 | dmiAbstractDataRdEn_27; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_28 = dmiAbstractDataWrEnMaybe_28 | dmiAbstractDataRdEn_28; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_29 = dmiAbstractDataWrEnMaybe_29 | dmiAbstractDataRdEn_29; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_30 = dmiAbstractDataWrEnMaybe_30 | dmiAbstractDataRdEn_30; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
assign dmiAbstractDataAccessVec_31 = dmiAbstractDataWrEnMaybe_31 | dmiAbstractDataRdEn_31; // @[Debug.scala:891:39, :893:44, :1257:45, :1258:105]
wire dmiProgramBufferAccessVec_0; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46]
wire dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46]
assign dmiProgramBufferAccessVec_0 = dmiProgramBufferWrEnMaybe_0 | dmiProgramBufferRdEn_0; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_1 = dmiProgramBufferWrEnMaybe_1 | dmiProgramBufferRdEn_1; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_2 = dmiProgramBufferWrEnMaybe_2 | dmiProgramBufferRdEn_2; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_3 = dmiProgramBufferWrEnMaybe_3 | dmiProgramBufferRdEn_3; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_4 = dmiProgramBufferWrEnMaybe_4 | dmiProgramBufferRdEn_4; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_5 = dmiProgramBufferWrEnMaybe_5 | dmiProgramBufferRdEn_5; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_6 = dmiProgramBufferWrEnMaybe_6 | dmiProgramBufferRdEn_6; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_7 = dmiProgramBufferWrEnMaybe_7 | dmiProgramBufferRdEn_7; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_8 = dmiProgramBufferWrEnMaybe_8 | dmiProgramBufferRdEn_8; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_9 = dmiProgramBufferWrEnMaybe_9 | dmiProgramBufferRdEn_9; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_10 = dmiProgramBufferWrEnMaybe_10 | dmiProgramBufferRdEn_10; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_11 = dmiProgramBufferWrEnMaybe_11 | dmiProgramBufferRdEn_11; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_12 = dmiProgramBufferWrEnMaybe_12 | dmiProgramBufferRdEn_12; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_13 = dmiProgramBufferWrEnMaybe_13 | dmiProgramBufferRdEn_13; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_14 = dmiProgramBufferWrEnMaybe_14 | dmiProgramBufferRdEn_14; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_15 = dmiProgramBufferWrEnMaybe_15 | dmiProgramBufferRdEn_15; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_16 = dmiProgramBufferWrEnMaybe_16 | dmiProgramBufferRdEn_16; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_17 = dmiProgramBufferWrEnMaybe_17 | dmiProgramBufferRdEn_17; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_18 = dmiProgramBufferWrEnMaybe_18 | dmiProgramBufferRdEn_18; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_19 = dmiProgramBufferWrEnMaybe_19 | dmiProgramBufferRdEn_19; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_20 = dmiProgramBufferWrEnMaybe_20 | dmiProgramBufferRdEn_20; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_21 = dmiProgramBufferWrEnMaybe_21 | dmiProgramBufferRdEn_21; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_22 = dmiProgramBufferWrEnMaybe_22 | dmiProgramBufferRdEn_22; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_23 = dmiProgramBufferWrEnMaybe_23 | dmiProgramBufferRdEn_23; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_24 = dmiProgramBufferWrEnMaybe_24 | dmiProgramBufferRdEn_24; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_25 = dmiProgramBufferWrEnMaybe_25 | dmiProgramBufferRdEn_25; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_26 = dmiProgramBufferWrEnMaybe_26 | dmiProgramBufferRdEn_26; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_27 = dmiProgramBufferWrEnMaybe_27 | dmiProgramBufferRdEn_27; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_28 = dmiProgramBufferWrEnMaybe_28 | dmiProgramBufferRdEn_28; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_29 = dmiProgramBufferWrEnMaybe_29 | dmiProgramBufferRdEn_29; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_30 = dmiProgramBufferWrEnMaybe_30 | dmiProgramBufferRdEn_30; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_31 = dmiProgramBufferWrEnMaybe_31 | dmiProgramBufferRdEn_31; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_32 = dmiProgramBufferWrEnMaybe_32 | dmiProgramBufferRdEn_32; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_33 = dmiProgramBufferWrEnMaybe_33 | dmiProgramBufferRdEn_33; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_34 = dmiProgramBufferWrEnMaybe_34 | dmiProgramBufferRdEn_34; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_35 = dmiProgramBufferWrEnMaybe_35 | dmiProgramBufferRdEn_35; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_36 = dmiProgramBufferWrEnMaybe_36 | dmiProgramBufferRdEn_36; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_37 = dmiProgramBufferWrEnMaybe_37 | dmiProgramBufferRdEn_37; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_38 = dmiProgramBufferWrEnMaybe_38 | dmiProgramBufferRdEn_38; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_39 = dmiProgramBufferWrEnMaybe_39 | dmiProgramBufferRdEn_39; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_40 = dmiProgramBufferWrEnMaybe_40 | dmiProgramBufferRdEn_40; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_41 = dmiProgramBufferWrEnMaybe_41 | dmiProgramBufferRdEn_41; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_42 = dmiProgramBufferWrEnMaybe_42 | dmiProgramBufferRdEn_42; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_43 = dmiProgramBufferWrEnMaybe_43 | dmiProgramBufferRdEn_43; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_44 = dmiProgramBufferWrEnMaybe_44 | dmiProgramBufferRdEn_44; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_45 = dmiProgramBufferWrEnMaybe_45 | dmiProgramBufferRdEn_45; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_46 = dmiProgramBufferWrEnMaybe_46 | dmiProgramBufferRdEn_46; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_47 = dmiProgramBufferWrEnMaybe_47 | dmiProgramBufferRdEn_47; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_48 = dmiProgramBufferWrEnMaybe_48 | dmiProgramBufferRdEn_48; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_49 = dmiProgramBufferWrEnMaybe_49 | dmiProgramBufferRdEn_49; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_50 = dmiProgramBufferWrEnMaybe_50 | dmiProgramBufferRdEn_50; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_51 = dmiProgramBufferWrEnMaybe_51 | dmiProgramBufferRdEn_51; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_52 = dmiProgramBufferWrEnMaybe_52 | dmiProgramBufferRdEn_52; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_53 = dmiProgramBufferWrEnMaybe_53 | dmiProgramBufferRdEn_53; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_54 = dmiProgramBufferWrEnMaybe_54 | dmiProgramBufferRdEn_54; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_55 = dmiProgramBufferWrEnMaybe_55 | dmiProgramBufferRdEn_55; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_56 = dmiProgramBufferWrEnMaybe_56 | dmiProgramBufferRdEn_56; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_57 = dmiProgramBufferWrEnMaybe_57 | dmiProgramBufferRdEn_57; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_58 = dmiProgramBufferWrEnMaybe_58 | dmiProgramBufferRdEn_58; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_59 = dmiProgramBufferWrEnMaybe_59 | dmiProgramBufferRdEn_59; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_60 = dmiProgramBufferWrEnMaybe_60 | dmiProgramBufferRdEn_60; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_61 = dmiProgramBufferWrEnMaybe_61 | dmiProgramBufferRdEn_61; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_62 = dmiProgramBufferWrEnMaybe_62 | dmiProgramBufferRdEn_62; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
assign dmiProgramBufferAccessVec_63 = dmiProgramBufferWrEnMaybe_63 | dmiProgramBufferRdEn_63; // @[Debug.scala:887:40, :889:45, :1260:46, :1261:108]
wire _dmiAbstractDataAccess_T = dmiAbstractDataAccessVec_0 | dmiAbstractDataAccessVec_1; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_1 = _dmiAbstractDataAccess_T | dmiAbstractDataAccessVec_2; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_2 = _dmiAbstractDataAccess_T_1 | dmiAbstractDataAccessVec_3; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_3 = _dmiAbstractDataAccess_T_2 | dmiAbstractDataAccessVec_4; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_4 = _dmiAbstractDataAccess_T_3 | dmiAbstractDataAccessVec_5; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_5 = _dmiAbstractDataAccess_T_4 | dmiAbstractDataAccessVec_6; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_6 = _dmiAbstractDataAccess_T_5 | dmiAbstractDataAccessVec_7; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_7 = _dmiAbstractDataAccess_T_6 | dmiAbstractDataAccessVec_8; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_8 = _dmiAbstractDataAccess_T_7 | dmiAbstractDataAccessVec_9; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_9 = _dmiAbstractDataAccess_T_8 | dmiAbstractDataAccessVec_10; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_10 = _dmiAbstractDataAccess_T_9 | dmiAbstractDataAccessVec_11; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_11 = _dmiAbstractDataAccess_T_10 | dmiAbstractDataAccessVec_12; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_12 = _dmiAbstractDataAccess_T_11 | dmiAbstractDataAccessVec_13; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_13 = _dmiAbstractDataAccess_T_12 | dmiAbstractDataAccessVec_14; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_14 = _dmiAbstractDataAccess_T_13 | dmiAbstractDataAccessVec_15; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_15 = _dmiAbstractDataAccess_T_14 | dmiAbstractDataAccessVec_16; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_16 = _dmiAbstractDataAccess_T_15 | dmiAbstractDataAccessVec_17; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_17 = _dmiAbstractDataAccess_T_16 | dmiAbstractDataAccessVec_18; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_18 = _dmiAbstractDataAccess_T_17 | dmiAbstractDataAccessVec_19; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_19 = _dmiAbstractDataAccess_T_18 | dmiAbstractDataAccessVec_20; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_20 = _dmiAbstractDataAccess_T_19 | dmiAbstractDataAccessVec_21; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_21 = _dmiAbstractDataAccess_T_20 | dmiAbstractDataAccessVec_22; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_22 = _dmiAbstractDataAccess_T_21 | dmiAbstractDataAccessVec_23; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_23 = _dmiAbstractDataAccess_T_22 | dmiAbstractDataAccessVec_24; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_24 = _dmiAbstractDataAccess_T_23 | dmiAbstractDataAccessVec_25; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_25 = _dmiAbstractDataAccess_T_24 | dmiAbstractDataAccessVec_26; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_26 = _dmiAbstractDataAccess_T_25 | dmiAbstractDataAccessVec_27; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_27 = _dmiAbstractDataAccess_T_26 | dmiAbstractDataAccessVec_28; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_28 = _dmiAbstractDataAccess_T_27 | dmiAbstractDataAccessVec_29; // @[Debug.scala:1257:45, :1263:68]
wire _dmiAbstractDataAccess_T_29 = _dmiAbstractDataAccess_T_28 | dmiAbstractDataAccessVec_30; // @[Debug.scala:1257:45, :1263:68]
wire dmiAbstractDataAccess = _dmiAbstractDataAccess_T_29 | dmiAbstractDataAccessVec_31; // @[Debug.scala:1257:45, :1263:68]
wire _dmiProgramBufferAccess_T = dmiProgramBufferAccessVec_0 | dmiProgramBufferAccessVec_1; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_1 = _dmiProgramBufferAccess_T | dmiProgramBufferAccessVec_2; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_2 = _dmiProgramBufferAccess_T_1 | dmiProgramBufferAccessVec_3; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_3 = _dmiProgramBufferAccess_T_2 | dmiProgramBufferAccessVec_4; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_4 = _dmiProgramBufferAccess_T_3 | dmiProgramBufferAccessVec_5; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_5 = _dmiProgramBufferAccess_T_4 | dmiProgramBufferAccessVec_6; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_6 = _dmiProgramBufferAccess_T_5 | dmiProgramBufferAccessVec_7; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_7 = _dmiProgramBufferAccess_T_6 | dmiProgramBufferAccessVec_8; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_8 = _dmiProgramBufferAccess_T_7 | dmiProgramBufferAccessVec_9; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_9 = _dmiProgramBufferAccess_T_8 | dmiProgramBufferAccessVec_10; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_10 = _dmiProgramBufferAccess_T_9 | dmiProgramBufferAccessVec_11; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_11 = _dmiProgramBufferAccess_T_10 | dmiProgramBufferAccessVec_12; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_12 = _dmiProgramBufferAccess_T_11 | dmiProgramBufferAccessVec_13; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_13 = _dmiProgramBufferAccess_T_12 | dmiProgramBufferAccessVec_14; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_14 = _dmiProgramBufferAccess_T_13 | dmiProgramBufferAccessVec_15; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_15 = _dmiProgramBufferAccess_T_14 | dmiProgramBufferAccessVec_16; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_16 = _dmiProgramBufferAccess_T_15 | dmiProgramBufferAccessVec_17; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_17 = _dmiProgramBufferAccess_T_16 | dmiProgramBufferAccessVec_18; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_18 = _dmiProgramBufferAccess_T_17 | dmiProgramBufferAccessVec_19; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_19 = _dmiProgramBufferAccess_T_18 | dmiProgramBufferAccessVec_20; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_20 = _dmiProgramBufferAccess_T_19 | dmiProgramBufferAccessVec_21; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_21 = _dmiProgramBufferAccess_T_20 | dmiProgramBufferAccessVec_22; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_22 = _dmiProgramBufferAccess_T_21 | dmiProgramBufferAccessVec_23; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_23 = _dmiProgramBufferAccess_T_22 | dmiProgramBufferAccessVec_24; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_24 = _dmiProgramBufferAccess_T_23 | dmiProgramBufferAccessVec_25; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_25 = _dmiProgramBufferAccess_T_24 | dmiProgramBufferAccessVec_26; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_26 = _dmiProgramBufferAccess_T_25 | dmiProgramBufferAccessVec_27; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_27 = _dmiProgramBufferAccess_T_26 | dmiProgramBufferAccessVec_28; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_28 = _dmiProgramBufferAccess_T_27 | dmiProgramBufferAccessVec_29; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_29 = _dmiProgramBufferAccess_T_28 | dmiProgramBufferAccessVec_30; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_30 = _dmiProgramBufferAccess_T_29 | dmiProgramBufferAccessVec_31; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_31 = _dmiProgramBufferAccess_T_30 | dmiProgramBufferAccessVec_32; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_32 = _dmiProgramBufferAccess_T_31 | dmiProgramBufferAccessVec_33; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_33 = _dmiProgramBufferAccess_T_32 | dmiProgramBufferAccessVec_34; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_34 = _dmiProgramBufferAccess_T_33 | dmiProgramBufferAccessVec_35; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_35 = _dmiProgramBufferAccess_T_34 | dmiProgramBufferAccessVec_36; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_36 = _dmiProgramBufferAccess_T_35 | dmiProgramBufferAccessVec_37; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_37 = _dmiProgramBufferAccess_T_36 | dmiProgramBufferAccessVec_38; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_38 = _dmiProgramBufferAccess_T_37 | dmiProgramBufferAccessVec_39; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_39 = _dmiProgramBufferAccess_T_38 | dmiProgramBufferAccessVec_40; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_40 = _dmiProgramBufferAccess_T_39 | dmiProgramBufferAccessVec_41; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_41 = _dmiProgramBufferAccess_T_40 | dmiProgramBufferAccessVec_42; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_42 = _dmiProgramBufferAccess_T_41 | dmiProgramBufferAccessVec_43; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_43 = _dmiProgramBufferAccess_T_42 | dmiProgramBufferAccessVec_44; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_44 = _dmiProgramBufferAccess_T_43 | dmiProgramBufferAccessVec_45; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_45 = _dmiProgramBufferAccess_T_44 | dmiProgramBufferAccessVec_46; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_46 = _dmiProgramBufferAccess_T_45 | dmiProgramBufferAccessVec_47; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_47 = _dmiProgramBufferAccess_T_46 | dmiProgramBufferAccessVec_48; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_48 = _dmiProgramBufferAccess_T_47 | dmiProgramBufferAccessVec_49; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_49 = _dmiProgramBufferAccess_T_48 | dmiProgramBufferAccessVec_50; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_50 = _dmiProgramBufferAccess_T_49 | dmiProgramBufferAccessVec_51; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_51 = _dmiProgramBufferAccess_T_50 | dmiProgramBufferAccessVec_52; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_52 = _dmiProgramBufferAccess_T_51 | dmiProgramBufferAccessVec_53; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_53 = _dmiProgramBufferAccess_T_52 | dmiProgramBufferAccessVec_54; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_54 = _dmiProgramBufferAccess_T_53 | dmiProgramBufferAccessVec_55; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_55 = _dmiProgramBufferAccess_T_54 | dmiProgramBufferAccessVec_56; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_56 = _dmiProgramBufferAccess_T_55 | dmiProgramBufferAccessVec_57; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_57 = _dmiProgramBufferAccess_T_56 | dmiProgramBufferAccessVec_58; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_58 = _dmiProgramBufferAccess_T_57 | dmiProgramBufferAccessVec_59; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_59 = _dmiProgramBufferAccess_T_58 | dmiProgramBufferAccessVec_60; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_60 = _dmiProgramBufferAccess_T_59 | dmiProgramBufferAccessVec_61; // @[Debug.scala:1260:46, :1264:69]
wire _dmiProgramBufferAccess_T_61 = _dmiProgramBufferAccess_T_60 | dmiProgramBufferAccessVec_62; // @[Debug.scala:1260:46, :1264:69]
wire dmiProgramBufferAccess = _dmiProgramBufferAccess_T_61 | dmiProgramBufferAccessVec_63; // @[Debug.scala:1260:46, :1264:69]
wire _autoexecData_0_T; // @[Debug.scala:1269:140]
wire _autoexecData_1_T; // @[Debug.scala:1269:140]
wire _autoexecData_2_T; // @[Debug.scala:1269:140]
wire _autoexecData_3_T; // @[Debug.scala:1269:140]
wire _autoexecData_4_T; // @[Debug.scala:1269:140]
wire _autoexecData_5_T; // @[Debug.scala:1269:140]
wire _autoexecData_6_T; // @[Debug.scala:1269:140]
wire _autoexecData_7_T; // @[Debug.scala:1269:140]
wire autoexecData_0; // @[Debug.scala:1267:33]
wire autoexecData_1; // @[Debug.scala:1267:33]
wire autoexecData_2; // @[Debug.scala:1267:33]
wire autoexecData_3; // @[Debug.scala:1267:33]
wire autoexecData_4; // @[Debug.scala:1267:33]
wire autoexecData_5; // @[Debug.scala:1267:33]
wire autoexecData_6; // @[Debug.scala:1267:33]
wire autoexecData_7; // @[Debug.scala:1267:33]
wire _autoexecProg_0_T; // @[Debug.scala:1270:144]
wire _autoexecProg_1_T; // @[Debug.scala:1270:144]
wire _autoexecProg_2_T; // @[Debug.scala:1270:144]
wire _autoexecProg_3_T; // @[Debug.scala:1270:144]
wire _autoexecProg_4_T; // @[Debug.scala:1270:144]
wire _autoexecProg_5_T; // @[Debug.scala:1270:144]
wire _autoexecProg_6_T; // @[Debug.scala:1270:144]
wire _autoexecProg_7_T; // @[Debug.scala:1270:144]
wire _autoexecProg_8_T; // @[Debug.scala:1270:144]
wire _autoexecProg_9_T; // @[Debug.scala:1270:144]
wire _autoexecProg_10_T; // @[Debug.scala:1270:144]
wire _autoexecProg_11_T; // @[Debug.scala:1270:144]
wire _autoexecProg_12_T; // @[Debug.scala:1270:144]
wire _autoexecProg_13_T; // @[Debug.scala:1270:144]
wire _autoexecProg_14_T; // @[Debug.scala:1270:144]
wire _autoexecProg_15_T; // @[Debug.scala:1270:144]
wire autoexecProg_0; // @[Debug.scala:1268:33]
wire autoexecProg_1; // @[Debug.scala:1268:33]
wire autoexecProg_2; // @[Debug.scala:1268:33]
wire autoexecProg_3; // @[Debug.scala:1268:33]
wire autoexecProg_4; // @[Debug.scala:1268:33]
wire autoexecProg_5; // @[Debug.scala:1268:33]
wire autoexecProg_6; // @[Debug.scala:1268:33]
wire autoexecProg_7; // @[Debug.scala:1268:33]
wire autoexecProg_8; // @[Debug.scala:1268:33]
wire autoexecProg_9; // @[Debug.scala:1268:33]
wire autoexecProg_10; // @[Debug.scala:1268:33]
wire autoexecProg_11; // @[Debug.scala:1268:33]
wire autoexecProg_12; // @[Debug.scala:1268:33]
wire autoexecProg_13; // @[Debug.scala:1268:33]
wire autoexecProg_14; // @[Debug.scala:1268:33]
wire autoexecProg_15; // @[Debug.scala:1268:33]
assign _autoexecData_0_T = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_0 = _autoexecData_0_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_1_T = dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_1 = _autoexecData_1_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_2_T = dmiAbstractDataAccessVec_8 & ABSTRACTAUTOReg_autoexecdata[2]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_2 = _autoexecData_2_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_3_T = dmiAbstractDataAccessVec_12 & ABSTRACTAUTOReg_autoexecdata[3]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_3 = _autoexecData_3_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_4_T = dmiAbstractDataAccessVec_16 & ABSTRACTAUTOReg_autoexecdata[4]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_4 = _autoexecData_4_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_5_T = dmiAbstractDataAccessVec_20 & ABSTRACTAUTOReg_autoexecdata[5]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_5 = _autoexecData_5_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_6_T = dmiAbstractDataAccessVec_24 & ABSTRACTAUTOReg_autoexecdata[6]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_6 = _autoexecData_6_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecData_7_T = dmiAbstractDataAccessVec_28 & ABSTRACTAUTOReg_autoexecdata[7]; // @[Debug.scala:1235:36, :1257:45, :1269:{54,140}]
assign autoexecData_7 = _autoexecData_7_T; // @[Debug.scala:1267:33, :1269:140]
assign _autoexecProg_0_T = dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_0 = _autoexecProg_0_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_1_T = dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_1 = _autoexecProg_1_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_2_T = dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_2 = _autoexecProg_2_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_3_T = dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_3 = _autoexecProg_3_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_4_T = dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_4 = _autoexecProg_4_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_5_T = dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_5 = _autoexecProg_5_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_6_T = dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_6 = _autoexecProg_6_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_7_T = dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_7 = _autoexecProg_7_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_8_T = dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_8 = _autoexecProg_8_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_9_T = dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_9 = _autoexecProg_9_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_10_T = dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_10 = _autoexecProg_10_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_11_T = dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_11 = _autoexecProg_11_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_12_T = dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_12 = _autoexecProg_12_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_13_T = dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_13 = _autoexecProg_13_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_14_T = dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_14 = _autoexecProg_14_T; // @[Debug.scala:1268:33, :1270:144]
assign _autoexecProg_15_T = dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala:1235:36, :1260:46, :1270:{57,144}]
assign autoexecProg_15 = _autoexecProg_15_T; // @[Debug.scala:1268:33, :1270:144]
wire _autoexec_T = autoexecData_0 | autoexecData_1; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_1 = _autoexec_T | autoexecData_2; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_2 = _autoexec_T_1 | autoexecData_3; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_3 = _autoexec_T_2 | autoexecData_4; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_4 = _autoexec_T_3 | autoexecData_5; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_5 = _autoexec_T_4 | autoexecData_6; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_6 = _autoexec_T_5 | autoexecData_7; // @[Debug.scala:1267:33, :1272:42]
wire _autoexec_T_7 = autoexecProg_0 | autoexecProg_1; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_8 = _autoexec_T_7 | autoexecProg_2; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_9 = _autoexec_T_8 | autoexecProg_3; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_10 = _autoexec_T_9 | autoexecProg_4; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_11 = _autoexec_T_10 | autoexecProg_5; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_12 = _autoexec_T_11 | autoexecProg_6; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_13 = _autoexec_T_12 | autoexecProg_7; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_14 = _autoexec_T_13 | autoexecProg_8; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_15 = _autoexec_T_14 | autoexecProg_9; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_16 = _autoexec_T_15 | autoexecProg_10; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_17 = _autoexec_T_16 | autoexecProg_11; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_18 = _autoexec_T_17 | autoexecProg_12; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_19 = _autoexec_T_18 | autoexecProg_13; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_20 = _autoexec_T_19 | autoexecProg_14; // @[Debug.scala:1268:33, :1272:73]
wire _autoexec_T_21 = _autoexec_T_20 | autoexecProg_15; // @[Debug.scala:1268:33, :1272:73]
wire autoexec = _autoexec_T_6 | _autoexec_T_21; // @[Debug.scala:1272:{42,48,73}]
reg [7:0] COMMANDReg_cmdtype; // @[Debug.scala:1277:25]
reg [23:0] COMMANDReg_control; // @[Debug.scala:1277:25]
wire [31:0] COMMANDWrDataVal; // @[Debug.scala:1279:39]
wire [31:0] _COMMANDWrData_WIRE_1 = COMMANDWrDataVal; // @[Debug.scala:1279:39, :1280:65]
wire [7:0] _COMMANDWrData_T_1; // @[Debug.scala:1280:65]
wire [23:0] _COMMANDWrData_T; // @[Debug.scala:1280:65]
wire [7:0] COMMANDWrData_cmdtype = _COMMANDWrData_WIRE_cmdtype; // @[Debug.scala:1280:{39,65}]
wire [23:0] COMMANDWrData_control = _COMMANDWrData_WIRE_control; // @[Debug.scala:1280:{39,65}]
assign _COMMANDWrData_T = _COMMANDWrData_WIRE_1[23:0]; // @[Debug.scala:1280:65]
assign _COMMANDWrData_WIRE_control = _COMMANDWrData_T; // @[Debug.scala:1280:65]
assign _COMMANDWrData_T_1 = _COMMANDWrData_WIRE_1[31:24]; // @[Debug.scala:1280:65]
assign _COMMANDWrData_WIRE_cmdtype = _COMMANDWrData_T_1; // @[Debug.scala:1280:65]
wire out_f_woready_144; // @[RegisterRouter.scala:87:24]
wire COMMANDWrEnMaybe; // @[Debug.scala:1281:39]
wire _COMMANDWrEnLegal_T; // @[Debug.scala:1743:44]
wire COMMANDWrEnLegal; // @[Debug.scala:1282:39]
wire out_f_roready_144; // @[RegisterRouter.scala:87:24]
wire COMMANDRdEn; // @[Debug.scala:1283:32]
wire COMMANDWrEn = COMMANDWrEnMaybe & COMMANDWrEnLegal; // @[Debug.scala:1281:39, :1282:39, :1285:40]
reg [7:0] abstractDataMem_0; // @[Debug.scala:1300:36]
wire [7:0] _out_T_350 = abstractDataMem_0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2347 = abstractDataMem_0; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_1; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_2; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_3; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_4; // @[Debug.scala:1300:36]
wire [7:0] _out_T_79 = abstractDataMem_4; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_5; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_6; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_7; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_8; // @[Debug.scala:1300:36]
wire [7:0] _out_T_803 = abstractDataMem_8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2259 = abstractDataMem_8; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_9; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_10; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_11; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_12; // @[Debug.scala:1300:36]
wire [7:0] _out_T_1367 = abstractDataMem_12; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_13; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_14; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_15; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_16; // @[Debug.scala:1300:36]
wire [7:0] _out_T_306 = abstractDataMem_16; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3566 = abstractDataMem_16; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_17; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_18; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_19; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_20; // @[Debug.scala:1300:36]
wire [7:0] _out_T_134 = abstractDataMem_20; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_21; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_22; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_23; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_24; // @[Debug.scala:1300:36]
wire [7:0] _out_T_438 = abstractDataMem_24; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1707 = abstractDataMem_24; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_25; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_26; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_27; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_28; // @[Debug.scala:1300:36]
wire [7:0] _out_T_1455 = abstractDataMem_28; // @[RegisterRouter.scala:87:24]
reg [7:0] abstractDataMem_29; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_30; // @[Debug.scala:1300:36]
reg [7:0] abstractDataMem_31; // @[Debug.scala:1300:36]
wire [7:0] abstractDataNxt_0; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_1; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_2; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_3; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_4; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_5; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_6; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_7; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_8; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_9; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_10; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_11; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_12; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_13; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_14; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_15; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_16; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_17; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_18; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_19; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_20; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_21; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_22; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_23; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_24; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_25; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_26; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_27; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_28; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_29; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_30; // @[Debug.scala:1301:41]
wire [7:0] abstractDataNxt_31; // @[Debug.scala:1301:41]
reg [7:0] programBufferMem_0; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1170 = programBufferMem_0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2507 = programBufferMem_0; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_1; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_2; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_3; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_4; // @[Debug.scala:1306:34]
wire [7:0] _out_T_902 = programBufferMem_4; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_5; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_6; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_7; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_8; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1214 = programBufferMem_8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3174 = programBufferMem_8; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_9; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_10; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_11; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_12; // @[Debug.scala:1306:34]
wire [7:0] _out_T_222 = programBufferMem_12; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_13; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_14; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_15; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_16; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1598 = programBufferMem_16; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2027 = programBufferMem_16; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_17; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_18; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_19; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_20; // @[Debug.scala:1306:34]
wire [7:0] _out_T_704 = programBufferMem_20; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_21; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_22; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_23; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_24; // @[Debug.scala:1306:34]
wire [7:0] _out_T_858 = programBufferMem_24; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2667 = programBufferMem_24; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_25; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_26; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_27; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_28; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1411 = programBufferMem_28; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_29; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_30; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_31; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_32; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1543 = programBufferMem_32; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3406 = programBufferMem_32; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_33; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_34; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_35; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_36; // @[Debug.scala:1306:34]
wire [7:0] _out_T_178 = programBufferMem_36; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_37; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_38; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_39; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_40; // @[Debug.scala:1306:34]
wire [7:0] _out_T_629 = programBufferMem_40; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2942 = programBufferMem_40; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_41; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_42; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_43; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_44; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1499 = programBufferMem_44; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_45; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_46; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_47; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_48; // @[Debug.scala:1306:34]
wire [7:0] _out_T_1323 = programBufferMem_48; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1867 = programBufferMem_48; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_49; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_50; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_51; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_52; // @[Debug.scala:1306:34]
wire [7:0] _out_T_946 = programBufferMem_52; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_53; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_54; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_55; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_56; // @[Debug.scala:1306:34]
wire [7:0] _out_T_748 = programBufferMem_56; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2755 = programBufferMem_56; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_57; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_58; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_59; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_60; // @[Debug.scala:1306:34]
wire [7:0] _out_T_394 = programBufferMem_60; // @[RegisterRouter.scala:87:24]
reg [7:0] programBufferMem_61; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_62; // @[Debug.scala:1306:34]
reg [7:0] programBufferMem_63; // @[Debug.scala:1306:34]
wire [7:0] programBufferNxt_0; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_1; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_2; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_3; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_4; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_5; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_6; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_7; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_8; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_9; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_10; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_11; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_12; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_13; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_14; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_15; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_16; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_17; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_18; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_19; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_20; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_21; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_22; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_23; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_24; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_25; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_26; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_27; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_28; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_29; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_30; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_31; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_32; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_33; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_34; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_35; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_36; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_37; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_38; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_39; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_40; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_41; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_42; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_43; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_44; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_45; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_46; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_47; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_48; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_49; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_50; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_51; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_52; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_53; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_54; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_55; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_56; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_57; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_58; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_59; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_60; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_61; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_62; // @[Debug.scala:1307:39]
wire [7:0] programBufferNxt_63; // @[Debug.scala:1307:39]
wire [3:0] resumeReqRegs_lo = {resumeReqRegs_lo_hi, resumeReqRegs_lo_lo}; // @[Debug.scala:1320:62]
wire [3:0] resumeReqRegs_hi = {resumeReqRegs_hi_hi, resumeReqRegs_hi_lo}; // @[Debug.scala:1320:62]
wire [7:0] _resumeReqRegs_T = {resumeReqRegs_hi, resumeReqRegs_lo}; // @[Debug.scala:1320:62]
wire [7:0] _resumeReqRegs_T_1 = ~_resumeReqRegs_T; // @[Debug.scala:1320:{42,62}]
wire [7:0] _resumeReqRegs_T_2 = resumeReqRegs & _resumeReqRegs_T_1; // @[Debug.scala:863:31, :1320:{40,42}]
wire [1023:0] hartHaltedIdIndex = 1024'h1 << hartHaltedId; // @[OneHot.scala:58:35]
wire [1023:0] hartResumingIdIndex = 1024'h1 << hartResumingId; // @[OneHot.scala:58:35]
wire [1023:0] hartselIndex = 1024'h1 << io_innerCtrl_bits_hartsel_0; // @[OneHot.scala:58:35]
wire [1023:0] _haltedBitRegs_T = {1016'h0, haltedBitRegs} | hartHaltedIdIndex; // @[OneHot.scala:58:35]
wire [3:0] haltedBitRegs_lo = {haltedBitRegs_lo_hi, haltedBitRegs_lo_lo}; // @[Debug.scala:1327:86]
wire [3:0] haltedBitRegs_hi = {haltedBitRegs_hi_hi, haltedBitRegs_hi_lo}; // @[Debug.scala:1327:86]
wire [7:0] _haltedBitRegs_T_1 = {haltedBitRegs_hi, haltedBitRegs_lo}; // @[Debug.scala:1327:86]
wire [7:0] _haltedBitRegs_T_2 = ~_haltedBitRegs_T_1; // @[Debug.scala:1327:{66,86}]
wire [1023:0] _haltedBitRegs_T_3 = {1016'h0, _haltedBitRegs_T[7:0] & _haltedBitRegs_T_2}; // @[Debug.scala:1327:{43,64,66}]
wire [1023:0] _haltedBitRegs_T_4 = ~hartResumingIdIndex; // @[OneHot.scala:58:35]
wire [1023:0] _haltedBitRegs_T_5 = {1016'h0, _haltedBitRegs_T_4[7:0] & haltedBitRegs}; // @[Debug.scala:861:31, :1330:{43,45}]
wire [3:0] haltedBitRegs_lo_1 = {haltedBitRegs_lo_hi_1, haltedBitRegs_lo_lo_1}; // @[Debug.scala:1330:91]
wire [3:0] haltedBitRegs_hi_1 = {haltedBitRegs_hi_hi_1, haltedBitRegs_hi_lo_1}; // @[Debug.scala:1330:91]
wire [7:0] _haltedBitRegs_T_6 = {haltedBitRegs_hi_1, haltedBitRegs_lo_1}; // @[Debug.scala:1330:91]
wire [7:0] _haltedBitRegs_T_7 = ~_haltedBitRegs_T_6; // @[Debug.scala:1330:{71,91}]
wire [1023:0] _haltedBitRegs_T_8 = {1016'h0, _haltedBitRegs_T_5[7:0] & _haltedBitRegs_T_7}; // @[Debug.scala:1330:{43,69,71}]
wire [3:0] haltedBitRegs_lo_2 = {haltedBitRegs_lo_hi_2, haltedBitRegs_lo_lo_2}; // @[Debug.scala:1333:64]
wire [3:0] haltedBitRegs_hi_2 = {haltedBitRegs_hi_hi_2, haltedBitRegs_hi_lo_2}; // @[Debug.scala:1333:64]
wire [7:0] _haltedBitRegs_T_9 = {haltedBitRegs_hi_2, haltedBitRegs_lo_2}; // @[Debug.scala:1333:64]
wire [7:0] _haltedBitRegs_T_10 = ~_haltedBitRegs_T_9; // @[Debug.scala:1333:{44,64}]
wire [7:0] _haltedBitRegs_T_11 = haltedBitRegs & _haltedBitRegs_T_10; // @[Debug.scala:861:31, :1333:{42,44}]
wire [1023:0] _resumeReqRegs_T_3 = ~hartResumingIdIndex; // @[OneHot.scala:58:35]
wire [1023:0] _resumeReqRegs_T_4 = {1016'h0, _resumeReqRegs_T_3[7:0] & resumeReqRegs}; // @[Debug.scala:863:31, :1338:{43,45}]
wire [3:0] resumeReqRegs_lo_1 = {resumeReqRegs_lo_hi_1, resumeReqRegs_lo_lo_1}; // @[Debug.scala:1338:91]
wire [3:0] resumeReqRegs_hi_1 = {resumeReqRegs_hi_hi_1, resumeReqRegs_hi_lo_1}; // @[Debug.scala:1338:91]
wire [7:0] _resumeReqRegs_T_5 = {resumeReqRegs_hi_1, resumeReqRegs_lo_1}; // @[Debug.scala:1338:91]
wire [7:0] _resumeReqRegs_T_6 = ~_resumeReqRegs_T_5; // @[Debug.scala:1338:{71,91}]
wire [1023:0] _resumeReqRegs_T_7 = {1016'h0, _resumeReqRegs_T_4[7:0] & _resumeReqRegs_T_6}; // @[Debug.scala:1338:{43,69,71}]
wire [3:0] resumeReqRegs_lo_2 = {resumeReqRegs_lo_hi_2, resumeReqRegs_lo_lo_2}; // @[Debug.scala:1342:57]
wire [3:0] resumeReqRegs_hi_2 = {resumeReqRegs_hi_hi_2, resumeReqRegs_hi_lo_2}; // @[Debug.scala:1342:57]
wire [7:0] _resumeReqRegs_T_8 = {resumeReqRegs_hi_2, resumeReqRegs_lo_2}; // @[Debug.scala:1342:57]
wire [7:0] _resumeReqRegs_T_9 = resumeReqRegs | _resumeReqRegs_T_8; // @[Debug.scala:863:31, :1342:{43,57}]
wire [3:0] resumeReqRegs_lo_3 = {resumeReqRegs_lo_hi_3, resumeReqRegs_lo_lo_3}; // @[Debug.scala:1342:87]
wire [3:0] resumeReqRegs_hi_3 = {resumeReqRegs_hi_hi_3, resumeReqRegs_hi_lo_3}; // @[Debug.scala:1342:87]
wire [7:0] _resumeReqRegs_T_10 = {resumeReqRegs_hi_3, resumeReqRegs_lo_3}; // @[Debug.scala:1342:87]
wire [7:0] _resumeReqRegs_T_11 = ~_resumeReqRegs_T_10; // @[Debug.scala:1342:{67,87}]
wire [7:0] _resumeReqRegs_T_12 = _resumeReqRegs_T_9 & _resumeReqRegs_T_11; // @[Debug.scala:1342:{43,65,67}]
wire [7:0] _resumeAcks_T = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24]
wire [3:0] resumeAcks_lo = {resumeAcks_lo_hi, resumeAcks_lo_lo}; // @[Debug.scala:1349:55]
wire [3:0] resumeAcks_hi = {resumeAcks_hi_hi, resumeAcks_hi_lo}; // @[Debug.scala:1349:55]
wire [7:0] _resumeAcks_T_1 = {resumeAcks_hi, resumeAcks_lo}; // @[Debug.scala:1349:55]
wire [7:0] _resumeAcks_T_2 = ~_resumeAcks_T_1; // @[Debug.scala:1349:{41,55}]
wire [7:0] _resumeAcks_T_3 = _resumeAcks_T & _resumeAcks_T_2; // @[Debug.scala:1349:{24,39,41}]
wire [7:0] _resumeAcks_T_4 = ~resumeReqRegs; // @[Debug.scala:863:31, :1349:24, :1351:23]
assign resumeAcks = resumereq ? _resumeAcks_T_3 : _resumeAcks_T_4; // @[Debug.scala:869:32, :983:39, :1347:24, :1349:{20,39}, :1351:{20,23}]
wire _anyAddressWrEn_T_2; // @[SBA.scala:134:54]
wire anyAddressWrEn; // @[SBA.scala:42:34]
wire _anyDataRdEn_T_2; // @[SBA.scala:176:51]
wire anyDataRdEn; // @[SBA.scala:43:34]
wire _anyDataWrEn_T_2; // @[SBA.scala:177:51]
wire anyDataWrEn; // @[SBA.scala:44:34]
reg SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28]
wire SBCSRdData_sbbusyerror = SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :60:38]
reg SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28]
reg SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28]
wire SBCSRdData_sbreadonaddr = SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :60:38]
reg [2:0] SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28]
wire [2:0] SBCSRdData_sbaccess = SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :60:38]
reg SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28]
wire SBCSRdData_sbautoincrement = SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :60:38]
reg SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28]
wire SBCSRdData_sbreadondata = SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :60:38]
wire _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:51:67]
wire SBCSFieldsRegReset_sbbusy; // @[SBA.scala:49:38]
assign _SBCSFieldsRegReset_sbbusy_T = |_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67]
assign SBCSFieldsRegReset_sbbusy = _SBCSFieldsRegReset_sbbusy_T; // @[SBA.scala:49:38, :51:67]
wire sbBusy; // @[SBA.scala:203:46]
wire SBCSRdData_sbbusy; // @[SBA.scala:60:38]
wire [2:0] SBCSRdData_sberror; // @[SBA.scala:60:38]
wire _out_T_591; // @[RegisterRouter.scala:87:24]
wire _out_T_571; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_560; // @[RegisterRouter.scala:87:24]
wire _out_T_549; // @[RegisterRouter.scala:87:24]
wire _out_T_538; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_527; // @[RegisterRouter.scala:87:24]
wire SBCSWrData_sbbusyerror; // @[SBA.scala:63:38]
wire SBCSWrData_sbreadonaddr; // @[SBA.scala:63:38]
wire [2:0] SBCSWrData_sbaccess; // @[SBA.scala:63:38]
wire SBCSWrData_sbautoincrement; // @[SBA.scala:63:38]
wire SBCSWrData_sbreadondata; // @[SBA.scala:63:38]
wire [2:0] SBCSWrData_sberror; // @[SBA.scala:63:38]
wire out_f_woready_43; // @[RegisterRouter.scala:87:24]
wire sberrorWrEn; // @[SBA.scala:65:38]
wire out_f_woready_44; // @[RegisterRouter.scala:87:24]
wire sbreadondataWrEn; // @[SBA.scala:66:38]
wire out_f_woready_45; // @[RegisterRouter.scala:87:24]
wire sbautoincrementWrEn; // @[SBA.scala:67:38]
wire out_f_woready_46; // @[RegisterRouter.scala:87:24]
wire sbaccessWrEn; // @[SBA.scala:68:38]
wire out_f_woready_47; // @[RegisterRouter.scala:87:24]
wire sbreadonaddrWrEn; // @[SBA.scala:69:38]
wire out_f_woready_49; // @[RegisterRouter.scala:87:24]
wire sbbusyerrorWrEn; // @[SBA.scala:70:38]
reg [31:0] SBADDRESSFieldsReg_0; // @[SBA.scala:104:33]
wire [31:0] _out_T_792 = SBADDRESSFieldsReg_0; // @[RegisterRouter.scala:87:24]
wire [31:0] SBADDRESSWrData_0; // @[SBA.scala:106:38]
wire out_f_roready_67; // @[RegisterRouter.scala:87:24]
wire SBADDRESSRdEn_0; // @[SBA.scala:107:38]
wire out_f_woready_67; // @[RegisterRouter.scala:87:24]
wire _anyAddressWrEn_T = SBADDRESSWrEn_0; // @[SBA.scala:108:38, :134:54]
wire [127:0] _autoIncrementedAddr_T_3; // @[SBA.scala:111:60]
wire [127:0] autoIncrementedAddr; // @[SBA.scala:110:39]
wire [63:0] _GEN_16 = {32'h0, SBADDRESSFieldsReg_0}; // @[SBA.scala:104:33, :111:31]
wire [63:0] autoIncrementedAddr_lo; // @[SBA.scala:111:31]
assign autoIncrementedAddr_lo = _GEN_16; // @[SBA.scala:111:31]
wire [63:0] sb2tlOpt_io_addrIn_lo; // @[SBA.scala:133:10]
assign sb2tlOpt_io_addrIn_lo = _GEN_16; // @[SBA.scala:111:31, :133:10]
wire [127:0] _autoIncrementedAddr_T = {64'h0, autoIncrementedAddr_lo}; // @[SBA.scala:111:31]
wire [7:0] _autoIncrementedAddr_T_1 = 8'h1 << SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :111:67]
wire [128:0] _autoIncrementedAddr_T_2 = {1'h0, _autoIncrementedAddr_T} + {121'h0, _autoIncrementedAddr_T_1}; // @[SBA.scala:111:{31,60,67}]
assign _autoIncrementedAddr_T_3 = _autoIncrementedAddr_T_2[127:0]; // @[SBA.scala:111:60]
assign autoIncrementedAddr = _autoIncrementedAddr_T_3; // @[SBA.scala:110:39, :111:60]
wire _GEN_17 = SBCSRdData_sberror == 3'h0; // @[SBA.scala:60:38, :119:40]
wire _SBADDRESSFieldsReg_0_T; // @[SBA.scala:119:40]
assign _SBADDRESSFieldsReg_0_T = _GEN_17; // @[SBA.scala:119:40]
wire _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_0_0_T_4 = _GEN_17; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_0_1_T_4 = _GEN_17; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_0_2_T_4 = _GEN_17; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_0_3_T_4 = _GEN_17; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_1_0_T_4 = _GEN_17; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_1_1_T_4 = _GEN_17; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_1_2_T_4 = _GEN_17; // @[SBA.scala:119:40, :160:97]
wire _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:97]
assign _SBDATAFieldsReg_1_3_T_4 = _GEN_17; // @[SBA.scala:119:40, :160:97]
wire _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:118]
assign _sb2tlOpt_io_wrEn_T_5 = _GEN_17; // @[SBA.scala:119:40, :199:118]
wire _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:118]
assign _sb2tlOpt_io_rdEn_T_5 = _GEN_17; // @[SBA.scala:119:40, :200:118]
wire _SBADDRESSFieldsReg_0_T_1 = SBADDRESSWrEn_0 & _SBADDRESSFieldsReg_0_T; // @[SBA.scala:108:38, :119:{37,40}]
wire _SBADDRESSFieldsReg_0_T_2 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63]
wire _SBADDRESSFieldsReg_0_T_3 = _SBADDRESSFieldsReg_0_T_1 & _SBADDRESSFieldsReg_0_T_2; // @[SBA.scala:119:{37,60,63}]
wire _SBADDRESSFieldsReg_0_T_4 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88]
wire _SBADDRESSFieldsReg_0_T_5 = _SBADDRESSFieldsReg_0_T_3 & _SBADDRESSFieldsReg_0_T_4; // @[SBA.scala:119:{60,85,88}]
wire _GEN_18 = _sb2tlOpt_io_rdDone | _sb2tlOpt_io_wrDone; // @[SBA.scala:120:44]
wire _SBADDRESSFieldsReg_0_T_6; // @[SBA.scala:120:44]
assign _SBADDRESSFieldsReg_0_T_6 = _GEN_18; // @[SBA.scala:120:44]
wire _sbErrorReg_0_T_12; // @[SBA.scala:229:54]
assign _sbErrorReg_0_T_12 = _GEN_18; // @[SBA.scala:120:44, :229:54]
wire _sbErrorReg_1_T_12; // @[SBA.scala:229:54]
assign _sbErrorReg_1_T_12 = _GEN_18; // @[SBA.scala:120:44, :229:54]
wire _sbErrorReg_2_T_12; // @[SBA.scala:229:54]
assign _sbErrorReg_2_T_12 = _GEN_18; // @[SBA.scala:120:44, :229:54]
wire _SBADDRESSFieldsReg_0_T_7 = _SBADDRESSFieldsReg_0_T_6 & SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :120:{44,71}]
wire [31:0] _SBADDRESSFieldsReg_0_T_8 = autoIncrementedAddr[31:0]; // @[SBA.scala:110:39, :120:124]
wire [31:0] _SBADDRESSFieldsReg_0_T_9 = _SBADDRESSFieldsReg_0_T_7 ? _SBADDRESSFieldsReg_0_T_8 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :120:{19,71,124}]
wire [31:0] _SBADDRESSFieldsReg_0_T_10 = _SBADDRESSFieldsReg_0_T_5 ? SBADDRESSWrData_0 : _SBADDRESSFieldsReg_0_T_9; // @[SBA.scala:106:38, :119:{19,85}, :120:19]
wire [127:0] _sb2tlOpt_io_addrIn_T_1 = {96'h0, SBADDRESSWrData_0}; // @[SBA.scala:106:38, :132:10]
wire [127:0] _sb2tlOpt_io_addrIn_T_2 = {64'h0, sb2tlOpt_io_addrIn_lo}; // @[SBA.scala:133:10]
wire [127:0] _sb2tlOpt_io_addrIn_T_3 = SBADDRESSWrEn_0 ? _sb2tlOpt_io_addrIn_T_1 : _sb2tlOpt_io_addrIn_T_2; // @[SBA.scala:108:38, :131:34, :132:10, :133:10]
wire _anyAddressWrEn_T_1 = _anyAddressWrEn_T; // @[SBA.scala:134:54]
assign _anyAddressWrEn_T_2 = _anyAddressWrEn_T_1; // @[SBA.scala:134:54]
assign anyAddressWrEn = _anyAddressWrEn_T_2; // @[SBA.scala:42:34, :134:54]
reg [7:0] SBDATAFieldsReg_0_0; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_0_1; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_0_2; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_0_3; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_1_0; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_1_1; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_1_2; // @[SBA.scala:143:30]
reg [7:0] SBDATAFieldsReg_1_3; // @[SBA.scala:143:30]
wire [31:0] _SBDATARdData_0_T; // @[SBA.scala:165:31]
wire [31:0] _SBDATARdData_1_T; // @[SBA.scala:165:31]
wire [31:0] _out_T_847 = SBDATARdData_0; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_123 = SBDATARdData_1; // @[RegisterRouter.scala:87:24]
wire [31:0] SBDATAWrData_0; // @[SBA.scala:147:35]
wire [31:0] SBDATAWrData_1; // @[SBA.scala:147:35]
wire out_f_roready_72; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire SBDATARdEn_0; // @[SBA.scala:149:35]
wire SBDATARdEn_1; // @[SBA.scala:149:35]
wire out_f_woready_72; // @[RegisterRouter.scala:87:24]
wire _sb2tlOpt_io_wrEn_T = SBDATAWrEn_0; // @[SBA.scala:150:35, :199:49]
wire out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire SBDATAWrEn_1; // @[SBA.scala:150:35]
wire _SBDATAFieldsReg_0_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_0_0_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_0_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_0_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_0_0_T_3 = _SBDATAFieldsReg_0_0_T_1 & _SBDATAFieldsReg_0_0_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_0_0_T_5 = _SBDATAFieldsReg_0_0_T_3 & _SBDATAFieldsReg_0_0_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_0_0_T_6 = SBDATAWrData_0[7:0]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_0_0_T_7 = _sb2tlOpt_io_rdLoad_0 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_0; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_0_0_T_8 = _SBDATAFieldsReg_0_0_T_5 ? _SBDATAFieldsReg_0_0_T_6 : _SBDATAFieldsReg_0_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_0_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_0_1_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_1_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_0_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_0_1_T_3 = _SBDATAFieldsReg_0_1_T_1 & _SBDATAFieldsReg_0_1_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_0_1_T_5 = _SBDATAFieldsReg_0_1_T_3 & _SBDATAFieldsReg_0_1_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_0_1_T_6 = SBDATAWrData_0[15:8]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_0_1_T_7 = _sb2tlOpt_io_rdLoad_1 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_1; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_0_1_T_8 = _SBDATAFieldsReg_0_1_T_5 ? _SBDATAFieldsReg_0_1_T_6 : _SBDATAFieldsReg_0_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_0_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_0_2_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_2_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_0_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_0_2_T_3 = _SBDATAFieldsReg_0_2_T_1 & _SBDATAFieldsReg_0_2_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_0_2_T_5 = _SBDATAFieldsReg_0_2_T_3 & _SBDATAFieldsReg_0_2_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_0_2_T_6 = SBDATAWrData_0[23:16]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_0_2_T_7 = _sb2tlOpt_io_rdLoad_2 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_2; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_0_2_T_8 = _SBDATAFieldsReg_0_2_T_5 ? _SBDATAFieldsReg_0_2_T_6 : _SBDATAFieldsReg_0_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_0_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_0_3_T_1 = SBDATAWrEn_0 & _SBDATAFieldsReg_0_3_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_0_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_0_3_T_3 = _SBDATAFieldsReg_0_3_T_1 & _SBDATAFieldsReg_0_3_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_0_3_T_5 = _SBDATAFieldsReg_0_3_T_3 & _SBDATAFieldsReg_0_3_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_0_3_T_6 = SBDATAWrData_0[31:24]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_0_3_T_7 = _sb2tlOpt_io_rdLoad_3 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_0_3; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_0_3_T_8 = _SBDATAFieldsReg_0_3_T_5 ? _SBDATAFieldsReg_0_3_T_6 : _SBDATAFieldsReg_0_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire [15:0] _GEN_19 = {SBDATAFieldsReg_0_1, SBDATAFieldsReg_0_0}; // @[SBA.scala:143:30, :165:31]
wire [15:0] SBDATARdData_0_lo; // @[SBA.scala:165:31]
assign SBDATARdData_0_lo = _GEN_19; // @[SBA.scala:165:31]
wire [15:0] sb2tlOpt_io_dataIn_lo_lo_lo; // @[SBA.scala:175:85]
assign sb2tlOpt_io_dataIn_lo_lo_lo = _GEN_19; // @[SBA.scala:165:31, :175:85]
wire [15:0] _GEN_20 = {SBDATAFieldsReg_0_3, SBDATAFieldsReg_0_2}; // @[SBA.scala:143:30, :165:31]
wire [15:0] SBDATARdData_0_hi; // @[SBA.scala:165:31]
assign SBDATARdData_0_hi = _GEN_20; // @[SBA.scala:165:31]
wire [15:0] sb2tlOpt_io_dataIn_lo_lo_hi; // @[SBA.scala:175:85]
assign sb2tlOpt_io_dataIn_lo_lo_hi = _GEN_20; // @[SBA.scala:165:31, :175:85]
assign _SBDATARdData_0_T = {SBDATARdData_0_hi, SBDATARdData_0_lo}; // @[SBA.scala:165:31]
assign SBDATARdData_0 = _SBDATARdData_0_T; // @[SBA.scala:145:35, :165:31]
wire _SBDATAFieldsReg_1_0_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_1_0_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_0_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_1_0_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_1_0_T_3 = _SBDATAFieldsReg_1_0_T_1 & _SBDATAFieldsReg_1_0_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_1_0_T_5 = _SBDATAFieldsReg_1_0_T_3 & _SBDATAFieldsReg_1_0_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_1_0_T_6 = SBDATAWrData_1[7:0]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_1_0_T_7 = _sb2tlOpt_io_rdLoad_4 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_0; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_1_0_T_8 = _SBDATAFieldsReg_1_0_T_5 ? _SBDATAFieldsReg_1_0_T_6 : _SBDATAFieldsReg_1_0_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_1_1_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_1_1_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_1_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_1_1_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_1_1_T_3 = _SBDATAFieldsReg_1_1_T_1 & _SBDATAFieldsReg_1_1_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_1_1_T_5 = _SBDATAFieldsReg_1_1_T_3 & _SBDATAFieldsReg_1_1_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_1_1_T_6 = SBDATAWrData_1[15:8]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_1_1_T_7 = _sb2tlOpt_io_rdLoad_5 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_1; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_1_1_T_8 = _SBDATAFieldsReg_1_1_T_5 ? _SBDATAFieldsReg_1_1_T_6 : _SBDATAFieldsReg_1_1_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_1_2_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_1_2_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_2_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_1_2_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_1_2_T_3 = _SBDATAFieldsReg_1_2_T_1 & _SBDATAFieldsReg_1_2_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_1_2_T_5 = _SBDATAFieldsReg_1_2_T_3 & _SBDATAFieldsReg_1_2_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_1_2_T_6 = SBDATAWrData_1[23:16]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_1_2_T_7 = _sb2tlOpt_io_rdLoad_6 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_2; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_1_2_T_8 = _SBDATAFieldsReg_1_2_T_5 ? _SBDATAFieldsReg_1_2_T_6 : _SBDATAFieldsReg_1_2_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire _SBDATAFieldsReg_1_3_T = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :160:42]
wire _SBDATAFieldsReg_1_3_T_1 = SBDATAWrEn_1 & _SBDATAFieldsReg_1_3_T; // @[SBA.scala:150:35, :160:{39,42}]
wire _SBDATAFieldsReg_1_3_T_2 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :160:67]
wire _SBDATAFieldsReg_1_3_T_3 = _SBDATAFieldsReg_1_3_T_1 & _SBDATAFieldsReg_1_3_T_2; // @[SBA.scala:160:{39,64,67}]
wire _SBDATAFieldsReg_1_3_T_5 = _SBDATAFieldsReg_1_3_T_3 & _SBDATAFieldsReg_1_3_T_4; // @[SBA.scala:160:{64,94,97}]
wire [7:0] _SBDATAFieldsReg_1_3_T_6 = SBDATAWrData_1[31:24]; // @[SBA.scala:147:35, :160:133]
wire [7:0] _SBDATAFieldsReg_1_3_T_7 = _sb2tlOpt_io_rdLoad_7 ? _sb2tlOpt_io_dataOut : SBDATAFieldsReg_1_3; // @[SBA.scala:143:30, :161:24]
wire [7:0] _SBDATAFieldsReg_1_3_T_8 = _SBDATAFieldsReg_1_3_T_5 ? _SBDATAFieldsReg_1_3_T_6 : _SBDATAFieldsReg_1_3_T_7; // @[SBA.scala:160:{24,94,133}, :161:24]
wire [15:0] _GEN_21 = {SBDATAFieldsReg_1_1, SBDATAFieldsReg_1_0}; // @[SBA.scala:143:30, :165:31]
wire [15:0] SBDATARdData_1_lo; // @[SBA.scala:165:31]
assign SBDATARdData_1_lo = _GEN_21; // @[SBA.scala:165:31]
wire [15:0] sb2tlOpt_io_dataIn_lo_hi_lo; // @[SBA.scala:175:85]
assign sb2tlOpt_io_dataIn_lo_hi_lo = _GEN_21; // @[SBA.scala:165:31, :175:85]
wire [15:0] _GEN_22 = {SBDATAFieldsReg_1_3, SBDATAFieldsReg_1_2}; // @[SBA.scala:143:30, :165:31]
wire [15:0] SBDATARdData_1_hi; // @[SBA.scala:165:31]
assign SBDATARdData_1_hi = _GEN_22; // @[SBA.scala:165:31]
wire [15:0] sb2tlOpt_io_dataIn_lo_hi_hi; // @[SBA.scala:175:85]
assign sb2tlOpt_io_dataIn_lo_hi_hi = _GEN_22; // @[SBA.scala:165:31, :175:85]
assign _SBDATARdData_1_T = {SBDATARdData_1_hi, SBDATARdData_1_lo}; // @[SBA.scala:165:31]
assign SBDATARdData_1 = _SBDATARdData_1_T; // @[SBA.scala:145:35, :165:31]
wire [63:0] sb2tlOpt_io_dataIn_lo = {SBDATAWrData_1, SBDATAWrData_0}; // @[SBA.scala:147:35, :175:59]
wire [127:0] _sb2tlOpt_io_dataIn_T = {64'h0, sb2tlOpt_io_dataIn_lo}; // @[SBA.scala:175:59]
wire [31:0] sb2tlOpt_io_dataIn_lo_lo = {sb2tlOpt_io_dataIn_lo_lo_hi, sb2tlOpt_io_dataIn_lo_lo_lo}; // @[SBA.scala:175:85]
wire [31:0] sb2tlOpt_io_dataIn_lo_hi = {sb2tlOpt_io_dataIn_lo_hi_hi, sb2tlOpt_io_dataIn_lo_hi_lo}; // @[SBA.scala:175:85]
wire [63:0] sb2tlOpt_io_dataIn_lo_1 = {sb2tlOpt_io_dataIn_lo_hi, sb2tlOpt_io_dataIn_lo_lo}; // @[SBA.scala:175:85]
wire [127:0] _sb2tlOpt_io_dataIn_T_1 = {64'h0, sb2tlOpt_io_dataIn_lo_1}; // @[SBA.scala:175:85]
wire _sb2tlOpt_io_wrEn_T_10; // @[SBA.scala:199:156]
wire [127:0] _sb2tlOpt_io_dataIn_T_2 = _sb2tlOpt_io_wrEn_T_10 ? _sb2tlOpt_io_dataIn_T : _sb2tlOpt_io_dataIn_T_1; // @[SBA.scala:175:{34,59,85}, :199:156]
wire _anyDataRdEn_T = SBDATARdEn_0 | SBDATARdEn_1; // @[SBA.scala:149:35, :176:51]
wire _anyDataRdEn_T_1 = _anyDataRdEn_T; // @[SBA.scala:176:51]
assign _anyDataRdEn_T_2 = _anyDataRdEn_T_1; // @[SBA.scala:176:51]
assign anyDataRdEn = _anyDataRdEn_T_2; // @[SBA.scala:43:34, :176:51]
wire _anyDataWrEn_T = SBDATAWrEn_0 | SBDATAWrEn_1; // @[SBA.scala:150:35, :177:51]
wire _anyDataWrEn_T_1 = _anyDataWrEn_T; // @[SBA.scala:177:51]
assign _anyDataWrEn_T_2 = _anyDataWrEn_T_1; // @[SBA.scala:177:51]
assign anyDataWrEn = _anyDataWrEn_T_2; // @[SBA.scala:44:34, :177:51]
wire _tryRdEn_T = SBADDRESSWrEn_0 & SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :108:38, :180:37]
wire _tryRdEn_T_1 = SBDATARdEn_0 & SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :149:35, :180:86]
wire tryRdEn = _tryRdEn_T | _tryRdEn_T_1; // @[SBA.scala:180:{37,68,86}]
wire _sb2tlOpt_io_rdEn_T = tryRdEn; // @[SBA.scala:180:68, :200:49]
wire _sbAccessError_T = SBCSFieldsReg_sbaccess == 3'h0; // @[SBA.scala:47:28, :182:49]
wire _T_334 = SBCSFieldsReg_sbaccess == 3'h1; // @[SBA.scala:47:28, :183:49]
wire _sbAccessError_T_3; // @[SBA.scala:183:49]
assign _sbAccessError_T_3 = _T_334; // @[SBA.scala:183:49]
wire _sbAlignmentError_T; // @[SBA.scala:191:52]
assign _sbAlignmentError_T = _T_334; // @[SBA.scala:183:49, :191:52]
wire _T_341 = SBCSFieldsReg_sbaccess == 3'h2; // @[SBA.scala:47:28, :184:49]
wire _sbAccessError_T_7; // @[SBA.scala:184:49]
assign _sbAccessError_T_7 = _T_341; // @[SBA.scala:184:49]
wire _sbAlignmentError_T_4; // @[SBA.scala:192:52]
assign _sbAlignmentError_T_4 = _T_341; // @[SBA.scala:184:49, :192:52]
wire _T_348 = SBCSFieldsReg_sbaccess == 3'h3; // @[SBA.scala:47:28, :185:49]
wire _sbAccessError_T_11; // @[SBA.scala:185:49]
assign _sbAccessError_T_11 = _T_348; // @[SBA.scala:185:49]
wire _sbAlignmentError_T_9; // @[SBA.scala:193:52]
assign _sbAlignmentError_T_9 = _T_348; // @[SBA.scala:185:49, :193:52]
wire _T_355 = SBCSFieldsReg_sbaccess == 3'h4; // @[SBA.scala:47:28, :186:49]
wire _sbAccessError_T_15; // @[SBA.scala:186:49]
assign _sbAccessError_T_15 = _T_355; // @[SBA.scala:186:49]
wire _sbAlignmentError_T_14; // @[SBA.scala:194:52]
assign _sbAlignmentError_T_14 = _T_355; // @[SBA.scala:186:49, :194:52]
wire _sbAccessError_T_17 = _sbAccessError_T_15; // @[SBA.scala:186:{49,58}]
wire _sbAccessError_T_18 = _sbAccessError_T_17; // @[SBA.scala:185:97, :186:58]
wire _sbAccessError_T_19 = SBCSFieldsReg_sbaccess > 3'h4; // @[SBA.scala:47:28, :186:124]
wire sbAccessError = _sbAccessError_T_18 | _sbAccessError_T_19; // @[SBA.scala:185:97, :186:{97,124}]
wire [31:0] _compareAddr_T; // @[SBA.scala:189:23]
wire [31:0] compareAddr; // @[SBA.scala:188:27]
assign _compareAddr_T = SBADDRESSWrEn_0 ? SBADDRESSWrData_0 : SBADDRESSFieldsReg_0; // @[SBA.scala:104:33, :106:38, :108:38, :189:23]
assign compareAddr = _compareAddr_T; // @[SBA.scala:188:27, :189:23]
wire _sbAlignmentError_T_1 = compareAddr[0]; // @[SBA.scala:188:27, :191:76]
wire _sbAlignmentError_T_2 = _sbAlignmentError_T_1; // @[SBA.scala:191:{76,82}]
wire _sbAlignmentError_T_3 = _sbAlignmentError_T & _sbAlignmentError_T_2; // @[SBA.scala:191:{52,61,82}]
wire [1:0] _sbAlignmentError_T_5 = compareAddr[1:0]; // @[SBA.scala:188:27, :192:76]
wire _sbAlignmentError_T_6 = |_sbAlignmentError_T_5; // @[SBA.scala:192:{76,82}]
wire _sbAlignmentError_T_7 = _sbAlignmentError_T_4 & _sbAlignmentError_T_6; // @[SBA.scala:192:{52,61,82}]
wire _sbAlignmentError_T_8 = _sbAlignmentError_T_3 | _sbAlignmentError_T_7; // @[SBA.scala:191:{61,91}, :192:61]
wire [2:0] _sbAlignmentError_T_10 = compareAddr[2:0]; // @[SBA.scala:188:27, :193:76]
wire _sbAlignmentError_T_11 = |_sbAlignmentError_T_10; // @[SBA.scala:193:{76,82}]
wire _sbAlignmentError_T_12 = _sbAlignmentError_T_9 & _sbAlignmentError_T_11; // @[SBA.scala:193:{52,61,82}]
wire _sbAlignmentError_T_13 = _sbAlignmentError_T_8 | _sbAlignmentError_T_12; // @[SBA.scala:191:91, :192:91, :193:61]
wire [3:0] _sbAlignmentError_T_15 = compareAddr[3:0]; // @[SBA.scala:188:27, :194:76]
wire _sbAlignmentError_T_16 = |_sbAlignmentError_T_15; // @[SBA.scala:194:{76,82}]
wire _sbAlignmentError_T_17 = _sbAlignmentError_T_14 & _sbAlignmentError_T_16; // @[SBA.scala:194:{52,61,82}]
wire sbAlignmentError = _sbAlignmentError_T_13 | _sbAlignmentError_T_17; // @[SBA.scala:192:91, :193:91, :194:61]
wire _sb2tlOpt_io_wrEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :199:63]
wire _sb2tlOpt_io_wrEn_T_2 = _sb2tlOpt_io_wrEn_T & _sb2tlOpt_io_wrEn_T_1; // @[SBA.scala:199:{49,60,63}]
wire _sb2tlOpt_io_wrEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :199:88]
wire _sb2tlOpt_io_wrEn_T_4 = _sb2tlOpt_io_wrEn_T_2 & _sb2tlOpt_io_wrEn_T_3; // @[SBA.scala:199:{60,85,88}]
wire _sb2tlOpt_io_wrEn_T_6 = _sb2tlOpt_io_wrEn_T_4 & _sb2tlOpt_io_wrEn_T_5; // @[SBA.scala:199:{85,115,118}]
wire _sb2tlOpt_io_wrEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141]
wire _sb2tlOpt_io_wrEn_T_8 = _sb2tlOpt_io_wrEn_T_6 & _sb2tlOpt_io_wrEn_T_7; // @[SBA.scala:199:{115,138,141}]
wire _sb2tlOpt_io_wrEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159]
assign _sb2tlOpt_io_wrEn_T_10 = _sb2tlOpt_io_wrEn_T_8 & _sb2tlOpt_io_wrEn_T_9; // @[SBA.scala:199:{138,156,159}]
wire _sb2tlOpt_io_rdEn_T_1 = ~SBCSFieldsReg_sbbusy; // @[SBA.scala:47:28, :119:63, :200:63]
wire _sb2tlOpt_io_rdEn_T_2 = _sb2tlOpt_io_rdEn_T & _sb2tlOpt_io_rdEn_T_1; // @[SBA.scala:200:{49,60,63}]
wire _sb2tlOpt_io_rdEn_T_3 = ~SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :119:88, :200:88]
wire _sb2tlOpt_io_rdEn_T_4 = _sb2tlOpt_io_rdEn_T_2 & _sb2tlOpt_io_rdEn_T_3; // @[SBA.scala:200:{60,85,88}]
wire _sb2tlOpt_io_rdEn_T_6 = _sb2tlOpt_io_rdEn_T_4 & _sb2tlOpt_io_rdEn_T_5; // @[SBA.scala:200:{85,115,118}]
wire _sb2tlOpt_io_rdEn_T_7 = ~sbAccessError; // @[SBA.scala:186:97, :199:141, :200:141]
wire _sb2tlOpt_io_rdEn_T_8 = _sb2tlOpt_io_rdEn_T_6 & _sb2tlOpt_io_rdEn_T_7; // @[SBA.scala:200:{115,138,141}]
wire _sb2tlOpt_io_rdEn_T_9 = ~sbAlignmentError; // @[SBA.scala:193:91, :199:159, :200:159]
wire _sb2tlOpt_io_rdEn_T_10 = _sb2tlOpt_io_rdEn_T_8 & _sb2tlOpt_io_rdEn_T_9; // @[SBA.scala:200:{138,156,159}]
assign sbBusy = |_sb2tlOpt_io_sbStateOut; // @[SBA.scala:51:67, :203:46]
assign SBCSRdData_sbbusy = sbBusy; // @[SBA.scala:60:38, :203:46]
wire _SBCSFieldsReg_sbbusyerror_T = sbbusyerrorWrEn & SBCSWrData_sbbusyerror; // @[SBA.scala:63:38, :70:38, :208:60]
wire _SBCSFieldsReg_sbbusyerror_T_1 = anyAddressWrEn & sbBusy; // @[SBA.scala:42:34, :203:46, :209:59]
wire _SBCSFieldsReg_sbbusyerror_T_2 = anyDataRdEn | anyDataWrEn; // @[SBA.scala:43:34, :44:34, :210:57]
wire _SBCSFieldsReg_sbbusyerror_T_3 = _SBCSFieldsReg_sbbusyerror_T_2 & sbBusy; // @[SBA.scala:203:46, :210:{57,73}]
wire _SBCSFieldsReg_sbbusyerror_T_4 = _SBCSFieldsReg_sbbusyerror_T_3 | SBCSFieldsReg_sbbusyerror; // @[SBA.scala:47:28, :210:{43,73}]
wire _SBCSFieldsReg_sbbusyerror_T_5 = _SBCSFieldsReg_sbbusyerror_T_1 | _SBCSFieldsReg_sbbusyerror_T_4; // @[SBA.scala:209:{43,59}, :210:43]
wire _SBCSFieldsReg_sbbusyerror_T_6 = ~_SBCSFieldsReg_sbbusyerror_T & _SBCSFieldsReg_sbbusyerror_T_5; // @[SBA.scala:208:{43,60}, :209:43]
wire _SBCSFieldsReg_sbreadonaddr_T = sbreadonaddrWrEn ? SBCSWrData_sbreadonaddr : SBCSFieldsReg_sbreadonaddr; // @[SBA.scala:47:28, :63:38, :69:38, :211:43]
wire _SBCSFieldsReg_sbautoincrement_T = sbautoincrementWrEn ? SBCSWrData_sbautoincrement : SBCSFieldsReg_sbautoincrement; // @[SBA.scala:47:28, :63:38, :67:38, :212:43]
wire _SBCSFieldsReg_sbreadondata_T = sbreadondataWrEn ? SBCSWrData_sbreadondata : SBCSFieldsReg_sbreadondata; // @[SBA.scala:47:28, :63:38, :66:38, :213:43]
wire [2:0] _SBCSFieldsReg_sbaccess_T = sbaccessWrEn ? SBCSWrData_sbaccess : SBCSFieldsReg_sbaccess; // @[SBA.scala:47:28, :63:38, :68:38, :214:43]
reg sbErrorReg_0; // @[SBA.scala:219:25]
reg sbErrorReg_1; // @[SBA.scala:219:25]
reg sbErrorReg_2; // @[SBA.scala:219:25]
wire _sbErrorReg_0_T = SBCSWrData_sberror[0]; // @[SBA.scala:63:38, :225:63]
wire _sbErrorReg_0_T_1 = _sbErrorReg_0_T; // @[SBA.scala:225:{63,67}]
wire _sbErrorReg_0_T_2 = sberrorWrEn & _sbErrorReg_0_T_1; // @[SBA.scala:65:38, :225:{42,67}]
wire _sbErrorReg_0_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55]
wire _sbErrorReg_0_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_0_T_3; // @[SBA.scala:199:156, :226:{52,55}]
wire _sbErrorReg_0_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109]
wire _sbErrorReg_0_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_0_T_5; // @[SBA.scala:200:156, :226:{106,109}]
wire _sbErrorReg_0_T_7 = _sbErrorReg_0_T_4 | _sbErrorReg_0_T_6; // @[SBA.scala:226:{52,81,106}]
wire _GEN_23 = SBDATAWrEn_0 | tryRdEn; // @[SBA.scala:150:35, :180:68, :227:39]
wire _sbErrorReg_0_T_8; // @[SBA.scala:227:39]
assign _sbErrorReg_0_T_8 = _GEN_23; // @[SBA.scala:227:39]
wire _sbErrorReg_0_T_10; // @[SBA.scala:228:39]
assign _sbErrorReg_0_T_10 = _GEN_23; // @[SBA.scala:227:39, :228:39]
wire _sbErrorReg_1_T_8; // @[SBA.scala:227:39]
assign _sbErrorReg_1_T_8 = _GEN_23; // @[SBA.scala:227:39]
wire _sbErrorReg_1_T_10; // @[SBA.scala:228:39]
assign _sbErrorReg_1_T_10 = _GEN_23; // @[SBA.scala:227:39, :228:39]
wire _sbErrorReg_2_T_8; // @[SBA.scala:227:39]
assign _sbErrorReg_2_T_8 = _GEN_23; // @[SBA.scala:227:39]
wire _sbErrorReg_2_T_10; // @[SBA.scala:228:39]
assign _sbErrorReg_2_T_10 = _GEN_23; // @[SBA.scala:227:39, :228:39]
wire _sbErrorReg_0_T_9 = _sbErrorReg_0_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}]
wire _sbErrorReg_0_T_11 = _sbErrorReg_0_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}]
wire _sbErrorReg_0_T_13 = _sbErrorReg_0_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}]
wire _sbErrorReg_0_T_14 = _sbErrorReg_0_T_13 | sbErrorReg_0; // @[SBA.scala:219:25, :229:{29,81}]
wire _sbErrorReg_0_T_15 = ~_sbErrorReg_0_T_11 & _sbErrorReg_0_T_14; // @[SBA.scala:228:{29,51}, :229:29]
wire _sbErrorReg_0_T_16 = _sbErrorReg_0_T_9 | _sbErrorReg_0_T_15; // @[SBA.scala:227:{29,51}, :228:29]
wire _sbErrorReg_0_T_17 = ~_sbErrorReg_0_T_7 & _sbErrorReg_0_T_16; // @[SBA.scala:226:{29,81}, :227:29]
wire _sbErrorReg_0_T_18 = ~_sbErrorReg_0_T_2 & _sbErrorReg_0_T_17; // @[SBA.scala:225:{29,42}, :226:29]
wire _sbErrorReg_1_T = SBCSWrData_sberror[1]; // @[SBA.scala:63:38, :225:63]
wire _sbErrorReg_1_T_1 = _sbErrorReg_1_T; // @[SBA.scala:225:{63,67}]
wire _sbErrorReg_1_T_2 = sberrorWrEn & _sbErrorReg_1_T_1; // @[SBA.scala:65:38, :225:{42,67}]
wire _sbErrorReg_1_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55]
wire _sbErrorReg_1_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_1_T_3; // @[SBA.scala:199:156, :226:{52,55}]
wire _sbErrorReg_1_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109]
wire _sbErrorReg_1_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_1_T_5; // @[SBA.scala:200:156, :226:{106,109}]
wire _sbErrorReg_1_T_7 = _sbErrorReg_1_T_4 | _sbErrorReg_1_T_6; // @[SBA.scala:226:{52,81,106}]
wire _sbErrorReg_1_T_9 = _sbErrorReg_1_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}]
wire _sbErrorReg_1_T_11 = _sbErrorReg_1_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}]
wire _sbErrorReg_1_T_13 = _sbErrorReg_1_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}]
wire _sbErrorReg_1_T_14 = _sbErrorReg_1_T_13 | sbErrorReg_1; // @[SBA.scala:219:25, :229:{29,81}]
wire _sbErrorReg_1_T_15 = ~_sbErrorReg_1_T_11 & _sbErrorReg_1_T_14; // @[SBA.scala:228:{29,51}, :229:29]
wire _sbErrorReg_1_T_16 = _sbErrorReg_1_T_9 | _sbErrorReg_1_T_15; // @[SBA.scala:227:{29,51}, :228:29]
wire _sbErrorReg_1_T_17 = _sbErrorReg_1_T_7 | _sbErrorReg_1_T_16; // @[SBA.scala:226:{29,81}, :227:29]
wire _sbErrorReg_1_T_18 = ~_sbErrorReg_1_T_2 & _sbErrorReg_1_T_17; // @[SBA.scala:225:{29,42}, :226:29]
wire _sbErrorReg_2_T = SBCSWrData_sberror[2]; // @[SBA.scala:63:38, :225:63]
wire _sbErrorReg_2_T_1 = _sbErrorReg_2_T; // @[SBA.scala:225:{63,67}]
wire _sbErrorReg_2_T_2 = sberrorWrEn & _sbErrorReg_2_T_1; // @[SBA.scala:65:38, :225:{42,67}]
wire _sbErrorReg_2_T_3 = ~_sb2tlOpt_io_wrLegal; // @[SBA.scala:226:55]
wire _sbErrorReg_2_T_4 = _sb2tlOpt_io_wrEn_T_10 & _sbErrorReg_2_T_3; // @[SBA.scala:199:156, :226:{52,55}]
wire _sbErrorReg_2_T_5 = ~_sb2tlOpt_io_rdLegal; // @[SBA.scala:226:109]
wire _sbErrorReg_2_T_6 = _sb2tlOpt_io_rdEn_T_10 & _sbErrorReg_2_T_5; // @[SBA.scala:200:156, :226:{106,109}]
wire _sbErrorReg_2_T_7 = _sbErrorReg_2_T_4 | _sbErrorReg_2_T_6; // @[SBA.scala:226:{52,81,106}]
wire _sbErrorReg_2_T_9 = _sbErrorReg_2_T_8 & sbAlignmentError; // @[SBA.scala:193:91, :227:{39,51}]
wire _sbErrorReg_2_T_11 = _sbErrorReg_2_T_10 & sbAccessError; // @[SBA.scala:186:97, :228:{39,51}]
wire _sbErrorReg_2_T_13 = _sbErrorReg_2_T_12 & _sb2tlOpt_io_respError; // @[SBA.scala:229:{54,81}]
wire _sbErrorReg_2_T_14 = _sbErrorReg_2_T_13 | sbErrorReg_2; // @[SBA.scala:219:25, :229:{29,81}]
wire _sbErrorReg_2_T_15 = _sbErrorReg_2_T_11 | _sbErrorReg_2_T_14; // @[SBA.scala:228:{29,51}, :229:29]
wire _sbErrorReg_2_T_16 = ~_sbErrorReg_2_T_9 & _sbErrorReg_2_T_15; // @[SBA.scala:227:{29,51}, :228:29]
wire _sbErrorReg_2_T_17 = ~_sbErrorReg_2_T_7 & _sbErrorReg_2_T_16; // @[SBA.scala:226:{29,81}, :227:29]
wire _sbErrorReg_2_T_18 = ~_sbErrorReg_2_T_2 & _sbErrorReg_2_T_17; // @[SBA.scala:225:{29,42}, :226:29]
wire [1:0] SBCSRdData_sberror_lo = {sbErrorReg_1, sbErrorReg_0}; // @[SBA.scala:219:25, :240:42]
wire [1:0] SBCSRdData_sberror_hi = {1'h0, sbErrorReg_2}; // @[SBA.scala:219:25, :240:42]
wire [3:0] _SBCSRdData_sberror_T = {SBCSRdData_sberror_hi, SBCSRdData_sberror_lo}; // @[SBA.scala:240:42]
assign SBCSRdData_sberror = _SBCSRdData_sberror_T[2:0]; // @[SBA.scala:60:38, :240:{28,42}]
wire [31:0] _T_367 = {COMMANDReg_cmdtype, COMMANDReg_control}; // @[Debug.scala:1277:25, :1435:40]
wire [31:0] _out_T_1587; // @[RegisterRouter.scala:87:24]
assign _out_T_1587 = _T_367; // @[RegisterRouter.scala:87:24]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
wire [31:0] _accessRegisterCommandReg_T; // @[Debug.scala:1533:56]
assign _accessRegisterCommandReg_T = _T_367; // @[Debug.scala:1435:40, :1533:56]
assign dmiNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire [6:0] _in_bits_index_T; // @[Edges.scala:192:34]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [6:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [31:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = dmiNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
assign _in_bits_index_T = dmiNodeIn_a_bits_address[8:2]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T; // @[RegisterRouter.scala:73:18]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _dmiNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign dmiNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_114 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_783 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_838 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_981 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1578 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1633 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [6:0] _GEN_24 = out_front_bits_index & 7'h40; // @[RegisterRouter.scala:87:24]
wire [6:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN_24; // @[RegisterRouter.scala:87:24]
wire [6:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN_24; // @[RegisterRouter.scala:87:24]
wire _GEN_25 = out_findex == 7'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_8; // @[RegisterRouter.scala:87:24]
assign _out_T_8 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_10; // @[RegisterRouter.scala:87:24]
assign _out_T_10 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_12; // @[RegisterRouter.scala:87:24]
assign _out_T_12 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_14; // @[RegisterRouter.scala:87:24]
assign _out_T_14 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_16; // @[RegisterRouter.scala:87:24]
assign _out_T_16 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_18; // @[RegisterRouter.scala:87:24]
assign _out_T_18 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_20; // @[RegisterRouter.scala:87:24]
assign _out_T_20 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_22; // @[RegisterRouter.scala:87:24]
assign _out_T_22 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_24; // @[RegisterRouter.scala:87:24]
assign _out_T_24 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_26; // @[RegisterRouter.scala:87:24]
assign _out_T_26 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_28; // @[RegisterRouter.scala:87:24]
assign _out_T_28 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_30; // @[RegisterRouter.scala:87:24]
assign _out_T_30 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_32; // @[RegisterRouter.scala:87:24]
assign _out_T_32 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_34; // @[RegisterRouter.scala:87:24]
assign _out_T_34 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_36; // @[RegisterRouter.scala:87:24]
assign _out_T_36 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_38; // @[RegisterRouter.scala:87:24]
assign _out_T_38 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_40; // @[RegisterRouter.scala:87:24]
assign _out_T_40 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_44; // @[RegisterRouter.scala:87:24]
assign _out_T_44 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_46; // @[RegisterRouter.scala:87:24]
assign _out_T_46 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_48; // @[RegisterRouter.scala:87:24]
assign _out_T_48 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_50; // @[RegisterRouter.scala:87:24]
assign _out_T_50 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_52; // @[RegisterRouter.scala:87:24]
assign _out_T_52 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_54; // @[RegisterRouter.scala:87:24]
assign _out_T_54 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_56; // @[RegisterRouter.scala:87:24]
assign _out_T_56 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_58; // @[RegisterRouter.scala:87:24]
assign _out_T_58 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_60; // @[RegisterRouter.scala:87:24]
assign _out_T_60 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_62; // @[RegisterRouter.scala:87:24]
assign _out_T_62 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_64; // @[RegisterRouter.scala:87:24]
assign _out_T_64 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_66; // @[RegisterRouter.scala:87:24]
assign _out_T_66 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _out_T_68; // @[RegisterRouter.scala:87:24]
assign _out_T_68 = _GEN_25; // @[RegisterRouter.scala:87:24]
wire _GEN_26 = out_bindex == 7'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_9; // @[RegisterRouter.scala:87:24]
assign _out_T_9 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_11; // @[RegisterRouter.scala:87:24]
assign _out_T_11 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_13; // @[RegisterRouter.scala:87:24]
assign _out_T_13 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_15; // @[RegisterRouter.scala:87:24]
assign _out_T_15 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_17; // @[RegisterRouter.scala:87:24]
assign _out_T_17 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_19; // @[RegisterRouter.scala:87:24]
assign _out_T_19 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_21; // @[RegisterRouter.scala:87:24]
assign _out_T_21 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_23; // @[RegisterRouter.scala:87:24]
assign _out_T_23 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_25; // @[RegisterRouter.scala:87:24]
assign _out_T_25 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_27; // @[RegisterRouter.scala:87:24]
assign _out_T_27 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_29; // @[RegisterRouter.scala:87:24]
assign _out_T_29 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_31; // @[RegisterRouter.scala:87:24]
assign _out_T_31 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_33; // @[RegisterRouter.scala:87:24]
assign _out_T_33 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_35; // @[RegisterRouter.scala:87:24]
assign _out_T_35 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_37; // @[RegisterRouter.scala:87:24]
assign _out_T_37 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_39; // @[RegisterRouter.scala:87:24]
assign _out_T_39 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_41; // @[RegisterRouter.scala:87:24]
assign _out_T_41 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_45; // @[RegisterRouter.scala:87:24]
assign _out_T_45 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_47; // @[RegisterRouter.scala:87:24]
assign _out_T_47 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_49; // @[RegisterRouter.scala:87:24]
assign _out_T_49 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_51; // @[RegisterRouter.scala:87:24]
assign _out_T_51 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_53; // @[RegisterRouter.scala:87:24]
assign _out_T_53 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_55; // @[RegisterRouter.scala:87:24]
assign _out_T_55 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_57; // @[RegisterRouter.scala:87:24]
assign _out_T_57 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_59; // @[RegisterRouter.scala:87:24]
assign _out_T_59 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_61; // @[RegisterRouter.scala:87:24]
assign _out_T_61 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_63; // @[RegisterRouter.scala:87:24]
assign _out_T_63 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_65; // @[RegisterRouter.scala:87:24]
assign _out_T_65 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_67; // @[RegisterRouter.scala:87:24]
assign _out_T_67 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_T_69; // @[RegisterRouter.scala:87:24]
assign _out_T_69 = _GEN_26; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_5 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_61 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_9 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_41 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_35 = _out_T_9; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_50 = _out_T_11; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_8 = _out_T_13; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_4 = _out_T_15; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_47 = _out_T_17; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_10 = _out_T_19; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_56 = _out_T_21; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_42 = _out_T_23; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_24 = _out_T_25; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_37 = _out_T_27; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_46 = _out_T_29; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_57 = _out_T_31; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_6 = _out_T_33; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_60 = _out_T_35; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_38 = _out_T_37; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_33 = _out_T_39; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_45 = _out_T_41; // @[MuxLiteral.scala:49:48]
wire _out_T_42 = out_findex == 7'h40; // @[RegisterRouter.scala:87:24]
wire _out_T_43 = out_bindex == 7'h40; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_43; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_17 = _out_T_45; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_32 = _out_T_47; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_34 = _out_T_49; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_22 = _out_T_51; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_44 = _out_T_53; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_7 = _out_T_55; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_39 = _out_T_57; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_11 = _out_T_59; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_43 = _out_T_61; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_40 = _out_T_63; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_23 = _out_T_65; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_36 = _out_T_67; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_19 = _out_T_69; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_203; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_16; // @[RegisterRouter.scala:87:24]
wire out_rivalid_17; // @[RegisterRouter.scala:87:24]
wire out_rivalid_18; // @[RegisterRouter.scala:87:24]
wire out_rivalid_19; // @[RegisterRouter.scala:87:24]
wire out_rivalid_20; // @[RegisterRouter.scala:87:24]
wire out_rivalid_21; // @[RegisterRouter.scala:87:24]
wire out_rivalid_22; // @[RegisterRouter.scala:87:24]
wire out_rivalid_23; // @[RegisterRouter.scala:87:24]
wire out_rivalid_24; // @[RegisterRouter.scala:87:24]
wire out_rivalid_25; // @[RegisterRouter.scala:87:24]
wire out_rivalid_26; // @[RegisterRouter.scala:87:24]
wire out_rivalid_27; // @[RegisterRouter.scala:87:24]
wire out_rivalid_28; // @[RegisterRouter.scala:87:24]
wire out_rivalid_29; // @[RegisterRouter.scala:87:24]
wire out_rivalid_30; // @[RegisterRouter.scala:87:24]
wire out_rivalid_31; // @[RegisterRouter.scala:87:24]
wire out_rivalid_32; // @[RegisterRouter.scala:87:24]
wire out_rivalid_33; // @[RegisterRouter.scala:87:24]
wire out_rivalid_34; // @[RegisterRouter.scala:87:24]
wire out_rivalid_35; // @[RegisterRouter.scala:87:24]
wire out_rivalid_36; // @[RegisterRouter.scala:87:24]
wire out_rivalid_37; // @[RegisterRouter.scala:87:24]
wire out_rivalid_38; // @[RegisterRouter.scala:87:24]
wire out_rivalid_39; // @[RegisterRouter.scala:87:24]
wire out_rivalid_40; // @[RegisterRouter.scala:87:24]
wire out_rivalid_41; // @[RegisterRouter.scala:87:24]
wire out_rivalid_42; // @[RegisterRouter.scala:87:24]
wire out_rivalid_43; // @[RegisterRouter.scala:87:24]
wire out_rivalid_44; // @[RegisterRouter.scala:87:24]
wire out_rivalid_45; // @[RegisterRouter.scala:87:24]
wire out_rivalid_46; // @[RegisterRouter.scala:87:24]
wire out_rivalid_47; // @[RegisterRouter.scala:87:24]
wire out_rivalid_48; // @[RegisterRouter.scala:87:24]
wire out_rivalid_49; // @[RegisterRouter.scala:87:24]
wire out_rivalid_50; // @[RegisterRouter.scala:87:24]
wire out_rivalid_51; // @[RegisterRouter.scala:87:24]
wire out_rivalid_52; // @[RegisterRouter.scala:87:24]
wire out_rivalid_53; // @[RegisterRouter.scala:87:24]
wire out_rivalid_54; // @[RegisterRouter.scala:87:24]
wire out_rivalid_55; // @[RegisterRouter.scala:87:24]
wire out_rivalid_56; // @[RegisterRouter.scala:87:24]
wire out_rivalid_57; // @[RegisterRouter.scala:87:24]
wire out_rivalid_58; // @[RegisterRouter.scala:87:24]
wire out_rivalid_59; // @[RegisterRouter.scala:87:24]
wire out_rivalid_60; // @[RegisterRouter.scala:87:24]
wire out_rivalid_61; // @[RegisterRouter.scala:87:24]
wire out_rivalid_62; // @[RegisterRouter.scala:87:24]
wire out_rivalid_63; // @[RegisterRouter.scala:87:24]
wire out_rivalid_64; // @[RegisterRouter.scala:87:24]
wire out_rivalid_65; // @[RegisterRouter.scala:87:24]
wire out_rivalid_66; // @[RegisterRouter.scala:87:24]
wire out_rivalid_67; // @[RegisterRouter.scala:87:24]
wire out_rivalid_68; // @[RegisterRouter.scala:87:24]
wire out_rivalid_69; // @[RegisterRouter.scala:87:24]
wire out_rivalid_70; // @[RegisterRouter.scala:87:24]
wire out_rivalid_71; // @[RegisterRouter.scala:87:24]
wire out_rivalid_72; // @[RegisterRouter.scala:87:24]
wire out_rivalid_73; // @[RegisterRouter.scala:87:24]
wire out_rivalid_74; // @[RegisterRouter.scala:87:24]
wire out_rivalid_75; // @[RegisterRouter.scala:87:24]
wire out_rivalid_76; // @[RegisterRouter.scala:87:24]
wire out_rivalid_77; // @[RegisterRouter.scala:87:24]
wire out_rivalid_78; // @[RegisterRouter.scala:87:24]
wire out_rivalid_79; // @[RegisterRouter.scala:87:24]
wire out_rivalid_80; // @[RegisterRouter.scala:87:24]
wire out_rivalid_81; // @[RegisterRouter.scala:87:24]
wire out_rivalid_82; // @[RegisterRouter.scala:87:24]
wire out_rivalid_83; // @[RegisterRouter.scala:87:24]
wire out_rivalid_84; // @[RegisterRouter.scala:87:24]
wire out_rivalid_85; // @[RegisterRouter.scala:87:24]
wire out_rivalid_86; // @[RegisterRouter.scala:87:24]
wire out_rivalid_87; // @[RegisterRouter.scala:87:24]
wire out_rivalid_88; // @[RegisterRouter.scala:87:24]
wire out_rivalid_89; // @[RegisterRouter.scala:87:24]
wire out_rivalid_90; // @[RegisterRouter.scala:87:24]
wire out_rivalid_91; // @[RegisterRouter.scala:87:24]
wire out_rivalid_92; // @[RegisterRouter.scala:87:24]
wire out_rivalid_93; // @[RegisterRouter.scala:87:24]
wire out_rivalid_94; // @[RegisterRouter.scala:87:24]
wire out_rivalid_95; // @[RegisterRouter.scala:87:24]
wire out_rivalid_96; // @[RegisterRouter.scala:87:24]
wire out_rivalid_97; // @[RegisterRouter.scala:87:24]
wire out_rivalid_98; // @[RegisterRouter.scala:87:24]
wire out_rivalid_99; // @[RegisterRouter.scala:87:24]
wire out_rivalid_100; // @[RegisterRouter.scala:87:24]
wire out_rivalid_101; // @[RegisterRouter.scala:87:24]
wire out_rivalid_102; // @[RegisterRouter.scala:87:24]
wire out_rivalid_103; // @[RegisterRouter.scala:87:24]
wire out_rivalid_104; // @[RegisterRouter.scala:87:24]
wire out_rivalid_105; // @[RegisterRouter.scala:87:24]
wire out_rivalid_106; // @[RegisterRouter.scala:87:24]
wire out_rivalid_107; // @[RegisterRouter.scala:87:24]
wire out_rivalid_108; // @[RegisterRouter.scala:87:24]
wire out_rivalid_109; // @[RegisterRouter.scala:87:24]
wire out_rivalid_110; // @[RegisterRouter.scala:87:24]
wire out_rivalid_111; // @[RegisterRouter.scala:87:24]
wire out_rivalid_112; // @[RegisterRouter.scala:87:24]
wire out_rivalid_113; // @[RegisterRouter.scala:87:24]
wire out_rivalid_114; // @[RegisterRouter.scala:87:24]
wire out_rivalid_115; // @[RegisterRouter.scala:87:24]
wire out_rivalid_116; // @[RegisterRouter.scala:87:24]
wire out_rivalid_117; // @[RegisterRouter.scala:87:24]
wire out_rivalid_118; // @[RegisterRouter.scala:87:24]
wire out_rivalid_119; // @[RegisterRouter.scala:87:24]
wire out_rivalid_120; // @[RegisterRouter.scala:87:24]
wire out_rivalid_121; // @[RegisterRouter.scala:87:24]
wire out_rivalid_122; // @[RegisterRouter.scala:87:24]
wire out_rivalid_123; // @[RegisterRouter.scala:87:24]
wire out_rivalid_124; // @[RegisterRouter.scala:87:24]
wire out_rivalid_125; // @[RegisterRouter.scala:87:24]
wire out_rivalid_126; // @[RegisterRouter.scala:87:24]
wire out_rivalid_127; // @[RegisterRouter.scala:87:24]
wire out_rivalid_128; // @[RegisterRouter.scala:87:24]
wire out_rivalid_129; // @[RegisterRouter.scala:87:24]
wire out_rivalid_130; // @[RegisterRouter.scala:87:24]
wire out_rivalid_131; // @[RegisterRouter.scala:87:24]
wire out_rivalid_132; // @[RegisterRouter.scala:87:24]
wire out_rivalid_133; // @[RegisterRouter.scala:87:24]
wire out_rivalid_134; // @[RegisterRouter.scala:87:24]
wire out_rivalid_135; // @[RegisterRouter.scala:87:24]
wire out_rivalid_136; // @[RegisterRouter.scala:87:24]
wire out_rivalid_137; // @[RegisterRouter.scala:87:24]
wire out_rivalid_138; // @[RegisterRouter.scala:87:24]
wire out_rivalid_139; // @[RegisterRouter.scala:87:24]
wire out_rivalid_140; // @[RegisterRouter.scala:87:24]
wire out_rivalid_141; // @[RegisterRouter.scala:87:24]
wire out_rivalid_142; // @[RegisterRouter.scala:87:24]
wire out_rivalid_143; // @[RegisterRouter.scala:87:24]
wire out_rivalid_144; // @[RegisterRouter.scala:87:24]
wire out_rivalid_145; // @[RegisterRouter.scala:87:24]
wire out_rivalid_146; // @[RegisterRouter.scala:87:24]
wire out_rivalid_147; // @[RegisterRouter.scala:87:24]
wire out_rivalid_148; // @[RegisterRouter.scala:87:24]
wire out_rivalid_149; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_204; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_wivalid_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_17; // @[RegisterRouter.scala:87:24]
wire out_wivalid_18; // @[RegisterRouter.scala:87:24]
wire out_wivalid_19; // @[RegisterRouter.scala:87:24]
wire out_wivalid_20; // @[RegisterRouter.scala:87:24]
wire out_wivalid_21; // @[RegisterRouter.scala:87:24]
wire out_wivalid_22; // @[RegisterRouter.scala:87:24]
wire out_wivalid_23; // @[RegisterRouter.scala:87:24]
wire out_wivalid_24; // @[RegisterRouter.scala:87:24]
wire out_wivalid_25; // @[RegisterRouter.scala:87:24]
wire out_wivalid_26; // @[RegisterRouter.scala:87:24]
wire out_wivalid_27; // @[RegisterRouter.scala:87:24]
wire out_wivalid_28; // @[RegisterRouter.scala:87:24]
wire out_wivalid_29; // @[RegisterRouter.scala:87:24]
wire out_wivalid_30; // @[RegisterRouter.scala:87:24]
wire out_wivalid_31; // @[RegisterRouter.scala:87:24]
wire out_wivalid_32; // @[RegisterRouter.scala:87:24]
wire out_wivalid_33; // @[RegisterRouter.scala:87:24]
wire out_wivalid_34; // @[RegisterRouter.scala:87:24]
wire out_wivalid_35; // @[RegisterRouter.scala:87:24]
wire out_wivalid_36; // @[RegisterRouter.scala:87:24]
wire out_wivalid_37; // @[RegisterRouter.scala:87:24]
wire out_wivalid_38; // @[RegisterRouter.scala:87:24]
wire out_wivalid_39; // @[RegisterRouter.scala:87:24]
wire out_wivalid_40; // @[RegisterRouter.scala:87:24]
wire out_wivalid_41; // @[RegisterRouter.scala:87:24]
wire out_wivalid_42; // @[RegisterRouter.scala:87:24]
wire out_wivalid_43; // @[RegisterRouter.scala:87:24]
wire out_wivalid_44; // @[RegisterRouter.scala:87:24]
wire out_wivalid_45; // @[RegisterRouter.scala:87:24]
wire out_wivalid_46; // @[RegisterRouter.scala:87:24]
wire out_wivalid_47; // @[RegisterRouter.scala:87:24]
wire out_wivalid_48; // @[RegisterRouter.scala:87:24]
wire out_wivalid_49; // @[RegisterRouter.scala:87:24]
wire out_wivalid_50; // @[RegisterRouter.scala:87:24]
wire out_wivalid_51; // @[RegisterRouter.scala:87:24]
wire out_wivalid_52; // @[RegisterRouter.scala:87:24]
wire out_wivalid_53; // @[RegisterRouter.scala:87:24]
wire out_wivalid_54; // @[RegisterRouter.scala:87:24]
wire out_wivalid_55; // @[RegisterRouter.scala:87:24]
wire out_wivalid_56; // @[RegisterRouter.scala:87:24]
wire out_wivalid_57; // @[RegisterRouter.scala:87:24]
wire out_wivalid_58; // @[RegisterRouter.scala:87:24]
wire out_wivalid_59; // @[RegisterRouter.scala:87:24]
wire out_wivalid_60; // @[RegisterRouter.scala:87:24]
wire out_wivalid_61; // @[RegisterRouter.scala:87:24]
wire out_wivalid_62; // @[RegisterRouter.scala:87:24]
wire out_wivalid_63; // @[RegisterRouter.scala:87:24]
wire out_wivalid_64; // @[RegisterRouter.scala:87:24]
wire out_wivalid_65; // @[RegisterRouter.scala:87:24]
wire out_wivalid_66; // @[RegisterRouter.scala:87:24]
wire out_wivalid_67; // @[RegisterRouter.scala:87:24]
wire out_wivalid_68; // @[RegisterRouter.scala:87:24]
wire out_wivalid_69; // @[RegisterRouter.scala:87:24]
wire out_wivalid_70; // @[RegisterRouter.scala:87:24]
wire out_wivalid_71; // @[RegisterRouter.scala:87:24]
wire out_wivalid_72; // @[RegisterRouter.scala:87:24]
wire out_wivalid_73; // @[RegisterRouter.scala:87:24]
wire out_wivalid_74; // @[RegisterRouter.scala:87:24]
wire out_wivalid_75; // @[RegisterRouter.scala:87:24]
wire out_wivalid_76; // @[RegisterRouter.scala:87:24]
wire out_wivalid_77; // @[RegisterRouter.scala:87:24]
wire out_wivalid_78; // @[RegisterRouter.scala:87:24]
wire out_wivalid_79; // @[RegisterRouter.scala:87:24]
wire out_wivalid_80; // @[RegisterRouter.scala:87:24]
wire out_wivalid_81; // @[RegisterRouter.scala:87:24]
wire out_wivalid_82; // @[RegisterRouter.scala:87:24]
wire out_wivalid_83; // @[RegisterRouter.scala:87:24]
wire out_wivalid_84; // @[RegisterRouter.scala:87:24]
wire out_wivalid_85; // @[RegisterRouter.scala:87:24]
wire out_wivalid_86; // @[RegisterRouter.scala:87:24]
wire out_wivalid_87; // @[RegisterRouter.scala:87:24]
wire out_wivalid_88; // @[RegisterRouter.scala:87:24]
wire out_wivalid_89; // @[RegisterRouter.scala:87:24]
wire out_wivalid_90; // @[RegisterRouter.scala:87:24]
wire out_wivalid_91; // @[RegisterRouter.scala:87:24]
wire out_wivalid_92; // @[RegisterRouter.scala:87:24]
wire out_wivalid_93; // @[RegisterRouter.scala:87:24]
wire out_wivalid_94; // @[RegisterRouter.scala:87:24]
wire out_wivalid_95; // @[RegisterRouter.scala:87:24]
wire out_wivalid_96; // @[RegisterRouter.scala:87:24]
wire out_wivalid_97; // @[RegisterRouter.scala:87:24]
wire out_wivalid_98; // @[RegisterRouter.scala:87:24]
wire out_wivalid_99; // @[RegisterRouter.scala:87:24]
wire out_wivalid_100; // @[RegisterRouter.scala:87:24]
wire out_wivalid_101; // @[RegisterRouter.scala:87:24]
wire out_wivalid_102; // @[RegisterRouter.scala:87:24]
wire out_wivalid_103; // @[RegisterRouter.scala:87:24]
wire out_wivalid_104; // @[RegisterRouter.scala:87:24]
wire out_wivalid_105; // @[RegisterRouter.scala:87:24]
wire out_wivalid_106; // @[RegisterRouter.scala:87:24]
wire out_wivalid_107; // @[RegisterRouter.scala:87:24]
wire out_wivalid_108; // @[RegisterRouter.scala:87:24]
wire out_wivalid_109; // @[RegisterRouter.scala:87:24]
wire out_wivalid_110; // @[RegisterRouter.scala:87:24]
wire out_wivalid_111; // @[RegisterRouter.scala:87:24]
wire out_wivalid_112; // @[RegisterRouter.scala:87:24]
wire out_wivalid_113; // @[RegisterRouter.scala:87:24]
wire out_wivalid_114; // @[RegisterRouter.scala:87:24]
wire out_wivalid_115; // @[RegisterRouter.scala:87:24]
wire out_wivalid_116; // @[RegisterRouter.scala:87:24]
wire out_wivalid_117; // @[RegisterRouter.scala:87:24]
wire out_wivalid_118; // @[RegisterRouter.scala:87:24]
wire out_wivalid_119; // @[RegisterRouter.scala:87:24]
wire out_wivalid_120; // @[RegisterRouter.scala:87:24]
wire out_wivalid_121; // @[RegisterRouter.scala:87:24]
wire out_wivalid_122; // @[RegisterRouter.scala:87:24]
wire out_wivalid_123; // @[RegisterRouter.scala:87:24]
wire out_wivalid_124; // @[RegisterRouter.scala:87:24]
wire out_wivalid_125; // @[RegisterRouter.scala:87:24]
wire out_wivalid_126; // @[RegisterRouter.scala:87:24]
wire out_wivalid_127; // @[RegisterRouter.scala:87:24]
wire out_wivalid_128; // @[RegisterRouter.scala:87:24]
wire out_wivalid_129; // @[RegisterRouter.scala:87:24]
wire out_wivalid_130; // @[RegisterRouter.scala:87:24]
wire out_wivalid_131; // @[RegisterRouter.scala:87:24]
wire out_wivalid_132; // @[RegisterRouter.scala:87:24]
wire out_wivalid_133; // @[RegisterRouter.scala:87:24]
wire out_wivalid_134; // @[RegisterRouter.scala:87:24]
wire out_wivalid_135; // @[RegisterRouter.scala:87:24]
wire out_wivalid_136; // @[RegisterRouter.scala:87:24]
wire out_wivalid_137; // @[RegisterRouter.scala:87:24]
wire out_wivalid_138; // @[RegisterRouter.scala:87:24]
wire out_wivalid_139; // @[RegisterRouter.scala:87:24]
wire out_wivalid_140; // @[RegisterRouter.scala:87:24]
wire out_wivalid_141; // @[RegisterRouter.scala:87:24]
wire out_wivalid_142; // @[RegisterRouter.scala:87:24]
wire out_wivalid_143; // @[RegisterRouter.scala:87:24]
wire out_wivalid_144; // @[RegisterRouter.scala:87:24]
wire out_wivalid_145; // @[RegisterRouter.scala:87:24]
wire out_wivalid_146; // @[RegisterRouter.scala:87:24]
wire out_wivalid_147; // @[RegisterRouter.scala:87:24]
wire out_wivalid_148; // @[RegisterRouter.scala:87:24]
wire out_wivalid_149; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_203; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire out_roready_16; // @[RegisterRouter.scala:87:24]
wire out_roready_17; // @[RegisterRouter.scala:87:24]
wire out_roready_18; // @[RegisterRouter.scala:87:24]
wire out_roready_19; // @[RegisterRouter.scala:87:24]
wire out_roready_20; // @[RegisterRouter.scala:87:24]
wire out_roready_21; // @[RegisterRouter.scala:87:24]
wire out_roready_22; // @[RegisterRouter.scala:87:24]
wire out_roready_23; // @[RegisterRouter.scala:87:24]
wire out_roready_24; // @[RegisterRouter.scala:87:24]
wire out_roready_25; // @[RegisterRouter.scala:87:24]
wire out_roready_26; // @[RegisterRouter.scala:87:24]
wire out_roready_27; // @[RegisterRouter.scala:87:24]
wire out_roready_28; // @[RegisterRouter.scala:87:24]
wire out_roready_29; // @[RegisterRouter.scala:87:24]
wire out_roready_30; // @[RegisterRouter.scala:87:24]
wire out_roready_31; // @[RegisterRouter.scala:87:24]
wire out_roready_32; // @[RegisterRouter.scala:87:24]
wire out_roready_33; // @[RegisterRouter.scala:87:24]
wire out_roready_34; // @[RegisterRouter.scala:87:24]
wire out_roready_35; // @[RegisterRouter.scala:87:24]
wire out_roready_36; // @[RegisterRouter.scala:87:24]
wire out_roready_37; // @[RegisterRouter.scala:87:24]
wire out_roready_38; // @[RegisterRouter.scala:87:24]
wire out_roready_39; // @[RegisterRouter.scala:87:24]
wire out_roready_40; // @[RegisterRouter.scala:87:24]
wire out_roready_41; // @[RegisterRouter.scala:87:24]
wire out_roready_42; // @[RegisterRouter.scala:87:24]
wire out_roready_43; // @[RegisterRouter.scala:87:24]
wire out_roready_44; // @[RegisterRouter.scala:87:24]
wire out_roready_45; // @[RegisterRouter.scala:87:24]
wire out_roready_46; // @[RegisterRouter.scala:87:24]
wire out_roready_47; // @[RegisterRouter.scala:87:24]
wire out_roready_48; // @[RegisterRouter.scala:87:24]
wire out_roready_49; // @[RegisterRouter.scala:87:24]
wire out_roready_50; // @[RegisterRouter.scala:87:24]
wire out_roready_51; // @[RegisterRouter.scala:87:24]
wire out_roready_52; // @[RegisterRouter.scala:87:24]
wire out_roready_53; // @[RegisterRouter.scala:87:24]
wire out_roready_54; // @[RegisterRouter.scala:87:24]
wire out_roready_55; // @[RegisterRouter.scala:87:24]
wire out_roready_56; // @[RegisterRouter.scala:87:24]
wire out_roready_57; // @[RegisterRouter.scala:87:24]
wire out_roready_58; // @[RegisterRouter.scala:87:24]
wire out_roready_59; // @[RegisterRouter.scala:87:24]
wire out_roready_60; // @[RegisterRouter.scala:87:24]
wire out_roready_61; // @[RegisterRouter.scala:87:24]
wire out_roready_62; // @[RegisterRouter.scala:87:24]
wire out_roready_63; // @[RegisterRouter.scala:87:24]
wire out_roready_64; // @[RegisterRouter.scala:87:24]
wire out_roready_65; // @[RegisterRouter.scala:87:24]
wire out_roready_66; // @[RegisterRouter.scala:87:24]
wire out_roready_67; // @[RegisterRouter.scala:87:24]
wire out_roready_68; // @[RegisterRouter.scala:87:24]
wire out_roready_69; // @[RegisterRouter.scala:87:24]
wire out_roready_70; // @[RegisterRouter.scala:87:24]
wire out_roready_71; // @[RegisterRouter.scala:87:24]
wire out_roready_72; // @[RegisterRouter.scala:87:24]
wire out_roready_73; // @[RegisterRouter.scala:87:24]
wire out_roready_74; // @[RegisterRouter.scala:87:24]
wire out_roready_75; // @[RegisterRouter.scala:87:24]
wire out_roready_76; // @[RegisterRouter.scala:87:24]
wire out_roready_77; // @[RegisterRouter.scala:87:24]
wire out_roready_78; // @[RegisterRouter.scala:87:24]
wire out_roready_79; // @[RegisterRouter.scala:87:24]
wire out_roready_80; // @[RegisterRouter.scala:87:24]
wire out_roready_81; // @[RegisterRouter.scala:87:24]
wire out_roready_82; // @[RegisterRouter.scala:87:24]
wire out_roready_83; // @[RegisterRouter.scala:87:24]
wire out_roready_84; // @[RegisterRouter.scala:87:24]
wire out_roready_85; // @[RegisterRouter.scala:87:24]
wire out_roready_86; // @[RegisterRouter.scala:87:24]
wire out_roready_87; // @[RegisterRouter.scala:87:24]
wire out_roready_88; // @[RegisterRouter.scala:87:24]
wire out_roready_89; // @[RegisterRouter.scala:87:24]
wire out_roready_90; // @[RegisterRouter.scala:87:24]
wire out_roready_91; // @[RegisterRouter.scala:87:24]
wire out_roready_92; // @[RegisterRouter.scala:87:24]
wire out_roready_93; // @[RegisterRouter.scala:87:24]
wire out_roready_94; // @[RegisterRouter.scala:87:24]
wire out_roready_95; // @[RegisterRouter.scala:87:24]
wire out_roready_96; // @[RegisterRouter.scala:87:24]
wire out_roready_97; // @[RegisterRouter.scala:87:24]
wire out_roready_98; // @[RegisterRouter.scala:87:24]
wire out_roready_99; // @[RegisterRouter.scala:87:24]
wire out_roready_100; // @[RegisterRouter.scala:87:24]
wire out_roready_101; // @[RegisterRouter.scala:87:24]
wire out_roready_102; // @[RegisterRouter.scala:87:24]
wire out_roready_103; // @[RegisterRouter.scala:87:24]
wire out_roready_104; // @[RegisterRouter.scala:87:24]
wire out_roready_105; // @[RegisterRouter.scala:87:24]
wire out_roready_106; // @[RegisterRouter.scala:87:24]
wire out_roready_107; // @[RegisterRouter.scala:87:24]
wire out_roready_108; // @[RegisterRouter.scala:87:24]
wire out_roready_109; // @[RegisterRouter.scala:87:24]
wire out_roready_110; // @[RegisterRouter.scala:87:24]
wire out_roready_111; // @[RegisterRouter.scala:87:24]
wire out_roready_112; // @[RegisterRouter.scala:87:24]
wire out_roready_113; // @[RegisterRouter.scala:87:24]
wire out_roready_114; // @[RegisterRouter.scala:87:24]
wire out_roready_115; // @[RegisterRouter.scala:87:24]
wire out_roready_116; // @[RegisterRouter.scala:87:24]
wire out_roready_117; // @[RegisterRouter.scala:87:24]
wire out_roready_118; // @[RegisterRouter.scala:87:24]
wire out_roready_119; // @[RegisterRouter.scala:87:24]
wire out_roready_120; // @[RegisterRouter.scala:87:24]
wire out_roready_121; // @[RegisterRouter.scala:87:24]
wire out_roready_122; // @[RegisterRouter.scala:87:24]
wire out_roready_123; // @[RegisterRouter.scala:87:24]
wire out_roready_124; // @[RegisterRouter.scala:87:24]
wire out_roready_125; // @[RegisterRouter.scala:87:24]
wire out_roready_126; // @[RegisterRouter.scala:87:24]
wire out_roready_127; // @[RegisterRouter.scala:87:24]
wire out_roready_128; // @[RegisterRouter.scala:87:24]
wire out_roready_129; // @[RegisterRouter.scala:87:24]
wire out_roready_130; // @[RegisterRouter.scala:87:24]
wire out_roready_131; // @[RegisterRouter.scala:87:24]
wire out_roready_132; // @[RegisterRouter.scala:87:24]
wire out_roready_133; // @[RegisterRouter.scala:87:24]
wire out_roready_134; // @[RegisterRouter.scala:87:24]
wire out_roready_135; // @[RegisterRouter.scala:87:24]
wire out_roready_136; // @[RegisterRouter.scala:87:24]
wire out_roready_137; // @[RegisterRouter.scala:87:24]
wire out_roready_138; // @[RegisterRouter.scala:87:24]
wire out_roready_139; // @[RegisterRouter.scala:87:24]
wire out_roready_140; // @[RegisterRouter.scala:87:24]
wire out_roready_141; // @[RegisterRouter.scala:87:24]
wire out_roready_142; // @[RegisterRouter.scala:87:24]
wire out_roready_143; // @[RegisterRouter.scala:87:24]
wire out_roready_144; // @[RegisterRouter.scala:87:24]
wire out_roready_145; // @[RegisterRouter.scala:87:24]
wire out_roready_146; // @[RegisterRouter.scala:87:24]
wire out_roready_147; // @[RegisterRouter.scala:87:24]
wire out_roready_148; // @[RegisterRouter.scala:87:24]
wire out_roready_149; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_204; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire out_woready_16; // @[RegisterRouter.scala:87:24]
wire out_woready_17; // @[RegisterRouter.scala:87:24]
wire out_woready_18; // @[RegisterRouter.scala:87:24]
wire out_woready_19; // @[RegisterRouter.scala:87:24]
wire out_woready_20; // @[RegisterRouter.scala:87:24]
wire out_woready_21; // @[RegisterRouter.scala:87:24]
wire out_woready_22; // @[RegisterRouter.scala:87:24]
wire out_woready_23; // @[RegisterRouter.scala:87:24]
wire out_woready_24; // @[RegisterRouter.scala:87:24]
wire out_woready_25; // @[RegisterRouter.scala:87:24]
wire out_woready_26; // @[RegisterRouter.scala:87:24]
wire out_woready_27; // @[RegisterRouter.scala:87:24]
wire out_woready_28; // @[RegisterRouter.scala:87:24]
wire out_woready_29; // @[RegisterRouter.scala:87:24]
wire out_woready_30; // @[RegisterRouter.scala:87:24]
wire out_woready_31; // @[RegisterRouter.scala:87:24]
wire out_woready_32; // @[RegisterRouter.scala:87:24]
wire out_woready_33; // @[RegisterRouter.scala:87:24]
wire out_woready_34; // @[RegisterRouter.scala:87:24]
wire out_woready_35; // @[RegisterRouter.scala:87:24]
wire out_woready_36; // @[RegisterRouter.scala:87:24]
wire out_woready_37; // @[RegisterRouter.scala:87:24]
wire out_woready_38; // @[RegisterRouter.scala:87:24]
wire out_woready_39; // @[RegisterRouter.scala:87:24]
wire out_woready_40; // @[RegisterRouter.scala:87:24]
wire out_woready_41; // @[RegisterRouter.scala:87:24]
wire out_woready_42; // @[RegisterRouter.scala:87:24]
wire out_woready_43; // @[RegisterRouter.scala:87:24]
wire out_woready_44; // @[RegisterRouter.scala:87:24]
wire out_woready_45; // @[RegisterRouter.scala:87:24]
wire out_woready_46; // @[RegisterRouter.scala:87:24]
wire out_woready_47; // @[RegisterRouter.scala:87:24]
wire out_woready_48; // @[RegisterRouter.scala:87:24]
wire out_woready_49; // @[RegisterRouter.scala:87:24]
wire out_woready_50; // @[RegisterRouter.scala:87:24]
wire out_woready_51; // @[RegisterRouter.scala:87:24]
wire out_woready_52; // @[RegisterRouter.scala:87:24]
wire out_woready_53; // @[RegisterRouter.scala:87:24]
wire out_woready_54; // @[RegisterRouter.scala:87:24]
wire out_woready_55; // @[RegisterRouter.scala:87:24]
wire out_woready_56; // @[RegisterRouter.scala:87:24]
wire out_woready_57; // @[RegisterRouter.scala:87:24]
wire out_woready_58; // @[RegisterRouter.scala:87:24]
wire out_woready_59; // @[RegisterRouter.scala:87:24]
wire out_woready_60; // @[RegisterRouter.scala:87:24]
wire out_woready_61; // @[RegisterRouter.scala:87:24]
wire out_woready_62; // @[RegisterRouter.scala:87:24]
wire out_woready_63; // @[RegisterRouter.scala:87:24]
wire out_woready_64; // @[RegisterRouter.scala:87:24]
wire out_woready_65; // @[RegisterRouter.scala:87:24]
wire out_woready_66; // @[RegisterRouter.scala:87:24]
wire out_woready_67; // @[RegisterRouter.scala:87:24]
wire out_woready_68; // @[RegisterRouter.scala:87:24]
wire out_woready_69; // @[RegisterRouter.scala:87:24]
wire out_woready_70; // @[RegisterRouter.scala:87:24]
wire out_woready_71; // @[RegisterRouter.scala:87:24]
wire out_woready_72; // @[RegisterRouter.scala:87:24]
wire out_woready_73; // @[RegisterRouter.scala:87:24]
wire out_woready_74; // @[RegisterRouter.scala:87:24]
wire out_woready_75; // @[RegisterRouter.scala:87:24]
wire out_woready_76; // @[RegisterRouter.scala:87:24]
wire out_woready_77; // @[RegisterRouter.scala:87:24]
wire out_woready_78; // @[RegisterRouter.scala:87:24]
wire out_woready_79; // @[RegisterRouter.scala:87:24]
wire out_woready_80; // @[RegisterRouter.scala:87:24]
wire out_woready_81; // @[RegisterRouter.scala:87:24]
wire out_woready_82; // @[RegisterRouter.scala:87:24]
wire out_woready_83; // @[RegisterRouter.scala:87:24]
wire out_woready_84; // @[RegisterRouter.scala:87:24]
wire out_woready_85; // @[RegisterRouter.scala:87:24]
wire out_woready_86; // @[RegisterRouter.scala:87:24]
wire out_woready_87; // @[RegisterRouter.scala:87:24]
wire out_woready_88; // @[RegisterRouter.scala:87:24]
wire out_woready_89; // @[RegisterRouter.scala:87:24]
wire out_woready_90; // @[RegisterRouter.scala:87:24]
wire out_woready_91; // @[RegisterRouter.scala:87:24]
wire out_woready_92; // @[RegisterRouter.scala:87:24]
wire out_woready_93; // @[RegisterRouter.scala:87:24]
wire out_woready_94; // @[RegisterRouter.scala:87:24]
wire out_woready_95; // @[RegisterRouter.scala:87:24]
wire out_woready_96; // @[RegisterRouter.scala:87:24]
wire out_woready_97; // @[RegisterRouter.scala:87:24]
wire out_woready_98; // @[RegisterRouter.scala:87:24]
wire out_woready_99; // @[RegisterRouter.scala:87:24]
wire out_woready_100; // @[RegisterRouter.scala:87:24]
wire out_woready_101; // @[RegisterRouter.scala:87:24]
wire out_woready_102; // @[RegisterRouter.scala:87:24]
wire out_woready_103; // @[RegisterRouter.scala:87:24]
wire out_woready_104; // @[RegisterRouter.scala:87:24]
wire out_woready_105; // @[RegisterRouter.scala:87:24]
wire out_woready_106; // @[RegisterRouter.scala:87:24]
wire out_woready_107; // @[RegisterRouter.scala:87:24]
wire out_woready_108; // @[RegisterRouter.scala:87:24]
wire out_woready_109; // @[RegisterRouter.scala:87:24]
wire out_woready_110; // @[RegisterRouter.scala:87:24]
wire out_woready_111; // @[RegisterRouter.scala:87:24]
wire out_woready_112; // @[RegisterRouter.scala:87:24]
wire out_woready_113; // @[RegisterRouter.scala:87:24]
wire out_woready_114; // @[RegisterRouter.scala:87:24]
wire out_woready_115; // @[RegisterRouter.scala:87:24]
wire out_woready_116; // @[RegisterRouter.scala:87:24]
wire out_woready_117; // @[RegisterRouter.scala:87:24]
wire out_woready_118; // @[RegisterRouter.scala:87:24]
wire out_woready_119; // @[RegisterRouter.scala:87:24]
wire out_woready_120; // @[RegisterRouter.scala:87:24]
wire out_woready_121; // @[RegisterRouter.scala:87:24]
wire out_woready_122; // @[RegisterRouter.scala:87:24]
wire out_woready_123; // @[RegisterRouter.scala:87:24]
wire out_woready_124; // @[RegisterRouter.scala:87:24]
wire out_woready_125; // @[RegisterRouter.scala:87:24]
wire out_woready_126; // @[RegisterRouter.scala:87:24]
wire out_woready_127; // @[RegisterRouter.scala:87:24]
wire out_woready_128; // @[RegisterRouter.scala:87:24]
wire out_woready_129; // @[RegisterRouter.scala:87:24]
wire out_woready_130; // @[RegisterRouter.scala:87:24]
wire out_woready_131; // @[RegisterRouter.scala:87:24]
wire out_woready_132; // @[RegisterRouter.scala:87:24]
wire out_woready_133; // @[RegisterRouter.scala:87:24]
wire out_woready_134; // @[RegisterRouter.scala:87:24]
wire out_woready_135; // @[RegisterRouter.scala:87:24]
wire out_woready_136; // @[RegisterRouter.scala:87:24]
wire out_woready_137; // @[RegisterRouter.scala:87:24]
wire out_woready_138; // @[RegisterRouter.scala:87:24]
wire out_woready_139; // @[RegisterRouter.scala:87:24]
wire out_woready_140; // @[RegisterRouter.scala:87:24]
wire out_woready_141; // @[RegisterRouter.scala:87:24]
wire out_woready_142; // @[RegisterRouter.scala:87:24]
wire out_woready_143; // @[RegisterRouter.scala:87:24]
wire out_woready_144; // @[RegisterRouter.scala:87:24]
wire out_woready_145; // @[RegisterRouter.scala:87:24]
wire out_woready_146; // @[RegisterRouter.scala:87:24]
wire out_woready_147; // @[RegisterRouter.scala:87:24]
wire out_woready_148; // @[RegisterRouter.scala:87:24]
wire out_woready_149; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_4 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_5 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_6 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_7 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo = {_out_frontMask_T_5, _out_frontMask_T_4}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi = {_out_frontMask_T_7, _out_frontMask_T_6}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_67 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_67 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_72 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_72 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_85 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_85 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_144 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_144 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_149 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_149 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_4 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_5 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_6 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_7 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo = {_out_backMask_T_5, _out_backMask_T_4}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi = {_out_backMask_T_7, _out_backMask_T_6}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_67 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_67 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_72 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_72 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_85 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_85 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_144 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_144 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_149 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_149 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_5 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_9 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_13 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_21 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_25 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_29 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_33 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_33 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_52 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_56 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_56 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_59 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_63 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_63 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_68 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_68 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_73 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_77 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_81 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_81 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_105 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_109 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_109 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_120 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_124 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_128 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_132 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_136 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_140 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_140 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_145 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_145 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_5 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_9 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_13 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_21 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_25 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_29 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_33 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_33 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_52 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_56 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_56 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_59 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_63 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_63 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_68 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_68 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_73 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_77 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_81 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_81 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_105 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_109 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_109 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_120 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_124 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_128 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_132 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_136 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_140 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_140 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_145 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_145 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_71 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
assign out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_4 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_73 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_4 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire _out_T_74 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_70 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_125 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_169 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_213 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_297 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_341 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_385 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_429 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_620 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_664 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_695 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_739 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_794 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_849 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_893 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_937 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1161 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1205 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1314 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1358 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1402 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1446 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1490 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1534 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1589 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_4 = out_f_woready ? _out_T_70 : abstractDataMem_4; // @[RegisterRouter.scala:87:24]
wire _out_T_75 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_77 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_78 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = _out_T_80; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_6 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_10 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_14 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_22 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_26 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_30 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_34 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_34 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_53 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_57 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_57 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_60 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_64 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_64 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_69 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_69 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_74 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_78 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_82 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_82 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_106 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_110 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_110 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_121 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_125 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_129 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_133 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_137 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_141 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_141 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_146 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_146 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_6 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_10 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_14 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_22 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_26 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_30 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_34 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_34 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_53 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_57 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_57 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_60 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_64 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_64 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_69 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_69 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_74 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_78 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_82 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_82 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_106 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_110 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_110 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_121 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_125 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_129 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_133 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_137 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_141 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_141 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_146 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_146 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_82 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
assign out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_5 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_83 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_84 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24]
assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_5 = out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_85 = out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_81 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_136 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_180 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_224 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_308 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_352 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_396 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_440 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_631 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_675 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_706 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_750 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_805 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_860 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_904 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_948 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1172 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1216 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1325 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1369 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1413 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1457 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1501 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1545 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1600 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_5 = out_f_woready_1 ? _out_T_81 : abstractDataMem_5; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_88 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_89 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend = {abstractDataMem_5, _out_prepend_T}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_90 = out_prepend; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1 = _out_T_91; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_7 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_11 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_15 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_23 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_27 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_31 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_35 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_35 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_54 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_54 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_61 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_65 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_65 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_70 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_70 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_75 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_79 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_83 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_83 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_107 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_111 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_111 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_122 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_126 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_130 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_134 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_138 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_142 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_142 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_147 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_147 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_7 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_11 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_15 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_23 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_27 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_31 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_35 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_35 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_54 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_54 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_61 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_65 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_65 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_70 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_70 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_75 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_79 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_83 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_83 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_107 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_111 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_111 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_122 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_126 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_130 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_134 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_138 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_142 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_142 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_147 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_147 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_93 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
assign out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_6 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire _out_T_94 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_95 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24]
assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_6 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_92 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_147 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_191 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_235 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_319 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_363 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_407 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_451 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_642 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_717 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_761 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_816 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_871 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_915 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_959 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1183 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1227 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1336 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1380 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1424 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1468 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1512 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1556 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1611 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_6 = out_f_woready_2 ? _out_T_92 : abstractDataMem_6; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_99 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_100 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1 = {abstractDataMem_6, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_101 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_2 = _out_T_102; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_8 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_12 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_16 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_24 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_28 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_32 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_36 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_36 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_55 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_55 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_62 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_66 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_66 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_71 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_71 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_76 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_80 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_84 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_84 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_108 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_112 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_112 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_123 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_127 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_131 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_135 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_139 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_143 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_143 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_148 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_148 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_8 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_12 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_16 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_24 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_28 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_32 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_36 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_36 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_55 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_55 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_62 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_66 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_66 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_71 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_71 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_76 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_80 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_84 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_84 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_108 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_112 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_112 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_123 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_127 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_131 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_135 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_139 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_143 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_143 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_148 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_148 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_104 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
assign out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_7 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire _out_T_105 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_106 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24]
assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_7 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_103 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_158 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_202 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_246 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_330 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_374 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_418 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_462 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_653 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_728 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_772 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_827 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_882 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_926 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_970 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1194 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1238 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1347 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1391 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1435 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1479 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1523 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1567 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1622 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_7 = out_f_woready_3 ? _out_T_103 : abstractDataMem_7; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_110 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_111 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_2 = {abstractDataMem_7, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_112 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_5 = _out_T_113; // @[MuxLiteral.scala:49:48]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_115 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
assign out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
assign SBDATARdEn_1 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_116 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24]
assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
assign SBDATAWrEn_1 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
assign SBDATAWrData_1 = out_f_woready_4 ? _out_T_114 : 32'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_120 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_121 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_122 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_61 = _out_T_124; // @[MuxLiteral.scala:49:48]
wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_126 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
assign out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_20 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24]
assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_20 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_20 = out_f_woready_5 ? _out_T_125 : abstractDataMem_20; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_131 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_132 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_133 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_3 = _out_T_135; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_137 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_21 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_138 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24]
assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_21 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_21 = out_f_woready_6 ? _out_T_136 : abstractDataMem_21; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_142 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_143 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_144 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_3 = {abstractDataMem_21, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_145 = out_prepend_3; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_4 = _out_T_146; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
assign out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_22 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_22 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_151 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_22 = out_f_woready_7 ? _out_T_147 : abstractDataMem_22; // @[RegisterRouter.scala:87:24]
wire _out_T_152 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_153 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_154 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_155 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_4 = {abstractDataMem_22, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_156 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_5 = _out_T_157; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
assign out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_23 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire _out_T_160 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_161 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24]
assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_23 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_23 = out_f_woready_8 ? _out_T_158 : abstractDataMem_23; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = ~out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = ~out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_165 = ~out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_166 = ~out_womask_8; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_5 = {abstractDataMem_23, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_167 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_9 = _out_T_168; // @[MuxLiteral.scala:49:48]
wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_170 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24]
assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_36 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_171 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_172 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_36 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_173 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_36 = out_f_woready_9 ? _out_T_169 : programBufferMem_36; // @[RegisterRouter.scala:87:24]
wire _out_T_174 = ~out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_175 = ~out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_176 = ~out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_177 = ~out_womask_9; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_6 = _out_T_179; // @[RegisterRouter.scala:87:24]
wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_181 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
assign out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_37 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire _out_T_182 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_183 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24]
assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_37 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire _out_T_184 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_37 = out_f_woready_10 ? _out_T_180 : programBufferMem_37; // @[RegisterRouter.scala:87:24]
wire _out_T_185 = ~out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_186 = ~out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_187 = ~out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_188 = ~out_womask_10; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_6 = {programBufferMem_37, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_189 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_7 = _out_T_190; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_192 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24]
assign out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_38 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_193 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_194 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_38 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_195 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_38 = out_f_woready_11 ? _out_T_191 : programBufferMem_38; // @[RegisterRouter.scala:87:24]
wire _out_T_196 = ~out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_197 = ~out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_198 = ~out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_199 = ~out_womask_11; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_7 = {programBufferMem_38, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_200 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_8 = _out_T_201; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_203 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
assign out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_39 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_204 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_205 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_39 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_206 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_39 = out_f_woready_12 ? _out_T_202 : programBufferMem_39; // @[RegisterRouter.scala:87:24]
wire _out_T_207 = ~out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_208 = ~out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_209 = ~out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_210 = ~out_womask_12; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_8 = {programBufferMem_39, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_211 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_212 = _out_T_211; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_41 = _out_T_212; // @[MuxLiteral.scala:49:48]
wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_214 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
assign out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_12 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire _out_T_215 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_216 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24]
assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_12 = out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire _out_T_217 = out_f_woready_13; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_12 = out_f_woready_13 ? _out_T_213 : programBufferMem_12; // @[RegisterRouter.scala:87:24]
wire _out_T_218 = ~out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_219 = ~out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_220 = ~out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_221 = ~out_womask_13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_223 = _out_T_222; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_9 = _out_T_223; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_225 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
assign out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_13 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire _out_T_226 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_227 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24]
assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_13 = out_f_woready_14; // @[RegisterRouter.scala:87:24]
wire _out_T_228 = out_f_woready_14; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_13 = out_f_woready_14 ? _out_T_224 : programBufferMem_13; // @[RegisterRouter.scala:87:24]
wire _out_T_229 = ~out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_230 = ~out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_231 = ~out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_232 = ~out_womask_14; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_9 = {programBufferMem_13, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_233 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_234 = _out_T_233; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_10 = _out_T_234; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_236 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
assign out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_14 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire _out_T_237 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_238 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24]
assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_14 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire _out_T_239 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_14 = out_f_woready_15 ? _out_T_235 : programBufferMem_14; // @[RegisterRouter.scala:87:24]
wire _out_T_240 = ~out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_241 = ~out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_242 = ~out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_243 = ~out_womask_15; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_10 = {programBufferMem_14, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_244 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_245 = _out_T_244; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_11 = _out_T_245; // @[RegisterRouter.scala:87:24]
wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24]
wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24]
wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24]
wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_247 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24]
assign out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_15 = out_f_roready_16; // @[RegisterRouter.scala:87:24]
wire _out_T_248 = out_f_roready_16; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_249 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24]
assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_15 = out_f_woready_16; // @[RegisterRouter.scala:87:24]
wire _out_T_250 = out_f_woready_16; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_15 = out_f_woready_16 ? _out_T_246 : programBufferMem_15; // @[RegisterRouter.scala:87:24]
wire _out_T_251 = ~out_rimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_252 = ~out_wimask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_253 = ~out_romask_16; // @[RegisterRouter.scala:87:24]
wire _out_T_254 = ~out_womask_16; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_11 = {programBufferMem_15, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_255 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_256 = _out_T_255; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_35 = _out_T_256; // @[MuxLiteral.scala:49:48]
wire _out_rimask_T_17 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_17 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_37 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_37 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_17 = _out_rimask_T_17; // @[RegisterRouter.scala:87:24]
wire out_wimask_17 = _out_wimask_T_17; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_17 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_17 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_37 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_37 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask_17 = _out_romask_T_17; // @[RegisterRouter.scala:87:24]
wire out_womask_17 = _out_womask_T_17; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_258 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24]
wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_259 = out_f_roready_17; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_260 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24]
assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24]
assign hgselectWrEn = out_f_woready_17; // @[RegisterRouter.scala:87:24]
wire _out_T_261 = out_f_woready_17; // @[RegisterRouter.scala:87:24]
assign _out_T_257 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_473 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
assign DMCS2WrData_hgselect = _out_T_257; // @[RegisterRouter.scala:87:24]
wire _out_T_262 = ~out_rimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_263 = ~out_wimask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_264 = ~out_romask_17; // @[RegisterRouter.scala:87:24]
wire _out_T_265 = ~out_womask_17; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_18 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_18 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_38 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_38 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_18 = _out_rimask_T_18; // @[RegisterRouter.scala:87:24]
wire out_wimask_18 = _out_wimask_T_18; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_18 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_18 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_38 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_38 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_18 = _out_romask_T_18; // @[RegisterRouter.scala:87:24]
wire out_womask_18 = _out_womask_T_18; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_18 = out_rivalid_18 & out_rimask_18; // @[RegisterRouter.scala:87:24]
wire out_f_roready_18 = out_roready_18 & out_romask_18; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_18 = out_wivalid_18 & out_wimask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_269 = out_f_wivalid_18; // @[RegisterRouter.scala:87:24]
assign out_f_woready_18 = out_woready_18 & out_womask_18; // @[RegisterRouter.scala:87:24]
assign hgwriteWrEn = out_f_woready_18; // @[RegisterRouter.scala:87:24]
wire _out_T_270 = out_f_woready_18; // @[RegisterRouter.scala:87:24]
assign _out_T_268 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_482 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
assign DMCS2WrData_hgwrite = _out_T_268; // @[RegisterRouter.scala:87:24]
wire _out_T_271 = ~out_rimask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_272 = ~out_wimask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_273 = ~out_romask_18; // @[RegisterRouter.scala:87:24]
wire _out_T_274 = ~out_womask_18; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_rimask_T_19 = out_frontMask[6:2]; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_wimask_T_19 = out_frontMask[6:2]; // @[RegisterRouter.scala:87:24]
wire out_rimask_19 = |_out_rimask_T_19; // @[RegisterRouter.scala:87:24]
wire out_wimask_19 = &_out_wimask_T_19; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_romask_T_19 = out_backMask[6:2]; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_womask_T_19 = out_backMask[6:2]; // @[RegisterRouter.scala:87:24]
wire out_romask_19 = |_out_romask_T_19; // @[RegisterRouter.scala:87:24]
wire out_womask_19 = &_out_womask_T_19; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_19 = out_rivalid_19 & out_rimask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_278 = out_f_rivalid_19; // @[RegisterRouter.scala:87:24]
wire out_f_roready_19 = out_roready_19 & out_romask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_279 = out_f_roready_19; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_280 = out_f_wivalid_19; // @[RegisterRouter.scala:87:24]
assign out_f_woready_19 = out_woready_19 & out_womask_19; // @[RegisterRouter.scala:87:24]
assign haltgroupWrEn = out_f_woready_19; // @[RegisterRouter.scala:87:24]
wire _out_T_281 = out_f_woready_19; // @[RegisterRouter.scala:87:24]
assign _out_T_277 = out_front_bits_data[6:2]; // @[RegisterRouter.scala:87:24]
assign DMCS2WrData_haltgroup = _out_T_277; // @[RegisterRouter.scala:87:24]
wire _out_T_282 = ~out_rimask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_283 = ~out_wimask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_284 = ~out_romask_19; // @[RegisterRouter.scala:87:24]
wire _out_T_285 = ~out_womask_19; // @[RegisterRouter.scala:87:24]
wire [6:0] out_prepend_13 = {DMCS2RdData_haltgroup, 2'h0}; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_286 = out_prepend_13; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_287 = _out_T_286; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_prepend_T_14 = _out_T_287; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_20 = out_frontMask[10:7]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_20 = out_frontMask[10:7]; // @[RegisterRouter.scala:87:24]
wire out_rimask_20 = |_out_rimask_T_20; // @[RegisterRouter.scala:87:24]
wire out_wimask_20 = &_out_wimask_T_20; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_20 = out_backMask[10:7]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_20 = out_backMask[10:7]; // @[RegisterRouter.scala:87:24]
wire out_romask_20 = |_out_romask_T_20; // @[RegisterRouter.scala:87:24]
wire out_womask_20 = &_out_womask_T_20; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_20 = out_rivalid_20 & out_rimask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_289 = out_f_rivalid_20; // @[RegisterRouter.scala:87:24]
wire out_f_roready_20 = out_roready_20 & out_romask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_290 = out_f_roready_20; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_20 = out_wivalid_20 & out_wimask_20; // @[RegisterRouter.scala:87:24]
wire out_f_woready_20 = out_woready_20 & out_womask_20; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_288 = out_front_bits_data[10:7]; // @[RegisterRouter.scala:87:24]
wire _out_T_291 = ~out_rimask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_292 = ~out_wimask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_293 = ~out_romask_20; // @[RegisterRouter.scala:87:24]
wire _out_T_294 = ~out_womask_20; // @[RegisterRouter.scala:87:24]
wire [7:0] out_prepend_14 = {1'h0, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_295 = {3'h0, out_prepend_14}; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_296 = _out_T_295; // @[RegisterRouter.scala:87:24]
wire out_rimask_21 = |_out_rimask_T_21; // @[RegisterRouter.scala:87:24]
wire out_wimask_21 = &_out_wimask_T_21; // @[RegisterRouter.scala:87:24]
wire out_romask_21 = |_out_romask_T_21; // @[RegisterRouter.scala:87:24]
wire out_womask_21 = &_out_womask_T_21; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_21 = out_rivalid_21 & out_rimask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_298 = out_f_rivalid_21; // @[RegisterRouter.scala:87:24]
assign out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_16 = out_f_roready_21; // @[RegisterRouter.scala:87:24]
wire _out_T_299 = out_f_roready_21; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_300 = out_f_wivalid_21; // @[RegisterRouter.scala:87:24]
assign out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_16 = out_f_woready_21; // @[RegisterRouter.scala:87:24]
wire _out_T_301 = out_f_woready_21; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_16 = out_f_woready_21 ? _out_T_297 : abstractDataMem_16; // @[RegisterRouter.scala:87:24]
wire _out_T_302 = ~out_rimask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_303 = ~out_wimask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_304 = ~out_romask_21; // @[RegisterRouter.scala:87:24]
wire _out_T_305 = ~out_womask_21; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_307 = _out_T_306; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_15 = _out_T_307; // @[RegisterRouter.scala:87:24]
wire out_rimask_22 = |_out_rimask_T_22; // @[RegisterRouter.scala:87:24]
wire out_wimask_22 = &_out_wimask_T_22; // @[RegisterRouter.scala:87:24]
wire out_romask_22 = |_out_romask_T_22; // @[RegisterRouter.scala:87:24]
wire out_womask_22 = &_out_womask_T_22; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_22 = out_rivalid_22 & out_rimask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_309 = out_f_rivalid_22; // @[RegisterRouter.scala:87:24]
assign out_f_roready_22 = out_roready_22 & out_romask_22; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_17 = out_f_roready_22; // @[RegisterRouter.scala:87:24]
wire _out_T_310 = out_f_roready_22; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_22 = out_wivalid_22 & out_wimask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_311 = out_f_wivalid_22; // @[RegisterRouter.scala:87:24]
assign out_f_woready_22 = out_woready_22 & out_womask_22; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_17 = out_f_woready_22; // @[RegisterRouter.scala:87:24]
wire _out_T_312 = out_f_woready_22; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_17 = out_f_woready_22 ? _out_T_308 : abstractDataMem_17; // @[RegisterRouter.scala:87:24]
wire _out_T_313 = ~out_rimask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_314 = ~out_wimask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_315 = ~out_romask_22; // @[RegisterRouter.scala:87:24]
wire _out_T_316 = ~out_womask_22; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_15 = {abstractDataMem_17, _out_prepend_T_15}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_317 = out_prepend_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_318 = _out_T_317; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_16 = _out_T_318; // @[RegisterRouter.scala:87:24]
wire out_rimask_23 = |_out_rimask_T_23; // @[RegisterRouter.scala:87:24]
wire out_wimask_23 = &_out_wimask_T_23; // @[RegisterRouter.scala:87:24]
wire out_romask_23 = |_out_romask_T_23; // @[RegisterRouter.scala:87:24]
wire out_womask_23 = &_out_womask_T_23; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_23 = out_rivalid_23 & out_rimask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_320 = out_f_rivalid_23; // @[RegisterRouter.scala:87:24]
assign out_f_roready_23 = out_roready_23 & out_romask_23; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_18 = out_f_roready_23; // @[RegisterRouter.scala:87:24]
wire _out_T_321 = out_f_roready_23; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_23 = out_wivalid_23 & out_wimask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_322 = out_f_wivalid_23; // @[RegisterRouter.scala:87:24]
assign out_f_woready_23 = out_woready_23 & out_womask_23; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_18 = out_f_woready_23; // @[RegisterRouter.scala:87:24]
wire _out_T_323 = out_f_woready_23; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_18 = out_f_woready_23 ? _out_T_319 : abstractDataMem_18; // @[RegisterRouter.scala:87:24]
wire _out_T_324 = ~out_rimask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_325 = ~out_wimask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_326 = ~out_romask_23; // @[RegisterRouter.scala:87:24]
wire _out_T_327 = ~out_womask_23; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_16 = {abstractDataMem_18, _out_prepend_T_16}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_328 = out_prepend_16; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_329 = _out_T_328; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_17 = _out_T_329; // @[RegisterRouter.scala:87:24]
wire out_rimask_24 = |_out_rimask_T_24; // @[RegisterRouter.scala:87:24]
wire out_wimask_24 = &_out_wimask_T_24; // @[RegisterRouter.scala:87:24]
wire out_romask_24 = |_out_romask_T_24; // @[RegisterRouter.scala:87:24]
wire out_womask_24 = &_out_womask_T_24; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_24 = out_rivalid_24 & out_rimask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_331 = out_f_rivalid_24; // @[RegisterRouter.scala:87:24]
assign out_f_roready_24 = out_roready_24 & out_romask_24; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_19 = out_f_roready_24; // @[RegisterRouter.scala:87:24]
wire _out_T_332 = out_f_roready_24; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_24 = out_wivalid_24 & out_wimask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_333 = out_f_wivalid_24; // @[RegisterRouter.scala:87:24]
assign out_f_woready_24 = out_woready_24 & out_womask_24; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_19 = out_f_woready_24; // @[RegisterRouter.scala:87:24]
wire _out_T_334 = out_f_woready_24; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_19 = out_f_woready_24 ? _out_T_330 : abstractDataMem_19; // @[RegisterRouter.scala:87:24]
wire _out_T_335 = ~out_rimask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_336 = ~out_wimask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_337 = ~out_romask_24; // @[RegisterRouter.scala:87:24]
wire _out_T_338 = ~out_womask_24; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_17 = {abstractDataMem_19, _out_prepend_T_17}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_339 = out_prepend_17; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_340 = _out_T_339; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_8 = _out_T_340; // @[MuxLiteral.scala:49:48]
wire out_rimask_25 = |_out_rimask_T_25; // @[RegisterRouter.scala:87:24]
wire out_wimask_25 = &_out_wimask_T_25; // @[RegisterRouter.scala:87:24]
wire out_romask_25 = |_out_romask_T_25; // @[RegisterRouter.scala:87:24]
wire out_womask_25 = &_out_womask_T_25; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_25 = out_rivalid_25 & out_rimask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_342 = out_f_rivalid_25; // @[RegisterRouter.scala:87:24]
assign out_f_roready_25 = out_roready_25 & out_romask_25; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_0 = out_f_roready_25; // @[RegisterRouter.scala:87:24]
wire _out_T_343 = out_f_roready_25; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_25 = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_344 = out_f_wivalid_25; // @[RegisterRouter.scala:87:24]
assign out_f_woready_25 = out_woready_25 & out_womask_25; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_0 = out_f_woready_25; // @[RegisterRouter.scala:87:24]
wire _out_T_345 = out_f_woready_25; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_0 = out_f_woready_25 ? _out_T_341 : abstractDataMem_0; // @[RegisterRouter.scala:87:24]
wire _out_T_346 = ~out_rimask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_347 = ~out_wimask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_348 = ~out_romask_25; // @[RegisterRouter.scala:87:24]
wire _out_T_349 = ~out_womask_25; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_351 = _out_T_350; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_18 = _out_T_351; // @[RegisterRouter.scala:87:24]
wire out_rimask_26 = |_out_rimask_T_26; // @[RegisterRouter.scala:87:24]
wire out_wimask_26 = &_out_wimask_T_26; // @[RegisterRouter.scala:87:24]
wire out_romask_26 = |_out_romask_T_26; // @[RegisterRouter.scala:87:24]
wire out_womask_26 = &_out_womask_T_26; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_26 = out_rivalid_26 & out_rimask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_353 = out_f_rivalid_26; // @[RegisterRouter.scala:87:24]
assign out_f_roready_26 = out_roready_26 & out_romask_26; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_1 = out_f_roready_26; // @[RegisterRouter.scala:87:24]
wire _out_T_354 = out_f_roready_26; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_26 = out_wivalid_26 & out_wimask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_355 = out_f_wivalid_26; // @[RegisterRouter.scala:87:24]
assign out_f_woready_26 = out_woready_26 & out_womask_26; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_1 = out_f_woready_26; // @[RegisterRouter.scala:87:24]
wire _out_T_356 = out_f_woready_26; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_1 = out_f_woready_26 ? _out_T_352 : abstractDataMem_1; // @[RegisterRouter.scala:87:24]
wire _out_T_357 = ~out_rimask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_358 = ~out_wimask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_359 = ~out_romask_26; // @[RegisterRouter.scala:87:24]
wire _out_T_360 = ~out_womask_26; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_18 = {abstractDataMem_1, _out_prepend_T_18}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_361 = out_prepend_18; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_362 = _out_T_361; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_19 = _out_T_362; // @[RegisterRouter.scala:87:24]
wire out_rimask_27 = |_out_rimask_T_27; // @[RegisterRouter.scala:87:24]
wire out_wimask_27 = &_out_wimask_T_27; // @[RegisterRouter.scala:87:24]
wire out_romask_27 = |_out_romask_T_27; // @[RegisterRouter.scala:87:24]
wire out_womask_27 = &_out_womask_T_27; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_27 = out_rivalid_27 & out_rimask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_364 = out_f_rivalid_27; // @[RegisterRouter.scala:87:24]
assign out_f_roready_27 = out_roready_27 & out_romask_27; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_2 = out_f_roready_27; // @[RegisterRouter.scala:87:24]
wire _out_T_365 = out_f_roready_27; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_27 = out_wivalid_27 & out_wimask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_366 = out_f_wivalid_27; // @[RegisterRouter.scala:87:24]
assign out_f_woready_27 = out_woready_27 & out_womask_27; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_2 = out_f_woready_27; // @[RegisterRouter.scala:87:24]
wire _out_T_367 = out_f_woready_27; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_2 = out_f_woready_27 ? _out_T_363 : abstractDataMem_2; // @[RegisterRouter.scala:87:24]
wire _out_T_368 = ~out_rimask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_369 = ~out_wimask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_370 = ~out_romask_27; // @[RegisterRouter.scala:87:24]
wire _out_T_371 = ~out_womask_27; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_19 = {abstractDataMem_2, _out_prepend_T_19}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_372 = out_prepend_19; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_373 = _out_T_372; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_20 = _out_T_373; // @[RegisterRouter.scala:87:24]
wire out_rimask_28 = |_out_rimask_T_28; // @[RegisterRouter.scala:87:24]
wire out_wimask_28 = &_out_wimask_T_28; // @[RegisterRouter.scala:87:24]
wire out_romask_28 = |_out_romask_T_28; // @[RegisterRouter.scala:87:24]
wire out_womask_28 = &_out_womask_T_28; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_28 = out_rivalid_28 & out_rimask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_375 = out_f_rivalid_28; // @[RegisterRouter.scala:87:24]
assign out_f_roready_28 = out_roready_28 & out_romask_28; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_3 = out_f_roready_28; // @[RegisterRouter.scala:87:24]
wire _out_T_376 = out_f_roready_28; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_28 = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_377 = out_f_wivalid_28; // @[RegisterRouter.scala:87:24]
assign out_f_woready_28 = out_woready_28 & out_womask_28; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_3 = out_f_woready_28; // @[RegisterRouter.scala:87:24]
wire _out_T_378 = out_f_woready_28; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_3 = out_f_woready_28 ? _out_T_374 : abstractDataMem_3; // @[RegisterRouter.scala:87:24]
wire _out_T_379 = ~out_rimask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_380 = ~out_wimask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_381 = ~out_romask_28; // @[RegisterRouter.scala:87:24]
wire _out_T_382 = ~out_womask_28; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_20 = {abstractDataMem_3, _out_prepend_T_20}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_383 = out_prepend_20; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_384 = _out_T_383; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_4 = _out_T_384; // @[MuxLiteral.scala:49:48]
wire out_rimask_29 = |_out_rimask_T_29; // @[RegisterRouter.scala:87:24]
wire out_wimask_29 = &_out_wimask_T_29; // @[RegisterRouter.scala:87:24]
wire out_romask_29 = |_out_romask_T_29; // @[RegisterRouter.scala:87:24]
wire out_womask_29 = &_out_womask_T_29; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_29 = out_rivalid_29 & out_rimask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_386 = out_f_rivalid_29; // @[RegisterRouter.scala:87:24]
assign out_f_roready_29 = out_roready_29 & out_romask_29; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_60 = out_f_roready_29; // @[RegisterRouter.scala:87:24]
wire _out_T_387 = out_f_roready_29; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_29 = out_wivalid_29 & out_wimask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_388 = out_f_wivalid_29; // @[RegisterRouter.scala:87:24]
assign out_f_woready_29 = out_woready_29 & out_womask_29; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_60 = out_f_woready_29; // @[RegisterRouter.scala:87:24]
wire _out_T_389 = out_f_woready_29; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_60 = out_f_woready_29 ? _out_T_385 : programBufferMem_60; // @[RegisterRouter.scala:87:24]
wire _out_T_390 = ~out_rimask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_391 = ~out_wimask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_392 = ~out_romask_29; // @[RegisterRouter.scala:87:24]
wire _out_T_393 = ~out_womask_29; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_395 = _out_T_394; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_21 = _out_T_395; // @[RegisterRouter.scala:87:24]
wire out_rimask_30 = |_out_rimask_T_30; // @[RegisterRouter.scala:87:24]
wire out_wimask_30 = &_out_wimask_T_30; // @[RegisterRouter.scala:87:24]
wire out_romask_30 = |_out_romask_T_30; // @[RegisterRouter.scala:87:24]
wire out_womask_30 = &_out_womask_T_30; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_30 = out_rivalid_30 & out_rimask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_397 = out_f_rivalid_30; // @[RegisterRouter.scala:87:24]
assign out_f_roready_30 = out_roready_30 & out_romask_30; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_61 = out_f_roready_30; // @[RegisterRouter.scala:87:24]
wire _out_T_398 = out_f_roready_30; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_30 = out_wivalid_30 & out_wimask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_399 = out_f_wivalid_30; // @[RegisterRouter.scala:87:24]
assign out_f_woready_30 = out_woready_30 & out_womask_30; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_61 = out_f_woready_30; // @[RegisterRouter.scala:87:24]
wire _out_T_400 = out_f_woready_30; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_61 = out_f_woready_30 ? _out_T_396 : programBufferMem_61; // @[RegisterRouter.scala:87:24]
wire _out_T_401 = ~out_rimask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_402 = ~out_wimask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_403 = ~out_romask_30; // @[RegisterRouter.scala:87:24]
wire _out_T_404 = ~out_womask_30; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_21 = {programBufferMem_61, _out_prepend_T_21}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_405 = out_prepend_21; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_406 = _out_T_405; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_22 = _out_T_406; // @[RegisterRouter.scala:87:24]
wire out_rimask_31 = |_out_rimask_T_31; // @[RegisterRouter.scala:87:24]
wire out_wimask_31 = &_out_wimask_T_31; // @[RegisterRouter.scala:87:24]
wire out_romask_31 = |_out_romask_T_31; // @[RegisterRouter.scala:87:24]
wire out_womask_31 = &_out_womask_T_31; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_31 = out_rivalid_31 & out_rimask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_408 = out_f_rivalid_31; // @[RegisterRouter.scala:87:24]
assign out_f_roready_31 = out_roready_31 & out_romask_31; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_62 = out_f_roready_31; // @[RegisterRouter.scala:87:24]
wire _out_T_409 = out_f_roready_31; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_31 = out_wivalid_31 & out_wimask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_410 = out_f_wivalid_31; // @[RegisterRouter.scala:87:24]
assign out_f_woready_31 = out_woready_31 & out_womask_31; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_62 = out_f_woready_31; // @[RegisterRouter.scala:87:24]
wire _out_T_411 = out_f_woready_31; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_62 = out_f_woready_31 ? _out_T_407 : programBufferMem_62; // @[RegisterRouter.scala:87:24]
wire _out_T_412 = ~out_rimask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_413 = ~out_wimask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_414 = ~out_romask_31; // @[RegisterRouter.scala:87:24]
wire _out_T_415 = ~out_womask_31; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_22 = {programBufferMem_62, _out_prepend_T_22}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_416 = out_prepend_22; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_417 = _out_T_416; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_23 = _out_T_417; // @[RegisterRouter.scala:87:24]
wire out_rimask_32 = |_out_rimask_T_32; // @[RegisterRouter.scala:87:24]
wire out_wimask_32 = &_out_wimask_T_32; // @[RegisterRouter.scala:87:24]
wire out_romask_32 = |_out_romask_T_32; // @[RegisterRouter.scala:87:24]
wire out_womask_32 = &_out_womask_T_32; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_32 = out_rivalid_32 & out_rimask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_419 = out_f_rivalid_32; // @[RegisterRouter.scala:87:24]
assign out_f_roready_32 = out_roready_32 & out_romask_32; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_63 = out_f_roready_32; // @[RegisterRouter.scala:87:24]
wire _out_T_420 = out_f_roready_32; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_421 = out_f_wivalid_32; // @[RegisterRouter.scala:87:24]
assign out_f_woready_32 = out_woready_32 & out_womask_32; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_63 = out_f_woready_32; // @[RegisterRouter.scala:87:24]
wire _out_T_422 = out_f_woready_32; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_63 = out_f_woready_32 ? _out_T_418 : programBufferMem_63; // @[RegisterRouter.scala:87:24]
wire _out_T_423 = ~out_rimask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_424 = ~out_wimask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_425 = ~out_romask_32; // @[RegisterRouter.scala:87:24]
wire _out_T_426 = ~out_womask_32; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_23 = {programBufferMem_63, _out_prepend_T_23}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_427 = out_prepend_23; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_428 = _out_T_427; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_47 = _out_T_428; // @[MuxLiteral.scala:49:48]
wire out_rimask_33 = |_out_rimask_T_33; // @[RegisterRouter.scala:87:24]
wire out_wimask_33 = &_out_wimask_T_33; // @[RegisterRouter.scala:87:24]
wire out_romask_33 = |_out_romask_T_33; // @[RegisterRouter.scala:87:24]
wire out_womask_33 = &_out_womask_T_33; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_33 = out_rivalid_33 & out_rimask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_430 = out_f_rivalid_33; // @[RegisterRouter.scala:87:24]
assign out_f_roready_33 = out_roready_33 & out_romask_33; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_24 = out_f_roready_33; // @[RegisterRouter.scala:87:24]
wire _out_T_431 = out_f_roready_33; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_432 = out_f_wivalid_33; // @[RegisterRouter.scala:87:24]
assign out_f_woready_33 = out_woready_33 & out_womask_33; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_24 = out_f_woready_33; // @[RegisterRouter.scala:87:24]
wire _out_T_433 = out_f_woready_33; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_24 = out_f_woready_33 ? _out_T_429 : abstractDataMem_24; // @[RegisterRouter.scala:87:24]
wire _out_T_434 = ~out_rimask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_435 = ~out_wimask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_436 = ~out_romask_33; // @[RegisterRouter.scala:87:24]
wire _out_T_437 = ~out_womask_33; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_439 = _out_T_438; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_24 = _out_T_439; // @[RegisterRouter.scala:87:24]
wire out_rimask_34 = |_out_rimask_T_34; // @[RegisterRouter.scala:87:24]
wire out_wimask_34 = &_out_wimask_T_34; // @[RegisterRouter.scala:87:24]
wire out_romask_34 = |_out_romask_T_34; // @[RegisterRouter.scala:87:24]
wire out_womask_34 = &_out_womask_T_34; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_34 = out_rivalid_34 & out_rimask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_441 = out_f_rivalid_34; // @[RegisterRouter.scala:87:24]
assign out_f_roready_34 = out_roready_34 & out_romask_34; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_25 = out_f_roready_34; // @[RegisterRouter.scala:87:24]
wire _out_T_442 = out_f_roready_34; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_34 = out_wivalid_34 & out_wimask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_443 = out_f_wivalid_34; // @[RegisterRouter.scala:87:24]
assign out_f_woready_34 = out_woready_34 & out_womask_34; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_25 = out_f_woready_34; // @[RegisterRouter.scala:87:24]
wire _out_T_444 = out_f_woready_34; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_25 = out_f_woready_34 ? _out_T_440 : abstractDataMem_25; // @[RegisterRouter.scala:87:24]
wire _out_T_445 = ~out_rimask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_446 = ~out_wimask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_447 = ~out_romask_34; // @[RegisterRouter.scala:87:24]
wire _out_T_448 = ~out_womask_34; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_24 = {abstractDataMem_25, _out_prepend_T_24}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_449 = out_prepend_24; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_450 = _out_T_449; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_25 = _out_T_450; // @[RegisterRouter.scala:87:24]
wire out_rimask_35 = |_out_rimask_T_35; // @[RegisterRouter.scala:87:24]
wire out_wimask_35 = &_out_wimask_T_35; // @[RegisterRouter.scala:87:24]
wire out_romask_35 = |_out_romask_T_35; // @[RegisterRouter.scala:87:24]
wire out_womask_35 = &_out_womask_T_35; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_35 = out_rivalid_35 & out_rimask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_452 = out_f_rivalid_35; // @[RegisterRouter.scala:87:24]
assign out_f_roready_35 = out_roready_35 & out_romask_35; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_26 = out_f_roready_35; // @[RegisterRouter.scala:87:24]
wire _out_T_453 = out_f_roready_35; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_35 = out_wivalid_35 & out_wimask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_454 = out_f_wivalid_35; // @[RegisterRouter.scala:87:24]
assign out_f_woready_35 = out_woready_35 & out_womask_35; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_26 = out_f_woready_35; // @[RegisterRouter.scala:87:24]
wire _out_T_455 = out_f_woready_35; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_26 = out_f_woready_35 ? _out_T_451 : abstractDataMem_26; // @[RegisterRouter.scala:87:24]
wire _out_T_456 = ~out_rimask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_457 = ~out_wimask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_458 = ~out_romask_35; // @[RegisterRouter.scala:87:24]
wire _out_T_459 = ~out_womask_35; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_25 = {abstractDataMem_26, _out_prepend_T_25}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_460 = out_prepend_25; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_461 = _out_T_460; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_26 = _out_T_461; // @[RegisterRouter.scala:87:24]
wire out_rimask_36 = |_out_rimask_T_36; // @[RegisterRouter.scala:87:24]
wire out_wimask_36 = &_out_wimask_T_36; // @[RegisterRouter.scala:87:24]
wire out_romask_36 = |_out_romask_T_36; // @[RegisterRouter.scala:87:24]
wire out_womask_36 = &_out_womask_T_36; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_36 = out_rivalid_36 & out_rimask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_463 = out_f_rivalid_36; // @[RegisterRouter.scala:87:24]
assign out_f_roready_36 = out_roready_36 & out_romask_36; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_27 = out_f_roready_36; // @[RegisterRouter.scala:87:24]
wire _out_T_464 = out_f_roready_36; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_36 = out_wivalid_36 & out_wimask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_465 = out_f_wivalid_36; // @[RegisterRouter.scala:87:24]
assign out_f_woready_36 = out_woready_36 & out_womask_36; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_27 = out_f_woready_36; // @[RegisterRouter.scala:87:24]
wire _out_T_466 = out_f_woready_36; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_27 = out_f_woready_36 ? _out_T_462 : abstractDataMem_27; // @[RegisterRouter.scala:87:24]
wire _out_T_467 = ~out_rimask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_468 = ~out_wimask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_469 = ~out_romask_36; // @[RegisterRouter.scala:87:24]
wire _out_T_470 = ~out_womask_36; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_26 = {abstractDataMem_27, _out_prepend_T_26}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_471 = out_prepend_26; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_472 = _out_T_471; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_10 = _out_T_472; // @[MuxLiteral.scala:49:48]
wire out_rimask_37 = _out_rimask_T_37; // @[RegisterRouter.scala:87:24]
wire out_wimask_37 = _out_wimask_T_37; // @[RegisterRouter.scala:87:24]
wire out_romask_37 = _out_romask_T_37; // @[RegisterRouter.scala:87:24]
wire out_womask_37 = _out_womask_T_37; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_37 = out_rivalid_37 & out_rimask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_474 = out_f_rivalid_37; // @[RegisterRouter.scala:87:24]
wire out_f_roready_37 = out_roready_37 & out_romask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_475 = out_f_roready_37; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_37 = out_wivalid_37 & out_wimask_37; // @[RegisterRouter.scala:87:24]
wire out_f_woready_37 = out_woready_37 & out_womask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_476 = ~out_rimask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_477 = ~out_wimask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_478 = ~out_romask_37; // @[RegisterRouter.scala:87:24]
wire _out_T_479 = ~out_womask_37; // @[RegisterRouter.scala:87:24]
wire out_rimask_38 = _out_rimask_T_38; // @[RegisterRouter.scala:87:24]
wire out_wimask_38 = _out_wimask_T_38; // @[RegisterRouter.scala:87:24]
wire out_romask_38 = _out_romask_T_38; // @[RegisterRouter.scala:87:24]
wire out_womask_38 = _out_womask_T_38; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_38 = out_rivalid_38 & out_rimask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_483 = out_f_rivalid_38; // @[RegisterRouter.scala:87:24]
wire out_f_roready_38 = out_roready_38 & out_romask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_484 = out_f_roready_38; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_38 = out_wivalid_38 & out_wimask_38; // @[RegisterRouter.scala:87:24]
wire out_f_woready_38 = out_woready_38 & out_womask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_485 = ~out_rimask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_486 = ~out_wimask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_487 = ~out_romask_38; // @[RegisterRouter.scala:87:24]
wire _out_T_488 = ~out_womask_38; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_39 = out_frontMask[2]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_39 = out_frontMask[2]; // @[RegisterRouter.scala:87:24]
wire out_rimask_39 = _out_rimask_T_39; // @[RegisterRouter.scala:87:24]
wire out_wimask_39 = _out_wimask_T_39; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_39 = out_backMask[2]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_39 = out_backMask[2]; // @[RegisterRouter.scala:87:24]
wire out_romask_39 = _out_romask_T_39; // @[RegisterRouter.scala:87:24]
wire out_womask_39 = _out_womask_T_39; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_39 = out_rivalid_39 & out_rimask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_492 = out_f_rivalid_39; // @[RegisterRouter.scala:87:24]
wire out_f_roready_39 = out_roready_39 & out_romask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_493 = out_f_roready_39; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_39 = out_wivalid_39 & out_wimask_39; // @[RegisterRouter.scala:87:24]
wire out_f_woready_39 = out_woready_39 & out_womask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_491 = out_front_bits_data[2]; // @[RegisterRouter.scala:87:24]
wire _out_T_494 = ~out_rimask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_495 = ~out_wimask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_496 = ~out_romask_39; // @[RegisterRouter.scala:87:24]
wire _out_T_497 = ~out_womask_39; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_40 = out_frontMask[3]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_40 = out_frontMask[3]; // @[RegisterRouter.scala:87:24]
wire out_rimask_40 = _out_rimask_T_40; // @[RegisterRouter.scala:87:24]
wire out_wimask_40 = _out_wimask_T_40; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_40 = out_backMask[3]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_40 = out_backMask[3]; // @[RegisterRouter.scala:87:24]
wire out_romask_40 = _out_romask_T_40; // @[RegisterRouter.scala:87:24]
wire out_womask_40 = _out_womask_T_40; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_40 = out_rivalid_40 & out_rimask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_501 = out_f_rivalid_40; // @[RegisterRouter.scala:87:24]
wire out_f_roready_40 = out_roready_40 & out_romask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_502 = out_f_roready_40; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_40 = out_wivalid_40 & out_wimask_40; // @[RegisterRouter.scala:87:24]
wire out_f_woready_40 = out_woready_40 & out_womask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_500 = out_front_bits_data[3]; // @[RegisterRouter.scala:87:24]
wire _out_T_503 = ~out_rimask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_504 = ~out_wimask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_505 = ~out_romask_40; // @[RegisterRouter.scala:87:24]
wire _out_T_506 = ~out_womask_40; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_41 = out_frontMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_41 = out_frontMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_87 = out_frontMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_87 = out_frontMask[4]; // @[RegisterRouter.scala:87:24]
wire out_rimask_41 = _out_rimask_T_41; // @[RegisterRouter.scala:87:24]
wire out_wimask_41 = _out_wimask_T_41; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_41 = out_backMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_41 = out_backMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_87 = out_backMask[4]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_87 = out_backMask[4]; // @[RegisterRouter.scala:87:24]
wire out_romask_41 = _out_romask_T_41; // @[RegisterRouter.scala:87:24]
wire out_womask_41 = _out_womask_T_41; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_41 = out_rivalid_41 & out_rimask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_510 = out_f_rivalid_41; // @[RegisterRouter.scala:87:24]
wire out_f_roready_41 = out_roready_41 & out_romask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_511 = out_f_roready_41; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_41 = out_wivalid_41 & out_wimask_41; // @[RegisterRouter.scala:87:24]
wire out_f_woready_41 = out_woready_41 & out_womask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_509 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24]
wire _out_T_999 = out_front_bits_data[4]; // @[RegisterRouter.scala:87:24]
wire _out_T_512 = ~out_rimask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_513 = ~out_wimask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_514 = ~out_romask_41; // @[RegisterRouter.scala:87:24]
wire _out_T_515 = ~out_womask_41; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_rimask_T_42 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_wimask_T_42 = out_frontMask[11:5]; // @[RegisterRouter.scala:87:24]
wire out_rimask_42 = |_out_rimask_T_42; // @[RegisterRouter.scala:87:24]
wire out_wimask_42 = &_out_wimask_T_42; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_romask_T_42 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_womask_T_42 = out_backMask[11:5]; // @[RegisterRouter.scala:87:24]
wire out_romask_42 = |_out_romask_T_42; // @[RegisterRouter.scala:87:24]
wire out_womask_42 = &_out_womask_T_42; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_42 = out_rivalid_42 & out_rimask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_519 = out_f_rivalid_42; // @[RegisterRouter.scala:87:24]
wire out_f_roready_42 = out_roready_42 & out_romask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_520 = out_f_roready_42; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_42 = out_wivalid_42 & out_wimask_42; // @[RegisterRouter.scala:87:24]
wire out_f_woready_42 = out_woready_42 & out_womask_42; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_518 = out_front_bits_data[11:5]; // @[RegisterRouter.scala:87:24]
wire _out_T_521 = ~out_rimask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_522 = ~out_wimask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_523 = ~out_romask_42; // @[RegisterRouter.scala:87:24]
wire _out_T_524 = ~out_womask_42; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_43 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_43 = out_frontMask[14:12]; // @[RegisterRouter.scala:87:24]
wire out_rimask_43 = |_out_rimask_T_43; // @[RegisterRouter.scala:87:24]
wire out_wimask_43 = &_out_wimask_T_43; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_43 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_43 = out_backMask[14:12]; // @[RegisterRouter.scala:87:24]
wire out_romask_43 = |_out_romask_T_43; // @[RegisterRouter.scala:87:24]
wire out_womask_43 = &_out_womask_T_43; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_43 = out_rivalid_43 & out_rimask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_528 = out_f_rivalid_43; // @[RegisterRouter.scala:87:24]
wire out_f_roready_43 = out_roready_43 & out_romask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_529 = out_f_roready_43; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_43 = out_wivalid_43 & out_wimask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_530 = out_f_wivalid_43; // @[RegisterRouter.scala:87:24]
assign out_f_woready_43 = out_woready_43 & out_womask_43; // @[RegisterRouter.scala:87:24]
assign sberrorWrEn = out_f_woready_43; // @[RegisterRouter.scala:87:24]
wire _out_T_531 = out_f_woready_43; // @[RegisterRouter.scala:87:24]
assign _out_T_527 = out_front_bits_data[14:12]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sberror = _out_T_527; // @[RegisterRouter.scala:87:24]
wire _out_T_532 = ~out_rimask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_533 = ~out_wimask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_534 = ~out_romask_43; // @[RegisterRouter.scala:87:24]
wire _out_T_535 = ~out_womask_43; // @[RegisterRouter.scala:87:24]
wire [14:0] out_prepend_32 = {SBCSRdData_sberror, 12'h40F}; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_T_536 = out_prepend_32; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_T_537 = _out_T_536; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_prepend_T_33 = _out_T_537; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_44 = out_frontMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_44 = out_frontMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_98 = out_frontMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_98 = out_frontMask[15]; // @[RegisterRouter.scala:87:24]
wire out_rimask_44 = _out_rimask_T_44; // @[RegisterRouter.scala:87:24]
wire out_wimask_44 = _out_wimask_T_44; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_44 = out_backMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_44 = out_backMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_98 = out_backMask[15]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_98 = out_backMask[15]; // @[RegisterRouter.scala:87:24]
wire out_romask_44 = _out_romask_T_44; // @[RegisterRouter.scala:87:24]
wire out_womask_44 = _out_womask_T_44; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_44 = out_rivalid_44 & out_rimask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_539 = out_f_rivalid_44; // @[RegisterRouter.scala:87:24]
wire out_f_roready_44 = out_roready_44 & out_romask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_540 = out_f_roready_44; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_44 = out_wivalid_44 & out_wimask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_541 = out_f_wivalid_44; // @[RegisterRouter.scala:87:24]
assign out_f_woready_44 = out_woready_44 & out_womask_44; // @[RegisterRouter.scala:87:24]
assign sbreadondataWrEn = out_f_woready_44; // @[RegisterRouter.scala:87:24]
wire _out_T_542 = out_f_woready_44; // @[RegisterRouter.scala:87:24]
assign _out_T_538 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24]
wire _out_T_1098 = out_front_bits_data[15]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbreadondata = _out_T_538; // @[RegisterRouter.scala:87:24]
wire _out_T_543 = ~out_rimask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_544 = ~out_wimask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_545 = ~out_romask_44; // @[RegisterRouter.scala:87:24]
wire _out_T_546 = ~out_womask_44; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_33 = {SBCSRdData_sbreadondata, _out_prepend_T_33}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_547 = out_prepend_33; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_548 = _out_T_547; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_34 = _out_T_548; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_45 = out_frontMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_45 = out_frontMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_99 = out_frontMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_99 = out_frontMask[16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_45 = _out_rimask_T_45; // @[RegisterRouter.scala:87:24]
wire out_wimask_45 = _out_wimask_T_45; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_45 = out_backMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_45 = out_backMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_99 = out_backMask[16]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_99 = out_backMask[16]; // @[RegisterRouter.scala:87:24]
wire out_romask_45 = _out_romask_T_45; // @[RegisterRouter.scala:87:24]
wire out_womask_45 = _out_womask_T_45; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_45 = out_rivalid_45 & out_rimask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_550 = out_f_rivalid_45; // @[RegisterRouter.scala:87:24]
wire out_f_roready_45 = out_roready_45 & out_romask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_551 = out_f_roready_45; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_45 = out_wivalid_45 & out_wimask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_552 = out_f_wivalid_45; // @[RegisterRouter.scala:87:24]
assign out_f_woready_45 = out_woready_45 & out_womask_45; // @[RegisterRouter.scala:87:24]
assign sbautoincrementWrEn = out_f_woready_45; // @[RegisterRouter.scala:87:24]
wire _out_T_553 = out_f_woready_45; // @[RegisterRouter.scala:87:24]
assign _out_T_549 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24]
wire _out_T_1107 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbautoincrement = _out_T_549; // @[RegisterRouter.scala:87:24]
wire _out_T_554 = ~out_rimask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_555 = ~out_wimask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_556 = ~out_romask_45; // @[RegisterRouter.scala:87:24]
wire _out_T_557 = ~out_womask_45; // @[RegisterRouter.scala:87:24]
wire [16:0] out_prepend_34 = {SBCSRdData_sbautoincrement, _out_prepend_T_34}; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_558 = out_prepend_34; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_559 = _out_T_558; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_prepend_T_35 = _out_T_559; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_46 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_46 = out_frontMask[19:17]; // @[RegisterRouter.scala:87:24]
wire out_rimask_46 = |_out_rimask_T_46; // @[RegisterRouter.scala:87:24]
wire out_wimask_46 = &_out_wimask_T_46; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_46 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_46 = out_backMask[19:17]; // @[RegisterRouter.scala:87:24]
wire out_romask_46 = |_out_romask_T_46; // @[RegisterRouter.scala:87:24]
wire out_womask_46 = &_out_womask_T_46; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_46 = out_rivalid_46 & out_rimask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_561 = out_f_rivalid_46; // @[RegisterRouter.scala:87:24]
wire out_f_roready_46 = out_roready_46 & out_romask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_562 = out_f_roready_46; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_46 = out_wivalid_46 & out_wimask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_563 = out_f_wivalid_46; // @[RegisterRouter.scala:87:24]
assign out_f_woready_46 = out_woready_46 & out_womask_46; // @[RegisterRouter.scala:87:24]
assign sbaccessWrEn = out_f_woready_46; // @[RegisterRouter.scala:87:24]
wire _out_T_564 = out_f_woready_46; // @[RegisterRouter.scala:87:24]
assign _out_T_560 = out_front_bits_data[19:17]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbaccess = _out_T_560; // @[RegisterRouter.scala:87:24]
wire _out_T_565 = ~out_rimask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_566 = ~out_wimask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_567 = ~out_romask_46; // @[RegisterRouter.scala:87:24]
wire _out_T_568 = ~out_womask_46; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_35 = {SBCSRdData_sbaccess, _out_prepend_T_35}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_569 = out_prepend_35; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_570 = _out_T_569; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_prepend_T_36 = _out_T_570; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_47 = out_frontMask[20]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_47 = out_frontMask[20]; // @[RegisterRouter.scala:87:24]
wire out_rimask_47 = _out_rimask_T_47; // @[RegisterRouter.scala:87:24]
wire out_wimask_47 = _out_wimask_T_47; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_47 = out_backMask[20]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_47 = out_backMask[20]; // @[RegisterRouter.scala:87:24]
wire out_romask_47 = _out_romask_T_47; // @[RegisterRouter.scala:87:24]
wire out_womask_47 = _out_womask_T_47; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_47 = out_rivalid_47 & out_rimask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_572 = out_f_rivalid_47; // @[RegisterRouter.scala:87:24]
wire out_f_roready_47 = out_roready_47 & out_romask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_573 = out_f_roready_47; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_47 = out_wivalid_47 & out_wimask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_574 = out_f_wivalid_47; // @[RegisterRouter.scala:87:24]
assign out_f_woready_47 = out_woready_47 & out_womask_47; // @[RegisterRouter.scala:87:24]
assign sbreadonaddrWrEn = out_f_woready_47; // @[RegisterRouter.scala:87:24]
wire _out_T_575 = out_f_woready_47; // @[RegisterRouter.scala:87:24]
assign _out_T_571 = out_front_bits_data[20]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbreadonaddr = _out_T_571; // @[RegisterRouter.scala:87:24]
wire _out_T_576 = ~out_rimask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_577 = ~out_wimask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_578 = ~out_romask_47; // @[RegisterRouter.scala:87:24]
wire _out_T_579 = ~out_womask_47; // @[RegisterRouter.scala:87:24]
wire [20:0] out_prepend_36 = {SBCSRdData_sbreadonaddr, _out_prepend_T_36}; // @[RegisterRouter.scala:87:24]
wire [20:0] _out_T_580 = out_prepend_36; // @[RegisterRouter.scala:87:24]
wire [20:0] _out_T_581 = _out_T_580; // @[RegisterRouter.scala:87:24]
wire [20:0] _out_prepend_T_37 = _out_T_581; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_48 = out_frontMask[21]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_48 = out_frontMask[21]; // @[RegisterRouter.scala:87:24]
wire out_rimask_48 = _out_rimask_T_48; // @[RegisterRouter.scala:87:24]
wire out_wimask_48 = _out_wimask_T_48; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_48 = out_backMask[21]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_48 = out_backMask[21]; // @[RegisterRouter.scala:87:24]
wire out_romask_48 = _out_romask_T_48; // @[RegisterRouter.scala:87:24]
wire out_womask_48 = _out_womask_T_48; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_48 = out_rivalid_48 & out_rimask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_583 = out_f_rivalid_48; // @[RegisterRouter.scala:87:24]
wire out_f_roready_48 = out_roready_48 & out_romask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_584 = out_f_roready_48; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_48 = out_wivalid_48 & out_wimask_48; // @[RegisterRouter.scala:87:24]
wire out_f_woready_48 = out_woready_48 & out_womask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_582 = out_front_bits_data[21]; // @[RegisterRouter.scala:87:24]
wire _out_T_585 = ~out_rimask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_586 = ~out_wimask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_587 = ~out_romask_48; // @[RegisterRouter.scala:87:24]
wire _out_T_588 = ~out_womask_48; // @[RegisterRouter.scala:87:24]
wire [21:0] out_prepend_37 = {SBCSRdData_sbbusy, _out_prepend_T_37}; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_T_589 = out_prepend_37; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_T_590 = _out_T_589; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_prepend_T_38 = _out_T_590; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_49 = out_frontMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_49 = out_frontMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_104 = out_frontMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_104 = out_frontMask[22]; // @[RegisterRouter.scala:87:24]
wire out_rimask_49 = _out_rimask_T_49; // @[RegisterRouter.scala:87:24]
wire out_wimask_49 = _out_wimask_T_49; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_49 = out_backMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_49 = out_backMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_104 = out_backMask[22]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_104 = out_backMask[22]; // @[RegisterRouter.scala:87:24]
wire out_romask_49 = _out_romask_T_49; // @[RegisterRouter.scala:87:24]
wire out_womask_49 = _out_womask_T_49; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_49 = out_rivalid_49 & out_rimask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_592 = out_f_rivalid_49; // @[RegisterRouter.scala:87:24]
wire out_f_roready_49 = out_roready_49 & out_romask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_593 = out_f_roready_49; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_49 = out_wivalid_49 & out_wimask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_594 = out_f_wivalid_49; // @[RegisterRouter.scala:87:24]
assign out_f_woready_49 = out_woready_49 & out_womask_49; // @[RegisterRouter.scala:87:24]
assign sbbusyerrorWrEn = out_f_woready_49; // @[RegisterRouter.scala:87:24]
wire _out_T_595 = out_f_woready_49; // @[RegisterRouter.scala:87:24]
assign _out_T_591 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24]
wire _out_T_1152 = out_front_bits_data[22]; // @[RegisterRouter.scala:87:24]
assign SBCSWrData_sbbusyerror = _out_T_591; // @[RegisterRouter.scala:87:24]
wire _out_T_596 = ~out_rimask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_597 = ~out_wimask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_598 = ~out_romask_49; // @[RegisterRouter.scala:87:24]
wire _out_T_599 = ~out_womask_49; // @[RegisterRouter.scala:87:24]
wire [22:0] out_prepend_38 = {SBCSRdData_sbbusyerror, _out_prepend_T_38}; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_600 = out_prepend_38; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_601 = _out_T_600; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_prepend_T_39 = _out_T_601; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_rimask_T_50 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_wimask_T_50 = out_frontMask[28:23]; // @[RegisterRouter.scala:87:24]
wire out_rimask_50 = |_out_rimask_T_50; // @[RegisterRouter.scala:87:24]
wire out_wimask_50 = &_out_wimask_T_50; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_romask_T_50 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_womask_T_50 = out_backMask[28:23]; // @[RegisterRouter.scala:87:24]
wire out_romask_50 = |_out_romask_T_50; // @[RegisterRouter.scala:87:24]
wire out_womask_50 = &_out_womask_T_50; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_50 = out_rivalid_50 & out_rimask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_603 = out_f_rivalid_50; // @[RegisterRouter.scala:87:24]
wire out_f_roready_50 = out_roready_50 & out_romask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_604 = out_f_roready_50; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_50 = out_wivalid_50 & out_wimask_50; // @[RegisterRouter.scala:87:24]
wire out_f_woready_50 = out_woready_50 & out_womask_50; // @[RegisterRouter.scala:87:24]
wire [5:0] _out_T_602 = out_front_bits_data[28:23]; // @[RegisterRouter.scala:87:24]
wire _out_T_605 = ~out_rimask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_606 = ~out_wimask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_607 = ~out_romask_50; // @[RegisterRouter.scala:87:24]
wire _out_T_608 = ~out_womask_50; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_39 = {1'h0, _out_prepend_T_39}; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_609 = {5'h0, out_prepend_39}; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_610 = _out_T_609; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_prepend_T_40 = _out_T_610; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_51 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_51 = out_frontMask[31:29]; // @[RegisterRouter.scala:87:24]
wire out_rimask_51 = |_out_rimask_T_51; // @[RegisterRouter.scala:87:24]
wire out_wimask_51 = &_out_wimask_T_51; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_51 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_51 = out_backMask[31:29]; // @[RegisterRouter.scala:87:24]
wire out_romask_51 = |_out_romask_T_51; // @[RegisterRouter.scala:87:24]
wire out_womask_51 = &_out_womask_T_51; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_51 = out_rivalid_51 & out_rimask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_612 = out_f_rivalid_51; // @[RegisterRouter.scala:87:24]
wire out_f_roready_51 = out_roready_51 & out_romask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_613 = out_f_roready_51; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_51 = out_wivalid_51 & out_wimask_51; // @[RegisterRouter.scala:87:24]
wire out_f_woready_51 = out_woready_51 & out_womask_51; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_611 = out_front_bits_data[31:29]; // @[RegisterRouter.scala:87:24]
wire _out_T_614 = ~out_rimask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_615 = ~out_wimask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_616 = ~out_romask_51; // @[RegisterRouter.scala:87:24]
wire _out_T_617 = ~out_womask_51; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_40 = {3'h1, _out_prepend_T_40}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_618 = out_prepend_40; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_619 = _out_T_618; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_56 = _out_T_619; // @[MuxLiteral.scala:49:48]
wire out_rimask_52 = |_out_rimask_T_52; // @[RegisterRouter.scala:87:24]
wire out_wimask_52 = &_out_wimask_T_52; // @[RegisterRouter.scala:87:24]
wire out_romask_52 = |_out_romask_T_52; // @[RegisterRouter.scala:87:24]
wire out_womask_52 = &_out_womask_T_52; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_52 = out_rivalid_52 & out_rimask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_621 = out_f_rivalid_52; // @[RegisterRouter.scala:87:24]
assign out_f_roready_52 = out_roready_52 & out_romask_52; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_40 = out_f_roready_52; // @[RegisterRouter.scala:87:24]
wire _out_T_622 = out_f_roready_52; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_52 = out_wivalid_52 & out_wimask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_623 = out_f_wivalid_52; // @[RegisterRouter.scala:87:24]
assign out_f_woready_52 = out_woready_52 & out_womask_52; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_40 = out_f_woready_52; // @[RegisterRouter.scala:87:24]
wire _out_T_624 = out_f_woready_52; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_40 = out_f_woready_52 ? _out_T_620 : programBufferMem_40; // @[RegisterRouter.scala:87:24]
wire _out_T_625 = ~out_rimask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_626 = ~out_wimask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_627 = ~out_romask_52; // @[RegisterRouter.scala:87:24]
wire _out_T_628 = ~out_womask_52; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_630 = _out_T_629; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_41 = _out_T_630; // @[RegisterRouter.scala:87:24]
wire out_rimask_53 = |_out_rimask_T_53; // @[RegisterRouter.scala:87:24]
wire out_wimask_53 = &_out_wimask_T_53; // @[RegisterRouter.scala:87:24]
wire out_romask_53 = |_out_romask_T_53; // @[RegisterRouter.scala:87:24]
wire out_womask_53 = &_out_womask_T_53; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_53 = out_rivalid_53 & out_rimask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_632 = out_f_rivalid_53; // @[RegisterRouter.scala:87:24]
assign out_f_roready_53 = out_roready_53 & out_romask_53; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_41 = out_f_roready_53; // @[RegisterRouter.scala:87:24]
wire _out_T_633 = out_f_roready_53; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_53 = out_wivalid_53 & out_wimask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_634 = out_f_wivalid_53; // @[RegisterRouter.scala:87:24]
assign out_f_woready_53 = out_woready_53 & out_womask_53; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_41 = out_f_woready_53; // @[RegisterRouter.scala:87:24]
wire _out_T_635 = out_f_woready_53; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_41 = out_f_woready_53 ? _out_T_631 : programBufferMem_41; // @[RegisterRouter.scala:87:24]
wire _out_T_636 = ~out_rimask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_637 = ~out_wimask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_638 = ~out_romask_53; // @[RegisterRouter.scala:87:24]
wire _out_T_639 = ~out_womask_53; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_41 = {programBufferMem_41, _out_prepend_T_41}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_640 = out_prepend_41; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_641 = _out_T_640; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_42 = _out_T_641; // @[RegisterRouter.scala:87:24]
wire out_rimask_54 = |_out_rimask_T_54; // @[RegisterRouter.scala:87:24]
wire out_wimask_54 = &_out_wimask_T_54; // @[RegisterRouter.scala:87:24]
wire out_romask_54 = |_out_romask_T_54; // @[RegisterRouter.scala:87:24]
wire out_womask_54 = &_out_womask_T_54; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_54 = out_rivalid_54 & out_rimask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_643 = out_f_rivalid_54; // @[RegisterRouter.scala:87:24]
assign out_f_roready_54 = out_roready_54 & out_romask_54; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_42 = out_f_roready_54; // @[RegisterRouter.scala:87:24]
wire _out_T_644 = out_f_roready_54; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_54 = out_wivalid_54 & out_wimask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_645 = out_f_wivalid_54; // @[RegisterRouter.scala:87:24]
assign out_f_woready_54 = out_woready_54 & out_womask_54; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_42 = out_f_woready_54; // @[RegisterRouter.scala:87:24]
wire _out_T_646 = out_f_woready_54; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_42 = out_f_woready_54 ? _out_T_642 : programBufferMem_42; // @[RegisterRouter.scala:87:24]
wire _out_T_647 = ~out_rimask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_648 = ~out_wimask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_649 = ~out_romask_54; // @[RegisterRouter.scala:87:24]
wire _out_T_650 = ~out_womask_54; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_42 = {programBufferMem_42, _out_prepend_T_42}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_651 = out_prepend_42; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_652 = _out_T_651; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_43 = _out_T_652; // @[RegisterRouter.scala:87:24]
wire out_rimask_55 = |_out_rimask_T_55; // @[RegisterRouter.scala:87:24]
wire out_wimask_55 = &_out_wimask_T_55; // @[RegisterRouter.scala:87:24]
wire out_romask_55 = |_out_romask_T_55; // @[RegisterRouter.scala:87:24]
wire out_womask_55 = &_out_womask_T_55; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_55 = out_rivalid_55 & out_rimask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_654 = out_f_rivalid_55; // @[RegisterRouter.scala:87:24]
assign out_f_roready_55 = out_roready_55 & out_romask_55; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_43 = out_f_roready_55; // @[RegisterRouter.scala:87:24]
wire _out_T_655 = out_f_roready_55; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_55 = out_wivalid_55 & out_wimask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_656 = out_f_wivalid_55; // @[RegisterRouter.scala:87:24]
assign out_f_woready_55 = out_woready_55 & out_womask_55; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_43 = out_f_woready_55; // @[RegisterRouter.scala:87:24]
wire _out_T_657 = out_f_woready_55; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_43 = out_f_woready_55 ? _out_T_653 : programBufferMem_43; // @[RegisterRouter.scala:87:24]
wire _out_T_658 = ~out_rimask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_659 = ~out_wimask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_660 = ~out_romask_55; // @[RegisterRouter.scala:87:24]
wire _out_T_661 = ~out_womask_55; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_43 = {programBufferMem_43, _out_prepend_T_43}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_662 = out_prepend_43; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_663 = _out_T_662; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_42 = _out_T_663; // @[MuxLiteral.scala:49:48]
wire out_rimask_56 = |_out_rimask_T_56; // @[RegisterRouter.scala:87:24]
wire out_wimask_56 = &_out_wimask_T_56; // @[RegisterRouter.scala:87:24]
wire out_romask_56 = |_out_romask_T_56; // @[RegisterRouter.scala:87:24]
wire out_womask_56 = &_out_womask_T_56; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_56 = out_rivalid_56 & out_rimask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_665 = out_f_rivalid_56; // @[RegisterRouter.scala:87:24]
wire out_f_roready_56 = out_roready_56 & out_romask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_666 = out_f_roready_56; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_56 = out_wivalid_56 & out_wimask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_667 = out_f_wivalid_56; // @[RegisterRouter.scala:87:24]
assign out_f_woready_56 = out_woready_56 & out_womask_56; // @[RegisterRouter.scala:87:24]
assign autoexecdataWrEnMaybe = out_f_woready_56; // @[RegisterRouter.scala:87:24]
wire _out_T_668 = out_f_woready_56; // @[RegisterRouter.scala:87:24]
assign ABSTRACTAUTOWrData_autoexecdata = {4'h0, _out_T_664}; // @[RegisterRouter.scala:87:24]
wire _out_T_669 = ~out_rimask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_670 = ~out_wimask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_671 = ~out_romask_56; // @[RegisterRouter.scala:87:24]
wire _out_T_672 = ~out_womask_56; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_674 = _out_T_673[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_44 = _out_T_674; // @[RegisterRouter.scala:87:24]
wire out_rimask_57 = |_out_rimask_T_57; // @[RegisterRouter.scala:87:24]
wire out_wimask_57 = &_out_wimask_T_57; // @[RegisterRouter.scala:87:24]
wire out_romask_57 = |_out_romask_T_57; // @[RegisterRouter.scala:87:24]
wire out_womask_57 = &_out_womask_T_57; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_57 = out_rivalid_57 & out_rimask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_676 = out_f_rivalid_57; // @[RegisterRouter.scala:87:24]
wire out_f_roready_57 = out_roready_57 & out_romask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_677 = out_f_roready_57; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_57 = out_wivalid_57 & out_wimask_57; // @[RegisterRouter.scala:87:24]
wire out_f_woready_57 = out_woready_57 & out_womask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_678 = ~out_rimask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_679 = ~out_wimask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_680 = ~out_romask_57; // @[RegisterRouter.scala:87:24]
wire _out_T_681 = ~out_womask_57; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend_44 = {1'h0, _out_prepend_T_44}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_682 = {7'h0, out_prepend_44}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_683 = _out_T_682; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_45 = _out_T_683; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_rimask_T_58 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_wimask_T_58 = out_frontMask[31:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_58 = |_out_rimask_T_58; // @[RegisterRouter.scala:87:24]
wire out_wimask_58 = &_out_wimask_T_58; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_romask_T_58 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_womask_T_58 = out_backMask[31:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_58 = |_out_romask_T_58; // @[RegisterRouter.scala:87:24]
wire out_womask_58 = &_out_womask_T_58; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_58 = out_rivalid_58 & out_rimask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_685 = out_f_rivalid_58; // @[RegisterRouter.scala:87:24]
wire out_f_roready_58 = out_roready_58 & out_romask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_686 = out_f_roready_58; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_58 = out_wivalid_58 & out_wimask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_687 = out_f_wivalid_58; // @[RegisterRouter.scala:87:24]
assign out_f_woready_58 = out_woready_58 & out_womask_58; // @[RegisterRouter.scala:87:24]
assign autoexecprogbufWrEnMaybe = out_f_woready_58; // @[RegisterRouter.scala:87:24]
wire _out_T_688 = out_f_woready_58; // @[RegisterRouter.scala:87:24]
assign _out_T_684 = out_front_bits_data[31:16]; // @[RegisterRouter.scala:87:24]
assign ABSTRACTAUTOWrData_autoexecprogbuf = _out_T_684; // @[RegisterRouter.scala:87:24]
wire _out_T_689 = ~out_rimask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_690 = ~out_wimask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_691 = ~out_romask_58; // @[RegisterRouter.scala:87:24]
wire _out_T_692 = ~out_womask_58; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_45 = {ABSTRACTAUTORdData_autoexecprogbuf, _out_prepend_T_45}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_693 = out_prepend_45; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_694 = _out_T_693; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_24 = _out_T_694; // @[MuxLiteral.scala:49:48]
wire out_rimask_59 = |_out_rimask_T_59; // @[RegisterRouter.scala:87:24]
wire out_wimask_59 = &_out_wimask_T_59; // @[RegisterRouter.scala:87:24]
wire out_romask_59 = |_out_romask_T_59; // @[RegisterRouter.scala:87:24]
wire out_womask_59 = &_out_womask_T_59; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_59 = out_rivalid_59 & out_rimask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_696 = out_f_rivalid_59; // @[RegisterRouter.scala:87:24]
assign out_f_roready_59 = out_roready_59 & out_romask_59; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_20 = out_f_roready_59; // @[RegisterRouter.scala:87:24]
wire _out_T_697 = out_f_roready_59; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_59 = out_wivalid_59 & out_wimask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_698 = out_f_wivalid_59; // @[RegisterRouter.scala:87:24]
assign out_f_woready_59 = out_woready_59 & out_womask_59; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_20 = out_f_woready_59; // @[RegisterRouter.scala:87:24]
wire _out_T_699 = out_f_woready_59; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_20 = out_f_woready_59 ? _out_T_695 : programBufferMem_20; // @[RegisterRouter.scala:87:24]
wire _out_T_700 = ~out_rimask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_701 = ~out_wimask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_702 = ~out_romask_59; // @[RegisterRouter.scala:87:24]
wire _out_T_703 = ~out_womask_59; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_705 = _out_T_704; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_46 = _out_T_705; // @[RegisterRouter.scala:87:24]
wire out_rimask_60 = |_out_rimask_T_60; // @[RegisterRouter.scala:87:24]
wire out_wimask_60 = &_out_wimask_T_60; // @[RegisterRouter.scala:87:24]
wire out_romask_60 = |_out_romask_T_60; // @[RegisterRouter.scala:87:24]
wire out_womask_60 = &_out_womask_T_60; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_60 = out_rivalid_60 & out_rimask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_707 = out_f_rivalid_60; // @[RegisterRouter.scala:87:24]
assign out_f_roready_60 = out_roready_60 & out_romask_60; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_21 = out_f_roready_60; // @[RegisterRouter.scala:87:24]
wire _out_T_708 = out_f_roready_60; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_60 = out_wivalid_60 & out_wimask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_709 = out_f_wivalid_60; // @[RegisterRouter.scala:87:24]
assign out_f_woready_60 = out_woready_60 & out_womask_60; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_21 = out_f_woready_60; // @[RegisterRouter.scala:87:24]
wire _out_T_710 = out_f_woready_60; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_21 = out_f_woready_60 ? _out_T_706 : programBufferMem_21; // @[RegisterRouter.scala:87:24]
wire _out_T_711 = ~out_rimask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_712 = ~out_wimask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_713 = ~out_romask_60; // @[RegisterRouter.scala:87:24]
wire _out_T_714 = ~out_womask_60; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_46 = {programBufferMem_21, _out_prepend_T_46}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_715 = out_prepend_46; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_716 = _out_T_715; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_47 = _out_T_716; // @[RegisterRouter.scala:87:24]
wire out_rimask_61 = |_out_rimask_T_61; // @[RegisterRouter.scala:87:24]
wire out_wimask_61 = &_out_wimask_T_61; // @[RegisterRouter.scala:87:24]
wire out_romask_61 = |_out_romask_T_61; // @[RegisterRouter.scala:87:24]
wire out_womask_61 = &_out_womask_T_61; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_61 = out_rivalid_61 & out_rimask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_718 = out_f_rivalid_61; // @[RegisterRouter.scala:87:24]
assign out_f_roready_61 = out_roready_61 & out_romask_61; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_22 = out_f_roready_61; // @[RegisterRouter.scala:87:24]
wire _out_T_719 = out_f_roready_61; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_61 = out_wivalid_61 & out_wimask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_720 = out_f_wivalid_61; // @[RegisterRouter.scala:87:24]
assign out_f_woready_61 = out_woready_61 & out_womask_61; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_22 = out_f_woready_61; // @[RegisterRouter.scala:87:24]
wire _out_T_721 = out_f_woready_61; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_22 = out_f_woready_61 ? _out_T_717 : programBufferMem_22; // @[RegisterRouter.scala:87:24]
wire _out_T_722 = ~out_rimask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_723 = ~out_wimask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_724 = ~out_romask_61; // @[RegisterRouter.scala:87:24]
wire _out_T_725 = ~out_womask_61; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_47 = {programBufferMem_22, _out_prepend_T_47}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_726 = out_prepend_47; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_727 = _out_T_726; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_48 = _out_T_727; // @[RegisterRouter.scala:87:24]
wire out_rimask_62 = |_out_rimask_T_62; // @[RegisterRouter.scala:87:24]
wire out_wimask_62 = &_out_wimask_T_62; // @[RegisterRouter.scala:87:24]
wire out_romask_62 = |_out_romask_T_62; // @[RegisterRouter.scala:87:24]
wire out_womask_62 = &_out_womask_T_62; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_62 = out_rivalid_62 & out_rimask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_729 = out_f_rivalid_62; // @[RegisterRouter.scala:87:24]
assign out_f_roready_62 = out_roready_62 & out_romask_62; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_23 = out_f_roready_62; // @[RegisterRouter.scala:87:24]
wire _out_T_730 = out_f_roready_62; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_62 = out_wivalid_62 & out_wimask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_731 = out_f_wivalid_62; // @[RegisterRouter.scala:87:24]
assign out_f_woready_62 = out_woready_62 & out_womask_62; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_23 = out_f_woready_62; // @[RegisterRouter.scala:87:24]
wire _out_T_732 = out_f_woready_62; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_23 = out_f_woready_62 ? _out_T_728 : programBufferMem_23; // @[RegisterRouter.scala:87:24]
wire _out_T_733 = ~out_rimask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_734 = ~out_wimask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_735 = ~out_romask_62; // @[RegisterRouter.scala:87:24]
wire _out_T_736 = ~out_womask_62; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_48 = {programBufferMem_23, _out_prepend_T_48}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_737 = out_prepend_48; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_738 = _out_T_737; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_37 = _out_T_738; // @[MuxLiteral.scala:49:48]
wire out_rimask_63 = |_out_rimask_T_63; // @[RegisterRouter.scala:87:24]
wire out_wimask_63 = &_out_wimask_T_63; // @[RegisterRouter.scala:87:24]
wire out_romask_63 = |_out_romask_T_63; // @[RegisterRouter.scala:87:24]
wire out_womask_63 = &_out_womask_T_63; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_63 = out_rivalid_63 & out_rimask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_740 = out_f_rivalid_63; // @[RegisterRouter.scala:87:24]
assign out_f_roready_63 = out_roready_63 & out_romask_63; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_56 = out_f_roready_63; // @[RegisterRouter.scala:87:24]
wire _out_T_741 = out_f_roready_63; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_63 = out_wivalid_63 & out_wimask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_742 = out_f_wivalid_63; // @[RegisterRouter.scala:87:24]
assign out_f_woready_63 = out_woready_63 & out_womask_63; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_56 = out_f_woready_63; // @[RegisterRouter.scala:87:24]
wire _out_T_743 = out_f_woready_63; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_56 = out_f_woready_63 ? _out_T_739 : programBufferMem_56; // @[RegisterRouter.scala:87:24]
wire _out_T_744 = ~out_rimask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_745 = ~out_wimask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_746 = ~out_romask_63; // @[RegisterRouter.scala:87:24]
wire _out_T_747 = ~out_womask_63; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_749 = _out_T_748; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_49 = _out_T_749; // @[RegisterRouter.scala:87:24]
wire out_rimask_64 = |_out_rimask_T_64; // @[RegisterRouter.scala:87:24]
wire out_wimask_64 = &_out_wimask_T_64; // @[RegisterRouter.scala:87:24]
wire out_romask_64 = |_out_romask_T_64; // @[RegisterRouter.scala:87:24]
wire out_womask_64 = &_out_womask_T_64; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_64 = out_rivalid_64 & out_rimask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_751 = out_f_rivalid_64; // @[RegisterRouter.scala:87:24]
assign out_f_roready_64 = out_roready_64 & out_romask_64; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_57 = out_f_roready_64; // @[RegisterRouter.scala:87:24]
wire _out_T_752 = out_f_roready_64; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_64 = out_wivalid_64 & out_wimask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_753 = out_f_wivalid_64; // @[RegisterRouter.scala:87:24]
assign out_f_woready_64 = out_woready_64 & out_womask_64; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_57 = out_f_woready_64; // @[RegisterRouter.scala:87:24]
wire _out_T_754 = out_f_woready_64; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_57 = out_f_woready_64 ? _out_T_750 : programBufferMem_57; // @[RegisterRouter.scala:87:24]
wire _out_T_755 = ~out_rimask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_756 = ~out_wimask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_757 = ~out_romask_64; // @[RegisterRouter.scala:87:24]
wire _out_T_758 = ~out_womask_64; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_49 = {programBufferMem_57, _out_prepend_T_49}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_759 = out_prepend_49; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_760 = _out_T_759; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_50 = _out_T_760; // @[RegisterRouter.scala:87:24]
wire out_rimask_65 = |_out_rimask_T_65; // @[RegisterRouter.scala:87:24]
wire out_wimask_65 = &_out_wimask_T_65; // @[RegisterRouter.scala:87:24]
wire out_romask_65 = |_out_romask_T_65; // @[RegisterRouter.scala:87:24]
wire out_womask_65 = &_out_womask_T_65; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_65 = out_rivalid_65 & out_rimask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_762 = out_f_rivalid_65; // @[RegisterRouter.scala:87:24]
assign out_f_roready_65 = out_roready_65 & out_romask_65; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_58 = out_f_roready_65; // @[RegisterRouter.scala:87:24]
wire _out_T_763 = out_f_roready_65; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_65 = out_wivalid_65 & out_wimask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_764 = out_f_wivalid_65; // @[RegisterRouter.scala:87:24]
assign out_f_woready_65 = out_woready_65 & out_womask_65; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_58 = out_f_woready_65; // @[RegisterRouter.scala:87:24]
wire _out_T_765 = out_f_woready_65; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_58 = out_f_woready_65 ? _out_T_761 : programBufferMem_58; // @[RegisterRouter.scala:87:24]
wire _out_T_766 = ~out_rimask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_767 = ~out_wimask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_768 = ~out_romask_65; // @[RegisterRouter.scala:87:24]
wire _out_T_769 = ~out_womask_65; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_50 = {programBufferMem_58, _out_prepend_T_50}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_770 = out_prepend_50; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_771 = _out_T_770; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_51 = _out_T_771; // @[RegisterRouter.scala:87:24]
wire out_rimask_66 = |_out_rimask_T_66; // @[RegisterRouter.scala:87:24]
wire out_wimask_66 = &_out_wimask_T_66; // @[RegisterRouter.scala:87:24]
wire out_romask_66 = |_out_romask_T_66; // @[RegisterRouter.scala:87:24]
wire out_womask_66 = &_out_womask_T_66; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_66 = out_rivalid_66 & out_rimask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_773 = out_f_rivalid_66; // @[RegisterRouter.scala:87:24]
assign out_f_roready_66 = out_roready_66 & out_romask_66; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_59 = out_f_roready_66; // @[RegisterRouter.scala:87:24]
wire _out_T_774 = out_f_roready_66; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_66 = out_wivalid_66 & out_wimask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_775 = out_f_wivalid_66; // @[RegisterRouter.scala:87:24]
assign out_f_woready_66 = out_woready_66 & out_womask_66; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_59 = out_f_woready_66; // @[RegisterRouter.scala:87:24]
wire _out_T_776 = out_f_woready_66; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_59 = out_f_woready_66 ? _out_T_772 : programBufferMem_59; // @[RegisterRouter.scala:87:24]
wire _out_T_777 = ~out_rimask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_778 = ~out_wimask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_779 = ~out_romask_66; // @[RegisterRouter.scala:87:24]
wire _out_T_780 = ~out_womask_66; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_51 = {programBufferMem_59, _out_prepend_T_51}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_781 = out_prepend_51; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_782 = _out_T_781; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_46 = _out_T_782; // @[MuxLiteral.scala:49:48]
wire out_rimask_67 = |_out_rimask_T_67; // @[RegisterRouter.scala:87:24]
wire out_wimask_67 = &_out_wimask_T_67; // @[RegisterRouter.scala:87:24]
wire out_romask_67 = |_out_romask_T_67; // @[RegisterRouter.scala:87:24]
wire out_womask_67 = &_out_womask_T_67; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_67 = out_rivalid_67 & out_rimask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_784 = out_f_rivalid_67; // @[RegisterRouter.scala:87:24]
assign out_f_roready_67 = out_roready_67 & out_romask_67; // @[RegisterRouter.scala:87:24]
assign SBADDRESSRdEn_0 = out_f_roready_67; // @[RegisterRouter.scala:87:24]
wire _out_T_785 = out_f_roready_67; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_67 = out_wivalid_67 & out_wimask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_786 = out_f_wivalid_67; // @[RegisterRouter.scala:87:24]
assign out_f_woready_67 = out_woready_67 & out_womask_67; // @[RegisterRouter.scala:87:24]
assign SBADDRESSWrEn_0 = out_f_woready_67; // @[RegisterRouter.scala:87:24]
wire _out_T_787 = out_f_woready_67; // @[RegisterRouter.scala:87:24]
assign SBADDRESSWrData_0 = out_f_woready_67 ? _out_T_783 : 32'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_788 = ~out_rimask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_789 = ~out_wimask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_790 = ~out_romask_67; // @[RegisterRouter.scala:87:24]
wire _out_T_791 = ~out_womask_67; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_793 = _out_T_792; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_57 = _out_T_793; // @[MuxLiteral.scala:49:48]
wire out_rimask_68 = |_out_rimask_T_68; // @[RegisterRouter.scala:87:24]
wire out_wimask_68 = &_out_wimask_T_68; // @[RegisterRouter.scala:87:24]
wire out_romask_68 = |_out_romask_T_68; // @[RegisterRouter.scala:87:24]
wire out_womask_68 = &_out_womask_T_68; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_68 = out_rivalid_68 & out_rimask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_795 = out_f_rivalid_68; // @[RegisterRouter.scala:87:24]
assign out_f_roready_68 = out_roready_68 & out_romask_68; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_8 = out_f_roready_68; // @[RegisterRouter.scala:87:24]
wire _out_T_796 = out_f_roready_68; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_68 = out_wivalid_68 & out_wimask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_797 = out_f_wivalid_68; // @[RegisterRouter.scala:87:24]
assign out_f_woready_68 = out_woready_68 & out_womask_68; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_8 = out_f_woready_68; // @[RegisterRouter.scala:87:24]
wire _out_T_798 = out_f_woready_68; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_8 = out_f_woready_68 ? _out_T_794 : abstractDataMem_8; // @[RegisterRouter.scala:87:24]
wire _out_T_799 = ~out_rimask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_800 = ~out_wimask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_801 = ~out_romask_68; // @[RegisterRouter.scala:87:24]
wire _out_T_802 = ~out_womask_68; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_804 = _out_T_803; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_52 = _out_T_804; // @[RegisterRouter.scala:87:24]
wire out_rimask_69 = |_out_rimask_T_69; // @[RegisterRouter.scala:87:24]
wire out_wimask_69 = &_out_wimask_T_69; // @[RegisterRouter.scala:87:24]
wire out_romask_69 = |_out_romask_T_69; // @[RegisterRouter.scala:87:24]
wire out_womask_69 = &_out_womask_T_69; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_69 = out_rivalid_69 & out_rimask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_806 = out_f_rivalid_69; // @[RegisterRouter.scala:87:24]
assign out_f_roready_69 = out_roready_69 & out_romask_69; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_9 = out_f_roready_69; // @[RegisterRouter.scala:87:24]
wire _out_T_807 = out_f_roready_69; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_69 = out_wivalid_69 & out_wimask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_808 = out_f_wivalid_69; // @[RegisterRouter.scala:87:24]
assign out_f_woready_69 = out_woready_69 & out_womask_69; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_9 = out_f_woready_69; // @[RegisterRouter.scala:87:24]
wire _out_T_809 = out_f_woready_69; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_9 = out_f_woready_69 ? _out_T_805 : abstractDataMem_9; // @[RegisterRouter.scala:87:24]
wire _out_T_810 = ~out_rimask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_811 = ~out_wimask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_812 = ~out_romask_69; // @[RegisterRouter.scala:87:24]
wire _out_T_813 = ~out_womask_69; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_52 = {abstractDataMem_9, _out_prepend_T_52}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_814 = out_prepend_52; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_815 = _out_T_814; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_53 = _out_T_815; // @[RegisterRouter.scala:87:24]
wire out_rimask_70 = |_out_rimask_T_70; // @[RegisterRouter.scala:87:24]
wire out_wimask_70 = &_out_wimask_T_70; // @[RegisterRouter.scala:87:24]
wire out_romask_70 = |_out_romask_T_70; // @[RegisterRouter.scala:87:24]
wire out_womask_70 = &_out_womask_T_70; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_70 = out_rivalid_70 & out_rimask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_817 = out_f_rivalid_70; // @[RegisterRouter.scala:87:24]
assign out_f_roready_70 = out_roready_70 & out_romask_70; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_10 = out_f_roready_70; // @[RegisterRouter.scala:87:24]
wire _out_T_818 = out_f_roready_70; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_70 = out_wivalid_70 & out_wimask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_819 = out_f_wivalid_70; // @[RegisterRouter.scala:87:24]
assign out_f_woready_70 = out_woready_70 & out_womask_70; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_10 = out_f_woready_70; // @[RegisterRouter.scala:87:24]
wire _out_T_820 = out_f_woready_70; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_10 = out_f_woready_70 ? _out_T_816 : abstractDataMem_10; // @[RegisterRouter.scala:87:24]
wire _out_T_821 = ~out_rimask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_822 = ~out_wimask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_823 = ~out_romask_70; // @[RegisterRouter.scala:87:24]
wire _out_T_824 = ~out_womask_70; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_53 = {abstractDataMem_10, _out_prepend_T_53}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_825 = out_prepend_53; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_826 = _out_T_825; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_54 = _out_T_826; // @[RegisterRouter.scala:87:24]
wire out_rimask_71 = |_out_rimask_T_71; // @[RegisterRouter.scala:87:24]
wire out_wimask_71 = &_out_wimask_T_71; // @[RegisterRouter.scala:87:24]
wire out_romask_71 = |_out_romask_T_71; // @[RegisterRouter.scala:87:24]
wire out_womask_71 = &_out_womask_T_71; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_71 = out_rivalid_71 & out_rimask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_828 = out_f_rivalid_71; // @[RegisterRouter.scala:87:24]
assign out_f_roready_71 = out_roready_71 & out_romask_71; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_11 = out_f_roready_71; // @[RegisterRouter.scala:87:24]
wire _out_T_829 = out_f_roready_71; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_71 = out_wivalid_71 & out_wimask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_830 = out_f_wivalid_71; // @[RegisterRouter.scala:87:24]
assign out_f_woready_71 = out_woready_71 & out_womask_71; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_11 = out_f_woready_71; // @[RegisterRouter.scala:87:24]
wire _out_T_831 = out_f_woready_71; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_11 = out_f_woready_71 ? _out_T_827 : abstractDataMem_11; // @[RegisterRouter.scala:87:24]
wire _out_T_832 = ~out_rimask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_833 = ~out_wimask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_834 = ~out_romask_71; // @[RegisterRouter.scala:87:24]
wire _out_T_835 = ~out_womask_71; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_54 = {abstractDataMem_11, _out_prepend_T_54}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_836 = out_prepend_54; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_837 = _out_T_836; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_6 = _out_T_837; // @[MuxLiteral.scala:49:48]
wire out_rimask_72 = |_out_rimask_T_72; // @[RegisterRouter.scala:87:24]
wire out_wimask_72 = &_out_wimask_T_72; // @[RegisterRouter.scala:87:24]
wire out_romask_72 = |_out_romask_T_72; // @[RegisterRouter.scala:87:24]
wire out_womask_72 = &_out_womask_T_72; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_72 = out_rivalid_72 & out_rimask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_839 = out_f_rivalid_72; // @[RegisterRouter.scala:87:24]
assign out_f_roready_72 = out_roready_72 & out_romask_72; // @[RegisterRouter.scala:87:24]
assign SBDATARdEn_0 = out_f_roready_72; // @[RegisterRouter.scala:87:24]
wire _out_T_840 = out_f_roready_72; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_72 = out_wivalid_72 & out_wimask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_841 = out_f_wivalid_72; // @[RegisterRouter.scala:87:24]
assign out_f_woready_72 = out_woready_72 & out_womask_72; // @[RegisterRouter.scala:87:24]
assign SBDATAWrEn_0 = out_f_woready_72; // @[RegisterRouter.scala:87:24]
wire _out_T_842 = out_f_woready_72; // @[RegisterRouter.scala:87:24]
assign SBDATAWrData_0 = out_f_woready_72 ? _out_T_838 : 32'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_843 = ~out_rimask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_844 = ~out_wimask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_845 = ~out_romask_72; // @[RegisterRouter.scala:87:24]
wire _out_T_846 = ~out_womask_72; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_848 = _out_T_847; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_60 = _out_T_848; // @[MuxLiteral.scala:49:48]
wire out_rimask_73 = |_out_rimask_T_73; // @[RegisterRouter.scala:87:24]
wire out_wimask_73 = &_out_wimask_T_73; // @[RegisterRouter.scala:87:24]
wire out_romask_73 = |_out_romask_T_73; // @[RegisterRouter.scala:87:24]
wire out_womask_73 = &_out_womask_T_73; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_73 = out_rivalid_73 & out_rimask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_850 = out_f_rivalid_73; // @[RegisterRouter.scala:87:24]
assign out_f_roready_73 = out_roready_73 & out_romask_73; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_24 = out_f_roready_73; // @[RegisterRouter.scala:87:24]
wire _out_T_851 = out_f_roready_73; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_73 = out_wivalid_73 & out_wimask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_852 = out_f_wivalid_73; // @[RegisterRouter.scala:87:24]
assign out_f_woready_73 = out_woready_73 & out_womask_73; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_24 = out_f_woready_73; // @[RegisterRouter.scala:87:24]
wire _out_T_853 = out_f_woready_73; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_24 = out_f_woready_73 ? _out_T_849 : programBufferMem_24; // @[RegisterRouter.scala:87:24]
wire _out_T_854 = ~out_rimask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_855 = ~out_wimask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_856 = ~out_romask_73; // @[RegisterRouter.scala:87:24]
wire _out_T_857 = ~out_womask_73; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_859 = _out_T_858; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_55 = _out_T_859; // @[RegisterRouter.scala:87:24]
wire out_rimask_74 = |_out_rimask_T_74; // @[RegisterRouter.scala:87:24]
wire out_wimask_74 = &_out_wimask_T_74; // @[RegisterRouter.scala:87:24]
wire out_romask_74 = |_out_romask_T_74; // @[RegisterRouter.scala:87:24]
wire out_womask_74 = &_out_womask_T_74; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_74 = out_rivalid_74 & out_rimask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_861 = out_f_rivalid_74; // @[RegisterRouter.scala:87:24]
assign out_f_roready_74 = out_roready_74 & out_romask_74; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_25 = out_f_roready_74; // @[RegisterRouter.scala:87:24]
wire _out_T_862 = out_f_roready_74; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_74 = out_wivalid_74 & out_wimask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_863 = out_f_wivalid_74; // @[RegisterRouter.scala:87:24]
assign out_f_woready_74 = out_woready_74 & out_womask_74; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_25 = out_f_woready_74; // @[RegisterRouter.scala:87:24]
wire _out_T_864 = out_f_woready_74; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_25 = out_f_woready_74 ? _out_T_860 : programBufferMem_25; // @[RegisterRouter.scala:87:24]
wire _out_T_865 = ~out_rimask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_866 = ~out_wimask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_867 = ~out_romask_74; // @[RegisterRouter.scala:87:24]
wire _out_T_868 = ~out_womask_74; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_55 = {programBufferMem_25, _out_prepend_T_55}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_869 = out_prepend_55; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_870 = _out_T_869; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_56 = _out_T_870; // @[RegisterRouter.scala:87:24]
wire out_rimask_75 = |_out_rimask_T_75; // @[RegisterRouter.scala:87:24]
wire out_wimask_75 = &_out_wimask_T_75; // @[RegisterRouter.scala:87:24]
wire out_romask_75 = |_out_romask_T_75; // @[RegisterRouter.scala:87:24]
wire out_womask_75 = &_out_womask_T_75; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_75 = out_rivalid_75 & out_rimask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_872 = out_f_rivalid_75; // @[RegisterRouter.scala:87:24]
assign out_f_roready_75 = out_roready_75 & out_romask_75; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_26 = out_f_roready_75; // @[RegisterRouter.scala:87:24]
wire _out_T_873 = out_f_roready_75; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_75 = out_wivalid_75 & out_wimask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_874 = out_f_wivalid_75; // @[RegisterRouter.scala:87:24]
assign out_f_woready_75 = out_woready_75 & out_womask_75; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_26 = out_f_woready_75; // @[RegisterRouter.scala:87:24]
wire _out_T_875 = out_f_woready_75; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_26 = out_f_woready_75 ? _out_T_871 : programBufferMem_26; // @[RegisterRouter.scala:87:24]
wire _out_T_876 = ~out_rimask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_877 = ~out_wimask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_878 = ~out_romask_75; // @[RegisterRouter.scala:87:24]
wire _out_T_879 = ~out_womask_75; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_56 = {programBufferMem_26, _out_prepend_T_56}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_880 = out_prepend_56; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_881 = _out_T_880; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_57 = _out_T_881; // @[RegisterRouter.scala:87:24]
wire out_rimask_76 = |_out_rimask_T_76; // @[RegisterRouter.scala:87:24]
wire out_wimask_76 = &_out_wimask_T_76; // @[RegisterRouter.scala:87:24]
wire out_romask_76 = |_out_romask_T_76; // @[RegisterRouter.scala:87:24]
wire out_womask_76 = &_out_womask_T_76; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_76 = out_rivalid_76 & out_rimask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_883 = out_f_rivalid_76; // @[RegisterRouter.scala:87:24]
assign out_f_roready_76 = out_roready_76 & out_romask_76; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_27 = out_f_roready_76; // @[RegisterRouter.scala:87:24]
wire _out_T_884 = out_f_roready_76; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_76 = out_wivalid_76 & out_wimask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_885 = out_f_wivalid_76; // @[RegisterRouter.scala:87:24]
assign out_f_woready_76 = out_woready_76 & out_womask_76; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_27 = out_f_woready_76; // @[RegisterRouter.scala:87:24]
wire _out_T_886 = out_f_woready_76; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_27 = out_f_woready_76 ? _out_T_882 : programBufferMem_27; // @[RegisterRouter.scala:87:24]
wire _out_T_887 = ~out_rimask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_888 = ~out_wimask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_889 = ~out_romask_76; // @[RegisterRouter.scala:87:24]
wire _out_T_890 = ~out_womask_76; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_57 = {programBufferMem_27, _out_prepend_T_57}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_891 = out_prepend_57; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_892 = _out_T_891; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_38 = _out_T_892; // @[MuxLiteral.scala:49:48]
wire out_rimask_77 = |_out_rimask_T_77; // @[RegisterRouter.scala:87:24]
wire out_wimask_77 = &_out_wimask_T_77; // @[RegisterRouter.scala:87:24]
wire out_romask_77 = |_out_romask_T_77; // @[RegisterRouter.scala:87:24]
wire out_womask_77 = &_out_womask_T_77; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_77 = out_rivalid_77 & out_rimask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_894 = out_f_rivalid_77; // @[RegisterRouter.scala:87:24]
assign out_f_roready_77 = out_roready_77 & out_romask_77; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_4 = out_f_roready_77; // @[RegisterRouter.scala:87:24]
wire _out_T_895 = out_f_roready_77; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_77 = out_wivalid_77 & out_wimask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_896 = out_f_wivalid_77; // @[RegisterRouter.scala:87:24]
assign out_f_woready_77 = out_woready_77 & out_womask_77; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_4 = out_f_woready_77; // @[RegisterRouter.scala:87:24]
wire _out_T_897 = out_f_woready_77; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_4 = out_f_woready_77 ? _out_T_893 : programBufferMem_4; // @[RegisterRouter.scala:87:24]
wire _out_T_898 = ~out_rimask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_899 = ~out_wimask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_900 = ~out_romask_77; // @[RegisterRouter.scala:87:24]
wire _out_T_901 = ~out_womask_77; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_903 = _out_T_902; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_58 = _out_T_903; // @[RegisterRouter.scala:87:24]
wire out_rimask_78 = |_out_rimask_T_78; // @[RegisterRouter.scala:87:24]
wire out_wimask_78 = &_out_wimask_T_78; // @[RegisterRouter.scala:87:24]
wire out_romask_78 = |_out_romask_T_78; // @[RegisterRouter.scala:87:24]
wire out_womask_78 = &_out_womask_T_78; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_78 = out_rivalid_78 & out_rimask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_905 = out_f_rivalid_78; // @[RegisterRouter.scala:87:24]
assign out_f_roready_78 = out_roready_78 & out_romask_78; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_5 = out_f_roready_78; // @[RegisterRouter.scala:87:24]
wire _out_T_906 = out_f_roready_78; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_78 = out_wivalid_78 & out_wimask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_907 = out_f_wivalid_78; // @[RegisterRouter.scala:87:24]
assign out_f_woready_78 = out_woready_78 & out_womask_78; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_5 = out_f_woready_78; // @[RegisterRouter.scala:87:24]
wire _out_T_908 = out_f_woready_78; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_5 = out_f_woready_78 ? _out_T_904 : programBufferMem_5; // @[RegisterRouter.scala:87:24]
wire _out_T_909 = ~out_rimask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_910 = ~out_wimask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_911 = ~out_romask_78; // @[RegisterRouter.scala:87:24]
wire _out_T_912 = ~out_womask_78; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_58 = {programBufferMem_5, _out_prepend_T_58}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_913 = out_prepend_58; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_914 = _out_T_913; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_59 = _out_T_914; // @[RegisterRouter.scala:87:24]
wire out_rimask_79 = |_out_rimask_T_79; // @[RegisterRouter.scala:87:24]
wire out_wimask_79 = &_out_wimask_T_79; // @[RegisterRouter.scala:87:24]
wire out_romask_79 = |_out_romask_T_79; // @[RegisterRouter.scala:87:24]
wire out_womask_79 = &_out_womask_T_79; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_79 = out_rivalid_79 & out_rimask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_916 = out_f_rivalid_79; // @[RegisterRouter.scala:87:24]
assign out_f_roready_79 = out_roready_79 & out_romask_79; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_6 = out_f_roready_79; // @[RegisterRouter.scala:87:24]
wire _out_T_917 = out_f_roready_79; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_79 = out_wivalid_79 & out_wimask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_918 = out_f_wivalid_79; // @[RegisterRouter.scala:87:24]
assign out_f_woready_79 = out_woready_79 & out_womask_79; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_6 = out_f_woready_79; // @[RegisterRouter.scala:87:24]
wire _out_T_919 = out_f_woready_79; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_6 = out_f_woready_79 ? _out_T_915 : programBufferMem_6; // @[RegisterRouter.scala:87:24]
wire _out_T_920 = ~out_rimask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_921 = ~out_wimask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_922 = ~out_romask_79; // @[RegisterRouter.scala:87:24]
wire _out_T_923 = ~out_womask_79; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_59 = {programBufferMem_6, _out_prepend_T_59}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_924 = out_prepend_59; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_925 = _out_T_924; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_60 = _out_T_925; // @[RegisterRouter.scala:87:24]
wire out_rimask_80 = |_out_rimask_T_80; // @[RegisterRouter.scala:87:24]
wire out_wimask_80 = &_out_wimask_T_80; // @[RegisterRouter.scala:87:24]
wire out_romask_80 = |_out_romask_T_80; // @[RegisterRouter.scala:87:24]
wire out_womask_80 = &_out_womask_T_80; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_80 = out_rivalid_80 & out_rimask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_927 = out_f_rivalid_80; // @[RegisterRouter.scala:87:24]
assign out_f_roready_80 = out_roready_80 & out_romask_80; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_7 = out_f_roready_80; // @[RegisterRouter.scala:87:24]
wire _out_T_928 = out_f_roready_80; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_80 = out_wivalid_80 & out_wimask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_929 = out_f_wivalid_80; // @[RegisterRouter.scala:87:24]
assign out_f_woready_80 = out_woready_80 & out_womask_80; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_7 = out_f_woready_80; // @[RegisterRouter.scala:87:24]
wire _out_T_930 = out_f_woready_80; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_7 = out_f_woready_80 ? _out_T_926 : programBufferMem_7; // @[RegisterRouter.scala:87:24]
wire _out_T_931 = ~out_rimask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_932 = ~out_wimask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_933 = ~out_romask_80; // @[RegisterRouter.scala:87:24]
wire _out_T_934 = ~out_womask_80; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_60 = {programBufferMem_7, _out_prepend_T_60}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_935 = out_prepend_60; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_936 = _out_T_935; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_33 = _out_T_936; // @[MuxLiteral.scala:49:48]
wire out_rimask_81 = |_out_rimask_T_81; // @[RegisterRouter.scala:87:24]
wire out_wimask_81 = &_out_wimask_T_81; // @[RegisterRouter.scala:87:24]
wire out_romask_81 = |_out_romask_T_81; // @[RegisterRouter.scala:87:24]
wire out_womask_81 = &_out_womask_T_81; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_81 = out_rivalid_81 & out_rimask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_938 = out_f_rivalid_81; // @[RegisterRouter.scala:87:24]
assign out_f_roready_81 = out_roready_81 & out_romask_81; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_52 = out_f_roready_81; // @[RegisterRouter.scala:87:24]
wire _out_T_939 = out_f_roready_81; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_81 = out_wivalid_81 & out_wimask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_940 = out_f_wivalid_81; // @[RegisterRouter.scala:87:24]
assign out_f_woready_81 = out_woready_81 & out_womask_81; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_52 = out_f_woready_81; // @[RegisterRouter.scala:87:24]
wire _out_T_941 = out_f_woready_81; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_52 = out_f_woready_81 ? _out_T_937 : programBufferMem_52; // @[RegisterRouter.scala:87:24]
wire _out_T_942 = ~out_rimask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_943 = ~out_wimask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_944 = ~out_romask_81; // @[RegisterRouter.scala:87:24]
wire _out_T_945 = ~out_womask_81; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_947 = _out_T_946; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_61 = _out_T_947; // @[RegisterRouter.scala:87:24]
wire out_rimask_82 = |_out_rimask_T_82; // @[RegisterRouter.scala:87:24]
wire out_wimask_82 = &_out_wimask_T_82; // @[RegisterRouter.scala:87:24]
wire out_romask_82 = |_out_romask_T_82; // @[RegisterRouter.scala:87:24]
wire out_womask_82 = &_out_womask_T_82; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_82 = out_rivalid_82 & out_rimask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_949 = out_f_rivalid_82; // @[RegisterRouter.scala:87:24]
assign out_f_roready_82 = out_roready_82 & out_romask_82; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_53 = out_f_roready_82; // @[RegisterRouter.scala:87:24]
wire _out_T_950 = out_f_roready_82; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_82 = out_wivalid_82 & out_wimask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_951 = out_f_wivalid_82; // @[RegisterRouter.scala:87:24]
assign out_f_woready_82 = out_woready_82 & out_womask_82; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_53 = out_f_woready_82; // @[RegisterRouter.scala:87:24]
wire _out_T_952 = out_f_woready_82; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_53 = out_f_woready_82 ? _out_T_948 : programBufferMem_53; // @[RegisterRouter.scala:87:24]
wire _out_T_953 = ~out_rimask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_954 = ~out_wimask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_955 = ~out_romask_82; // @[RegisterRouter.scala:87:24]
wire _out_T_956 = ~out_womask_82; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_61 = {programBufferMem_53, _out_prepend_T_61}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_957 = out_prepend_61; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_958 = _out_T_957; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_62 = _out_T_958; // @[RegisterRouter.scala:87:24]
wire out_rimask_83 = |_out_rimask_T_83; // @[RegisterRouter.scala:87:24]
wire out_wimask_83 = &_out_wimask_T_83; // @[RegisterRouter.scala:87:24]
wire out_romask_83 = |_out_romask_T_83; // @[RegisterRouter.scala:87:24]
wire out_womask_83 = &_out_womask_T_83; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_83 = out_rivalid_83 & out_rimask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_960 = out_f_rivalid_83; // @[RegisterRouter.scala:87:24]
assign out_f_roready_83 = out_roready_83 & out_romask_83; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_54 = out_f_roready_83; // @[RegisterRouter.scala:87:24]
wire _out_T_961 = out_f_roready_83; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_83 = out_wivalid_83 & out_wimask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_962 = out_f_wivalid_83; // @[RegisterRouter.scala:87:24]
assign out_f_woready_83 = out_woready_83 & out_womask_83; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_54 = out_f_woready_83; // @[RegisterRouter.scala:87:24]
wire _out_T_963 = out_f_woready_83; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_54 = out_f_woready_83 ? _out_T_959 : programBufferMem_54; // @[RegisterRouter.scala:87:24]
wire _out_T_964 = ~out_rimask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_965 = ~out_wimask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_966 = ~out_romask_83; // @[RegisterRouter.scala:87:24]
wire _out_T_967 = ~out_womask_83; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_62 = {programBufferMem_54, _out_prepend_T_62}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_968 = out_prepend_62; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_969 = _out_T_968; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_63 = _out_T_969; // @[RegisterRouter.scala:87:24]
wire out_rimask_84 = |_out_rimask_T_84; // @[RegisterRouter.scala:87:24]
wire out_wimask_84 = &_out_wimask_T_84; // @[RegisterRouter.scala:87:24]
wire out_romask_84 = |_out_romask_T_84; // @[RegisterRouter.scala:87:24]
wire out_womask_84 = &_out_womask_T_84; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_84 = out_rivalid_84 & out_rimask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_971 = out_f_rivalid_84; // @[RegisterRouter.scala:87:24]
assign out_f_roready_84 = out_roready_84 & out_romask_84; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_55 = out_f_roready_84; // @[RegisterRouter.scala:87:24]
wire _out_T_972 = out_f_roready_84; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_84 = out_wivalid_84 & out_wimask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_973 = out_f_wivalid_84; // @[RegisterRouter.scala:87:24]
assign out_f_woready_84 = out_woready_84 & out_womask_84; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_55 = out_f_woready_84; // @[RegisterRouter.scala:87:24]
wire _out_T_974 = out_f_woready_84; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_55 = out_f_woready_84 ? _out_T_970 : programBufferMem_55; // @[RegisterRouter.scala:87:24]
wire _out_T_975 = ~out_rimask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_976 = ~out_wimask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_977 = ~out_romask_84; // @[RegisterRouter.scala:87:24]
wire _out_T_978 = ~out_womask_84; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_63 = {programBufferMem_55, _out_prepend_T_63}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_979 = out_prepend_63; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_980 = _out_T_979; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_45 = _out_T_980; // @[MuxLiteral.scala:49:48]
wire out_rimask_85 = |_out_rimask_T_85; // @[RegisterRouter.scala:87:24]
wire out_wimask_85 = &_out_wimask_T_85; // @[RegisterRouter.scala:87:24]
wire out_romask_85 = |_out_romask_T_85; // @[RegisterRouter.scala:87:24]
wire out_womask_85 = &_out_womask_T_85; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_85 = out_rivalid_85 & out_rimask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_982 = out_f_rivalid_85; // @[RegisterRouter.scala:87:24]
wire out_f_roready_85 = out_roready_85 & out_romask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_983 = out_f_roready_85; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_85 = out_wivalid_85 & out_wimask_85; // @[RegisterRouter.scala:87:24]
wire out_f_woready_85 = out_woready_85 & out_womask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_984 = ~out_rimask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_985 = ~out_wimask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_986 = ~out_romask_85; // @[RegisterRouter.scala:87:24]
wire _out_T_987 = ~out_womask_85; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_989 = _out_T_988; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_0 = _out_T_989; // @[MuxLiteral.scala:49:48]
wire [3:0] _out_rimask_T_86 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_86 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_113 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_113 = out_frontMask[3:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_86 = |_out_rimask_T_86; // @[RegisterRouter.scala:87:24]
wire out_wimask_86 = &_out_wimask_T_86; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_86 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_86 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_113 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_113 = out_backMask[3:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_86 = |_out_romask_T_86; // @[RegisterRouter.scala:87:24]
wire out_womask_86 = &_out_womask_T_86; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_86 = out_rivalid_86 & out_rimask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_991 = out_f_rivalid_86; // @[RegisterRouter.scala:87:24]
wire out_f_roready_86 = out_roready_86 & out_romask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_992 = out_f_roready_86; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_86 = out_wivalid_86 & out_wimask_86; // @[RegisterRouter.scala:87:24]
wire out_f_woready_86 = out_woready_86 & out_womask_86; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_990 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_1249 = out_front_bits_data[3:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_993 = ~out_rimask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_994 = ~out_wimask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_995 = ~out_romask_86; // @[RegisterRouter.scala:87:24]
wire _out_T_996 = ~out_womask_86; // @[RegisterRouter.scala:87:24]
wire out_rimask_87 = _out_rimask_T_87; // @[RegisterRouter.scala:87:24]
wire out_wimask_87 = _out_wimask_T_87; // @[RegisterRouter.scala:87:24]
wire out_romask_87 = _out_romask_T_87; // @[RegisterRouter.scala:87:24]
wire out_womask_87 = _out_womask_T_87; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_87 = out_rivalid_87 & out_rimask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_1000 = out_f_rivalid_87; // @[RegisterRouter.scala:87:24]
wire out_f_roready_87 = out_roready_87 & out_romask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_1001 = out_f_roready_87; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_87 = out_wivalid_87 & out_wimask_87; // @[RegisterRouter.scala:87:24]
wire out_f_woready_87 = out_woready_87 & out_womask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_1002 = ~out_rimask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_1003 = ~out_wimask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_1004 = ~out_romask_87; // @[RegisterRouter.scala:87:24]
wire _out_T_1005 = ~out_womask_87; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_88 = out_frontMask[5]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_88 = out_frontMask[5]; // @[RegisterRouter.scala:87:24]
wire out_rimask_88 = _out_rimask_T_88; // @[RegisterRouter.scala:87:24]
wire out_wimask_88 = _out_wimask_T_88; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_88 = out_backMask[5]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_88 = out_backMask[5]; // @[RegisterRouter.scala:87:24]
wire out_romask_88 = _out_romask_T_88; // @[RegisterRouter.scala:87:24]
wire out_womask_88 = _out_womask_T_88; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_88 = out_rivalid_88 & out_rimask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1009 = out_f_rivalid_88; // @[RegisterRouter.scala:87:24]
wire out_f_roready_88 = out_roready_88 & out_romask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1010 = out_f_roready_88; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_88 = out_wivalid_88 & out_wimask_88; // @[RegisterRouter.scala:87:24]
wire out_f_woready_88 = out_woready_88 & out_womask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1008 = out_front_bits_data[5]; // @[RegisterRouter.scala:87:24]
wire _out_T_1011 = ~out_rimask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1012 = ~out_wimask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1013 = ~out_romask_88; // @[RegisterRouter.scala:87:24]
wire _out_T_1014 = ~out_womask_88; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_89 = out_frontMask[6]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_89 = out_frontMask[6]; // @[RegisterRouter.scala:87:24]
wire out_rimask_89 = _out_rimask_T_89; // @[RegisterRouter.scala:87:24]
wire out_wimask_89 = _out_wimask_T_89; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_89 = out_backMask[6]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_89 = out_backMask[6]; // @[RegisterRouter.scala:87:24]
wire out_romask_89 = _out_romask_T_89; // @[RegisterRouter.scala:87:24]
wire out_womask_89 = _out_womask_T_89; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_89 = out_rivalid_89 & out_rimask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1018 = out_f_rivalid_89; // @[RegisterRouter.scala:87:24]
wire out_f_roready_89 = out_roready_89 & out_romask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1019 = out_f_roready_89; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_89 = out_wivalid_89 & out_wimask_89; // @[RegisterRouter.scala:87:24]
wire out_f_woready_89 = out_woready_89 & out_womask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1017 = out_front_bits_data[6]; // @[RegisterRouter.scala:87:24]
wire _out_T_1020 = ~out_rimask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1021 = ~out_wimask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1022 = ~out_romask_89; // @[RegisterRouter.scala:87:24]
wire _out_T_1023 = ~out_womask_89; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_90 = out_frontMask[7]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_90 = out_frontMask[7]; // @[RegisterRouter.scala:87:24]
wire out_rimask_90 = _out_rimask_T_90; // @[RegisterRouter.scala:87:24]
wire out_wimask_90 = _out_wimask_T_90; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_90 = out_backMask[7]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_90 = out_backMask[7]; // @[RegisterRouter.scala:87:24]
wire out_romask_90 = _out_romask_T_90; // @[RegisterRouter.scala:87:24]
wire out_womask_90 = _out_womask_T_90; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_90 = out_rivalid_90 & out_rimask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1027 = out_f_rivalid_90; // @[RegisterRouter.scala:87:24]
wire out_f_roready_90 = out_roready_90 & out_romask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1028 = out_f_roready_90; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_90 = out_wivalid_90 & out_wimask_90; // @[RegisterRouter.scala:87:24]
wire out_f_woready_90 = out_woready_90 & out_womask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1026 = out_front_bits_data[7]; // @[RegisterRouter.scala:87:24]
wire _out_T_1029 = ~out_rimask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1030 = ~out_wimask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1031 = ~out_romask_90; // @[RegisterRouter.scala:87:24]
wire _out_T_1032 = ~out_womask_90; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_91 = out_frontMask[8]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_91 = out_frontMask[8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_91 = _out_rimask_T_91; // @[RegisterRouter.scala:87:24]
wire out_wimask_91 = _out_wimask_T_91; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_91 = out_backMask[8]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_91 = out_backMask[8]; // @[RegisterRouter.scala:87:24]
wire out_romask_91 = _out_romask_T_91; // @[RegisterRouter.scala:87:24]
wire out_womask_91 = _out_womask_T_91; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_91 = out_rivalid_91 & out_rimask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1036 = out_f_rivalid_91; // @[RegisterRouter.scala:87:24]
wire out_f_roready_91 = out_roready_91 & out_romask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1037 = out_f_roready_91; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_91 = out_wivalid_91 & out_wimask_91; // @[RegisterRouter.scala:87:24]
wire out_f_woready_91 = out_woready_91 & out_womask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1035 = out_front_bits_data[8]; // @[RegisterRouter.scala:87:24]
wire _out_T_1038 = ~out_rimask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1039 = ~out_wimask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1040 = ~out_romask_91; // @[RegisterRouter.scala:87:24]
wire _out_T_1041 = ~out_womask_91; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend_68 = {DMSTATUSRdData_anyhalted, 8'hA2}; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_T_1042 = out_prepend_68; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_T_1043 = _out_T_1042; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_prepend_T_69 = _out_T_1043; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_92 = out_frontMask[9]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_92 = out_frontMask[9]; // @[RegisterRouter.scala:87:24]
wire out_rimask_92 = _out_rimask_T_92; // @[RegisterRouter.scala:87:24]
wire out_wimask_92 = _out_wimask_T_92; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_92 = out_backMask[9]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_92 = out_backMask[9]; // @[RegisterRouter.scala:87:24]
wire out_romask_92 = _out_romask_T_92; // @[RegisterRouter.scala:87:24]
wire out_womask_92 = _out_womask_T_92; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_92 = out_rivalid_92 & out_rimask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1045 = out_f_rivalid_92; // @[RegisterRouter.scala:87:24]
wire out_f_roready_92 = out_roready_92 & out_romask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1046 = out_f_roready_92; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_92 = out_wivalid_92 & out_wimask_92; // @[RegisterRouter.scala:87:24]
wire out_f_woready_92 = out_woready_92 & out_womask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1044 = out_front_bits_data[9]; // @[RegisterRouter.scala:87:24]
wire _out_T_1047 = ~out_rimask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1048 = ~out_wimask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1049 = ~out_romask_92; // @[RegisterRouter.scala:87:24]
wire _out_T_1050 = ~out_womask_92; // @[RegisterRouter.scala:87:24]
wire [9:0] out_prepend_69 = {DMSTATUSRdData_allhalted, _out_prepend_T_69}; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_1051 = out_prepend_69; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_T_1052 = _out_T_1051; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_prepend_T_70 = _out_T_1052; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_93 = out_frontMask[10]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_93 = out_frontMask[10]; // @[RegisterRouter.scala:87:24]
wire out_rimask_93 = _out_rimask_T_93; // @[RegisterRouter.scala:87:24]
wire out_wimask_93 = _out_wimask_T_93; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_93 = out_backMask[10]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_93 = out_backMask[10]; // @[RegisterRouter.scala:87:24]
wire out_romask_93 = _out_romask_T_93; // @[RegisterRouter.scala:87:24]
wire out_womask_93 = _out_womask_T_93; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_93 = out_rivalid_93 & out_rimask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1054 = out_f_rivalid_93; // @[RegisterRouter.scala:87:24]
wire out_f_roready_93 = out_roready_93 & out_romask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1055 = out_f_roready_93; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_93 = out_wivalid_93 & out_wimask_93; // @[RegisterRouter.scala:87:24]
wire out_f_woready_93 = out_woready_93 & out_womask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1053 = out_front_bits_data[10]; // @[RegisterRouter.scala:87:24]
wire _out_T_1056 = ~out_rimask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1057 = ~out_wimask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1058 = ~out_romask_93; // @[RegisterRouter.scala:87:24]
wire _out_T_1059 = ~out_womask_93; // @[RegisterRouter.scala:87:24]
wire [10:0] out_prepend_70 = {DMSTATUSRdData_anyrunning, _out_prepend_T_70}; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1060 = out_prepend_70; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1061 = _out_T_1060; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_prepend_T_71 = _out_T_1061; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_94 = out_frontMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_94 = out_frontMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_116 = out_frontMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_116 = out_frontMask[11]; // @[RegisterRouter.scala:87:24]
wire out_rimask_94 = _out_rimask_T_94; // @[RegisterRouter.scala:87:24]
wire out_wimask_94 = _out_wimask_T_94; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_94 = out_backMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_94 = out_backMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_116 = out_backMask[11]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_116 = out_backMask[11]; // @[RegisterRouter.scala:87:24]
wire out_romask_94 = _out_romask_T_94; // @[RegisterRouter.scala:87:24]
wire out_womask_94 = _out_womask_T_94; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_94 = out_rivalid_94 & out_rimask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1063 = out_f_rivalid_94; // @[RegisterRouter.scala:87:24]
wire out_f_roready_94 = out_roready_94 & out_romask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1064 = out_f_roready_94; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_94 = out_wivalid_94 & out_wimask_94; // @[RegisterRouter.scala:87:24]
wire out_f_woready_94 = out_woready_94 & out_womask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1062 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24]
wire _out_T_1278 = out_front_bits_data[11]; // @[RegisterRouter.scala:87:24]
wire _out_T_1065 = ~out_rimask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1066 = ~out_wimask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1067 = ~out_romask_94; // @[RegisterRouter.scala:87:24]
wire _out_T_1068 = ~out_womask_94; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend_71 = {DMSTATUSRdData_allrunning, _out_prepend_T_71}; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_1069 = out_prepend_71; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_1070 = _out_T_1069; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_prepend_T_72 = _out_T_1070; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_95 = out_frontMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_95 = out_frontMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_117 = out_frontMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_117 = out_frontMask[12]; // @[RegisterRouter.scala:87:24]
wire out_rimask_95 = _out_rimask_T_95; // @[RegisterRouter.scala:87:24]
wire out_wimask_95 = _out_wimask_T_95; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_95 = out_backMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_95 = out_backMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_117 = out_backMask[12]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_117 = out_backMask[12]; // @[RegisterRouter.scala:87:24]
wire out_romask_95 = _out_romask_T_95; // @[RegisterRouter.scala:87:24]
wire out_womask_95 = _out_womask_T_95; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_95 = out_rivalid_95 & out_rimask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1072 = out_f_rivalid_95; // @[RegisterRouter.scala:87:24]
wire out_f_roready_95 = out_roready_95 & out_romask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1073 = out_f_roready_95; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_95 = out_wivalid_95 & out_wimask_95; // @[RegisterRouter.scala:87:24]
wire out_f_woready_95 = out_woready_95 & out_womask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1071 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24]
wire _out_T_1287 = out_front_bits_data[12]; // @[RegisterRouter.scala:87:24]
wire _out_T_1074 = ~out_rimask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1075 = ~out_wimask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1076 = ~out_romask_95; // @[RegisterRouter.scala:87:24]
wire _out_T_1077 = ~out_womask_95; // @[RegisterRouter.scala:87:24]
wire [12:0] out_prepend_72 = {1'h0, _out_prepend_T_72}; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_T_1078 = out_prepend_72; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_T_1079 = _out_T_1078; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_prepend_T_73 = _out_T_1079; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_96 = out_frontMask[13]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_96 = out_frontMask[13]; // @[RegisterRouter.scala:87:24]
wire out_rimask_96 = _out_rimask_T_96; // @[RegisterRouter.scala:87:24]
wire out_wimask_96 = _out_wimask_T_96; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_96 = out_backMask[13]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_96 = out_backMask[13]; // @[RegisterRouter.scala:87:24]
wire out_romask_96 = _out_romask_T_96; // @[RegisterRouter.scala:87:24]
wire out_womask_96 = _out_womask_T_96; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_96 = out_rivalid_96 & out_rimask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1081 = out_f_rivalid_96; // @[RegisterRouter.scala:87:24]
wire out_f_roready_96 = out_roready_96 & out_romask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1082 = out_f_roready_96; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_96 = out_wivalid_96 & out_wimask_96; // @[RegisterRouter.scala:87:24]
wire out_f_woready_96 = out_woready_96 & out_womask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1080 = out_front_bits_data[13]; // @[RegisterRouter.scala:87:24]
wire _out_T_1083 = ~out_rimask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1084 = ~out_wimask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1085 = ~out_romask_96; // @[RegisterRouter.scala:87:24]
wire _out_T_1086 = ~out_womask_96; // @[RegisterRouter.scala:87:24]
wire [13:0] out_prepend_73 = {DMSTATUSRdData_allunavail, _out_prepend_T_73}; // @[RegisterRouter.scala:87:24]
wire [13:0] _out_T_1087 = out_prepend_73; // @[RegisterRouter.scala:87:24]
wire [13:0] _out_T_1088 = _out_T_1087; // @[RegisterRouter.scala:87:24]
wire [13:0] _out_prepend_T_74 = _out_T_1088; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_97 = out_frontMask[14]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_97 = out_frontMask[14]; // @[RegisterRouter.scala:87:24]
wire out_rimask_97 = _out_rimask_T_97; // @[RegisterRouter.scala:87:24]
wire out_wimask_97 = _out_wimask_T_97; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_97 = out_backMask[14]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_97 = out_backMask[14]; // @[RegisterRouter.scala:87:24]
wire out_romask_97 = _out_romask_T_97; // @[RegisterRouter.scala:87:24]
wire out_womask_97 = _out_womask_T_97; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_97 = out_rivalid_97 & out_rimask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1090 = out_f_rivalid_97; // @[RegisterRouter.scala:87:24]
wire out_f_roready_97 = out_roready_97 & out_romask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1091 = out_f_roready_97; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_97 = out_wivalid_97 & out_wimask_97; // @[RegisterRouter.scala:87:24]
wire out_f_woready_97 = out_woready_97 & out_womask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1089 = out_front_bits_data[14]; // @[RegisterRouter.scala:87:24]
wire _out_T_1092 = ~out_rimask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1093 = ~out_wimask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1094 = ~out_romask_97; // @[RegisterRouter.scala:87:24]
wire _out_T_1095 = ~out_womask_97; // @[RegisterRouter.scala:87:24]
wire [14:0] out_prepend_74 = {1'h0, _out_prepend_T_74}; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_T_1096 = out_prepend_74; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_T_1097 = _out_T_1096; // @[RegisterRouter.scala:87:24]
wire [14:0] _out_prepend_T_75 = _out_T_1097; // @[RegisterRouter.scala:87:24]
wire out_rimask_98 = _out_rimask_T_98; // @[RegisterRouter.scala:87:24]
wire out_wimask_98 = _out_wimask_T_98; // @[RegisterRouter.scala:87:24]
wire out_romask_98 = _out_romask_T_98; // @[RegisterRouter.scala:87:24]
wire out_womask_98 = _out_womask_T_98; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_98 = out_rivalid_98 & out_rimask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1099 = out_f_rivalid_98; // @[RegisterRouter.scala:87:24]
wire out_f_roready_98 = out_roready_98 & out_romask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1100 = out_f_roready_98; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_98 = out_wivalid_98 & out_wimask_98; // @[RegisterRouter.scala:87:24]
wire out_f_woready_98 = out_woready_98 & out_womask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1101 = ~out_rimask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1102 = ~out_wimask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1103 = ~out_romask_98; // @[RegisterRouter.scala:87:24]
wire _out_T_1104 = ~out_womask_98; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_75 = {1'h0, _out_prepend_T_75}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1105 = out_prepend_75; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1106 = _out_T_1105; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_76 = _out_T_1106; // @[RegisterRouter.scala:87:24]
wire out_rimask_99 = _out_rimask_T_99; // @[RegisterRouter.scala:87:24]
wire out_wimask_99 = _out_wimask_T_99; // @[RegisterRouter.scala:87:24]
wire out_romask_99 = _out_romask_T_99; // @[RegisterRouter.scala:87:24]
wire out_womask_99 = _out_womask_T_99; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_99 = out_rivalid_99 & out_rimask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1108 = out_f_rivalid_99; // @[RegisterRouter.scala:87:24]
wire out_f_roready_99 = out_roready_99 & out_romask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1109 = out_f_roready_99; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_99 = out_wivalid_99 & out_wimask_99; // @[RegisterRouter.scala:87:24]
wire out_f_woready_99 = out_woready_99 & out_womask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1110 = ~out_rimask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1111 = ~out_wimask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1112 = ~out_romask_99; // @[RegisterRouter.scala:87:24]
wire _out_T_1113 = ~out_womask_99; // @[RegisterRouter.scala:87:24]
wire [16:0] out_prepend_76 = {DMSTATUSRdData_anyresumeack, _out_prepend_T_76}; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_1114 = out_prepend_76; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_1115 = _out_T_1114; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_prepend_T_77 = _out_T_1115; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_100 = out_frontMask[17]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_100 = out_frontMask[17]; // @[RegisterRouter.scala:87:24]
wire out_rimask_100 = _out_rimask_T_100; // @[RegisterRouter.scala:87:24]
wire out_wimask_100 = _out_wimask_T_100; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_100 = out_backMask[17]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_100 = out_backMask[17]; // @[RegisterRouter.scala:87:24]
wire out_romask_100 = _out_romask_T_100; // @[RegisterRouter.scala:87:24]
wire out_womask_100 = _out_womask_T_100; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_100 = out_rivalid_100 & out_rimask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1117 = out_f_rivalid_100; // @[RegisterRouter.scala:87:24]
wire out_f_roready_100 = out_roready_100 & out_romask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1118 = out_f_roready_100; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_100 = out_wivalid_100 & out_wimask_100; // @[RegisterRouter.scala:87:24]
wire out_f_woready_100 = out_woready_100 & out_womask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1116 = out_front_bits_data[17]; // @[RegisterRouter.scala:87:24]
wire _out_T_1119 = ~out_rimask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1120 = ~out_wimask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1121 = ~out_romask_100; // @[RegisterRouter.scala:87:24]
wire _out_T_1122 = ~out_womask_100; // @[RegisterRouter.scala:87:24]
wire [17:0] out_prepend_77 = {DMSTATUSRdData_allresumeack, _out_prepend_T_77}; // @[RegisterRouter.scala:87:24]
wire [17:0] _out_T_1123 = out_prepend_77; // @[RegisterRouter.scala:87:24]
wire [17:0] _out_T_1124 = _out_T_1123; // @[RegisterRouter.scala:87:24]
wire [17:0] _out_prepend_T_78 = _out_T_1124; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_101 = out_frontMask[18]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_101 = out_frontMask[18]; // @[RegisterRouter.scala:87:24]
wire out_rimask_101 = _out_rimask_T_101; // @[RegisterRouter.scala:87:24]
wire out_wimask_101 = _out_wimask_T_101; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_101 = out_backMask[18]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_101 = out_backMask[18]; // @[RegisterRouter.scala:87:24]
wire out_romask_101 = _out_romask_T_101; // @[RegisterRouter.scala:87:24]
wire out_womask_101 = _out_womask_T_101; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_101 = out_rivalid_101 & out_rimask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1126 = out_f_rivalid_101; // @[RegisterRouter.scala:87:24]
wire out_f_roready_101 = out_roready_101 & out_romask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1127 = out_f_roready_101; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_101 = out_wivalid_101 & out_wimask_101; // @[RegisterRouter.scala:87:24]
wire out_f_woready_101 = out_woready_101 & out_womask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1125 = out_front_bits_data[18]; // @[RegisterRouter.scala:87:24]
wire _out_T_1128 = ~out_rimask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1129 = ~out_wimask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1130 = ~out_romask_101; // @[RegisterRouter.scala:87:24]
wire _out_T_1131 = ~out_womask_101; // @[RegisterRouter.scala:87:24]
wire [18:0] out_prepend_78 = {DMSTATUSRdData_anyhavereset, _out_prepend_T_78}; // @[RegisterRouter.scala:87:24]
wire [18:0] _out_T_1132 = out_prepend_78; // @[RegisterRouter.scala:87:24]
wire [18:0] _out_T_1133 = _out_T_1132; // @[RegisterRouter.scala:87:24]
wire [18:0] _out_prepend_T_79 = _out_T_1133; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_102 = out_frontMask[19]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_102 = out_frontMask[19]; // @[RegisterRouter.scala:87:24]
wire out_rimask_102 = _out_rimask_T_102; // @[RegisterRouter.scala:87:24]
wire out_wimask_102 = _out_wimask_T_102; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_102 = out_backMask[19]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_102 = out_backMask[19]; // @[RegisterRouter.scala:87:24]
wire out_romask_102 = _out_romask_T_102; // @[RegisterRouter.scala:87:24]
wire out_womask_102 = _out_womask_T_102; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_102 = out_rivalid_102 & out_rimask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1135 = out_f_rivalid_102; // @[RegisterRouter.scala:87:24]
wire out_f_roready_102 = out_roready_102 & out_romask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1136 = out_f_roready_102; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_102 = out_wivalid_102 & out_wimask_102; // @[RegisterRouter.scala:87:24]
wire out_f_woready_102 = out_woready_102 & out_womask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1134 = out_front_bits_data[19]; // @[RegisterRouter.scala:87:24]
wire _out_T_1137 = ~out_rimask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1138 = ~out_wimask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1139 = ~out_romask_102; // @[RegisterRouter.scala:87:24]
wire _out_T_1140 = ~out_womask_102; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_79 = {DMSTATUSRdData_allhavereset, _out_prepend_T_79}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_1141 = out_prepend_79; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_1142 = _out_T_1141; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_prepend_T_80 = _out_T_1142; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_rimask_T_103 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_wimask_T_103 = out_frontMask[21:20]; // @[RegisterRouter.scala:87:24]
wire out_rimask_103 = |_out_rimask_T_103; // @[RegisterRouter.scala:87:24]
wire out_wimask_103 = &_out_wimask_T_103; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_romask_T_103 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_womask_T_103 = out_backMask[21:20]; // @[RegisterRouter.scala:87:24]
wire out_romask_103 = |_out_romask_T_103; // @[RegisterRouter.scala:87:24]
wire out_womask_103 = &_out_womask_T_103; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_103 = out_rivalid_103 & out_rimask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1144 = out_f_rivalid_103; // @[RegisterRouter.scala:87:24]
wire out_f_roready_103 = out_roready_103 & out_romask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1145 = out_f_roready_103; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_103 = out_wivalid_103 & out_wimask_103; // @[RegisterRouter.scala:87:24]
wire out_f_woready_103 = out_woready_103 & out_womask_103; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_1143 = out_front_bits_data[21:20]; // @[RegisterRouter.scala:87:24]
wire _out_T_1146 = ~out_rimask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1147 = ~out_wimask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1148 = ~out_romask_103; // @[RegisterRouter.scala:87:24]
wire _out_T_1149 = ~out_womask_103; // @[RegisterRouter.scala:87:24]
wire [20:0] out_prepend_80 = {1'h0, _out_prepend_T_80}; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_T_1150 = {1'h0, out_prepend_80}; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_T_1151 = _out_T_1150; // @[RegisterRouter.scala:87:24]
wire [21:0] _out_prepend_T_81 = _out_T_1151; // @[RegisterRouter.scala:87:24]
wire out_rimask_104 = _out_rimask_T_104; // @[RegisterRouter.scala:87:24]
wire out_wimask_104 = _out_wimask_T_104; // @[RegisterRouter.scala:87:24]
wire out_romask_104 = _out_romask_T_104; // @[RegisterRouter.scala:87:24]
wire out_womask_104 = _out_womask_T_104; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_104 = out_rivalid_104 & out_rimask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1153 = out_f_rivalid_104; // @[RegisterRouter.scala:87:24]
wire out_f_roready_104 = out_roready_104 & out_romask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1154 = out_f_roready_104; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_104 = out_wivalid_104 & out_wimask_104; // @[RegisterRouter.scala:87:24]
wire out_f_woready_104 = out_woready_104 & out_womask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1155 = ~out_rimask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1156 = ~out_wimask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1157 = ~out_romask_104; // @[RegisterRouter.scala:87:24]
wire _out_T_1158 = ~out_womask_104; // @[RegisterRouter.scala:87:24]
wire [22:0] out_prepend_81 = {1'h0, _out_prepend_T_81}; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_1159 = out_prepend_81; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_1160 = _out_T_1159; // @[RegisterRouter.scala:87:24]
wire out_rimask_105 = |_out_rimask_T_105; // @[RegisterRouter.scala:87:24]
wire out_wimask_105 = &_out_wimask_T_105; // @[RegisterRouter.scala:87:24]
wire out_romask_105 = |_out_romask_T_105; // @[RegisterRouter.scala:87:24]
wire out_womask_105 = &_out_womask_T_105; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_105 = out_rivalid_105 & out_rimask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1162 = out_f_rivalid_105; // @[RegisterRouter.scala:87:24]
assign out_f_roready_105 = out_roready_105 & out_romask_105; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_0 = out_f_roready_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1163 = out_f_roready_105; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_105 = out_wivalid_105 & out_wimask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1164 = out_f_wivalid_105; // @[RegisterRouter.scala:87:24]
assign out_f_woready_105 = out_woready_105 & out_womask_105; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_0 = out_f_woready_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1165 = out_f_woready_105; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_0 = out_f_woready_105 ? _out_T_1161 : programBufferMem_0; // @[RegisterRouter.scala:87:24]
wire _out_T_1166 = ~out_rimask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1167 = ~out_wimask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1168 = ~out_romask_105; // @[RegisterRouter.scala:87:24]
wire _out_T_1169 = ~out_womask_105; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1171 = _out_T_1170; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_82 = _out_T_1171; // @[RegisterRouter.scala:87:24]
wire out_rimask_106 = |_out_rimask_T_106; // @[RegisterRouter.scala:87:24]
wire out_wimask_106 = &_out_wimask_T_106; // @[RegisterRouter.scala:87:24]
wire out_romask_106 = |_out_romask_T_106; // @[RegisterRouter.scala:87:24]
wire out_womask_106 = &_out_womask_T_106; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_106 = out_rivalid_106 & out_rimask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1173 = out_f_rivalid_106; // @[RegisterRouter.scala:87:24]
assign out_f_roready_106 = out_roready_106 & out_romask_106; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_1 = out_f_roready_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1174 = out_f_roready_106; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_106 = out_wivalid_106 & out_wimask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1175 = out_f_wivalid_106; // @[RegisterRouter.scala:87:24]
assign out_f_woready_106 = out_woready_106 & out_womask_106; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_1 = out_f_woready_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1176 = out_f_woready_106; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_1 = out_f_woready_106 ? _out_T_1172 : programBufferMem_1; // @[RegisterRouter.scala:87:24]
wire _out_T_1177 = ~out_rimask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1178 = ~out_wimask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1179 = ~out_romask_106; // @[RegisterRouter.scala:87:24]
wire _out_T_1180 = ~out_womask_106; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_82 = {programBufferMem_1, _out_prepend_T_82}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1181 = out_prepend_82; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1182 = _out_T_1181; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_83 = _out_T_1182; // @[RegisterRouter.scala:87:24]
wire out_rimask_107 = |_out_rimask_T_107; // @[RegisterRouter.scala:87:24]
wire out_wimask_107 = &_out_wimask_T_107; // @[RegisterRouter.scala:87:24]
wire out_romask_107 = |_out_romask_T_107; // @[RegisterRouter.scala:87:24]
wire out_womask_107 = &_out_womask_T_107; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_107 = out_rivalid_107 & out_rimask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1184 = out_f_rivalid_107; // @[RegisterRouter.scala:87:24]
assign out_f_roready_107 = out_roready_107 & out_romask_107; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_2 = out_f_roready_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1185 = out_f_roready_107; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_107 = out_wivalid_107 & out_wimask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1186 = out_f_wivalid_107; // @[RegisterRouter.scala:87:24]
assign out_f_woready_107 = out_woready_107 & out_womask_107; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_2 = out_f_woready_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1187 = out_f_woready_107; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_2 = out_f_woready_107 ? _out_T_1183 : programBufferMem_2; // @[RegisterRouter.scala:87:24]
wire _out_T_1188 = ~out_rimask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1189 = ~out_wimask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1190 = ~out_romask_107; // @[RegisterRouter.scala:87:24]
wire _out_T_1191 = ~out_womask_107; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_83 = {programBufferMem_2, _out_prepend_T_83}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1192 = out_prepend_83; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1193 = _out_T_1192; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_84 = _out_T_1193; // @[RegisterRouter.scala:87:24]
wire out_rimask_108 = |_out_rimask_T_108; // @[RegisterRouter.scala:87:24]
wire out_wimask_108 = &_out_wimask_T_108; // @[RegisterRouter.scala:87:24]
wire out_romask_108 = |_out_romask_T_108; // @[RegisterRouter.scala:87:24]
wire out_womask_108 = &_out_womask_T_108; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_108 = out_rivalid_108 & out_rimask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1195 = out_f_rivalid_108; // @[RegisterRouter.scala:87:24]
assign out_f_roready_108 = out_roready_108 & out_romask_108; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_3 = out_f_roready_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1196 = out_f_roready_108; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_108 = out_wivalid_108 & out_wimask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1197 = out_f_wivalid_108; // @[RegisterRouter.scala:87:24]
assign out_f_woready_108 = out_woready_108 & out_womask_108; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_3 = out_f_woready_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1198 = out_f_woready_108; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_3 = out_f_woready_108 ? _out_T_1194 : programBufferMem_3; // @[RegisterRouter.scala:87:24]
wire _out_T_1199 = ~out_rimask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1200 = ~out_wimask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1201 = ~out_romask_108; // @[RegisterRouter.scala:87:24]
wire _out_T_1202 = ~out_womask_108; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_84 = {programBufferMem_3, _out_prepend_T_84}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1203 = out_prepend_84; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1204 = _out_T_1203; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_32 = _out_T_1204; // @[MuxLiteral.scala:49:48]
wire out_rimask_109 = |_out_rimask_T_109; // @[RegisterRouter.scala:87:24]
wire out_wimask_109 = &_out_wimask_T_109; // @[RegisterRouter.scala:87:24]
wire out_romask_109 = |_out_romask_T_109; // @[RegisterRouter.scala:87:24]
wire out_womask_109 = &_out_womask_T_109; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_109 = out_rivalid_109 & out_rimask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1206 = out_f_rivalid_109; // @[RegisterRouter.scala:87:24]
assign out_f_roready_109 = out_roready_109 & out_romask_109; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_8 = out_f_roready_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1207 = out_f_roready_109; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_109 = out_wivalid_109 & out_wimask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1208 = out_f_wivalid_109; // @[RegisterRouter.scala:87:24]
assign out_f_woready_109 = out_woready_109 & out_womask_109; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_8 = out_f_woready_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1209 = out_f_woready_109; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_8 = out_f_woready_109 ? _out_T_1205 : programBufferMem_8; // @[RegisterRouter.scala:87:24]
wire _out_T_1210 = ~out_rimask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1211 = ~out_wimask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1212 = ~out_romask_109; // @[RegisterRouter.scala:87:24]
wire _out_T_1213 = ~out_womask_109; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1215 = _out_T_1214; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_85 = _out_T_1215; // @[RegisterRouter.scala:87:24]
wire out_rimask_110 = |_out_rimask_T_110; // @[RegisterRouter.scala:87:24]
wire out_wimask_110 = &_out_wimask_T_110; // @[RegisterRouter.scala:87:24]
wire out_romask_110 = |_out_romask_T_110; // @[RegisterRouter.scala:87:24]
wire out_womask_110 = &_out_womask_T_110; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_110 = out_rivalid_110 & out_rimask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1217 = out_f_rivalid_110; // @[RegisterRouter.scala:87:24]
assign out_f_roready_110 = out_roready_110 & out_romask_110; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_9 = out_f_roready_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1218 = out_f_roready_110; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_110 = out_wivalid_110 & out_wimask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1219 = out_f_wivalid_110; // @[RegisterRouter.scala:87:24]
assign out_f_woready_110 = out_woready_110 & out_womask_110; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_9 = out_f_woready_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1220 = out_f_woready_110; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_9 = out_f_woready_110 ? _out_T_1216 : programBufferMem_9; // @[RegisterRouter.scala:87:24]
wire _out_T_1221 = ~out_rimask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1222 = ~out_wimask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1223 = ~out_romask_110; // @[RegisterRouter.scala:87:24]
wire _out_T_1224 = ~out_womask_110; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_85 = {programBufferMem_9, _out_prepend_T_85}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1225 = out_prepend_85; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1226 = _out_T_1225; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_86 = _out_T_1226; // @[RegisterRouter.scala:87:24]
wire out_rimask_111 = |_out_rimask_T_111; // @[RegisterRouter.scala:87:24]
wire out_wimask_111 = &_out_wimask_T_111; // @[RegisterRouter.scala:87:24]
wire out_romask_111 = |_out_romask_T_111; // @[RegisterRouter.scala:87:24]
wire out_womask_111 = &_out_womask_T_111; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_111 = out_rivalid_111 & out_rimask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1228 = out_f_rivalid_111; // @[RegisterRouter.scala:87:24]
assign out_f_roready_111 = out_roready_111 & out_romask_111; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_10 = out_f_roready_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1229 = out_f_roready_111; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_111 = out_wivalid_111 & out_wimask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1230 = out_f_wivalid_111; // @[RegisterRouter.scala:87:24]
assign out_f_woready_111 = out_woready_111 & out_womask_111; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_10 = out_f_woready_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1231 = out_f_woready_111; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_10 = out_f_woready_111 ? _out_T_1227 : programBufferMem_10; // @[RegisterRouter.scala:87:24]
wire _out_T_1232 = ~out_rimask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1233 = ~out_wimask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1234 = ~out_romask_111; // @[RegisterRouter.scala:87:24]
wire _out_T_1235 = ~out_womask_111; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_86 = {programBufferMem_10, _out_prepend_T_86}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1236 = out_prepend_86; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1237 = _out_T_1236; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_87 = _out_T_1237; // @[RegisterRouter.scala:87:24]
wire out_rimask_112 = |_out_rimask_T_112; // @[RegisterRouter.scala:87:24]
wire out_wimask_112 = &_out_wimask_T_112; // @[RegisterRouter.scala:87:24]
wire out_romask_112 = |_out_romask_T_112; // @[RegisterRouter.scala:87:24]
wire out_womask_112 = &_out_womask_T_112; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_112 = out_rivalid_112 & out_rimask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1239 = out_f_rivalid_112; // @[RegisterRouter.scala:87:24]
assign out_f_roready_112 = out_roready_112 & out_romask_112; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_11 = out_f_roready_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1240 = out_f_roready_112; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_112 = out_wivalid_112 & out_wimask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1241 = out_f_wivalid_112; // @[RegisterRouter.scala:87:24]
assign out_f_woready_112 = out_woready_112 & out_womask_112; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_11 = out_f_woready_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1242 = out_f_woready_112; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_11 = out_f_woready_112 ? _out_T_1238 : programBufferMem_11; // @[RegisterRouter.scala:87:24]
wire _out_T_1243 = ~out_rimask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1244 = ~out_wimask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1245 = ~out_romask_112; // @[RegisterRouter.scala:87:24]
wire _out_T_1246 = ~out_womask_112; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_87 = {programBufferMem_11, _out_prepend_T_87}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1247 = out_prepend_87; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1248 = _out_T_1247; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_34 = _out_T_1248; // @[MuxLiteral.scala:49:48]
wire out_rimask_113 = |_out_rimask_T_113; // @[RegisterRouter.scala:87:24]
wire out_wimask_113 = &_out_wimask_T_113; // @[RegisterRouter.scala:87:24]
wire out_romask_113 = |_out_romask_T_113; // @[RegisterRouter.scala:87:24]
wire out_womask_113 = &_out_womask_T_113; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_113 = out_rivalid_113 & out_rimask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1250 = out_f_rivalid_113; // @[RegisterRouter.scala:87:24]
wire out_f_roready_113 = out_roready_113 & out_romask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1251 = out_f_roready_113; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_113 = out_wivalid_113 & out_wimask_113; // @[RegisterRouter.scala:87:24]
wire out_f_woready_113 = out_woready_113 & out_womask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1252 = ~out_rimask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1253 = ~out_wimask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1254 = ~out_romask_113; // @[RegisterRouter.scala:87:24]
wire _out_T_1255 = ~out_womask_113; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_114 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_114 = out_frontMask[7:4]; // @[RegisterRouter.scala:87:24]
wire out_rimask_114 = |_out_rimask_T_114; // @[RegisterRouter.scala:87:24]
wire out_wimask_114 = &_out_wimask_T_114; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_114 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_114 = out_backMask[7:4]; // @[RegisterRouter.scala:87:24]
wire out_romask_114 = |_out_romask_T_114; // @[RegisterRouter.scala:87:24]
wire out_womask_114 = &_out_womask_T_114; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_114 = out_rivalid_114 & out_rimask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1259 = out_f_rivalid_114; // @[RegisterRouter.scala:87:24]
wire out_f_roready_114 = out_roready_114 & out_romask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1260 = out_f_roready_114; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_114 = out_wivalid_114 & out_wimask_114; // @[RegisterRouter.scala:87:24]
wire out_f_woready_114 = out_woready_114 & out_womask_114; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_1258 = out_front_bits_data[7:4]; // @[RegisterRouter.scala:87:24]
wire _out_T_1261 = ~out_rimask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1262 = ~out_wimask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1263 = ~out_romask_114; // @[RegisterRouter.scala:87:24]
wire _out_T_1264 = ~out_womask_114; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_115 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_115 = out_frontMask[10:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_115 = |_out_rimask_T_115; // @[RegisterRouter.scala:87:24]
wire out_wimask_115 = &_out_wimask_T_115; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_115 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_115 = out_backMask[10:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_115 = |_out_romask_T_115; // @[RegisterRouter.scala:87:24]
wire out_womask_115 = &_out_womask_T_115; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_115 = out_rivalid_115 & out_rimask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1268 = out_f_rivalid_115; // @[RegisterRouter.scala:87:24]
wire out_f_roready_115 = out_roready_115 & out_romask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1269 = out_f_roready_115; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_115 = out_wivalid_115 & out_wimask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1270 = out_f_wivalid_115; // @[RegisterRouter.scala:87:24]
assign out_f_woready_115 = out_woready_115 & out_womask_115; // @[RegisterRouter.scala:87:24]
assign ABSTRACTCSWrEnMaybe = out_f_woready_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1271 = out_f_woready_115; // @[RegisterRouter.scala:87:24]
assign _out_T_1267 = out_front_bits_data[10:8]; // @[RegisterRouter.scala:87:24]
assign ABSTRACTCSWrData_cmderr = _out_T_1267; // @[RegisterRouter.scala:87:24]
wire _out_T_1272 = ~out_rimask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1273 = ~out_wimask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1274 = ~out_romask_115; // @[RegisterRouter.scala:87:24]
wire _out_T_1275 = ~out_womask_115; // @[RegisterRouter.scala:87:24]
wire [10:0] out_prepend_89 = {ABSTRACTCSRdData_cmderr, 8'h8}; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1276 = out_prepend_89; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1277 = _out_T_1276; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_prepend_T_90 = _out_T_1277; // @[RegisterRouter.scala:87:24]
wire out_rimask_116 = _out_rimask_T_116; // @[RegisterRouter.scala:87:24]
wire out_wimask_116 = _out_wimask_T_116; // @[RegisterRouter.scala:87:24]
wire out_romask_116 = _out_romask_T_116; // @[RegisterRouter.scala:87:24]
wire out_womask_116 = _out_womask_T_116; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_116 = out_rivalid_116 & out_rimask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1279 = out_f_rivalid_116; // @[RegisterRouter.scala:87:24]
wire out_f_roready_116 = out_roready_116 & out_romask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1280 = out_f_roready_116; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_116 = out_wivalid_116 & out_wimask_116; // @[RegisterRouter.scala:87:24]
wire out_f_woready_116 = out_woready_116 & out_womask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1281 = ~out_rimask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1282 = ~out_wimask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1283 = ~out_romask_116; // @[RegisterRouter.scala:87:24]
wire _out_T_1284 = ~out_womask_116; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend_90 = {1'h0, _out_prepend_T_90}; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_1285 = out_prepend_90; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_1286 = _out_T_1285; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_prepend_T_91 = _out_T_1286; // @[RegisterRouter.scala:87:24]
wire out_rimask_117 = _out_rimask_T_117; // @[RegisterRouter.scala:87:24]
wire out_wimask_117 = _out_wimask_T_117; // @[RegisterRouter.scala:87:24]
wire out_romask_117 = _out_romask_T_117; // @[RegisterRouter.scala:87:24]
wire out_womask_117 = _out_womask_T_117; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_117 = out_rivalid_117 & out_rimask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1288 = out_f_rivalid_117; // @[RegisterRouter.scala:87:24]
wire out_f_roready_117 = out_roready_117 & out_romask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1289 = out_f_roready_117; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_117 = out_wivalid_117 & out_wimask_117; // @[RegisterRouter.scala:87:24]
wire out_f_woready_117 = out_woready_117 & out_womask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1290 = ~out_rimask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1291 = ~out_wimask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1292 = ~out_romask_117; // @[RegisterRouter.scala:87:24]
wire _out_T_1293 = ~out_womask_117; // @[RegisterRouter.scala:87:24]
wire [12:0] out_prepend_91 = {ABSTRACTCSRdData_busy, _out_prepend_T_91}; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_T_1294 = out_prepend_91; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_T_1295 = _out_T_1294; // @[RegisterRouter.scala:87:24]
wire [12:0] _out_prepend_T_92 = _out_T_1295; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_rimask_T_118 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_wimask_T_118 = out_frontMask[23:13]; // @[RegisterRouter.scala:87:24]
wire out_rimask_118 = |_out_rimask_T_118; // @[RegisterRouter.scala:87:24]
wire out_wimask_118 = &_out_wimask_T_118; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_romask_T_118 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_womask_T_118 = out_backMask[23:13]; // @[RegisterRouter.scala:87:24]
wire out_romask_118 = |_out_romask_T_118; // @[RegisterRouter.scala:87:24]
wire out_womask_118 = &_out_womask_T_118; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_118 = out_rivalid_118 & out_rimask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1297 = out_f_rivalid_118; // @[RegisterRouter.scala:87:24]
wire out_f_roready_118 = out_roready_118 & out_romask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1298 = out_f_roready_118; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_118 = out_wivalid_118 & out_wimask_118; // @[RegisterRouter.scala:87:24]
wire out_f_woready_118 = out_woready_118 & out_womask_118; // @[RegisterRouter.scala:87:24]
wire [10:0] _out_T_1296 = out_front_bits_data[23:13]; // @[RegisterRouter.scala:87:24]
wire _out_T_1299 = ~out_rimask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1300 = ~out_wimask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1301 = ~out_romask_118; // @[RegisterRouter.scala:87:24]
wire _out_T_1302 = ~out_womask_118; // @[RegisterRouter.scala:87:24]
wire [13:0] out_prepend_92 = {1'h0, _out_prepend_T_92}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1303 = {10'h0, out_prepend_92}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1304 = _out_T_1303; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_93 = _out_T_1304; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_rimask_T_119 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_wimask_T_119 = out_frontMask[28:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_119 = |_out_rimask_T_119; // @[RegisterRouter.scala:87:24]
wire out_wimask_119 = &_out_wimask_T_119; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_romask_T_119 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_womask_T_119 = out_backMask[28:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_119 = |_out_romask_T_119; // @[RegisterRouter.scala:87:24]
wire out_womask_119 = &_out_womask_T_119; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_119 = out_rivalid_119 & out_rimask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1306 = out_f_rivalid_119; // @[RegisterRouter.scala:87:24]
wire out_f_roready_119 = out_roready_119 & out_romask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1307 = out_f_roready_119; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_119 = out_wivalid_119 & out_wimask_119; // @[RegisterRouter.scala:87:24]
wire out_f_woready_119 = out_woready_119 & out_womask_119; // @[RegisterRouter.scala:87:24]
wire [4:0] _out_T_1305 = out_front_bits_data[28:24]; // @[RegisterRouter.scala:87:24]
wire _out_T_1308 = ~out_rimask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1309 = ~out_wimask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1310 = ~out_romask_119; // @[RegisterRouter.scala:87:24]
wire _out_T_1311 = ~out_womask_119; // @[RegisterRouter.scala:87:24]
wire [28:0] out_prepend_93 = {5'h10, _out_prepend_T_93}; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_1312 = out_prepend_93; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_1313 = _out_T_1312; // @[RegisterRouter.scala:87:24]
wire out_rimask_120 = |_out_rimask_T_120; // @[RegisterRouter.scala:87:24]
wire out_wimask_120 = &_out_wimask_T_120; // @[RegisterRouter.scala:87:24]
wire out_romask_120 = |_out_romask_T_120; // @[RegisterRouter.scala:87:24]
wire out_womask_120 = &_out_womask_T_120; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_120 = out_rivalid_120 & out_rimask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1315 = out_f_rivalid_120; // @[RegisterRouter.scala:87:24]
assign out_f_roready_120 = out_roready_120 & out_romask_120; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_48 = out_f_roready_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1316 = out_f_roready_120; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_120 = out_wivalid_120 & out_wimask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1317 = out_f_wivalid_120; // @[RegisterRouter.scala:87:24]
assign out_f_woready_120 = out_woready_120 & out_womask_120; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_48 = out_f_woready_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1318 = out_f_woready_120; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_48 = out_f_woready_120 ? _out_T_1314 : programBufferMem_48; // @[RegisterRouter.scala:87:24]
wire _out_T_1319 = ~out_rimask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1320 = ~out_wimask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1321 = ~out_romask_120; // @[RegisterRouter.scala:87:24]
wire _out_T_1322 = ~out_womask_120; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1324 = _out_T_1323; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_94 = _out_T_1324; // @[RegisterRouter.scala:87:24]
wire out_rimask_121 = |_out_rimask_T_121; // @[RegisterRouter.scala:87:24]
wire out_wimask_121 = &_out_wimask_T_121; // @[RegisterRouter.scala:87:24]
wire out_romask_121 = |_out_romask_T_121; // @[RegisterRouter.scala:87:24]
wire out_womask_121 = &_out_womask_T_121; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_121 = out_rivalid_121 & out_rimask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1326 = out_f_rivalid_121; // @[RegisterRouter.scala:87:24]
assign out_f_roready_121 = out_roready_121 & out_romask_121; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_49 = out_f_roready_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1327 = out_f_roready_121; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_121 = out_wivalid_121 & out_wimask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1328 = out_f_wivalid_121; // @[RegisterRouter.scala:87:24]
assign out_f_woready_121 = out_woready_121 & out_womask_121; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_49 = out_f_woready_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1329 = out_f_woready_121; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_49 = out_f_woready_121 ? _out_T_1325 : programBufferMem_49; // @[RegisterRouter.scala:87:24]
wire _out_T_1330 = ~out_rimask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1331 = ~out_wimask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1332 = ~out_romask_121; // @[RegisterRouter.scala:87:24]
wire _out_T_1333 = ~out_womask_121; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_94 = {programBufferMem_49, _out_prepend_T_94}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1334 = out_prepend_94; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1335 = _out_T_1334; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_95 = _out_T_1335; // @[RegisterRouter.scala:87:24]
wire out_rimask_122 = |_out_rimask_T_122; // @[RegisterRouter.scala:87:24]
wire out_wimask_122 = &_out_wimask_T_122; // @[RegisterRouter.scala:87:24]
wire out_romask_122 = |_out_romask_T_122; // @[RegisterRouter.scala:87:24]
wire out_womask_122 = &_out_womask_T_122; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_122 = out_rivalid_122 & out_rimask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1337 = out_f_rivalid_122; // @[RegisterRouter.scala:87:24]
assign out_f_roready_122 = out_roready_122 & out_romask_122; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_50 = out_f_roready_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1338 = out_f_roready_122; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_122 = out_wivalid_122 & out_wimask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1339 = out_f_wivalid_122; // @[RegisterRouter.scala:87:24]
assign out_f_woready_122 = out_woready_122 & out_womask_122; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_50 = out_f_woready_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1340 = out_f_woready_122; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_50 = out_f_woready_122 ? _out_T_1336 : programBufferMem_50; // @[RegisterRouter.scala:87:24]
wire _out_T_1341 = ~out_rimask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1342 = ~out_wimask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1343 = ~out_romask_122; // @[RegisterRouter.scala:87:24]
wire _out_T_1344 = ~out_womask_122; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_95 = {programBufferMem_50, _out_prepend_T_95}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1345 = out_prepend_95; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1346 = _out_T_1345; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_96 = _out_T_1346; // @[RegisterRouter.scala:87:24]
wire out_rimask_123 = |_out_rimask_T_123; // @[RegisterRouter.scala:87:24]
wire out_wimask_123 = &_out_wimask_T_123; // @[RegisterRouter.scala:87:24]
wire out_romask_123 = |_out_romask_T_123; // @[RegisterRouter.scala:87:24]
wire out_womask_123 = &_out_womask_T_123; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_123 = out_rivalid_123 & out_rimask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1348 = out_f_rivalid_123; // @[RegisterRouter.scala:87:24]
assign out_f_roready_123 = out_roready_123 & out_romask_123; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_51 = out_f_roready_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1349 = out_f_roready_123; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_123 = out_wivalid_123 & out_wimask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1350 = out_f_wivalid_123; // @[RegisterRouter.scala:87:24]
assign out_f_woready_123 = out_woready_123 & out_womask_123; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_51 = out_f_woready_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1351 = out_f_woready_123; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_51 = out_f_woready_123 ? _out_T_1347 : programBufferMem_51; // @[RegisterRouter.scala:87:24]
wire _out_T_1352 = ~out_rimask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1353 = ~out_wimask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1354 = ~out_romask_123; // @[RegisterRouter.scala:87:24]
wire _out_T_1355 = ~out_womask_123; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_96 = {programBufferMem_51, _out_prepend_T_96}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1356 = out_prepend_96; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1357 = _out_T_1356; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_44 = _out_T_1357; // @[MuxLiteral.scala:49:48]
wire out_rimask_124 = |_out_rimask_T_124; // @[RegisterRouter.scala:87:24]
wire out_wimask_124 = &_out_wimask_T_124; // @[RegisterRouter.scala:87:24]
wire out_romask_124 = |_out_romask_T_124; // @[RegisterRouter.scala:87:24]
wire out_womask_124 = &_out_womask_T_124; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_124 = out_rivalid_124 & out_rimask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1359 = out_f_rivalid_124; // @[RegisterRouter.scala:87:24]
assign out_f_roready_124 = out_roready_124 & out_romask_124; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_12 = out_f_roready_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1360 = out_f_roready_124; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_124 = out_wivalid_124 & out_wimask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1361 = out_f_wivalid_124; // @[RegisterRouter.scala:87:24]
assign out_f_woready_124 = out_woready_124 & out_womask_124; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_12 = out_f_woready_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1362 = out_f_woready_124; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_12 = out_f_woready_124 ? _out_T_1358 : abstractDataMem_12; // @[RegisterRouter.scala:87:24]
wire _out_T_1363 = ~out_rimask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1364 = ~out_wimask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1365 = ~out_romask_124; // @[RegisterRouter.scala:87:24]
wire _out_T_1366 = ~out_womask_124; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1368 = _out_T_1367; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_97 = _out_T_1368; // @[RegisterRouter.scala:87:24]
wire out_rimask_125 = |_out_rimask_T_125; // @[RegisterRouter.scala:87:24]
wire out_wimask_125 = &_out_wimask_T_125; // @[RegisterRouter.scala:87:24]
wire out_romask_125 = |_out_romask_T_125; // @[RegisterRouter.scala:87:24]
wire out_womask_125 = &_out_womask_T_125; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_125 = out_rivalid_125 & out_rimask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1370 = out_f_rivalid_125; // @[RegisterRouter.scala:87:24]
assign out_f_roready_125 = out_roready_125 & out_romask_125; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_13 = out_f_roready_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1371 = out_f_roready_125; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_125 = out_wivalid_125 & out_wimask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1372 = out_f_wivalid_125; // @[RegisterRouter.scala:87:24]
assign out_f_woready_125 = out_woready_125 & out_womask_125; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_13 = out_f_woready_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1373 = out_f_woready_125; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_13 = out_f_woready_125 ? _out_T_1369 : abstractDataMem_13; // @[RegisterRouter.scala:87:24]
wire _out_T_1374 = ~out_rimask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1375 = ~out_wimask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1376 = ~out_romask_125; // @[RegisterRouter.scala:87:24]
wire _out_T_1377 = ~out_womask_125; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_97 = {abstractDataMem_13, _out_prepend_T_97}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1378 = out_prepend_97; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1379 = _out_T_1378; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_98 = _out_T_1379; // @[RegisterRouter.scala:87:24]
wire out_rimask_126 = |_out_rimask_T_126; // @[RegisterRouter.scala:87:24]
wire out_wimask_126 = &_out_wimask_T_126; // @[RegisterRouter.scala:87:24]
wire out_romask_126 = |_out_romask_T_126; // @[RegisterRouter.scala:87:24]
wire out_womask_126 = &_out_womask_T_126; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_126 = out_rivalid_126 & out_rimask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1381 = out_f_rivalid_126; // @[RegisterRouter.scala:87:24]
assign out_f_roready_126 = out_roready_126 & out_romask_126; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_14 = out_f_roready_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1382 = out_f_roready_126; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_126 = out_wivalid_126 & out_wimask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1383 = out_f_wivalid_126; // @[RegisterRouter.scala:87:24]
assign out_f_woready_126 = out_woready_126 & out_womask_126; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_14 = out_f_woready_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1384 = out_f_woready_126; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_14 = out_f_woready_126 ? _out_T_1380 : abstractDataMem_14; // @[RegisterRouter.scala:87:24]
wire _out_T_1385 = ~out_rimask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1386 = ~out_wimask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1387 = ~out_romask_126; // @[RegisterRouter.scala:87:24]
wire _out_T_1388 = ~out_womask_126; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_98 = {abstractDataMem_14, _out_prepend_T_98}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1389 = out_prepend_98; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1390 = _out_T_1389; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_99 = _out_T_1390; // @[RegisterRouter.scala:87:24]
wire out_rimask_127 = |_out_rimask_T_127; // @[RegisterRouter.scala:87:24]
wire out_wimask_127 = &_out_wimask_T_127; // @[RegisterRouter.scala:87:24]
wire out_romask_127 = |_out_romask_T_127; // @[RegisterRouter.scala:87:24]
wire out_womask_127 = &_out_womask_T_127; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_127 = out_rivalid_127 & out_rimask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1392 = out_f_rivalid_127; // @[RegisterRouter.scala:87:24]
assign out_f_roready_127 = out_roready_127 & out_romask_127; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_15 = out_f_roready_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1393 = out_f_roready_127; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_127 = out_wivalid_127 & out_wimask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1394 = out_f_wivalid_127; // @[RegisterRouter.scala:87:24]
assign out_f_woready_127 = out_woready_127 & out_womask_127; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_15 = out_f_woready_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1395 = out_f_woready_127; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_15 = out_f_woready_127 ? _out_T_1391 : abstractDataMem_15; // @[RegisterRouter.scala:87:24]
wire _out_T_1396 = ~out_rimask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1397 = ~out_wimask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1398 = ~out_romask_127; // @[RegisterRouter.scala:87:24]
wire _out_T_1399 = ~out_womask_127; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_99 = {abstractDataMem_15, _out_prepend_T_99}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1400 = out_prepend_99; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1401 = _out_T_1400; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_7 = _out_T_1401; // @[MuxLiteral.scala:49:48]
wire out_rimask_128 = |_out_rimask_T_128; // @[RegisterRouter.scala:87:24]
wire out_wimask_128 = &_out_wimask_T_128; // @[RegisterRouter.scala:87:24]
wire out_romask_128 = |_out_romask_T_128; // @[RegisterRouter.scala:87:24]
wire out_womask_128 = &_out_womask_T_128; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_128 = out_rivalid_128 & out_rimask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1403 = out_f_rivalid_128; // @[RegisterRouter.scala:87:24]
assign out_f_roready_128 = out_roready_128 & out_romask_128; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_28 = out_f_roready_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1404 = out_f_roready_128; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_128 = out_wivalid_128 & out_wimask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1405 = out_f_wivalid_128; // @[RegisterRouter.scala:87:24]
assign out_f_woready_128 = out_woready_128 & out_womask_128; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_28 = out_f_woready_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1406 = out_f_woready_128; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_28 = out_f_woready_128 ? _out_T_1402 : programBufferMem_28; // @[RegisterRouter.scala:87:24]
wire _out_T_1407 = ~out_rimask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1408 = ~out_wimask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1409 = ~out_romask_128; // @[RegisterRouter.scala:87:24]
wire _out_T_1410 = ~out_womask_128; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1412 = _out_T_1411; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_100 = _out_T_1412; // @[RegisterRouter.scala:87:24]
wire out_rimask_129 = |_out_rimask_T_129; // @[RegisterRouter.scala:87:24]
wire out_wimask_129 = &_out_wimask_T_129; // @[RegisterRouter.scala:87:24]
wire out_romask_129 = |_out_romask_T_129; // @[RegisterRouter.scala:87:24]
wire out_womask_129 = &_out_womask_T_129; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_129 = out_rivalid_129 & out_rimask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1414 = out_f_rivalid_129; // @[RegisterRouter.scala:87:24]
assign out_f_roready_129 = out_roready_129 & out_romask_129; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_29 = out_f_roready_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1415 = out_f_roready_129; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_129 = out_wivalid_129 & out_wimask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1416 = out_f_wivalid_129; // @[RegisterRouter.scala:87:24]
assign out_f_woready_129 = out_woready_129 & out_womask_129; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_29 = out_f_woready_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1417 = out_f_woready_129; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_29 = out_f_woready_129 ? _out_T_1413 : programBufferMem_29; // @[RegisterRouter.scala:87:24]
wire _out_T_1418 = ~out_rimask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1419 = ~out_wimask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1420 = ~out_romask_129; // @[RegisterRouter.scala:87:24]
wire _out_T_1421 = ~out_womask_129; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_100 = {programBufferMem_29, _out_prepend_T_100}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1422 = out_prepend_100; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1423 = _out_T_1422; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_101 = _out_T_1423; // @[RegisterRouter.scala:87:24]
wire out_rimask_130 = |_out_rimask_T_130; // @[RegisterRouter.scala:87:24]
wire out_wimask_130 = &_out_wimask_T_130; // @[RegisterRouter.scala:87:24]
wire out_romask_130 = |_out_romask_T_130; // @[RegisterRouter.scala:87:24]
wire out_womask_130 = &_out_womask_T_130; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_130 = out_rivalid_130 & out_rimask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1425 = out_f_rivalid_130; // @[RegisterRouter.scala:87:24]
assign out_f_roready_130 = out_roready_130 & out_romask_130; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_30 = out_f_roready_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1426 = out_f_roready_130; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_130 = out_wivalid_130 & out_wimask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1427 = out_f_wivalid_130; // @[RegisterRouter.scala:87:24]
assign out_f_woready_130 = out_woready_130 & out_womask_130; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_30 = out_f_woready_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1428 = out_f_woready_130; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_30 = out_f_woready_130 ? _out_T_1424 : programBufferMem_30; // @[RegisterRouter.scala:87:24]
wire _out_T_1429 = ~out_rimask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1430 = ~out_wimask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1431 = ~out_romask_130; // @[RegisterRouter.scala:87:24]
wire _out_T_1432 = ~out_womask_130; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_101 = {programBufferMem_30, _out_prepend_T_101}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1433 = out_prepend_101; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1434 = _out_T_1433; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_102 = _out_T_1434; // @[RegisterRouter.scala:87:24]
wire out_rimask_131 = |_out_rimask_T_131; // @[RegisterRouter.scala:87:24]
wire out_wimask_131 = &_out_wimask_T_131; // @[RegisterRouter.scala:87:24]
wire out_romask_131 = |_out_romask_T_131; // @[RegisterRouter.scala:87:24]
wire out_womask_131 = &_out_womask_T_131; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_131 = out_rivalid_131 & out_rimask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1436 = out_f_rivalid_131; // @[RegisterRouter.scala:87:24]
assign out_f_roready_131 = out_roready_131 & out_romask_131; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_31 = out_f_roready_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1437 = out_f_roready_131; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_131 = out_wivalid_131 & out_wimask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1438 = out_f_wivalid_131; // @[RegisterRouter.scala:87:24]
assign out_f_woready_131 = out_woready_131 & out_womask_131; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_31 = out_f_woready_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1439 = out_f_woready_131; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_31 = out_f_woready_131 ? _out_T_1435 : programBufferMem_31; // @[RegisterRouter.scala:87:24]
wire _out_T_1440 = ~out_rimask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1441 = ~out_wimask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1442 = ~out_romask_131; // @[RegisterRouter.scala:87:24]
wire _out_T_1443 = ~out_womask_131; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_102 = {programBufferMem_31, _out_prepend_T_102}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1444 = out_prepend_102; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1445 = _out_T_1444; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_39 = _out_T_1445; // @[MuxLiteral.scala:49:48]
wire out_rimask_132 = |_out_rimask_T_132; // @[RegisterRouter.scala:87:24]
wire out_wimask_132 = &_out_wimask_T_132; // @[RegisterRouter.scala:87:24]
wire out_romask_132 = |_out_romask_T_132; // @[RegisterRouter.scala:87:24]
wire out_womask_132 = &_out_womask_T_132; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_132 = out_rivalid_132 & out_rimask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1447 = out_f_rivalid_132; // @[RegisterRouter.scala:87:24]
assign out_f_roready_132 = out_roready_132 & out_romask_132; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_28 = out_f_roready_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1448 = out_f_roready_132; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_132 = out_wivalid_132 & out_wimask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1449 = out_f_wivalid_132; // @[RegisterRouter.scala:87:24]
assign out_f_woready_132 = out_woready_132 & out_womask_132; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_28 = out_f_woready_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1450 = out_f_woready_132; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_28 = out_f_woready_132 ? _out_T_1446 : abstractDataMem_28; // @[RegisterRouter.scala:87:24]
wire _out_T_1451 = ~out_rimask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1452 = ~out_wimask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1453 = ~out_romask_132; // @[RegisterRouter.scala:87:24]
wire _out_T_1454 = ~out_womask_132; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1456 = _out_T_1455; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_103 = _out_T_1456; // @[RegisterRouter.scala:87:24]
wire out_rimask_133 = |_out_rimask_T_133; // @[RegisterRouter.scala:87:24]
wire out_wimask_133 = &_out_wimask_T_133; // @[RegisterRouter.scala:87:24]
wire out_romask_133 = |_out_romask_T_133; // @[RegisterRouter.scala:87:24]
wire out_womask_133 = &_out_womask_T_133; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_133 = out_rivalid_133 & out_rimask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1458 = out_f_rivalid_133; // @[RegisterRouter.scala:87:24]
assign out_f_roready_133 = out_roready_133 & out_romask_133; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_29 = out_f_roready_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1459 = out_f_roready_133; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_133 = out_wivalid_133 & out_wimask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1460 = out_f_wivalid_133; // @[RegisterRouter.scala:87:24]
assign out_f_woready_133 = out_woready_133 & out_womask_133; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_29 = out_f_woready_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1461 = out_f_woready_133; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_29 = out_f_woready_133 ? _out_T_1457 : abstractDataMem_29; // @[RegisterRouter.scala:87:24]
wire _out_T_1462 = ~out_rimask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1463 = ~out_wimask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1464 = ~out_romask_133; // @[RegisterRouter.scala:87:24]
wire _out_T_1465 = ~out_womask_133; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_103 = {abstractDataMem_29, _out_prepend_T_103}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1466 = out_prepend_103; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1467 = _out_T_1466; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_104 = _out_T_1467; // @[RegisterRouter.scala:87:24]
wire out_rimask_134 = |_out_rimask_T_134; // @[RegisterRouter.scala:87:24]
wire out_wimask_134 = &_out_wimask_T_134; // @[RegisterRouter.scala:87:24]
wire out_romask_134 = |_out_romask_T_134; // @[RegisterRouter.scala:87:24]
wire out_womask_134 = &_out_womask_T_134; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_134 = out_rivalid_134 & out_rimask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1469 = out_f_rivalid_134; // @[RegisterRouter.scala:87:24]
assign out_f_roready_134 = out_roready_134 & out_romask_134; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_30 = out_f_roready_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1470 = out_f_roready_134; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_134 = out_wivalid_134 & out_wimask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1471 = out_f_wivalid_134; // @[RegisterRouter.scala:87:24]
assign out_f_woready_134 = out_woready_134 & out_womask_134; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_30 = out_f_woready_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1472 = out_f_woready_134; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_30 = out_f_woready_134 ? _out_T_1468 : abstractDataMem_30; // @[RegisterRouter.scala:87:24]
wire _out_T_1473 = ~out_rimask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1474 = ~out_wimask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1475 = ~out_romask_134; // @[RegisterRouter.scala:87:24]
wire _out_T_1476 = ~out_womask_134; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_104 = {abstractDataMem_30, _out_prepend_T_104}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1477 = out_prepend_104; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1478 = _out_T_1477; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_105 = _out_T_1478; // @[RegisterRouter.scala:87:24]
wire out_rimask_135 = |_out_rimask_T_135; // @[RegisterRouter.scala:87:24]
wire out_wimask_135 = &_out_wimask_T_135; // @[RegisterRouter.scala:87:24]
wire out_romask_135 = |_out_romask_T_135; // @[RegisterRouter.scala:87:24]
wire out_womask_135 = &_out_womask_T_135; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_135 = out_rivalid_135 & out_rimask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1480 = out_f_rivalid_135; // @[RegisterRouter.scala:87:24]
assign out_f_roready_135 = out_roready_135 & out_romask_135; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataRdEn_31 = out_f_roready_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1481 = out_f_roready_135; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_135 = out_wivalid_135 & out_wimask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1482 = out_f_wivalid_135; // @[RegisterRouter.scala:87:24]
assign out_f_woready_135 = out_woready_135 & out_womask_135; // @[RegisterRouter.scala:87:24]
assign dmiAbstractDataWrEnMaybe_31 = out_f_woready_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1483 = out_f_woready_135; // @[RegisterRouter.scala:87:24]
assign abstractDataNxt_31 = out_f_woready_135 ? _out_T_1479 : abstractDataMem_31; // @[RegisterRouter.scala:87:24]
wire _out_T_1484 = ~out_rimask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1485 = ~out_wimask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1486 = ~out_romask_135; // @[RegisterRouter.scala:87:24]
wire _out_T_1487 = ~out_womask_135; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_105 = {abstractDataMem_31, _out_prepend_T_105}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1488 = out_prepend_105; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1489 = _out_T_1488; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_11 = _out_T_1489; // @[MuxLiteral.scala:49:48]
wire out_rimask_136 = |_out_rimask_T_136; // @[RegisterRouter.scala:87:24]
wire out_wimask_136 = &_out_wimask_T_136; // @[RegisterRouter.scala:87:24]
wire out_romask_136 = |_out_romask_T_136; // @[RegisterRouter.scala:87:24]
wire out_womask_136 = &_out_womask_T_136; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_136 = out_rivalid_136 & out_rimask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1491 = out_f_rivalid_136; // @[RegisterRouter.scala:87:24]
assign out_f_roready_136 = out_roready_136 & out_romask_136; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_44 = out_f_roready_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1492 = out_f_roready_136; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_136 = out_wivalid_136 & out_wimask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1493 = out_f_wivalid_136; // @[RegisterRouter.scala:87:24]
assign out_f_woready_136 = out_woready_136 & out_womask_136; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_44 = out_f_woready_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1494 = out_f_woready_136; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_44 = out_f_woready_136 ? _out_T_1490 : programBufferMem_44; // @[RegisterRouter.scala:87:24]
wire _out_T_1495 = ~out_rimask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1496 = ~out_wimask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1497 = ~out_romask_136; // @[RegisterRouter.scala:87:24]
wire _out_T_1498 = ~out_womask_136; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1500 = _out_T_1499; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_106 = _out_T_1500; // @[RegisterRouter.scala:87:24]
wire out_rimask_137 = |_out_rimask_T_137; // @[RegisterRouter.scala:87:24]
wire out_wimask_137 = &_out_wimask_T_137; // @[RegisterRouter.scala:87:24]
wire out_romask_137 = |_out_romask_T_137; // @[RegisterRouter.scala:87:24]
wire out_womask_137 = &_out_womask_T_137; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_137 = out_rivalid_137 & out_rimask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1502 = out_f_rivalid_137; // @[RegisterRouter.scala:87:24]
assign out_f_roready_137 = out_roready_137 & out_romask_137; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_45 = out_f_roready_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1503 = out_f_roready_137; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_137 = out_wivalid_137 & out_wimask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1504 = out_f_wivalid_137; // @[RegisterRouter.scala:87:24]
assign out_f_woready_137 = out_woready_137 & out_womask_137; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_45 = out_f_woready_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1505 = out_f_woready_137; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_45 = out_f_woready_137 ? _out_T_1501 : programBufferMem_45; // @[RegisterRouter.scala:87:24]
wire _out_T_1506 = ~out_rimask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1507 = ~out_wimask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1508 = ~out_romask_137; // @[RegisterRouter.scala:87:24]
wire _out_T_1509 = ~out_womask_137; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_106 = {programBufferMem_45, _out_prepend_T_106}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1510 = out_prepend_106; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1511 = _out_T_1510; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_107 = _out_T_1511; // @[RegisterRouter.scala:87:24]
wire out_rimask_138 = |_out_rimask_T_138; // @[RegisterRouter.scala:87:24]
wire out_wimask_138 = &_out_wimask_T_138; // @[RegisterRouter.scala:87:24]
wire out_romask_138 = |_out_romask_T_138; // @[RegisterRouter.scala:87:24]
wire out_womask_138 = &_out_womask_T_138; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_138 = out_rivalid_138 & out_rimask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1513 = out_f_rivalid_138; // @[RegisterRouter.scala:87:24]
assign out_f_roready_138 = out_roready_138 & out_romask_138; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_46 = out_f_roready_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1514 = out_f_roready_138; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_138 = out_wivalid_138 & out_wimask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1515 = out_f_wivalid_138; // @[RegisterRouter.scala:87:24]
assign out_f_woready_138 = out_woready_138 & out_womask_138; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_46 = out_f_woready_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1516 = out_f_woready_138; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_46 = out_f_woready_138 ? _out_T_1512 : programBufferMem_46; // @[RegisterRouter.scala:87:24]
wire _out_T_1517 = ~out_rimask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1518 = ~out_wimask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1519 = ~out_romask_138; // @[RegisterRouter.scala:87:24]
wire _out_T_1520 = ~out_womask_138; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_107 = {programBufferMem_46, _out_prepend_T_107}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1521 = out_prepend_107; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1522 = _out_T_1521; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_108 = _out_T_1522; // @[RegisterRouter.scala:87:24]
wire out_rimask_139 = |_out_rimask_T_139; // @[RegisterRouter.scala:87:24]
wire out_wimask_139 = &_out_wimask_T_139; // @[RegisterRouter.scala:87:24]
wire out_romask_139 = |_out_romask_T_139; // @[RegisterRouter.scala:87:24]
wire out_womask_139 = &_out_womask_T_139; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_139 = out_rivalid_139 & out_rimask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1524 = out_f_rivalid_139; // @[RegisterRouter.scala:87:24]
assign out_f_roready_139 = out_roready_139 & out_romask_139; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_47 = out_f_roready_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1525 = out_f_roready_139; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_139 = out_wivalid_139 & out_wimask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1526 = out_f_wivalid_139; // @[RegisterRouter.scala:87:24]
assign out_f_woready_139 = out_woready_139 & out_womask_139; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_47 = out_f_woready_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1527 = out_f_woready_139; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_47 = out_f_woready_139 ? _out_T_1523 : programBufferMem_47; // @[RegisterRouter.scala:87:24]
wire _out_T_1528 = ~out_rimask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1529 = ~out_wimask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1530 = ~out_romask_139; // @[RegisterRouter.scala:87:24]
wire _out_T_1531 = ~out_womask_139; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_108 = {programBufferMem_47, _out_prepend_T_108}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1532 = out_prepend_108; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1533 = _out_T_1532; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_43 = _out_T_1533; // @[MuxLiteral.scala:49:48]
wire out_rimask_140 = |_out_rimask_T_140; // @[RegisterRouter.scala:87:24]
wire out_wimask_140 = &_out_wimask_T_140; // @[RegisterRouter.scala:87:24]
wire out_romask_140 = |_out_romask_T_140; // @[RegisterRouter.scala:87:24]
wire out_womask_140 = &_out_womask_T_140; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_140 = out_rivalid_140 & out_rimask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1535 = out_f_rivalid_140; // @[RegisterRouter.scala:87:24]
assign out_f_roready_140 = out_roready_140 & out_romask_140; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_32 = out_f_roready_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1536 = out_f_roready_140; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_140 = out_wivalid_140 & out_wimask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1537 = out_f_wivalid_140; // @[RegisterRouter.scala:87:24]
assign out_f_woready_140 = out_woready_140 & out_womask_140; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_32 = out_f_woready_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1538 = out_f_woready_140; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_32 = out_f_woready_140 ? _out_T_1534 : programBufferMem_32; // @[RegisterRouter.scala:87:24]
wire _out_T_1539 = ~out_rimask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1540 = ~out_wimask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1541 = ~out_romask_140; // @[RegisterRouter.scala:87:24]
wire _out_T_1542 = ~out_womask_140; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1544 = _out_T_1543; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_109 = _out_T_1544; // @[RegisterRouter.scala:87:24]
wire out_rimask_141 = |_out_rimask_T_141; // @[RegisterRouter.scala:87:24]
wire out_wimask_141 = &_out_wimask_T_141; // @[RegisterRouter.scala:87:24]
wire out_romask_141 = |_out_romask_T_141; // @[RegisterRouter.scala:87:24]
wire out_womask_141 = &_out_womask_T_141; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_141 = out_rivalid_141 & out_rimask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1546 = out_f_rivalid_141; // @[RegisterRouter.scala:87:24]
assign out_f_roready_141 = out_roready_141 & out_romask_141; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_33 = out_f_roready_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1547 = out_f_roready_141; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_141 = out_wivalid_141 & out_wimask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1548 = out_f_wivalid_141; // @[RegisterRouter.scala:87:24]
assign out_f_woready_141 = out_woready_141 & out_womask_141; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_33 = out_f_woready_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1549 = out_f_woready_141; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_33 = out_f_woready_141 ? _out_T_1545 : programBufferMem_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1550 = ~out_rimask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1551 = ~out_wimask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1552 = ~out_romask_141; // @[RegisterRouter.scala:87:24]
wire _out_T_1553 = ~out_womask_141; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_109 = {programBufferMem_33, _out_prepend_T_109}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1554 = out_prepend_109; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1555 = _out_T_1554; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_110 = _out_T_1555; // @[RegisterRouter.scala:87:24]
wire out_rimask_142 = |_out_rimask_T_142; // @[RegisterRouter.scala:87:24]
wire out_wimask_142 = &_out_wimask_T_142; // @[RegisterRouter.scala:87:24]
wire out_romask_142 = |_out_romask_T_142; // @[RegisterRouter.scala:87:24]
wire out_womask_142 = &_out_womask_T_142; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_142 = out_rivalid_142 & out_rimask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1557 = out_f_rivalid_142; // @[RegisterRouter.scala:87:24]
assign out_f_roready_142 = out_roready_142 & out_romask_142; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_34 = out_f_roready_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1558 = out_f_roready_142; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_142 = out_wivalid_142 & out_wimask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1559 = out_f_wivalid_142; // @[RegisterRouter.scala:87:24]
assign out_f_woready_142 = out_woready_142 & out_womask_142; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_34 = out_f_woready_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1560 = out_f_woready_142; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_34 = out_f_woready_142 ? _out_T_1556 : programBufferMem_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1561 = ~out_rimask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1562 = ~out_wimask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1563 = ~out_romask_142; // @[RegisterRouter.scala:87:24]
wire _out_T_1564 = ~out_womask_142; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_110 = {programBufferMem_34, _out_prepend_T_110}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1565 = out_prepend_110; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1566 = _out_T_1565; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_111 = _out_T_1566; // @[RegisterRouter.scala:87:24]
wire out_rimask_143 = |_out_rimask_T_143; // @[RegisterRouter.scala:87:24]
wire out_wimask_143 = &_out_wimask_T_143; // @[RegisterRouter.scala:87:24]
wire out_romask_143 = |_out_romask_T_143; // @[RegisterRouter.scala:87:24]
wire out_womask_143 = &_out_womask_T_143; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_143 = out_rivalid_143 & out_rimask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1568 = out_f_rivalid_143; // @[RegisterRouter.scala:87:24]
assign out_f_roready_143 = out_roready_143 & out_romask_143; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_35 = out_f_roready_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1569 = out_f_roready_143; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_143 = out_wivalid_143 & out_wimask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1570 = out_f_wivalid_143; // @[RegisterRouter.scala:87:24]
assign out_f_woready_143 = out_woready_143 & out_womask_143; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_35 = out_f_woready_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1571 = out_f_woready_143; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_35 = out_f_woready_143 ? _out_T_1567 : programBufferMem_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1572 = ~out_rimask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1573 = ~out_wimask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1574 = ~out_romask_143; // @[RegisterRouter.scala:87:24]
wire _out_T_1575 = ~out_womask_143; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_111 = {programBufferMem_35, _out_prepend_T_111}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1576 = out_prepend_111; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1577 = _out_T_1576; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_40 = _out_T_1577; // @[MuxLiteral.scala:49:48]
wire out_rimask_144 = |_out_rimask_T_144; // @[RegisterRouter.scala:87:24]
wire out_wimask_144 = &_out_wimask_T_144; // @[RegisterRouter.scala:87:24]
wire out_romask_144 = |_out_romask_T_144; // @[RegisterRouter.scala:87:24]
wire out_womask_144 = &_out_womask_T_144; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_144 = out_rivalid_144 & out_rimask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1579 = out_f_rivalid_144; // @[RegisterRouter.scala:87:24]
assign out_f_roready_144 = out_roready_144 & out_romask_144; // @[RegisterRouter.scala:87:24]
assign COMMANDRdEn = out_f_roready_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1580 = out_f_roready_144; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_144 = out_wivalid_144 & out_wimask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1581 = out_f_wivalid_144; // @[RegisterRouter.scala:87:24]
assign out_f_woready_144 = out_woready_144 & out_womask_144; // @[RegisterRouter.scala:87:24]
assign COMMANDWrEnMaybe = out_f_woready_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1582 = out_f_woready_144; // @[RegisterRouter.scala:87:24]
assign COMMANDWrDataVal = out_f_woready_144 ? _out_T_1578 : 32'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1583 = ~out_rimask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1584 = ~out_wimask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1585 = ~out_romask_144; // @[RegisterRouter.scala:87:24]
wire _out_T_1586 = ~out_womask_144; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1588 = _out_T_1587; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_23 = _out_T_1588; // @[MuxLiteral.scala:49:48]
wire out_rimask_145 = |_out_rimask_T_145; // @[RegisterRouter.scala:87:24]
wire out_wimask_145 = &_out_wimask_T_145; // @[RegisterRouter.scala:87:24]
wire out_romask_145 = |_out_romask_T_145; // @[RegisterRouter.scala:87:24]
wire out_womask_145 = &_out_womask_T_145; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_145 = out_rivalid_145 & out_rimask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1590 = out_f_rivalid_145; // @[RegisterRouter.scala:87:24]
assign out_f_roready_145 = out_roready_145 & out_romask_145; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_16 = out_f_roready_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1591 = out_f_roready_145; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_145 = out_wivalid_145 & out_wimask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1592 = out_f_wivalid_145; // @[RegisterRouter.scala:87:24]
assign out_f_woready_145 = out_woready_145 & out_womask_145; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_16 = out_f_woready_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1593 = out_f_woready_145; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_16 = out_f_woready_145 ? _out_T_1589 : programBufferMem_16; // @[RegisterRouter.scala:87:24]
wire _out_T_1594 = ~out_rimask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1595 = ~out_wimask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1596 = ~out_romask_145; // @[RegisterRouter.scala:87:24]
wire _out_T_1597 = ~out_womask_145; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1599 = _out_T_1598; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_112 = _out_T_1599; // @[RegisterRouter.scala:87:24]
wire out_rimask_146 = |_out_rimask_T_146; // @[RegisterRouter.scala:87:24]
wire out_wimask_146 = &_out_wimask_T_146; // @[RegisterRouter.scala:87:24]
wire out_romask_146 = |_out_romask_T_146; // @[RegisterRouter.scala:87:24]
wire out_womask_146 = &_out_womask_T_146; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_146 = out_rivalid_146 & out_rimask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1601 = out_f_rivalid_146; // @[RegisterRouter.scala:87:24]
assign out_f_roready_146 = out_roready_146 & out_romask_146; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_17 = out_f_roready_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1602 = out_f_roready_146; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_146 = out_wivalid_146 & out_wimask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1603 = out_f_wivalid_146; // @[RegisterRouter.scala:87:24]
assign out_f_woready_146 = out_woready_146 & out_womask_146; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_17 = out_f_woready_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1604 = out_f_woready_146; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_17 = out_f_woready_146 ? _out_T_1600 : programBufferMem_17; // @[RegisterRouter.scala:87:24]
wire _out_T_1605 = ~out_rimask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1606 = ~out_wimask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1607 = ~out_romask_146; // @[RegisterRouter.scala:87:24]
wire _out_T_1608 = ~out_womask_146; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_112 = {programBufferMem_17, _out_prepend_T_112}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1609 = out_prepend_112; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1610 = _out_T_1609; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_113 = _out_T_1610; // @[RegisterRouter.scala:87:24]
wire out_rimask_147 = |_out_rimask_T_147; // @[RegisterRouter.scala:87:24]
wire out_wimask_147 = &_out_wimask_T_147; // @[RegisterRouter.scala:87:24]
wire out_romask_147 = |_out_romask_T_147; // @[RegisterRouter.scala:87:24]
wire out_womask_147 = &_out_womask_T_147; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_147 = out_rivalid_147 & out_rimask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1612 = out_f_rivalid_147; // @[RegisterRouter.scala:87:24]
assign out_f_roready_147 = out_roready_147 & out_romask_147; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_18 = out_f_roready_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1613 = out_f_roready_147; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_147 = out_wivalid_147 & out_wimask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1614 = out_f_wivalid_147; // @[RegisterRouter.scala:87:24]
assign out_f_woready_147 = out_woready_147 & out_womask_147; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_18 = out_f_woready_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1615 = out_f_woready_147; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_18 = out_f_woready_147 ? _out_T_1611 : programBufferMem_18; // @[RegisterRouter.scala:87:24]
wire _out_T_1616 = ~out_rimask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1617 = ~out_wimask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1618 = ~out_romask_147; // @[RegisterRouter.scala:87:24]
wire _out_T_1619 = ~out_womask_147; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_113 = {programBufferMem_18, _out_prepend_T_113}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1620 = out_prepend_113; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1621 = _out_T_1620; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_114 = _out_T_1621; // @[RegisterRouter.scala:87:24]
wire out_rimask_148 = |_out_rimask_T_148; // @[RegisterRouter.scala:87:24]
wire out_wimask_148 = &_out_wimask_T_148; // @[RegisterRouter.scala:87:24]
wire out_romask_148 = |_out_romask_T_148; // @[RegisterRouter.scala:87:24]
wire out_womask_148 = &_out_womask_T_148; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_148 = out_rivalid_148 & out_rimask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1623 = out_f_rivalid_148; // @[RegisterRouter.scala:87:24]
assign out_f_roready_148 = out_roready_148 & out_romask_148; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferRdEn_19 = out_f_roready_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1624 = out_f_roready_148; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_148 = out_wivalid_148 & out_wimask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1625 = out_f_wivalid_148; // @[RegisterRouter.scala:87:24]
assign out_f_woready_148 = out_woready_148 & out_womask_148; // @[RegisterRouter.scala:87:24]
assign dmiProgramBufferWrEnMaybe_19 = out_f_woready_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1626 = out_f_woready_148; // @[RegisterRouter.scala:87:24]
assign programBufferNxt_19 = out_f_woready_148 ? _out_T_1622 : programBufferMem_19; // @[RegisterRouter.scala:87:24]
wire _out_T_1627 = ~out_rimask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1628 = ~out_wimask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1629 = ~out_romask_148; // @[RegisterRouter.scala:87:24]
wire _out_T_1630 = ~out_womask_148; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_114 = {programBufferMem_19, _out_prepend_T_114}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1631 = out_prepend_114; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1632 = _out_T_1631; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_36 = _out_T_1632; // @[MuxLiteral.scala:49:48]
wire out_rimask_149 = |_out_rimask_T_149; // @[RegisterRouter.scala:87:24]
wire out_wimask_149 = &_out_wimask_T_149; // @[RegisterRouter.scala:87:24]
wire out_romask_149 = |_out_romask_T_149; // @[RegisterRouter.scala:87:24]
wire out_womask_149 = &_out_womask_T_149; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_149 = out_rivalid_149 & out_rimask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1634 = out_f_rivalid_149; // @[RegisterRouter.scala:87:24]
wire out_f_roready_149 = out_roready_149 & out_romask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1635 = out_f_roready_149; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_149 = out_wivalid_149 & out_wimask_149; // @[RegisterRouter.scala:87:24]
wire out_f_woready_149 = out_woready_149 & out_womask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1636 = ~out_rimask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1637 = ~out_wimask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1638 = ~out_romask_149; // @[RegisterRouter.scala:87:24]
wire _out_T_1639 = ~out_womask_149; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1641 = _out_T_1640; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_19 = _out_T_1641; // @[MuxLiteral.scala:49:48]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_lo_hi = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24]
wire [2:0] out_iindex_lo = {out_iindex_lo_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_hi_hi = {_out_iindex_T_5, _out_iindex_T_4}; // @[RegisterRouter.scala:87:24]
wire [2:0] out_iindex_hi = {out_iindex_hi_hi, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24]
wire [5:0] out_iindex = {out_iindex_hi, out_iindex_lo}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_lo_hi = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24]
wire [2:0] out_oindex_lo = {out_oindex_lo_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_hi_hi = {_out_oindex_T_5, _out_oindex_T_4}; // @[RegisterRouter.scala:87:24]
wire [2:0] out_oindex_hi = {out_oindex_hi_hi, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24]
wire [5:0] out_oindex = {out_oindex_hi, out_oindex_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_frontSel_T = 64'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35]
wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35]
wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35]
wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35]
wire out_frontSel_8 = _out_frontSel_T[8]; // @[OneHot.scala:58:35]
wire out_frontSel_9 = _out_frontSel_T[9]; // @[OneHot.scala:58:35]
wire out_frontSel_10 = _out_frontSel_T[10]; // @[OneHot.scala:58:35]
wire out_frontSel_11 = _out_frontSel_T[11]; // @[OneHot.scala:58:35]
wire out_frontSel_12 = _out_frontSel_T[12]; // @[OneHot.scala:58:35]
wire out_frontSel_13 = _out_frontSel_T[13]; // @[OneHot.scala:58:35]
wire out_frontSel_14 = _out_frontSel_T[14]; // @[OneHot.scala:58:35]
wire out_frontSel_15 = _out_frontSel_T[15]; // @[OneHot.scala:58:35]
wire out_frontSel_16 = _out_frontSel_T[16]; // @[OneHot.scala:58:35]
wire out_frontSel_17 = _out_frontSel_T[17]; // @[OneHot.scala:58:35]
wire out_frontSel_18 = _out_frontSel_T[18]; // @[OneHot.scala:58:35]
wire out_frontSel_19 = _out_frontSel_T[19]; // @[OneHot.scala:58:35]
wire out_frontSel_20 = _out_frontSel_T[20]; // @[OneHot.scala:58:35]
wire out_frontSel_21 = _out_frontSel_T[21]; // @[OneHot.scala:58:35]
wire out_frontSel_22 = _out_frontSel_T[22]; // @[OneHot.scala:58:35]
wire out_frontSel_23 = _out_frontSel_T[23]; // @[OneHot.scala:58:35]
wire out_frontSel_24 = _out_frontSel_T[24]; // @[OneHot.scala:58:35]
wire out_frontSel_25 = _out_frontSel_T[25]; // @[OneHot.scala:58:35]
wire out_frontSel_26 = _out_frontSel_T[26]; // @[OneHot.scala:58:35]
wire out_frontSel_27 = _out_frontSel_T[27]; // @[OneHot.scala:58:35]
wire out_frontSel_28 = _out_frontSel_T[28]; // @[OneHot.scala:58:35]
wire out_frontSel_29 = _out_frontSel_T[29]; // @[OneHot.scala:58:35]
wire out_frontSel_30 = _out_frontSel_T[30]; // @[OneHot.scala:58:35]
wire out_frontSel_31 = _out_frontSel_T[31]; // @[OneHot.scala:58:35]
wire out_frontSel_32 = _out_frontSel_T[32]; // @[OneHot.scala:58:35]
wire out_frontSel_33 = _out_frontSel_T[33]; // @[OneHot.scala:58:35]
wire out_frontSel_34 = _out_frontSel_T[34]; // @[OneHot.scala:58:35]
wire out_frontSel_35 = _out_frontSel_T[35]; // @[OneHot.scala:58:35]
wire out_frontSel_36 = _out_frontSel_T[36]; // @[OneHot.scala:58:35]
wire out_frontSel_37 = _out_frontSel_T[37]; // @[OneHot.scala:58:35]
wire out_frontSel_38 = _out_frontSel_T[38]; // @[OneHot.scala:58:35]
wire out_frontSel_39 = _out_frontSel_T[39]; // @[OneHot.scala:58:35]
wire out_frontSel_40 = _out_frontSel_T[40]; // @[OneHot.scala:58:35]
wire out_frontSel_41 = _out_frontSel_T[41]; // @[OneHot.scala:58:35]
wire out_frontSel_42 = _out_frontSel_T[42]; // @[OneHot.scala:58:35]
wire out_frontSel_43 = _out_frontSel_T[43]; // @[OneHot.scala:58:35]
wire out_frontSel_44 = _out_frontSel_T[44]; // @[OneHot.scala:58:35]
wire out_frontSel_45 = _out_frontSel_T[45]; // @[OneHot.scala:58:35]
wire out_frontSel_46 = _out_frontSel_T[46]; // @[OneHot.scala:58:35]
wire out_frontSel_47 = _out_frontSel_T[47]; // @[OneHot.scala:58:35]
wire out_frontSel_48 = _out_frontSel_T[48]; // @[OneHot.scala:58:35]
wire out_frontSel_49 = _out_frontSel_T[49]; // @[OneHot.scala:58:35]
wire out_frontSel_50 = _out_frontSel_T[50]; // @[OneHot.scala:58:35]
wire out_frontSel_51 = _out_frontSel_T[51]; // @[OneHot.scala:58:35]
wire out_frontSel_52 = _out_frontSel_T[52]; // @[OneHot.scala:58:35]
wire out_frontSel_53 = _out_frontSel_T[53]; // @[OneHot.scala:58:35]
wire out_frontSel_54 = _out_frontSel_T[54]; // @[OneHot.scala:58:35]
wire out_frontSel_55 = _out_frontSel_T[55]; // @[OneHot.scala:58:35]
wire out_frontSel_56 = _out_frontSel_T[56]; // @[OneHot.scala:58:35]
wire out_frontSel_57 = _out_frontSel_T[57]; // @[OneHot.scala:58:35]
wire out_frontSel_58 = _out_frontSel_T[58]; // @[OneHot.scala:58:35]
wire out_frontSel_59 = _out_frontSel_T[59]; // @[OneHot.scala:58:35]
wire out_frontSel_60 = _out_frontSel_T[60]; // @[OneHot.scala:58:35]
wire out_frontSel_61 = _out_frontSel_T[61]; // @[OneHot.scala:58:35]
wire out_frontSel_62 = _out_frontSel_T[62]; // @[OneHot.scala:58:35]
wire out_frontSel_63 = _out_frontSel_T[63]; // @[OneHot.scala:58:35]
wire [63:0] _out_backSel_T = 64'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35]
wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35]
wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35]
wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35]
wire out_backSel_8 = _out_backSel_T[8]; // @[OneHot.scala:58:35]
wire out_backSel_9 = _out_backSel_T[9]; // @[OneHot.scala:58:35]
wire out_backSel_10 = _out_backSel_T[10]; // @[OneHot.scala:58:35]
wire out_backSel_11 = _out_backSel_T[11]; // @[OneHot.scala:58:35]
wire out_backSel_12 = _out_backSel_T[12]; // @[OneHot.scala:58:35]
wire out_backSel_13 = _out_backSel_T[13]; // @[OneHot.scala:58:35]
wire out_backSel_14 = _out_backSel_T[14]; // @[OneHot.scala:58:35]
wire out_backSel_15 = _out_backSel_T[15]; // @[OneHot.scala:58:35]
wire out_backSel_16 = _out_backSel_T[16]; // @[OneHot.scala:58:35]
wire out_backSel_17 = _out_backSel_T[17]; // @[OneHot.scala:58:35]
wire out_backSel_18 = _out_backSel_T[18]; // @[OneHot.scala:58:35]
wire out_backSel_19 = _out_backSel_T[19]; // @[OneHot.scala:58:35]
wire out_backSel_20 = _out_backSel_T[20]; // @[OneHot.scala:58:35]
wire out_backSel_21 = _out_backSel_T[21]; // @[OneHot.scala:58:35]
wire out_backSel_22 = _out_backSel_T[22]; // @[OneHot.scala:58:35]
wire out_backSel_23 = _out_backSel_T[23]; // @[OneHot.scala:58:35]
wire out_backSel_24 = _out_backSel_T[24]; // @[OneHot.scala:58:35]
wire out_backSel_25 = _out_backSel_T[25]; // @[OneHot.scala:58:35]
wire out_backSel_26 = _out_backSel_T[26]; // @[OneHot.scala:58:35]
wire out_backSel_27 = _out_backSel_T[27]; // @[OneHot.scala:58:35]
wire out_backSel_28 = _out_backSel_T[28]; // @[OneHot.scala:58:35]
wire out_backSel_29 = _out_backSel_T[29]; // @[OneHot.scala:58:35]
wire out_backSel_30 = _out_backSel_T[30]; // @[OneHot.scala:58:35]
wire out_backSel_31 = _out_backSel_T[31]; // @[OneHot.scala:58:35]
wire out_backSel_32 = _out_backSel_T[32]; // @[OneHot.scala:58:35]
wire out_backSel_33 = _out_backSel_T[33]; // @[OneHot.scala:58:35]
wire out_backSel_34 = _out_backSel_T[34]; // @[OneHot.scala:58:35]
wire out_backSel_35 = _out_backSel_T[35]; // @[OneHot.scala:58:35]
wire out_backSel_36 = _out_backSel_T[36]; // @[OneHot.scala:58:35]
wire out_backSel_37 = _out_backSel_T[37]; // @[OneHot.scala:58:35]
wire out_backSel_38 = _out_backSel_T[38]; // @[OneHot.scala:58:35]
wire out_backSel_39 = _out_backSel_T[39]; // @[OneHot.scala:58:35]
wire out_backSel_40 = _out_backSel_T[40]; // @[OneHot.scala:58:35]
wire out_backSel_41 = _out_backSel_T[41]; // @[OneHot.scala:58:35]
wire out_backSel_42 = _out_backSel_T[42]; // @[OneHot.scala:58:35]
wire out_backSel_43 = _out_backSel_T[43]; // @[OneHot.scala:58:35]
wire out_backSel_44 = _out_backSel_T[44]; // @[OneHot.scala:58:35]
wire out_backSel_45 = _out_backSel_T[45]; // @[OneHot.scala:58:35]
wire out_backSel_46 = _out_backSel_T[46]; // @[OneHot.scala:58:35]
wire out_backSel_47 = _out_backSel_T[47]; // @[OneHot.scala:58:35]
wire out_backSel_48 = _out_backSel_T[48]; // @[OneHot.scala:58:35]
wire out_backSel_49 = _out_backSel_T[49]; // @[OneHot.scala:58:35]
wire out_backSel_50 = _out_backSel_T[50]; // @[OneHot.scala:58:35]
wire out_backSel_51 = _out_backSel_T[51]; // @[OneHot.scala:58:35]
wire out_backSel_52 = _out_backSel_T[52]; // @[OneHot.scala:58:35]
wire out_backSel_53 = _out_backSel_T[53]; // @[OneHot.scala:58:35]
wire out_backSel_54 = _out_backSel_T[54]; // @[OneHot.scala:58:35]
wire out_backSel_55 = _out_backSel_T[55]; // @[OneHot.scala:58:35]
wire out_backSel_56 = _out_backSel_T[56]; // @[OneHot.scala:58:35]
wire out_backSel_57 = _out_backSel_T[57]; // @[OneHot.scala:58:35]
wire out_backSel_58 = _out_backSel_T[58]; // @[OneHot.scala:58:35]
wire out_backSel_59 = _out_backSel_T[59]; // @[OneHot.scala:58:35]
wire out_backSel_60 = _out_backSel_T[60]; // @[OneHot.scala:58:35]
wire out_backSel_61 = _out_backSel_T[61]; // @[OneHot.scala:58:35]
wire out_backSel_62 = _out_backSel_T[62]; // @[OneHot.scala:58:35]
wire out_backSel_63 = _out_backSel_T[63]; // @[OneHot.scala:58:35]
wire _GEN_27 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_27; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_27; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T_42; // @[RegisterRouter.scala:87:24]
assign out_rivalid_85 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T_42; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11 = _out_rifireMux_T_10; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_14; // @[RegisterRouter.scala:87:24]
assign out_rivalid_25 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_rivalid_26 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_rivalid_27 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_rivalid_28 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_20 = ~_out_T_14; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_24 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_32; // @[RegisterRouter.scala:87:24]
assign out_rivalid_68 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_rivalid_69 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_rivalid_70 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_rivalid_71 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_28 = ~_out_T_32; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_31 = _out_rifireMux_T_30 & _out_T_54; // @[RegisterRouter.scala:87:24]
assign out_rivalid_124 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_rivalid_125 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_rivalid_126 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_rivalid_127 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_32 = ~_out_T_54; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_34 = _out_rifireMux_T_1 & out_frontSel_8; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_35 = _out_rifireMux_T_34 & _out_T_12; // @[RegisterRouter.scala:87:24]
assign out_rivalid_21 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_rivalid_22 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_rivalid_23 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_rivalid_24 = _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_36 = ~_out_T_12; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_38 = _out_rifireMux_T_1 & out_frontSel_9; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_39 = _out_rifireMux_T_38 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_40 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_42 = _out_rifireMux_T_1 & out_frontSel_10; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_43 = _out_rifireMux_T_42 & _out_T_18; // @[RegisterRouter.scala:87:24]
assign out_rivalid_33 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_rivalid_34 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_rivalid_35 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_rivalid_36 = _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_44 = ~_out_T_18; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_46 = _out_rifireMux_T_1 & out_frontSel_11; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_47 = _out_rifireMux_T_46 & _out_T_58; // @[RegisterRouter.scala:87:24]
assign out_rivalid_132 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_rivalid_133 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_rivalid_134 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_rivalid_135 = _out_rifireMux_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_48 = ~_out_T_58; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_50 = _out_rifireMux_T_1 & out_frontSel_12; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_51 = _out_rifireMux_T_50; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_54 = _out_rifireMux_T_1 & out_frontSel_13; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_55 = _out_rifireMux_T_54; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_58 = _out_rifireMux_T_1 & out_frontSel_14; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_59 = _out_rifireMux_T_58; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_62 = _out_rifireMux_T_1 & out_frontSel_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_63 = _out_rifireMux_T_62; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_66 = _out_rifireMux_T_1 & out_frontSel_16; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_67 = _out_rifireMux_T_66; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_70 = _out_rifireMux_T_1 & out_frontSel_17; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_71 = _out_rifireMux_T_70 & _out_T_44; // @[RegisterRouter.scala:87:24]
assign out_rivalid_86 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_87 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_88 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_89 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_90 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_91 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_92 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_93 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_94 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_95 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_96 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_97 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_98 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_99 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_100 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_101 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_102 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_103 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_rivalid_104 = _out_rifireMux_T_71; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_72 = ~_out_T_44; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_74 = _out_rifireMux_T_1 & out_frontSel_18; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_75 = _out_rifireMux_T_74; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_78 = _out_rifireMux_T_1 & out_frontSel_19; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_79 = _out_rifireMux_T_78 & _out_T_68; // @[RegisterRouter.scala:87:24]
assign out_rivalid_149 = _out_rifireMux_T_79; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_80 = ~_out_T_68; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_82 = _out_rifireMux_T_1 & out_frontSel_20; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_83 = _out_rifireMux_T_82; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_86 = _out_rifireMux_T_1 & out_frontSel_21; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_87 = _out_rifireMux_T_86; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_90 = _out_rifireMux_T_1 & out_frontSel_22; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_91 = _out_rifireMux_T_90 & _out_T_50; // @[RegisterRouter.scala:87:24]
assign out_rivalid_113 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_114 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_115 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_116 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_117 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_118 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_rivalid_119 = _out_rifireMux_T_91; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_92 = ~_out_T_50; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_94 = _out_rifireMux_T_1 & out_frontSel_23; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_95 = _out_rifireMux_T_94 & _out_T_64; // @[RegisterRouter.scala:87:24]
assign out_rivalid_144 = _out_rifireMux_T_95; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_96 = ~_out_T_64; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_98 = _out_rifireMux_T_1 & out_frontSel_24; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_99 = _out_rifireMux_T_98 & _out_T_24; // @[RegisterRouter.scala:87:24]
assign out_rivalid_56 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24]
assign out_rivalid_57 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24]
assign out_rivalid_58 = _out_rifireMux_T_99; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_100 = ~_out_T_24; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_102 = _out_rifireMux_T_1 & out_frontSel_25; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_103 = _out_rifireMux_T_102; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_106 = _out_rifireMux_T_1 & out_frontSel_26; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_107 = _out_rifireMux_T_106; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_110 = _out_rifireMux_T_1 & out_frontSel_27; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_111 = _out_rifireMux_T_110; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_114 = _out_rifireMux_T_1 & out_frontSel_28; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_115 = _out_rifireMux_T_114; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_118 = _out_rifireMux_T_1 & out_frontSel_29; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_119 = _out_rifireMux_T_118; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_122 = _out_rifireMux_T_1 & out_frontSel_30; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_123 = _out_rifireMux_T_122; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_126 = _out_rifireMux_T_1 & out_frontSel_31; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_127 = _out_rifireMux_T_126; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_130 = _out_rifireMux_T_1 & out_frontSel_32; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_131 = _out_rifireMux_T_130 & _out_T_46; // @[RegisterRouter.scala:87:24]
assign out_rivalid_105 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_rivalid_106 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_rivalid_107 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_rivalid_108 = _out_rifireMux_T_131; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_132 = ~_out_T_46; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_134 = _out_rifireMux_T_1 & out_frontSel_33; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_135 = _out_rifireMux_T_134 & _out_T_38; // @[RegisterRouter.scala:87:24]
assign out_rivalid_77 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_rivalid_78 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_rivalid_79 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_rivalid_80 = _out_rifireMux_T_135; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_136 = ~_out_T_38; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_138 = _out_rifireMux_T_1 & out_frontSel_34; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_139 = _out_rifireMux_T_138 & _out_T_48; // @[RegisterRouter.scala:87:24]
assign out_rivalid_109 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_rivalid_110 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_rivalid_111 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_rivalid_112 = _out_rifireMux_T_139; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_140 = ~_out_T_48; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_142 = _out_rifireMux_T_1 & out_frontSel_35; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_143 = _out_rifireMux_T_142 & _out_T_8; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_rivalid_16 = _out_rifireMux_T_143; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_144 = ~_out_T_8; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_146 = _out_rifireMux_T_1 & out_frontSel_36; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_147 = _out_rifireMux_T_146 & _out_T_66; // @[RegisterRouter.scala:87:24]
assign out_rivalid_145 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_rivalid_146 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_rivalid_147 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_rivalid_148 = _out_rifireMux_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_148 = ~_out_T_66; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_150 = _out_rifireMux_T_1 & out_frontSel_37; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_151 = _out_rifireMux_T_150 & _out_T_26; // @[RegisterRouter.scala:87:24]
assign out_rivalid_59 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_rivalid_60 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_rivalid_61 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_rivalid_62 = _out_rifireMux_T_151; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_152 = ~_out_T_26; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_154 = _out_rifireMux_T_1 & out_frontSel_38; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_155 = _out_rifireMux_T_154 & _out_T_36; // @[RegisterRouter.scala:87:24]
assign out_rivalid_73 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_rivalid_74 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_rivalid_75 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_rivalid_76 = _out_rifireMux_T_155; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_156 = ~_out_T_36; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_158 = _out_rifireMux_T_1 & out_frontSel_39; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_159 = _out_rifireMux_T_158 & _out_T_56; // @[RegisterRouter.scala:87:24]
assign out_rivalid_128 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_rivalid_129 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_rivalid_130 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_rivalid_131 = _out_rifireMux_T_159; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_160 = ~_out_T_56; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_162 = _out_rifireMux_T_1 & out_frontSel_40; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_163 = _out_rifireMux_T_162 & _out_T_62; // @[RegisterRouter.scala:87:24]
assign out_rivalid_140 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_rivalid_141 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_rivalid_142 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_rivalid_143 = _out_rifireMux_T_163; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_164 = ~_out_T_62; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_166 = _out_rifireMux_T_1 & out_frontSel_41; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_167 = _out_rifireMux_T_166 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_167; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_168 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_170 = _out_rifireMux_T_1 & out_frontSel_42; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_171 = _out_rifireMux_T_170 & _out_T_22; // @[RegisterRouter.scala:87:24]
assign out_rivalid_52 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_rivalid_53 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_rivalid_54 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_rivalid_55 = _out_rifireMux_T_171; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_172 = ~_out_T_22; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_174 = _out_rifireMux_T_1 & out_frontSel_43; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_175 = _out_rifireMux_T_174 & _out_T_60; // @[RegisterRouter.scala:87:24]
assign out_rivalid_136 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_rivalid_137 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_rivalid_138 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_rivalid_139 = _out_rifireMux_T_175; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_176 = ~_out_T_60; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_178 = _out_rifireMux_T_1 & out_frontSel_44; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_179 = _out_rifireMux_T_178 & _out_T_52; // @[RegisterRouter.scala:87:24]
assign out_rivalid_120 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_rivalid_121 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_rivalid_122 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_rivalid_123 = _out_rifireMux_T_179; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_180 = ~_out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_182 = _out_rifireMux_T_1 & out_frontSel_45; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_183 = _out_rifireMux_T_182 & _out_T_40; // @[RegisterRouter.scala:87:24]
assign out_rivalid_81 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_rivalid_82 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_rivalid_83 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_rivalid_84 = _out_rifireMux_T_183; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_184 = ~_out_T_40; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_186 = _out_rifireMux_T_1 & out_frontSel_46; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_187 = _out_rifireMux_T_186 & _out_T_28; // @[RegisterRouter.scala:87:24]
assign out_rivalid_63 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_rivalid_64 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_rivalid_65 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_rivalid_66 = _out_rifireMux_T_187; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_188 = ~_out_T_28; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_190 = _out_rifireMux_T_1 & out_frontSel_47; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_191 = _out_rifireMux_T_190 & _out_T_16; // @[RegisterRouter.scala:87:24]
assign out_rivalid_29 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_rivalid_30 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_rivalid_31 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_rivalid_32 = _out_rifireMux_T_191; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_192 = ~_out_T_16; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_194 = _out_rifireMux_T_1 & out_frontSel_48; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_195 = _out_rifireMux_T_194; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_198 = _out_rifireMux_T_1 & out_frontSel_49; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_199 = _out_rifireMux_T_198; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_202 = _out_rifireMux_T_1 & out_frontSel_50; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_203 = _out_rifireMux_T_202 & _out_T_10; // @[RegisterRouter.scala:87:24]
assign out_rivalid_17 = _out_rifireMux_T_203; // @[RegisterRouter.scala:87:24]
assign out_rivalid_18 = _out_rifireMux_T_203; // @[RegisterRouter.scala:87:24]
assign out_rivalid_19 = _out_rifireMux_T_203; // @[RegisterRouter.scala:87:24]
assign out_rivalid_20 = _out_rifireMux_T_203; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_204 = ~_out_T_10; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_206 = _out_rifireMux_T_1 & out_frontSel_51; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_207 = _out_rifireMux_T_206; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_210 = _out_rifireMux_T_1 & out_frontSel_52; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_211 = _out_rifireMux_T_210; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_214 = _out_rifireMux_T_1 & out_frontSel_53; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_215 = _out_rifireMux_T_214; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_218 = _out_rifireMux_T_1 & out_frontSel_54; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_219 = _out_rifireMux_T_218; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_222 = _out_rifireMux_T_1 & out_frontSel_55; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_223 = _out_rifireMux_T_222; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_226 = _out_rifireMux_T_1 & out_frontSel_56; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_227 = _out_rifireMux_T_226 & _out_T_20; // @[RegisterRouter.scala:87:24]
assign out_rivalid_37 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_38 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_39 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_40 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_41 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_42 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_43 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_44 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_45 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_46 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_47 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_48 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_49 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_50 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_rivalid_51 = _out_rifireMux_T_227; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_228 = ~_out_T_20; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_230 = _out_rifireMux_T_1 & out_frontSel_57; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_231 = _out_rifireMux_T_230 & _out_T_30; // @[RegisterRouter.scala:87:24]
assign out_rivalid_67 = _out_rifireMux_T_231; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_232 = ~_out_T_30; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_234 = _out_rifireMux_T_1 & out_frontSel_58; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_235 = _out_rifireMux_T_234; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_238 = _out_rifireMux_T_1 & out_frontSel_59; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_239 = _out_rifireMux_T_238; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_242 = _out_rifireMux_T_1 & out_frontSel_60; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_243 = _out_rifireMux_T_242 & _out_T_34; // @[RegisterRouter.scala:87:24]
assign out_rivalid_72 = _out_rifireMux_T_243; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_244 = ~_out_T_34; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_246 = _out_rifireMux_T_1 & out_frontSel_61; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_247 = _out_rifireMux_T_246 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_247; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_248 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_250 = _out_rifireMux_T_1 & out_frontSel_62; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_251 = _out_rifireMux_T_250; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_254 = _out_rifireMux_T_1 & out_frontSel_63; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_255 = _out_rifireMux_T_254; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T_42; // @[RegisterRouter.scala:87:24]
assign out_wivalid_85 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T_42; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12 = _out_wifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_14; // @[RegisterRouter.scala:87:24]
assign out_wivalid_25 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_wivalid_26 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_wivalid_27 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_wivalid_28 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_21 = ~_out_T_14; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_25 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_32; // @[RegisterRouter.scala:87:24]
assign out_wivalid_68 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_wivalid_69 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_wivalid_70 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_wivalid_71 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_29 = ~_out_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_32 = _out_wifireMux_T_31 & _out_T_54; // @[RegisterRouter.scala:87:24]
assign out_wivalid_124 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_wivalid_125 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_wivalid_126 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_wivalid_127 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_33 = ~_out_T_54; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_35 = _out_wifireMux_T_2 & out_frontSel_8; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_36 = _out_wifireMux_T_35 & _out_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_21 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_wivalid_22 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_wivalid_23 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_wivalid_24 = _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_37 = ~_out_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_39 = _out_wifireMux_T_2 & out_frontSel_9; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_40 = _out_wifireMux_T_39 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_41 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_43 = _out_wifireMux_T_2 & out_frontSel_10; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_44 = _out_wifireMux_T_43 & _out_T_18; // @[RegisterRouter.scala:87:24]
assign out_wivalid_33 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_wivalid_34 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_wivalid_35 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_wivalid_36 = _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_45 = ~_out_T_18; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_47 = _out_wifireMux_T_2 & out_frontSel_11; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_48 = _out_wifireMux_T_47 & _out_T_58; // @[RegisterRouter.scala:87:24]
assign out_wivalid_132 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_wivalid_133 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_wivalid_134 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_wivalid_135 = _out_wifireMux_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_49 = ~_out_T_58; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_51 = _out_wifireMux_T_2 & out_frontSel_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_52 = _out_wifireMux_T_51; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_55 = _out_wifireMux_T_2 & out_frontSel_13; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_56 = _out_wifireMux_T_55; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_59 = _out_wifireMux_T_2 & out_frontSel_14; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_60 = _out_wifireMux_T_59; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_63 = _out_wifireMux_T_2 & out_frontSel_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_64 = _out_wifireMux_T_63; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_67 = _out_wifireMux_T_2 & out_frontSel_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_68 = _out_wifireMux_T_67; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_71 = _out_wifireMux_T_2 & out_frontSel_17; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_72 = _out_wifireMux_T_71 & _out_T_44; // @[RegisterRouter.scala:87:24]
assign out_wivalid_86 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_87 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_88 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_89 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_90 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_91 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_92 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_93 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_94 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_95 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_96 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_97 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_98 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_99 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_100 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_101 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_102 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_103 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_wivalid_104 = _out_wifireMux_T_72; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_73 = ~_out_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_75 = _out_wifireMux_T_2 & out_frontSel_18; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_76 = _out_wifireMux_T_75; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_79 = _out_wifireMux_T_2 & out_frontSel_19; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_80 = _out_wifireMux_T_79 & _out_T_68; // @[RegisterRouter.scala:87:24]
assign out_wivalid_149 = _out_wifireMux_T_80; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_81 = ~_out_T_68; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_83 = _out_wifireMux_T_2 & out_frontSel_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_84 = _out_wifireMux_T_83; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_87 = _out_wifireMux_T_2 & out_frontSel_21; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_88 = _out_wifireMux_T_87; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_91 = _out_wifireMux_T_2 & out_frontSel_22; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_92 = _out_wifireMux_T_91 & _out_T_50; // @[RegisterRouter.scala:87:24]
assign out_wivalid_113 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_114 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_115 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_116 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_117 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_118 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_wivalid_119 = _out_wifireMux_T_92; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_93 = ~_out_T_50; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_95 = _out_wifireMux_T_2 & out_frontSel_23; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_96 = _out_wifireMux_T_95 & _out_T_64; // @[RegisterRouter.scala:87:24]
assign out_wivalid_144 = _out_wifireMux_T_96; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_97 = ~_out_T_64; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_99 = _out_wifireMux_T_2 & out_frontSel_24; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_100 = _out_wifireMux_T_99 & _out_T_24; // @[RegisterRouter.scala:87:24]
assign out_wivalid_56 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_57 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24]
assign out_wivalid_58 = _out_wifireMux_T_100; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_101 = ~_out_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_103 = _out_wifireMux_T_2 & out_frontSel_25; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_104 = _out_wifireMux_T_103; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_107 = _out_wifireMux_T_2 & out_frontSel_26; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_108 = _out_wifireMux_T_107; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_111 = _out_wifireMux_T_2 & out_frontSel_27; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_112 = _out_wifireMux_T_111; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_115 = _out_wifireMux_T_2 & out_frontSel_28; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_116 = _out_wifireMux_T_115; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_119 = _out_wifireMux_T_2 & out_frontSel_29; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_120 = _out_wifireMux_T_119; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_123 = _out_wifireMux_T_2 & out_frontSel_30; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_124 = _out_wifireMux_T_123; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_127 = _out_wifireMux_T_2 & out_frontSel_31; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_128 = _out_wifireMux_T_127; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_131 = _out_wifireMux_T_2 & out_frontSel_32; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_132 = _out_wifireMux_T_131 & _out_T_46; // @[RegisterRouter.scala:87:24]
assign out_wivalid_105 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_106 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_107 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_wivalid_108 = _out_wifireMux_T_132; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_133 = ~_out_T_46; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_135 = _out_wifireMux_T_2 & out_frontSel_33; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_136 = _out_wifireMux_T_135 & _out_T_38; // @[RegisterRouter.scala:87:24]
assign out_wivalid_77 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_78 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_79 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_wivalid_80 = _out_wifireMux_T_136; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_137 = ~_out_T_38; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_139 = _out_wifireMux_T_2 & out_frontSel_34; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_140 = _out_wifireMux_T_139 & _out_T_48; // @[RegisterRouter.scala:87:24]
assign out_wivalid_109 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_110 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_111 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_wivalid_112 = _out_wifireMux_T_140; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_141 = ~_out_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_143 = _out_wifireMux_T_2 & out_frontSel_35; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_144 = _out_wifireMux_T_143 & _out_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_wivalid_16 = _out_wifireMux_T_144; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_145 = ~_out_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_147 = _out_wifireMux_T_2 & out_frontSel_36; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_148 = _out_wifireMux_T_147 & _out_T_66; // @[RegisterRouter.scala:87:24]
assign out_wivalid_145 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_146 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_147 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_wivalid_148 = _out_wifireMux_T_148; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_149 = ~_out_T_66; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_151 = _out_wifireMux_T_2 & out_frontSel_37; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_152 = _out_wifireMux_T_151 & _out_T_26; // @[RegisterRouter.scala:87:24]
assign out_wivalid_59 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_60 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_61 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_wivalid_62 = _out_wifireMux_T_152; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_153 = ~_out_T_26; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_155 = _out_wifireMux_T_2 & out_frontSel_38; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_156 = _out_wifireMux_T_155 & _out_T_36; // @[RegisterRouter.scala:87:24]
assign out_wivalid_73 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_74 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_75 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_wivalid_76 = _out_wifireMux_T_156; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_157 = ~_out_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_159 = _out_wifireMux_T_2 & out_frontSel_39; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_160 = _out_wifireMux_T_159 & _out_T_56; // @[RegisterRouter.scala:87:24]
assign out_wivalid_128 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_129 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_130 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_wivalid_131 = _out_wifireMux_T_160; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_161 = ~_out_T_56; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_163 = _out_wifireMux_T_2 & out_frontSel_40; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_164 = _out_wifireMux_T_163 & _out_T_62; // @[RegisterRouter.scala:87:24]
assign out_wivalid_140 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_141 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_142 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_wivalid_143 = _out_wifireMux_T_164; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_165 = ~_out_T_62; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_167 = _out_wifireMux_T_2 & out_frontSel_41; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_168 = _out_wifireMux_T_167 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_168; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_169 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_171 = _out_wifireMux_T_2 & out_frontSel_42; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_172 = _out_wifireMux_T_171 & _out_T_22; // @[RegisterRouter.scala:87:24]
assign out_wivalid_52 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_53 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_54 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_wivalid_55 = _out_wifireMux_T_172; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_173 = ~_out_T_22; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_175 = _out_wifireMux_T_2 & out_frontSel_43; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_176 = _out_wifireMux_T_175 & _out_T_60; // @[RegisterRouter.scala:87:24]
assign out_wivalid_136 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_137 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_138 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_wivalid_139 = _out_wifireMux_T_176; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_177 = ~_out_T_60; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_179 = _out_wifireMux_T_2 & out_frontSel_44; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_180 = _out_wifireMux_T_179 & _out_T_52; // @[RegisterRouter.scala:87:24]
assign out_wivalid_120 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_121 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_122 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_wivalid_123 = _out_wifireMux_T_180; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_181 = ~_out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_183 = _out_wifireMux_T_2 & out_frontSel_45; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_184 = _out_wifireMux_T_183 & _out_T_40; // @[RegisterRouter.scala:87:24]
assign out_wivalid_81 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_82 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_83 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_wivalid_84 = _out_wifireMux_T_184; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_185 = ~_out_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_187 = _out_wifireMux_T_2 & out_frontSel_46; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_188 = _out_wifireMux_T_187 & _out_T_28; // @[RegisterRouter.scala:87:24]
assign out_wivalid_63 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_64 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_65 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_wivalid_66 = _out_wifireMux_T_188; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_189 = ~_out_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_191 = _out_wifireMux_T_2 & out_frontSel_47; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_192 = _out_wifireMux_T_191 & _out_T_16; // @[RegisterRouter.scala:87:24]
assign out_wivalid_29 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_30 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_31 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_wivalid_32 = _out_wifireMux_T_192; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_193 = ~_out_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_195 = _out_wifireMux_T_2 & out_frontSel_48; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_196 = _out_wifireMux_T_195; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_199 = _out_wifireMux_T_2 & out_frontSel_49; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_200 = _out_wifireMux_T_199; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_203 = _out_wifireMux_T_2 & out_frontSel_50; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_204 = _out_wifireMux_T_203 & _out_T_10; // @[RegisterRouter.scala:87:24]
assign out_wivalid_17 = _out_wifireMux_T_204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_18 = _out_wifireMux_T_204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_19 = _out_wifireMux_T_204; // @[RegisterRouter.scala:87:24]
assign out_wivalid_20 = _out_wifireMux_T_204; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_205 = ~_out_T_10; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_207 = _out_wifireMux_T_2 & out_frontSel_51; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_208 = _out_wifireMux_T_207; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_211 = _out_wifireMux_T_2 & out_frontSel_52; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_212 = _out_wifireMux_T_211; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_215 = _out_wifireMux_T_2 & out_frontSel_53; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_216 = _out_wifireMux_T_215; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_219 = _out_wifireMux_T_2 & out_frontSel_54; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_220 = _out_wifireMux_T_219; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_223 = _out_wifireMux_T_2 & out_frontSel_55; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_224 = _out_wifireMux_T_223; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_227 = _out_wifireMux_T_2 & out_frontSel_56; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_228 = _out_wifireMux_T_227 & _out_T_20; // @[RegisterRouter.scala:87:24]
assign out_wivalid_37 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_38 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_39 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_40 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_41 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_42 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_43 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_44 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_45 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_46 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_47 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_48 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_49 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_50 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_wivalid_51 = _out_wifireMux_T_228; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_229 = ~_out_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_231 = _out_wifireMux_T_2 & out_frontSel_57; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_232 = _out_wifireMux_T_231 & _out_T_30; // @[RegisterRouter.scala:87:24]
assign out_wivalid_67 = _out_wifireMux_T_232; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_233 = ~_out_T_30; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_235 = _out_wifireMux_T_2 & out_frontSel_58; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_236 = _out_wifireMux_T_235; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_239 = _out_wifireMux_T_2 & out_frontSel_59; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_240 = _out_wifireMux_T_239; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_243 = _out_wifireMux_T_2 & out_frontSel_60; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_244 = _out_wifireMux_T_243 & _out_T_34; // @[RegisterRouter.scala:87:24]
assign out_wivalid_72 = _out_wifireMux_T_244; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_245 = ~_out_T_34; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_247 = _out_wifireMux_T_2 & out_frontSel_61; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_248 = _out_wifireMux_T_247 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_248; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_249 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_251 = _out_wifireMux_T_2 & out_frontSel_62; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_252 = _out_wifireMux_T_251; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_255 = _out_wifireMux_T_2 & out_frontSel_63; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_256 = _out_wifireMux_T_255; // @[RegisterRouter.scala:87:24]
wire _GEN_28 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_28; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_28; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_43; // @[RegisterRouter.scala:87:24]
assign out_roready_85 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11 = _out_rofireMux_T_10; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_18 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_19 = _out_rofireMux_T_18 & _out_T_15; // @[RegisterRouter.scala:87:24]
assign out_roready_25 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_roready_26 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_roready_27 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
assign out_roready_28 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_20 = ~_out_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_22 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_23 = _out_rofireMux_T_22 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_24 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_26 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_27 = _out_rofireMux_T_26 & _out_T_33; // @[RegisterRouter.scala:87:24]
assign out_roready_68 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_roready_69 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_roready_70 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
assign out_roready_71 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_28 = ~_out_T_33; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_30 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_31 = _out_rofireMux_T_30 & _out_T_55; // @[RegisterRouter.scala:87:24]
assign out_roready_124 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_roready_125 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_roready_126 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
assign out_roready_127 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_32 = ~_out_T_55; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_34 = _out_rofireMux_T_1 & out_backSel_8; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_35 = _out_rofireMux_T_34 & _out_T_13; // @[RegisterRouter.scala:87:24]
assign out_roready_21 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_roready_22 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_roready_23 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
assign out_roready_24 = _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_36 = ~_out_T_13; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_38 = _out_rofireMux_T_1 & out_backSel_9; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_39 = _out_rofireMux_T_38 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_40 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_42 = _out_rofireMux_T_1 & out_backSel_10; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_43 = _out_rofireMux_T_42 & _out_T_19; // @[RegisterRouter.scala:87:24]
assign out_roready_33 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_roready_34 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_roready_35 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
assign out_roready_36 = _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_44 = ~_out_T_19; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_46 = _out_rofireMux_T_1 & out_backSel_11; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_47 = _out_rofireMux_T_46 & _out_T_59; // @[RegisterRouter.scala:87:24]
assign out_roready_132 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_roready_133 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_roready_134 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
assign out_roready_135 = _out_rofireMux_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_48 = ~_out_T_59; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_50 = _out_rofireMux_T_1 & out_backSel_12; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_51 = _out_rofireMux_T_50; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_54 = _out_rofireMux_T_1 & out_backSel_13; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_55 = _out_rofireMux_T_54; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_58 = _out_rofireMux_T_1 & out_backSel_14; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_59 = _out_rofireMux_T_58; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_62 = _out_rofireMux_T_1 & out_backSel_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_63 = _out_rofireMux_T_62; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_66 = _out_rofireMux_T_1 & out_backSel_16; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_67 = _out_rofireMux_T_66; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_70 = _out_rofireMux_T_1 & out_backSel_17; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_71 = _out_rofireMux_T_70 & _out_T_45; // @[RegisterRouter.scala:87:24]
assign out_roready_86 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_87 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_88 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_89 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_90 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_91 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_92 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_93 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_94 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_95 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_96 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_97 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_98 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_99 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_100 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_101 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_102 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_103 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
assign out_roready_104 = _out_rofireMux_T_71; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_72 = ~_out_T_45; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_74 = _out_rofireMux_T_1 & out_backSel_18; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_75 = _out_rofireMux_T_74; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_78 = _out_rofireMux_T_1 & out_backSel_19; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_79 = _out_rofireMux_T_78 & _out_T_69; // @[RegisterRouter.scala:87:24]
assign out_roready_149 = _out_rofireMux_T_79; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_80 = ~_out_T_69; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_82 = _out_rofireMux_T_1 & out_backSel_20; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_83 = _out_rofireMux_T_82; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_86 = _out_rofireMux_T_1 & out_backSel_21; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_87 = _out_rofireMux_T_86; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_90 = _out_rofireMux_T_1 & out_backSel_22; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_91 = _out_rofireMux_T_90 & _out_T_51; // @[RegisterRouter.scala:87:24]
assign out_roready_113 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_114 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_115 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_116 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_117 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_118 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
assign out_roready_119 = _out_rofireMux_T_91; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_92 = ~_out_T_51; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_94 = _out_rofireMux_T_1 & out_backSel_23; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_95 = _out_rofireMux_T_94 & _out_T_65; // @[RegisterRouter.scala:87:24]
assign out_roready_144 = _out_rofireMux_T_95; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_96 = ~_out_T_65; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_98 = _out_rofireMux_T_1 & out_backSel_24; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_99 = _out_rofireMux_T_98 & _out_T_25; // @[RegisterRouter.scala:87:24]
assign out_roready_56 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24]
assign out_roready_57 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24]
assign out_roready_58 = _out_rofireMux_T_99; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_100 = ~_out_T_25; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_102 = _out_rofireMux_T_1 & out_backSel_25; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_103 = _out_rofireMux_T_102; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_106 = _out_rofireMux_T_1 & out_backSel_26; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_107 = _out_rofireMux_T_106; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_110 = _out_rofireMux_T_1 & out_backSel_27; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_111 = _out_rofireMux_T_110; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_114 = _out_rofireMux_T_1 & out_backSel_28; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_115 = _out_rofireMux_T_114; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_118 = _out_rofireMux_T_1 & out_backSel_29; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_119 = _out_rofireMux_T_118; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_122 = _out_rofireMux_T_1 & out_backSel_30; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_123 = _out_rofireMux_T_122; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_126 = _out_rofireMux_T_1 & out_backSel_31; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_127 = _out_rofireMux_T_126; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_130 = _out_rofireMux_T_1 & out_backSel_32; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_131 = _out_rofireMux_T_130 & _out_T_47; // @[RegisterRouter.scala:87:24]
assign out_roready_105 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_roready_106 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_roready_107 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
assign out_roready_108 = _out_rofireMux_T_131; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_132 = ~_out_T_47; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_134 = _out_rofireMux_T_1 & out_backSel_33; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_135 = _out_rofireMux_T_134 & _out_T_39; // @[RegisterRouter.scala:87:24]
assign out_roready_77 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_roready_78 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_roready_79 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
assign out_roready_80 = _out_rofireMux_T_135; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_136 = ~_out_T_39; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_138 = _out_rofireMux_T_1 & out_backSel_34; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_139 = _out_rofireMux_T_138 & _out_T_49; // @[RegisterRouter.scala:87:24]
assign out_roready_109 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_roready_110 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_roready_111 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
assign out_roready_112 = _out_rofireMux_T_139; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_140 = ~_out_T_49; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_142 = _out_rofireMux_T_1 & out_backSel_35; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_143 = _out_rofireMux_T_142 & _out_T_9; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
assign out_roready_16 = _out_rofireMux_T_143; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_144 = ~_out_T_9; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_146 = _out_rofireMux_T_1 & out_backSel_36; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_147 = _out_rofireMux_T_146 & _out_T_67; // @[RegisterRouter.scala:87:24]
assign out_roready_145 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_roready_146 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_roready_147 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
assign out_roready_148 = _out_rofireMux_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_148 = ~_out_T_67; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_150 = _out_rofireMux_T_1 & out_backSel_37; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_151 = _out_rofireMux_T_150 & _out_T_27; // @[RegisterRouter.scala:87:24]
assign out_roready_59 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_roready_60 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_roready_61 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
assign out_roready_62 = _out_rofireMux_T_151; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_152 = ~_out_T_27; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_154 = _out_rofireMux_T_1 & out_backSel_38; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_155 = _out_rofireMux_T_154 & _out_T_37; // @[RegisterRouter.scala:87:24]
assign out_roready_73 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_roready_74 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_roready_75 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
assign out_roready_76 = _out_rofireMux_T_155; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_156 = ~_out_T_37; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_158 = _out_rofireMux_T_1 & out_backSel_39; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_159 = _out_rofireMux_T_158 & _out_T_57; // @[RegisterRouter.scala:87:24]
assign out_roready_128 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_roready_129 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_roready_130 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
assign out_roready_131 = _out_rofireMux_T_159; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_160 = ~_out_T_57; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_162 = _out_rofireMux_T_1 & out_backSel_40; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_163 = _out_rofireMux_T_162 & _out_T_63; // @[RegisterRouter.scala:87:24]
assign out_roready_140 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_roready_141 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_roready_142 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
assign out_roready_143 = _out_rofireMux_T_163; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_164 = ~_out_T_63; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_166 = _out_rofireMux_T_1 & out_backSel_41; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_167 = _out_rofireMux_T_166 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_167; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_168 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_170 = _out_rofireMux_T_1 & out_backSel_42; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_171 = _out_rofireMux_T_170 & _out_T_23; // @[RegisterRouter.scala:87:24]
assign out_roready_52 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_roready_53 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_roready_54 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
assign out_roready_55 = _out_rofireMux_T_171; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_172 = ~_out_T_23; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_174 = _out_rofireMux_T_1 & out_backSel_43; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_175 = _out_rofireMux_T_174 & _out_T_61; // @[RegisterRouter.scala:87:24]
assign out_roready_136 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_roready_137 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_roready_138 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
assign out_roready_139 = _out_rofireMux_T_175; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_176 = ~_out_T_61; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_178 = _out_rofireMux_T_1 & out_backSel_44; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_179 = _out_rofireMux_T_178 & _out_T_53; // @[RegisterRouter.scala:87:24]
assign out_roready_120 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_roready_121 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_roready_122 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
assign out_roready_123 = _out_rofireMux_T_179; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_180 = ~_out_T_53; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_182 = _out_rofireMux_T_1 & out_backSel_45; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_183 = _out_rofireMux_T_182 & _out_T_41; // @[RegisterRouter.scala:87:24]
assign out_roready_81 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_roready_82 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_roready_83 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
assign out_roready_84 = _out_rofireMux_T_183; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_184 = ~_out_T_41; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_186 = _out_rofireMux_T_1 & out_backSel_46; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_187 = _out_rofireMux_T_186 & _out_T_29; // @[RegisterRouter.scala:87:24]
assign out_roready_63 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_roready_64 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_roready_65 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
assign out_roready_66 = _out_rofireMux_T_187; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_188 = ~_out_T_29; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_190 = _out_rofireMux_T_1 & out_backSel_47; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_191 = _out_rofireMux_T_190 & _out_T_17; // @[RegisterRouter.scala:87:24]
assign out_roready_29 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_roready_30 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_roready_31 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
assign out_roready_32 = _out_rofireMux_T_191; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_192 = ~_out_T_17; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_194 = _out_rofireMux_T_1 & out_backSel_48; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_195 = _out_rofireMux_T_194; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_198 = _out_rofireMux_T_1 & out_backSel_49; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_199 = _out_rofireMux_T_198; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_202 = _out_rofireMux_T_1 & out_backSel_50; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_203 = _out_rofireMux_T_202 & _out_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_17 = _out_rofireMux_T_203; // @[RegisterRouter.scala:87:24]
assign out_roready_18 = _out_rofireMux_T_203; // @[RegisterRouter.scala:87:24]
assign out_roready_19 = _out_rofireMux_T_203; // @[RegisterRouter.scala:87:24]
assign out_roready_20 = _out_rofireMux_T_203; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_204 = ~_out_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_206 = _out_rofireMux_T_1 & out_backSel_51; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_207 = _out_rofireMux_T_206; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_210 = _out_rofireMux_T_1 & out_backSel_52; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_211 = _out_rofireMux_T_210; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_214 = _out_rofireMux_T_1 & out_backSel_53; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_215 = _out_rofireMux_T_214; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_218 = _out_rofireMux_T_1 & out_backSel_54; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_219 = _out_rofireMux_T_218; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_222 = _out_rofireMux_T_1 & out_backSel_55; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_223 = _out_rofireMux_T_222; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_226 = _out_rofireMux_T_1 & out_backSel_56; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_227 = _out_rofireMux_T_226 & _out_T_21; // @[RegisterRouter.scala:87:24]
assign out_roready_37 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_38 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_39 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_40 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_41 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_42 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_43 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_44 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_45 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_46 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_47 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_48 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_49 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_50 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
assign out_roready_51 = _out_rofireMux_T_227; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_228 = ~_out_T_21; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_230 = _out_rofireMux_T_1 & out_backSel_57; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_231 = _out_rofireMux_T_230 & _out_T_31; // @[RegisterRouter.scala:87:24]
assign out_roready_67 = _out_rofireMux_T_231; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_232 = ~_out_T_31; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_234 = _out_rofireMux_T_1 & out_backSel_58; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_235 = _out_rofireMux_T_234; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_238 = _out_rofireMux_T_1 & out_backSel_59; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_239 = _out_rofireMux_T_238; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_242 = _out_rofireMux_T_1 & out_backSel_60; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_243 = _out_rofireMux_T_242 & _out_T_35; // @[RegisterRouter.scala:87:24]
assign out_roready_72 = _out_rofireMux_T_243; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_244 = ~_out_T_35; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_246 = _out_rofireMux_T_1 & out_backSel_61; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_247 = _out_rofireMux_T_246 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_247; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_248 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_250 = _out_rofireMux_T_1 & out_backSel_62; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_251 = _out_rofireMux_T_250; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_254 = _out_rofireMux_T_1 & out_backSel_63; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_255 = _out_rofireMux_T_254; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_43; // @[RegisterRouter.scala:87:24]
assign out_woready_85 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_43; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12 = _out_wofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_15; // @[RegisterRouter.scala:87:24]
assign out_woready_25 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_woready_26 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_woready_27 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
assign out_woready_28 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_21 = ~_out_T_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_25 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_33; // @[RegisterRouter.scala:87:24]
assign out_woready_68 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_woready_69 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_woready_70 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
assign out_woready_71 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_29 = ~_out_T_33; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_32 = _out_wofireMux_T_31 & _out_T_55; // @[RegisterRouter.scala:87:24]
assign out_woready_124 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_woready_125 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_woready_126 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
assign out_woready_127 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_33 = ~_out_T_55; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_35 = _out_wofireMux_T_2 & out_backSel_8; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_36 = _out_wofireMux_T_35 & _out_T_13; // @[RegisterRouter.scala:87:24]
assign out_woready_21 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_woready_22 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_woready_23 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
assign out_woready_24 = _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_37 = ~_out_T_13; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_39 = _out_wofireMux_T_2 & out_backSel_9; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_40 = _out_wofireMux_T_39 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_40; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_41 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_43 = _out_wofireMux_T_2 & out_backSel_10; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_44 = _out_wofireMux_T_43 & _out_T_19; // @[RegisterRouter.scala:87:24]
assign out_woready_33 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_woready_34 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_woready_35 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
assign out_woready_36 = _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_45 = ~_out_T_19; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_47 = _out_wofireMux_T_2 & out_backSel_11; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_48 = _out_wofireMux_T_47 & _out_T_59; // @[RegisterRouter.scala:87:24]
assign out_woready_132 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_woready_133 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_woready_134 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
assign out_woready_135 = _out_wofireMux_T_48; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_49 = ~_out_T_59; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_51 = _out_wofireMux_T_2 & out_backSel_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_52 = _out_wofireMux_T_51; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_55 = _out_wofireMux_T_2 & out_backSel_13; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_56 = _out_wofireMux_T_55; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_59 = _out_wofireMux_T_2 & out_backSel_14; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_60 = _out_wofireMux_T_59; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_63 = _out_wofireMux_T_2 & out_backSel_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_64 = _out_wofireMux_T_63; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_67 = _out_wofireMux_T_2 & out_backSel_16; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_68 = _out_wofireMux_T_67; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_71 = _out_wofireMux_T_2 & out_backSel_17; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_72 = _out_wofireMux_T_71 & _out_T_45; // @[RegisterRouter.scala:87:24]
assign out_woready_86 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_87 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_88 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_89 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_90 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_91 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_92 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_93 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_94 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_95 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_96 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_97 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_98 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_99 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_100 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_101 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_102 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_103 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
assign out_woready_104 = _out_wofireMux_T_72; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_73 = ~_out_T_45; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_75 = _out_wofireMux_T_2 & out_backSel_18; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_76 = _out_wofireMux_T_75; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_79 = _out_wofireMux_T_2 & out_backSel_19; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_80 = _out_wofireMux_T_79 & _out_T_69; // @[RegisterRouter.scala:87:24]
assign out_woready_149 = _out_wofireMux_T_80; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_81 = ~_out_T_69; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_83 = _out_wofireMux_T_2 & out_backSel_20; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_84 = _out_wofireMux_T_83; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_87 = _out_wofireMux_T_2 & out_backSel_21; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_88 = _out_wofireMux_T_87; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_91 = _out_wofireMux_T_2 & out_backSel_22; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_92 = _out_wofireMux_T_91 & _out_T_51; // @[RegisterRouter.scala:87:24]
assign out_woready_113 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_114 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_115 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_116 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_117 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_118 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
assign out_woready_119 = _out_wofireMux_T_92; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_93 = ~_out_T_51; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_95 = _out_wofireMux_T_2 & out_backSel_23; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_96 = _out_wofireMux_T_95 & _out_T_65; // @[RegisterRouter.scala:87:24]
assign out_woready_144 = _out_wofireMux_T_96; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_97 = ~_out_T_65; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_99 = _out_wofireMux_T_2 & out_backSel_24; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_100 = _out_wofireMux_T_99 & _out_T_25; // @[RegisterRouter.scala:87:24]
assign out_woready_56 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24]
assign out_woready_57 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24]
assign out_woready_58 = _out_wofireMux_T_100; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_101 = ~_out_T_25; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_103 = _out_wofireMux_T_2 & out_backSel_25; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_104 = _out_wofireMux_T_103; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_107 = _out_wofireMux_T_2 & out_backSel_26; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_108 = _out_wofireMux_T_107; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_111 = _out_wofireMux_T_2 & out_backSel_27; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_112 = _out_wofireMux_T_111; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_115 = _out_wofireMux_T_2 & out_backSel_28; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_116 = _out_wofireMux_T_115; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_119 = _out_wofireMux_T_2 & out_backSel_29; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_120 = _out_wofireMux_T_119; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_123 = _out_wofireMux_T_2 & out_backSel_30; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_124 = _out_wofireMux_T_123; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_127 = _out_wofireMux_T_2 & out_backSel_31; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_128 = _out_wofireMux_T_127; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_131 = _out_wofireMux_T_2 & out_backSel_32; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_132 = _out_wofireMux_T_131 & _out_T_47; // @[RegisterRouter.scala:87:24]
assign out_woready_105 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_woready_106 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_woready_107 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
assign out_woready_108 = _out_wofireMux_T_132; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_133 = ~_out_T_47; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_135 = _out_wofireMux_T_2 & out_backSel_33; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_136 = _out_wofireMux_T_135 & _out_T_39; // @[RegisterRouter.scala:87:24]
assign out_woready_77 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_woready_78 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_woready_79 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
assign out_woready_80 = _out_wofireMux_T_136; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_137 = ~_out_T_39; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_139 = _out_wofireMux_T_2 & out_backSel_34; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_140 = _out_wofireMux_T_139 & _out_T_49; // @[RegisterRouter.scala:87:24]
assign out_woready_109 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_woready_110 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_woready_111 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
assign out_woready_112 = _out_wofireMux_T_140; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_141 = ~_out_T_49; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_143 = _out_wofireMux_T_2 & out_backSel_35; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_144 = _out_wofireMux_T_143 & _out_T_9; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
assign out_woready_16 = _out_wofireMux_T_144; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_145 = ~_out_T_9; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_147 = _out_wofireMux_T_2 & out_backSel_36; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_148 = _out_wofireMux_T_147 & _out_T_67; // @[RegisterRouter.scala:87:24]
assign out_woready_145 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_woready_146 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_woready_147 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
assign out_woready_148 = _out_wofireMux_T_148; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_149 = ~_out_T_67; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_151 = _out_wofireMux_T_2 & out_backSel_37; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_152 = _out_wofireMux_T_151 & _out_T_27; // @[RegisterRouter.scala:87:24]
assign out_woready_59 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_woready_60 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_woready_61 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
assign out_woready_62 = _out_wofireMux_T_152; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_153 = ~_out_T_27; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_155 = _out_wofireMux_T_2 & out_backSel_38; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_156 = _out_wofireMux_T_155 & _out_T_37; // @[RegisterRouter.scala:87:24]
assign out_woready_73 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_woready_74 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_woready_75 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
assign out_woready_76 = _out_wofireMux_T_156; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_157 = ~_out_T_37; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_159 = _out_wofireMux_T_2 & out_backSel_39; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_160 = _out_wofireMux_T_159 & _out_T_57; // @[RegisterRouter.scala:87:24]
assign out_woready_128 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_woready_129 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_woready_130 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
assign out_woready_131 = _out_wofireMux_T_160; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_161 = ~_out_T_57; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_163 = _out_wofireMux_T_2 & out_backSel_40; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_164 = _out_wofireMux_T_163 & _out_T_63; // @[RegisterRouter.scala:87:24]
assign out_woready_140 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_woready_141 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_woready_142 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
assign out_woready_143 = _out_wofireMux_T_164; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_165 = ~_out_T_63; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_167 = _out_wofireMux_T_2 & out_backSel_41; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_168 = _out_wofireMux_T_167 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_168; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_169 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_171 = _out_wofireMux_T_2 & out_backSel_42; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_172 = _out_wofireMux_T_171 & _out_T_23; // @[RegisterRouter.scala:87:24]
assign out_woready_52 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_woready_53 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_woready_54 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
assign out_woready_55 = _out_wofireMux_T_172; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_173 = ~_out_T_23; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_175 = _out_wofireMux_T_2 & out_backSel_43; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_176 = _out_wofireMux_T_175 & _out_T_61; // @[RegisterRouter.scala:87:24]
assign out_woready_136 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_woready_137 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_woready_138 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
assign out_woready_139 = _out_wofireMux_T_176; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_177 = ~_out_T_61; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_179 = _out_wofireMux_T_2 & out_backSel_44; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_180 = _out_wofireMux_T_179 & _out_T_53; // @[RegisterRouter.scala:87:24]
assign out_woready_120 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_woready_121 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_woready_122 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
assign out_woready_123 = _out_wofireMux_T_180; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_181 = ~_out_T_53; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_183 = _out_wofireMux_T_2 & out_backSel_45; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_184 = _out_wofireMux_T_183 & _out_T_41; // @[RegisterRouter.scala:87:24]
assign out_woready_81 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_woready_82 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_woready_83 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
assign out_woready_84 = _out_wofireMux_T_184; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_185 = ~_out_T_41; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_187 = _out_wofireMux_T_2 & out_backSel_46; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_188 = _out_wofireMux_T_187 & _out_T_29; // @[RegisterRouter.scala:87:24]
assign out_woready_63 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_woready_64 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_woready_65 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
assign out_woready_66 = _out_wofireMux_T_188; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_189 = ~_out_T_29; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_191 = _out_wofireMux_T_2 & out_backSel_47; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_192 = _out_wofireMux_T_191 & _out_T_17; // @[RegisterRouter.scala:87:24]
assign out_woready_29 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_woready_30 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_woready_31 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
assign out_woready_32 = _out_wofireMux_T_192; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_193 = ~_out_T_17; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_195 = _out_wofireMux_T_2 & out_backSel_48; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_196 = _out_wofireMux_T_195; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_199 = _out_wofireMux_T_2 & out_backSel_49; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_200 = _out_wofireMux_T_199; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_203 = _out_wofireMux_T_2 & out_backSel_50; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_204 = _out_wofireMux_T_203 & _out_T_11; // @[RegisterRouter.scala:87:24]
assign out_woready_17 = _out_wofireMux_T_204; // @[RegisterRouter.scala:87:24]
assign out_woready_18 = _out_wofireMux_T_204; // @[RegisterRouter.scala:87:24]
assign out_woready_19 = _out_wofireMux_T_204; // @[RegisterRouter.scala:87:24]
assign out_woready_20 = _out_wofireMux_T_204; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_205 = ~_out_T_11; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_207 = _out_wofireMux_T_2 & out_backSel_51; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_208 = _out_wofireMux_T_207; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_211 = _out_wofireMux_T_2 & out_backSel_52; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_212 = _out_wofireMux_T_211; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_215 = _out_wofireMux_T_2 & out_backSel_53; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_216 = _out_wofireMux_T_215; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_219 = _out_wofireMux_T_2 & out_backSel_54; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_220 = _out_wofireMux_T_219; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_223 = _out_wofireMux_T_2 & out_backSel_55; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_224 = _out_wofireMux_T_223; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_227 = _out_wofireMux_T_2 & out_backSel_56; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_228 = _out_wofireMux_T_227 & _out_T_21; // @[RegisterRouter.scala:87:24]
assign out_woready_37 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_38 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_39 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_40 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_41 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_42 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_43 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_44 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_45 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_46 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_47 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_48 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_49 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_50 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
assign out_woready_51 = _out_wofireMux_T_228; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_229 = ~_out_T_21; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_231 = _out_wofireMux_T_2 & out_backSel_57; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_232 = _out_wofireMux_T_231 & _out_T_31; // @[RegisterRouter.scala:87:24]
assign out_woready_67 = _out_wofireMux_T_232; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_233 = ~_out_T_31; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_235 = _out_wofireMux_T_2 & out_backSel_58; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_236 = _out_wofireMux_T_235; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_239 = _out_wofireMux_T_2 & out_backSel_59; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_240 = _out_wofireMux_T_239; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_243 = _out_wofireMux_T_2 & out_backSel_60; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_244 = _out_wofireMux_T_243 & _out_T_35; // @[RegisterRouter.scala:87:24]
assign out_woready_72 = _out_wofireMux_T_244; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_245 = ~_out_T_35; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_247 = _out_wofireMux_T_2 & out_backSel_61; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_248 = _out_wofireMux_T_247 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_248; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_249 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_251 = _out_wofireMux_T_2 & out_backSel_62; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_252 = _out_wofireMux_T_251; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_255 = _out_wofireMux_T_2 & out_backSel_63; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_256 = _out_wofireMux_T_255; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [63:0] _GEN_29 = {{1'h1}, {1'h1}, {_out_out_bits_data_WIRE_61}, {_out_out_bits_data_WIRE_60}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_57}, {_out_out_bits_data_WIRE_56}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_50}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_47}, {_out_out_bits_data_WIRE_46}, {_out_out_bits_data_WIRE_45}, {_out_out_bits_data_WIRE_44}, {_out_out_bits_data_WIRE_43}, {_out_out_bits_data_WIRE_42}, {_out_out_bits_data_WIRE_41}, {_out_out_bits_data_WIRE_40}, {_out_out_bits_data_WIRE_39}, {_out_out_bits_data_WIRE_38}, {_out_out_bits_data_WIRE_37}, {_out_out_bits_data_WIRE_36}, {_out_out_bits_data_WIRE_35}, {_out_out_bits_data_WIRE_34}, {_out_out_bits_data_WIRE_33}, {_out_out_bits_data_WIRE_32}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_24}, {_out_out_bits_data_WIRE_23}, {_out_out_bits_data_WIRE_22}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_19}, {1'h1}, {_out_out_bits_data_WIRE_17}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_11}, {_out_out_bits_data_WIRE_10}, {_out_out_bits_data_WIRE_9}, {_out_out_bits_data_WIRE_8}, {_out_out_bits_data_WIRE_7}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {1'h1}, {1'h1}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_29[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [31:0] _out_out_bits_data_WIRE_1_17 = {9'h0, _out_T_1160}; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_22 = {3'h0, _out_T_1313}; // @[MuxLiteral.scala:49:48]
wire [31:0] _out_out_bits_data_WIRE_1_50 = {21'h0, _out_T_296}; // @[MuxLiteral.scala:49:48]
wire [63:0][31:0] _GEN_30 = {{32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_61}, {_out_out_bits_data_WIRE_1_60}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_57}, {_out_out_bits_data_WIRE_1_56}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_50}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_47}, {_out_out_bits_data_WIRE_1_46}, {_out_out_bits_data_WIRE_1_45}, {_out_out_bits_data_WIRE_1_44}, {_out_out_bits_data_WIRE_1_43}, {_out_out_bits_data_WIRE_1_42}, {_out_out_bits_data_WIRE_1_41}, {_out_out_bits_data_WIRE_1_40}, {_out_out_bits_data_WIRE_1_39}, {_out_out_bits_data_WIRE_1_38}, {_out_out_bits_data_WIRE_1_37}, {_out_out_bits_data_WIRE_1_36}, {_out_out_bits_data_WIRE_1_35}, {_out_out_bits_data_WIRE_1_34}, {_out_out_bits_data_WIRE_1_33}, {_out_out_bits_data_WIRE_1_32}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_24}, {_out_out_bits_data_WIRE_1_23}, {_out_out_bits_data_WIRE_1_22}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_19}, {32'h0}, {_out_out_bits_data_WIRE_1_17}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_11}, {_out_out_bits_data_WIRE_1_10}, {_out_out_bits_data_WIRE_1_9}, {_out_out_bits_data_WIRE_1_8}, {_out_out_bits_data_WIRE_1_7}, {_out_out_bits_data_WIRE_1_6}, {_out_out_bits_data_WIRE_1_5}, {_out_out_bits_data_WIRE_1_4}, {32'h0}, {32'h0}, {32'h0}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [31:0] _out_out_bits_data_T_3 = _GEN_30[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 32'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_bits_size = dmiNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign dmiNodeIn_d_bits_source = dmiNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign dmiNodeIn_d_bits_opcode = {2'h0, _dmiNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
reg goReg; // @[Debug.scala:1494:27]
wire goAbstract; // @[Debug.scala:1495:32]
wire goCustom; // @[Debug.scala:1496:32]
wire _flags_resume_T; // @[Debug.scala:1524:80]
wire _flags_resume_T_1; // @[Debug.scala:1524:80]
wire _flags_resume_T_2; // @[Debug.scala:1524:80]
wire _flags_resume_T_3; // @[Debug.scala:1524:80]
wire _flags_resume_T_4; // @[Debug.scala:1524:80]
wire _flags_resume_T_5; // @[Debug.scala:1524:80]
wire _flags_resume_T_6; // @[Debug.scala:1524:80]
wire _flags_resume_T_7; // @[Debug.scala:1524:80]
wire flags_0_resume; // @[Debug.scala:1517:25]
wire flags_0_go; // @[Debug.scala:1517:25]
wire flags_1_resume; // @[Debug.scala:1517:25]
wire flags_1_go; // @[Debug.scala:1517:25]
wire flags_2_resume; // @[Debug.scala:1517:25]
wire flags_2_go; // @[Debug.scala:1517:25]
wire flags_3_resume; // @[Debug.scala:1517:25]
wire flags_3_go; // @[Debug.scala:1517:25]
wire flags_4_resume; // @[Debug.scala:1517:25]
wire flags_4_go; // @[Debug.scala:1517:25]
wire flags_5_resume; // @[Debug.scala:1517:25]
wire flags_5_go; // @[Debug.scala:1517:25]
wire flags_6_resume; // @[Debug.scala:1517:25]
wire flags_6_go; // @[Debug.scala:1517:25]
wire flags_7_resume; // @[Debug.scala:1517:25]
wire flags_7_go; // @[Debug.scala:1517:25]
assign flags_0_go = _GEN & goReg; // @[Debug.scala:926:71, :1494:27, :1517:25, :1520:61]
assign flags_1_go = _GEN_0 & goReg; // @[Debug.scala:926:71, :1494:27, :1517:25, :1520:61]
assign flags_2_go = _GEN_1 & goReg; // @[Debug.scala:926:71, :1494:27, :1517:25, :1520:61]
assign flags_3_go = _GEN_2 & goReg; // @[Debug.scala:926:71, :1494:27, :1517:25, :1520:61]
assign flags_4_go = _GEN_3 & goReg; // @[Debug.scala:926:71, :1494:27, :1517:25, :1520:61]
assign flags_5_go = _GEN_4 & goReg; // @[Debug.scala:926:71, :1494:27, :1517:25, :1520:61]
assign flags_6_go = _GEN_5 & goReg; // @[Debug.scala:926:71, :1494:27, :1517:25, :1520:61]
assign flags_7_go = (&selectedHartReg) & goReg; // @[Debug.scala:901:30, :926:71, :1494:27, :1517:25, :1520:61]
assign _flags_resume_T = resumeReqRegs[0]; // @[Debug.scala:863:31, :1524:80]
assign flags_0_resume = _flags_resume_T; // @[Debug.scala:1517:25, :1524:80]
assign _flags_resume_T_1 = resumeReqRegs[1]; // @[Debug.scala:863:31, :1524:80]
assign flags_1_resume = _flags_resume_T_1; // @[Debug.scala:1517:25, :1524:80]
assign _flags_resume_T_2 = resumeReqRegs[2]; // @[Debug.scala:863:31, :1524:80]
assign flags_2_resume = _flags_resume_T_2; // @[Debug.scala:1517:25, :1524:80]
assign _flags_resume_T_3 = resumeReqRegs[3]; // @[Debug.scala:863:31, :1524:80]
assign flags_3_resume = _flags_resume_T_3; // @[Debug.scala:1517:25, :1524:80]
assign _flags_resume_T_4 = resumeReqRegs[4]; // @[Debug.scala:863:31, :1524:80]
assign flags_4_resume = _flags_resume_T_4; // @[Debug.scala:1517:25, :1524:80]
assign _flags_resume_T_5 = resumeReqRegs[5]; // @[Debug.scala:863:31, :1524:80]
assign flags_5_resume = _flags_resume_T_5; // @[Debug.scala:1517:25, :1524:80]
assign _flags_resume_T_6 = resumeReqRegs[6]; // @[Debug.scala:863:31, :1524:80]
assign flags_6_resume = _flags_resume_T_6; // @[Debug.scala:1517:25, :1524:80]
assign _flags_resume_T_7 = resumeReqRegs[7]; // @[Debug.scala:863:31, :1524:80]
assign flags_7_resume = _flags_resume_T_7; // @[Debug.scala:1517:25, :1524:80]
wire [31:0] _accessRegisterCommandWr_T = {COMMANDWrData_cmdtype, COMMANDWrData_control}; // @[Debug.scala:1280:39, :1531:59]
wire [31:0] _accessRegisterCommandWr_WIRE_1 = _accessRegisterCommandWr_T; // @[Debug.scala:1531:{59,74}]
wire [7:0] _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74]
wire _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74]
wire [7:0] accessRegisterCommandWr_cmdtype = _accessRegisterCommandWr_WIRE_cmdtype; // @[Debug.scala:1531:{44,74}]
wire [2:0] _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_reserved0 = _accessRegisterCommandWr_WIRE_reserved0; // @[Debug.scala:1531:{44,74}]
wire _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74]
wire [2:0] accessRegisterCommandWr_size = _accessRegisterCommandWr_WIRE_size; // @[Debug.scala:1531:{44,74}]
wire _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_reserved1 = _accessRegisterCommandWr_WIRE_reserved1; // @[Debug.scala:1531:{44,74}]
wire _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_postexec = _accessRegisterCommandWr_WIRE_postexec; // @[Debug.scala:1531:{44,74}]
wire _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_transfer = _accessRegisterCommandWr_WIRE_transfer; // @[Debug.scala:1531:{44,74}]
wire [15:0] _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74]
wire accessRegisterCommandWr_write = _accessRegisterCommandWr_WIRE_write; // @[Debug.scala:1531:{44,74}]
wire [15:0] accessRegisterCommandWr_regno = _accessRegisterCommandWr_WIRE_regno; // @[Debug.scala:1531:{44,74}]
assign _accessRegisterCommandWr_T_1 = _accessRegisterCommandWr_WIRE_1[15:0]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_regno = _accessRegisterCommandWr_T_1; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_2 = _accessRegisterCommandWr_WIRE_1[16]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_write = _accessRegisterCommandWr_T_2; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_3 = _accessRegisterCommandWr_WIRE_1[17]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_transfer = _accessRegisterCommandWr_T_3; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_4 = _accessRegisterCommandWr_WIRE_1[18]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_postexec = _accessRegisterCommandWr_T_4; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_5 = _accessRegisterCommandWr_WIRE_1[19]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_reserved1 = _accessRegisterCommandWr_T_5; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_6 = _accessRegisterCommandWr_WIRE_1[22:20]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_size = _accessRegisterCommandWr_T_6; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_7 = _accessRegisterCommandWr_WIRE_1[23]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_reserved0 = _accessRegisterCommandWr_T_7; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_T_8 = _accessRegisterCommandWr_WIRE_1[31:24]; // @[Debug.scala:1531:74]
assign _accessRegisterCommandWr_WIRE_cmdtype = _accessRegisterCommandWr_T_8; // @[Debug.scala:1531:74]
wire [31:0] _accessRegisterCommandReg_WIRE_1 = _accessRegisterCommandReg_T; // @[Debug.scala:1533:{56,71}]
wire [7:0] _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71]
wire _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71]
wire [7:0] accessRegisterCommandReg_cmdtype = _accessRegisterCommandReg_WIRE_cmdtype; // @[Debug.scala:1533:{44,71}]
wire [2:0] _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_reserved0 = _accessRegisterCommandReg_WIRE_reserved0; // @[Debug.scala:1533:{44,71}]
wire _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71]
wire [2:0] accessRegisterCommandReg_size = _accessRegisterCommandReg_WIRE_size; // @[Debug.scala:1533:{44,71}]
wire _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_reserved1 = _accessRegisterCommandReg_WIRE_reserved1; // @[Debug.scala:1533:{44,71}]
wire _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_postexec = _accessRegisterCommandReg_WIRE_postexec; // @[Debug.scala:1533:{44,71}]
wire _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_transfer = _accessRegisterCommandReg_WIRE_transfer; // @[Debug.scala:1533:{44,71}]
wire [15:0] _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71]
wire accessRegisterCommandReg_write = _accessRegisterCommandReg_WIRE_write; // @[Debug.scala:1533:{44,71}]
wire [15:0] accessRegisterCommandReg_regno = _accessRegisterCommandReg_WIRE_regno; // @[Debug.scala:1533:{44,71}]
assign _accessRegisterCommandReg_T_1 = _accessRegisterCommandReg_WIRE_1[15:0]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_regno = _accessRegisterCommandReg_T_1; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_2 = _accessRegisterCommandReg_WIRE_1[16]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_write = _accessRegisterCommandReg_T_2; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_3 = _accessRegisterCommandReg_WIRE_1[17]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_transfer = _accessRegisterCommandReg_T_3; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_4 = _accessRegisterCommandReg_WIRE_1[18]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_postexec = _accessRegisterCommandReg_T_4; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_5 = _accessRegisterCommandReg_WIRE_1[19]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_reserved1 = _accessRegisterCommandReg_T_5; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_6 = _accessRegisterCommandReg_WIRE_1[22:20]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_size = _accessRegisterCommandReg_T_6; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_7 = _accessRegisterCommandReg_WIRE_1[23]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_reserved0 = _accessRegisterCommandReg_T_7; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_T_8 = _accessRegisterCommandReg_WIRE_1[31:24]; // @[Debug.scala:1533:71]
assign _accessRegisterCommandReg_WIRE_cmdtype = _accessRegisterCommandReg_T_8; // @[Debug.scala:1533:71]
wire [2:0] abstractGeneratedMem_0_inst_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1589:22]
wire [2:0] abstractGeneratedMem_0_inst_1_funct3 = accessRegisterCommandReg_size; // @[Debug.scala:1533:44, :1601:22]
reg [31:0] abstractGeneratedMem_0; // @[Debug.scala:1586:35]
wire [31:0] _out_T_3386 = abstractGeneratedMem_0; // @[RegisterRouter.scala:87:24]
reg [31:0] abstractGeneratedMem_1; // @[Debug.scala:1586:35]
wire [4:0] abstractGeneratedMem_0_inst_rd; // @[Debug.scala:1589:22]
wire [15:0] _GEN_31 = {11'h0, accessRegisterCommandReg_regno[4:0]}; // @[Debug.scala:1533:44, :1593:54]
wire [15:0] _abstractGeneratedMem_0_inst_rd_T; // @[Debug.scala:1593:54]
assign _abstractGeneratedMem_0_inst_rd_T = _GEN_31; // @[Debug.scala:1593:54]
wire [15:0] _abstractGeneratedMem_0_inst_rs2_T; // @[Debug.scala:1608:54]
assign _abstractGeneratedMem_0_inst_rs2_T = _GEN_31; // @[Debug.scala:1593:54, :1608:54]
assign abstractGeneratedMem_0_inst_rd = _abstractGeneratedMem_0_inst_rd_T[4:0]; // @[Debug.scala:1589:22, :1593:{19,54}]
wire [11:0] abstractGeneratedMem_0_lo = {abstractGeneratedMem_0_inst_rd, 7'h3}; // @[Debug.scala:1589:22, :1597:12]
wire [19:0] abstractGeneratedMem_0_hi = {17'h7000, abstractGeneratedMem_0_inst_funct3}; // @[Debug.scala:1589:22, :1597:12]
wire [31:0] _abstractGeneratedMem_0_T = {abstractGeneratedMem_0_hi, abstractGeneratedMem_0_lo}; // @[Debug.scala:1597:12]
wire [4:0] abstractGeneratedMem_0_inst_1_rs2; // @[Debug.scala:1601:22]
assign abstractGeneratedMem_0_inst_1_rs2 = _abstractGeneratedMem_0_inst_rs2_T[4:0]; // @[Debug.scala:1601:22, :1608:{19,54}]
wire [7:0] abstractGeneratedMem_0_lo_hi = {abstractGeneratedMem_0_inst_1_funct3, 5'h0}; // @[Debug.scala:1601:22, :1610:12]
wire [14:0] abstractGeneratedMem_0_lo_1 = {abstractGeneratedMem_0_lo_hi, 7'h23}; // @[Debug.scala:1610:12]
wire [11:0] abstractGeneratedMem_0_hi_hi_1 = {7'h1C, abstractGeneratedMem_0_inst_1_rs2}; // @[Debug.scala:1601:22, :1610:12]
wire [16:0] abstractGeneratedMem_0_hi_1 = {abstractGeneratedMem_0_hi_hi_1, 5'h0}; // @[Debug.scala:1610:12]
wire [31:0] _abstractGeneratedMem_0_T_1 = {abstractGeneratedMem_0_hi_1, abstractGeneratedMem_0_lo_1}; // @[Debug.scala:1610:12]
wire [31:0] _abstractGeneratedMem_0_T_2 = accessRegisterCommandReg_write ? _abstractGeneratedMem_0_T : _abstractGeneratedMem_0_T_1; // @[Debug.scala:1533:44, :1597:12, :1610:12, :1641:14]
wire [31:0] _abstractGeneratedMem_0_T_4 = accessRegisterCommandReg_transfer ? _abstractGeneratedMem_0_T_2 : 32'h13; // @[Debug.scala:1533:44, :1640:39, :1641:14]
wire [31:0] _abstractGeneratedMem_1_T_1 = accessRegisterCommandReg_postexec ? 32'h13 : 32'h100073; // @[Debug.scala:1533:44, :1644:39]
wire [6:0] hi_1 = {6'h0, flags_0_resume}; // @[Debug.scala:1517:25, :1704:64]
wire [7:0] _out_T_3100 = {hi_1, flags_0_go}; // @[RegisterRouter.scala:87:24]
wire [6:0] hi_2 = {6'h0, flags_1_resume}; // @[Debug.scala:1517:25, :1704:64]
wire [6:0] hi_3 = {6'h0, flags_2_resume}; // @[Debug.scala:1517:25, :1704:64]
wire [6:0] hi_4 = {6'h0, flags_3_resume}; // @[Debug.scala:1517:25, :1704:64]
wire [6:0] hi_5 = {6'h0, flags_4_resume}; // @[Debug.scala:1517:25, :1704:64]
wire [6:0] hi_6 = {6'h0, flags_5_resume}; // @[Debug.scala:1517:25, :1704:64]
wire [6:0] hi_7 = {6'h0, flags_6_resume}; // @[Debug.scala:1517:25, :1704:64]
wire [6:0] hi_8 = {6'h0, flags_7_resume}; // @[Debug.scala:1517:25, :1704:64]
wire _out_in_ready_T_1; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_a_ready = in_1_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T_1; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T_1 = in_1_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] _in_bits_index_T_1; // @[Edges.scala:192:34]
wire out_front_1_bits_read = in_1_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_1_bits_index = in_1_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_1_bits_data = in_1_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_1_bits_mask = in_1_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_1_bits_extra_tlrr_extra_source = in_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_1_bits_extra_tlrr_extra_size = in_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T_1 = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_1_bits_read = _in_bits_read_T_1; // @[RegisterRouter.scala:73:18, :74:36]
assign _in_bits_index_T_1 = tlNodeIn_a_bits_address[11:3]; // @[Edges.scala:192:34]
assign in_1_bits_index = _in_bits_index_T_1; // @[RegisterRouter.scala:73:18]
wire _out_front_ready_T_1 = out_1_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T_1; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_valid = out_1_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_61; // @[RegisterRouter.scala:87:24]
wire _tlNodeIn_d_bits_opcode_T = out_1_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign tlNodeIn_d_bits_data = out_1_bits_data; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_d_source = out_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_d_size = out_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T_1 = out_front_1_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T_1 = out_front_1_valid; // @[RegisterRouter.scala:87:24]
assign out_1_bits_read = out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
assign out_1_bits_extra_tlrr_extra_source = out_front_1_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_1_bits_extra_tlrr_extra_size = out_front_1_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [8:0] _GEN_32 = out_front_1_bits_index & 9'h20; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex_1; // @[RegisterRouter.scala:87:24]
assign out_findex_1 = _GEN_32; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex_1; // @[RegisterRouter.scala:87:24]
assign out_bindex_1 = _GEN_32; // @[RegisterRouter.scala:87:24]
wire _GEN_33 = out_findex_1 == 9'h20; // @[RegisterRouter.scala:87:24]
wire _out_T_1642; // @[RegisterRouter.scala:87:24]
assign _out_T_1642 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1646; // @[RegisterRouter.scala:87:24]
assign _out_T_1646 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1650; // @[RegisterRouter.scala:87:24]
assign _out_T_1650 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1656; // @[RegisterRouter.scala:87:24]
assign _out_T_1656 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1658; // @[RegisterRouter.scala:87:24]
assign _out_T_1658 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1662; // @[RegisterRouter.scala:87:24]
assign _out_T_1662 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1666; // @[RegisterRouter.scala:87:24]
assign _out_T_1666 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1668; // @[RegisterRouter.scala:87:24]
assign _out_T_1668 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1672; // @[RegisterRouter.scala:87:24]
assign _out_T_1672 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1674; // @[RegisterRouter.scala:87:24]
assign _out_T_1674 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1676; // @[RegisterRouter.scala:87:24]
assign _out_T_1676 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1682; // @[RegisterRouter.scala:87:24]
assign _out_T_1682 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1686; // @[RegisterRouter.scala:87:24]
assign _out_T_1686 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1690; // @[RegisterRouter.scala:87:24]
assign _out_T_1690 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1692; // @[RegisterRouter.scala:87:24]
assign _out_T_1692 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _out_T_1696; // @[RegisterRouter.scala:87:24]
assign _out_T_1696 = _GEN_33; // @[RegisterRouter.scala:87:24]
wire _GEN_34 = out_bindex_1 == 9'h20; // @[RegisterRouter.scala:87:24]
wire _out_T_1643; // @[RegisterRouter.scala:87:24]
assign _out_T_1643 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1647; // @[RegisterRouter.scala:87:24]
assign _out_T_1647 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1651; // @[RegisterRouter.scala:87:24]
assign _out_T_1651 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1657; // @[RegisterRouter.scala:87:24]
assign _out_T_1657 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1659; // @[RegisterRouter.scala:87:24]
assign _out_T_1659 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1663; // @[RegisterRouter.scala:87:24]
assign _out_T_1663 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1667; // @[RegisterRouter.scala:87:24]
assign _out_T_1667 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1669; // @[RegisterRouter.scala:87:24]
assign _out_T_1669 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1673; // @[RegisterRouter.scala:87:24]
assign _out_T_1673 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1675; // @[RegisterRouter.scala:87:24]
assign _out_T_1675 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1677; // @[RegisterRouter.scala:87:24]
assign _out_T_1677 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1683; // @[RegisterRouter.scala:87:24]
assign _out_T_1683 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1687; // @[RegisterRouter.scala:87:24]
assign _out_T_1687 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1691; // @[RegisterRouter.scala:87:24]
assign _out_T_1691 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1693; // @[RegisterRouter.scala:87:24]
assign _out_T_1693 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _out_T_1697; // @[RegisterRouter.scala:87:24]
assign _out_T_1697 = _GEN_34; // @[RegisterRouter.scala:87:24]
wire _GEN_35 = out_findex_1 == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1644; // @[RegisterRouter.scala:87:24]
assign _out_T_1644 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1648; // @[RegisterRouter.scala:87:24]
assign _out_T_1648 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1652; // @[RegisterRouter.scala:87:24]
assign _out_T_1652 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1654; // @[RegisterRouter.scala:87:24]
assign _out_T_1654 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1660; // @[RegisterRouter.scala:87:24]
assign _out_T_1660 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1664; // @[RegisterRouter.scala:87:24]
assign _out_T_1664 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1670; // @[RegisterRouter.scala:87:24]
assign _out_T_1670 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1678; // @[RegisterRouter.scala:87:24]
assign _out_T_1678 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1680; // @[RegisterRouter.scala:87:24]
assign _out_T_1680 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1684; // @[RegisterRouter.scala:87:24]
assign _out_T_1684 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1688; // @[RegisterRouter.scala:87:24]
assign _out_T_1688 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _out_T_1694; // @[RegisterRouter.scala:87:24]
assign _out_T_1694 = _GEN_35; // @[RegisterRouter.scala:87:24]
wire _GEN_36 = out_bindex_1 == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1645; // @[RegisterRouter.scala:87:24]
assign _out_T_1645 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1649; // @[RegisterRouter.scala:87:24]
assign _out_T_1649 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1653; // @[RegisterRouter.scala:87:24]
assign _out_T_1653 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1655; // @[RegisterRouter.scala:87:24]
assign _out_T_1655 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1661; // @[RegisterRouter.scala:87:24]
assign _out_T_1661 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1665; // @[RegisterRouter.scala:87:24]
assign _out_T_1665 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1671; // @[RegisterRouter.scala:87:24]
assign _out_T_1671 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1679; // @[RegisterRouter.scala:87:24]
assign _out_T_1679 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1681; // @[RegisterRouter.scala:87:24]
assign _out_T_1681 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1685; // @[RegisterRouter.scala:87:24]
assign _out_T_1685 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1689; // @[RegisterRouter.scala:87:24]
assign _out_T_1689 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_T_1695; // @[RegisterRouter.scala:87:24]
assign _out_T_1695 = _GEN_36; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_418; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_16; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_17; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_18; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_19; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_20; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_21; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_22; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_23; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_24; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_25; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_26; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_27; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_28; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_29; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_30; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_31; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_32; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_33; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_34; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_35; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_36; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_37; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_38; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_39; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_40; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_41; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_42; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_43; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_44; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_45; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_46; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_47; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_48; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_49; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_50; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_51; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_52; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_53; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_54; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_55; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_56; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_57; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_58; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_59; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_60; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_61; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_62; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_63; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_64; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_65; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_66; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_67; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_68; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_69; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_70; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_71; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_72; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_73; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_74; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_75; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_76; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_77; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_78; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_79; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_80; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_81; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_82; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_83; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_84; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_85; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_86; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_87; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_88; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_89; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_90; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_91; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_92; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_93; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_94; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_95; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_96; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_97; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_98; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_99; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_100; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_101; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_102; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_103; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_104; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_105; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_106; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_107; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_108; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_109; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_110; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_111; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_112; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_113; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_114; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_115; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_116; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_117; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_118; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_119; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_120; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_121; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_122; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_123; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_124; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_125; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_126; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_127; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_128; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_129; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_130; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_131; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_132; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_133; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_134; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_135; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_136; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_137; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_138; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_139; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_140; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_141; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_142; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_143; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_144; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_145; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_146; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_147; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_148; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_149; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_150; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_151; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_152; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_153; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_154; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_155; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_156; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_157; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_158; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_159; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_160; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_161; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_162; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_163; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_164; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_165; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_166; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_167; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_168; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_169; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_170; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_171; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_172; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_173; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_174; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_175; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_176; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_177; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_178; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_179; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_180; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_181; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_182; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_183; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_184; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_185; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_186; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_187; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_188; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_189; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_190; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_191; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_192; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_193; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1_194; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_420; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_15; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_17; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_18; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_19; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_20; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_21; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_22; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_23; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_24; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_25; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_26; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_27; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_28; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_29; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_30; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_31; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_32; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_33; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_34; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_35; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_36; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_37; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_38; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_39; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_40; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_41; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_42; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_43; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_44; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_45; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_46; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_47; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_48; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_49; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_50; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_51; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_52; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_53; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_54; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_55; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_56; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_57; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_58; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_59; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_60; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_61; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_62; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_63; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_64; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_65; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_66; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_67; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_68; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_69; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_70; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_71; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_72; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_73; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_74; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_75; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_76; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_77; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_78; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_79; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_80; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_81; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_82; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_83; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_84; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_85; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_86; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_87; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_88; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_89; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_90; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_91; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_92; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_93; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_94; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_95; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_96; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_97; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_98; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_99; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_100; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_101; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_102; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_103; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_104; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_105; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_106; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_107; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_108; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_109; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_110; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_111; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_112; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_113; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_114; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_115; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_116; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_117; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_118; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_119; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_120; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_121; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_122; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_123; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_124; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_125; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_126; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_127; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_128; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_129; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_130; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_131; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_132; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_133; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_134; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_135; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_136; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_137; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_138; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_139; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_140; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_141; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_142; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_143; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_144; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_145; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_146; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_147; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_148; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_149; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_150; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_151; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_152; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_153; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_154; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_155; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_156; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_157; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_158; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_159; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_160; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_161; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_162; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_163; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_164; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_165; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_166; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_167; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_168; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_169; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_170; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_171; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_172; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_173; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_174; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_175; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_176; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_177; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_178; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_179; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_180; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_181; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_182; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_183; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_184; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_185; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_186; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_187; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_188; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_189; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_190; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_191; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_192; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_193; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1_194; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_418; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
wire out_roready_1_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1_1; // @[RegisterRouter.scala:87:24]
wire out_roready_1_2; // @[RegisterRouter.scala:87:24]
wire out_roready_1_3; // @[RegisterRouter.scala:87:24]
wire out_roready_1_4; // @[RegisterRouter.scala:87:24]
wire out_roready_1_5; // @[RegisterRouter.scala:87:24]
wire out_roready_1_6; // @[RegisterRouter.scala:87:24]
wire out_roready_1_7; // @[RegisterRouter.scala:87:24]
wire out_roready_1_8; // @[RegisterRouter.scala:87:24]
wire out_roready_1_9; // @[RegisterRouter.scala:87:24]
wire out_roready_1_10; // @[RegisterRouter.scala:87:24]
wire out_roready_1_11; // @[RegisterRouter.scala:87:24]
wire out_roready_1_12; // @[RegisterRouter.scala:87:24]
wire out_roready_1_13; // @[RegisterRouter.scala:87:24]
wire out_roready_1_14; // @[RegisterRouter.scala:87:24]
wire out_roready_1_15; // @[RegisterRouter.scala:87:24]
wire out_roready_1_16; // @[RegisterRouter.scala:87:24]
wire out_roready_1_17; // @[RegisterRouter.scala:87:24]
wire out_roready_1_18; // @[RegisterRouter.scala:87:24]
wire out_roready_1_19; // @[RegisterRouter.scala:87:24]
wire out_roready_1_20; // @[RegisterRouter.scala:87:24]
wire out_roready_1_21; // @[RegisterRouter.scala:87:24]
wire out_roready_1_22; // @[RegisterRouter.scala:87:24]
wire out_roready_1_23; // @[RegisterRouter.scala:87:24]
wire out_roready_1_24; // @[RegisterRouter.scala:87:24]
wire out_roready_1_25; // @[RegisterRouter.scala:87:24]
wire out_roready_1_26; // @[RegisterRouter.scala:87:24]
wire out_roready_1_27; // @[RegisterRouter.scala:87:24]
wire out_roready_1_28; // @[RegisterRouter.scala:87:24]
wire out_roready_1_29; // @[RegisterRouter.scala:87:24]
wire out_roready_1_30; // @[RegisterRouter.scala:87:24]
wire out_roready_1_31; // @[RegisterRouter.scala:87:24]
wire out_roready_1_32; // @[RegisterRouter.scala:87:24]
wire out_roready_1_33; // @[RegisterRouter.scala:87:24]
wire out_roready_1_34; // @[RegisterRouter.scala:87:24]
wire out_roready_1_35; // @[RegisterRouter.scala:87:24]
wire out_roready_1_36; // @[RegisterRouter.scala:87:24]
wire out_roready_1_37; // @[RegisterRouter.scala:87:24]
wire out_roready_1_38; // @[RegisterRouter.scala:87:24]
wire out_roready_1_39; // @[RegisterRouter.scala:87:24]
wire out_roready_1_40; // @[RegisterRouter.scala:87:24]
wire out_roready_1_41; // @[RegisterRouter.scala:87:24]
wire out_roready_1_42; // @[RegisterRouter.scala:87:24]
wire out_roready_1_43; // @[RegisterRouter.scala:87:24]
wire out_roready_1_44; // @[RegisterRouter.scala:87:24]
wire out_roready_1_45; // @[RegisterRouter.scala:87:24]
wire out_roready_1_46; // @[RegisterRouter.scala:87:24]
wire out_roready_1_47; // @[RegisterRouter.scala:87:24]
wire out_roready_1_48; // @[RegisterRouter.scala:87:24]
wire out_roready_1_49; // @[RegisterRouter.scala:87:24]
wire out_roready_1_50; // @[RegisterRouter.scala:87:24]
wire out_roready_1_51; // @[RegisterRouter.scala:87:24]
wire out_roready_1_52; // @[RegisterRouter.scala:87:24]
wire out_roready_1_53; // @[RegisterRouter.scala:87:24]
wire out_roready_1_54; // @[RegisterRouter.scala:87:24]
wire out_roready_1_55; // @[RegisterRouter.scala:87:24]
wire out_roready_1_56; // @[RegisterRouter.scala:87:24]
wire out_roready_1_57; // @[RegisterRouter.scala:87:24]
wire out_roready_1_58; // @[RegisterRouter.scala:87:24]
wire out_roready_1_59; // @[RegisterRouter.scala:87:24]
wire out_roready_1_60; // @[RegisterRouter.scala:87:24]
wire out_roready_1_61; // @[RegisterRouter.scala:87:24]
wire out_roready_1_62; // @[RegisterRouter.scala:87:24]
wire out_roready_1_63; // @[RegisterRouter.scala:87:24]
wire out_roready_1_64; // @[RegisterRouter.scala:87:24]
wire out_roready_1_65; // @[RegisterRouter.scala:87:24]
wire out_roready_1_66; // @[RegisterRouter.scala:87:24]
wire out_roready_1_67; // @[RegisterRouter.scala:87:24]
wire out_roready_1_68; // @[RegisterRouter.scala:87:24]
wire out_roready_1_69; // @[RegisterRouter.scala:87:24]
wire out_roready_1_70; // @[RegisterRouter.scala:87:24]
wire out_roready_1_71; // @[RegisterRouter.scala:87:24]
wire out_roready_1_72; // @[RegisterRouter.scala:87:24]
wire out_roready_1_73; // @[RegisterRouter.scala:87:24]
wire out_roready_1_74; // @[RegisterRouter.scala:87:24]
wire out_roready_1_75; // @[RegisterRouter.scala:87:24]
wire out_roready_1_76; // @[RegisterRouter.scala:87:24]
wire out_roready_1_77; // @[RegisterRouter.scala:87:24]
wire out_roready_1_78; // @[RegisterRouter.scala:87:24]
wire out_roready_1_79; // @[RegisterRouter.scala:87:24]
wire out_roready_1_80; // @[RegisterRouter.scala:87:24]
wire out_roready_1_81; // @[RegisterRouter.scala:87:24]
wire out_roready_1_82; // @[RegisterRouter.scala:87:24]
wire out_roready_1_83; // @[RegisterRouter.scala:87:24]
wire out_roready_1_84; // @[RegisterRouter.scala:87:24]
wire out_roready_1_85; // @[RegisterRouter.scala:87:24]
wire out_roready_1_86; // @[RegisterRouter.scala:87:24]
wire out_roready_1_87; // @[RegisterRouter.scala:87:24]
wire out_roready_1_88; // @[RegisterRouter.scala:87:24]
wire out_roready_1_89; // @[RegisterRouter.scala:87:24]
wire out_roready_1_90; // @[RegisterRouter.scala:87:24]
wire out_roready_1_91; // @[RegisterRouter.scala:87:24]
wire out_roready_1_92; // @[RegisterRouter.scala:87:24]
wire out_roready_1_93; // @[RegisterRouter.scala:87:24]
wire out_roready_1_94; // @[RegisterRouter.scala:87:24]
wire out_roready_1_95; // @[RegisterRouter.scala:87:24]
wire out_roready_1_96; // @[RegisterRouter.scala:87:24]
wire out_roready_1_97; // @[RegisterRouter.scala:87:24]
wire out_roready_1_98; // @[RegisterRouter.scala:87:24]
wire out_roready_1_99; // @[RegisterRouter.scala:87:24]
wire out_roready_1_100; // @[RegisterRouter.scala:87:24]
wire out_roready_1_101; // @[RegisterRouter.scala:87:24]
wire out_roready_1_102; // @[RegisterRouter.scala:87:24]
wire out_roready_1_103; // @[RegisterRouter.scala:87:24]
wire out_roready_1_104; // @[RegisterRouter.scala:87:24]
wire out_roready_1_105; // @[RegisterRouter.scala:87:24]
wire out_roready_1_106; // @[RegisterRouter.scala:87:24]
wire out_roready_1_107; // @[RegisterRouter.scala:87:24]
wire out_roready_1_108; // @[RegisterRouter.scala:87:24]
wire out_roready_1_109; // @[RegisterRouter.scala:87:24]
wire out_roready_1_110; // @[RegisterRouter.scala:87:24]
wire out_roready_1_111; // @[RegisterRouter.scala:87:24]
wire out_roready_1_112; // @[RegisterRouter.scala:87:24]
wire out_roready_1_113; // @[RegisterRouter.scala:87:24]
wire out_roready_1_114; // @[RegisterRouter.scala:87:24]
wire out_roready_1_115; // @[RegisterRouter.scala:87:24]
wire out_roready_1_116; // @[RegisterRouter.scala:87:24]
wire out_roready_1_117; // @[RegisterRouter.scala:87:24]
wire out_roready_1_118; // @[RegisterRouter.scala:87:24]
wire out_roready_1_119; // @[RegisterRouter.scala:87:24]
wire out_roready_1_120; // @[RegisterRouter.scala:87:24]
wire out_roready_1_121; // @[RegisterRouter.scala:87:24]
wire out_roready_1_122; // @[RegisterRouter.scala:87:24]
wire out_roready_1_123; // @[RegisterRouter.scala:87:24]
wire out_roready_1_124; // @[RegisterRouter.scala:87:24]
wire out_roready_1_125; // @[RegisterRouter.scala:87:24]
wire out_roready_1_126; // @[RegisterRouter.scala:87:24]
wire out_roready_1_127; // @[RegisterRouter.scala:87:24]
wire out_roready_1_128; // @[RegisterRouter.scala:87:24]
wire out_roready_1_129; // @[RegisterRouter.scala:87:24]
wire out_roready_1_130; // @[RegisterRouter.scala:87:24]
wire out_roready_1_131; // @[RegisterRouter.scala:87:24]
wire out_roready_1_132; // @[RegisterRouter.scala:87:24]
wire out_roready_1_133; // @[RegisterRouter.scala:87:24]
wire out_roready_1_134; // @[RegisterRouter.scala:87:24]
wire out_roready_1_135; // @[RegisterRouter.scala:87:24]
wire out_roready_1_136; // @[RegisterRouter.scala:87:24]
wire out_roready_1_137; // @[RegisterRouter.scala:87:24]
wire out_roready_1_138; // @[RegisterRouter.scala:87:24]
wire out_roready_1_139; // @[RegisterRouter.scala:87:24]
wire out_roready_1_140; // @[RegisterRouter.scala:87:24]
wire out_roready_1_141; // @[RegisterRouter.scala:87:24]
wire out_roready_1_142; // @[RegisterRouter.scala:87:24]
wire out_roready_1_143; // @[RegisterRouter.scala:87:24]
wire out_roready_1_144; // @[RegisterRouter.scala:87:24]
wire out_roready_1_145; // @[RegisterRouter.scala:87:24]
wire out_roready_1_146; // @[RegisterRouter.scala:87:24]
wire out_roready_1_147; // @[RegisterRouter.scala:87:24]
wire out_roready_1_148; // @[RegisterRouter.scala:87:24]
wire out_roready_1_149; // @[RegisterRouter.scala:87:24]
wire out_roready_1_150; // @[RegisterRouter.scala:87:24]
wire out_roready_1_151; // @[RegisterRouter.scala:87:24]
wire out_roready_1_152; // @[RegisterRouter.scala:87:24]
wire out_roready_1_153; // @[RegisterRouter.scala:87:24]
wire out_roready_1_154; // @[RegisterRouter.scala:87:24]
wire out_roready_1_155; // @[RegisterRouter.scala:87:24]
wire out_roready_1_156; // @[RegisterRouter.scala:87:24]
wire out_roready_1_157; // @[RegisterRouter.scala:87:24]
wire out_roready_1_158; // @[RegisterRouter.scala:87:24]
wire out_roready_1_159; // @[RegisterRouter.scala:87:24]
wire out_roready_1_160; // @[RegisterRouter.scala:87:24]
wire out_roready_1_161; // @[RegisterRouter.scala:87:24]
wire out_roready_1_162; // @[RegisterRouter.scala:87:24]
wire out_roready_1_163; // @[RegisterRouter.scala:87:24]
wire out_roready_1_164; // @[RegisterRouter.scala:87:24]
wire out_roready_1_165; // @[RegisterRouter.scala:87:24]
wire out_roready_1_166; // @[RegisterRouter.scala:87:24]
wire out_roready_1_167; // @[RegisterRouter.scala:87:24]
wire out_roready_1_168; // @[RegisterRouter.scala:87:24]
wire out_roready_1_169; // @[RegisterRouter.scala:87:24]
wire out_roready_1_170; // @[RegisterRouter.scala:87:24]
wire out_roready_1_171; // @[RegisterRouter.scala:87:24]
wire out_roready_1_172; // @[RegisterRouter.scala:87:24]
wire out_roready_1_173; // @[RegisterRouter.scala:87:24]
wire out_roready_1_174; // @[RegisterRouter.scala:87:24]
wire out_roready_1_175; // @[RegisterRouter.scala:87:24]
wire out_roready_1_176; // @[RegisterRouter.scala:87:24]
wire out_roready_1_177; // @[RegisterRouter.scala:87:24]
wire out_roready_1_178; // @[RegisterRouter.scala:87:24]
wire out_roready_1_179; // @[RegisterRouter.scala:87:24]
wire out_roready_1_180; // @[RegisterRouter.scala:87:24]
wire out_roready_1_181; // @[RegisterRouter.scala:87:24]
wire out_roready_1_182; // @[RegisterRouter.scala:87:24]
wire out_roready_1_183; // @[RegisterRouter.scala:87:24]
wire out_roready_1_184; // @[RegisterRouter.scala:87:24]
wire out_roready_1_185; // @[RegisterRouter.scala:87:24]
wire out_roready_1_186; // @[RegisterRouter.scala:87:24]
wire out_roready_1_187; // @[RegisterRouter.scala:87:24]
wire out_roready_1_188; // @[RegisterRouter.scala:87:24]
wire out_roready_1_189; // @[RegisterRouter.scala:87:24]
wire out_roready_1_190; // @[RegisterRouter.scala:87:24]
wire out_roready_1_191; // @[RegisterRouter.scala:87:24]
wire out_roready_1_192; // @[RegisterRouter.scala:87:24]
wire out_roready_1_193; // @[RegisterRouter.scala:87:24]
wire out_roready_1_194; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_420; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
wire out_woready_1_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1_1; // @[RegisterRouter.scala:87:24]
wire out_woready_1_2; // @[RegisterRouter.scala:87:24]
wire out_woready_1_3; // @[RegisterRouter.scala:87:24]
wire out_woready_1_4; // @[RegisterRouter.scala:87:24]
wire out_woready_1_5; // @[RegisterRouter.scala:87:24]
wire out_woready_1_6; // @[RegisterRouter.scala:87:24]
wire out_woready_1_7; // @[RegisterRouter.scala:87:24]
wire out_woready_1_8; // @[RegisterRouter.scala:87:24]
wire out_woready_1_9; // @[RegisterRouter.scala:87:24]
wire out_woready_1_10; // @[RegisterRouter.scala:87:24]
wire out_woready_1_11; // @[RegisterRouter.scala:87:24]
wire out_woready_1_12; // @[RegisterRouter.scala:87:24]
wire out_woready_1_13; // @[RegisterRouter.scala:87:24]
wire out_woready_1_14; // @[RegisterRouter.scala:87:24]
wire out_woready_1_15; // @[RegisterRouter.scala:87:24]
wire out_woready_1_16; // @[RegisterRouter.scala:87:24]
wire out_woready_1_17; // @[RegisterRouter.scala:87:24]
wire out_woready_1_18; // @[RegisterRouter.scala:87:24]
wire out_woready_1_19; // @[RegisterRouter.scala:87:24]
wire out_woready_1_20; // @[RegisterRouter.scala:87:24]
wire out_woready_1_21; // @[RegisterRouter.scala:87:24]
wire out_woready_1_22; // @[RegisterRouter.scala:87:24]
wire out_woready_1_23; // @[RegisterRouter.scala:87:24]
wire out_woready_1_24; // @[RegisterRouter.scala:87:24]
wire out_woready_1_25; // @[RegisterRouter.scala:87:24]
wire out_woready_1_26; // @[RegisterRouter.scala:87:24]
wire out_woready_1_27; // @[RegisterRouter.scala:87:24]
wire out_woready_1_28; // @[RegisterRouter.scala:87:24]
wire out_woready_1_29; // @[RegisterRouter.scala:87:24]
wire out_woready_1_30; // @[RegisterRouter.scala:87:24]
wire out_woready_1_31; // @[RegisterRouter.scala:87:24]
wire out_woready_1_32; // @[RegisterRouter.scala:87:24]
wire out_woready_1_33; // @[RegisterRouter.scala:87:24]
wire out_woready_1_34; // @[RegisterRouter.scala:87:24]
wire out_woready_1_35; // @[RegisterRouter.scala:87:24]
wire out_woready_1_36; // @[RegisterRouter.scala:87:24]
wire out_woready_1_37; // @[RegisterRouter.scala:87:24]
wire out_woready_1_38; // @[RegisterRouter.scala:87:24]
wire out_woready_1_39; // @[RegisterRouter.scala:87:24]
wire out_woready_1_40; // @[RegisterRouter.scala:87:24]
wire out_woready_1_41; // @[RegisterRouter.scala:87:24]
wire out_woready_1_42; // @[RegisterRouter.scala:87:24]
wire out_woready_1_43; // @[RegisterRouter.scala:87:24]
wire out_woready_1_44; // @[RegisterRouter.scala:87:24]
wire out_woready_1_45; // @[RegisterRouter.scala:87:24]
wire out_woready_1_46; // @[RegisterRouter.scala:87:24]
wire out_woready_1_47; // @[RegisterRouter.scala:87:24]
wire out_woready_1_48; // @[RegisterRouter.scala:87:24]
wire out_woready_1_49; // @[RegisterRouter.scala:87:24]
wire out_woready_1_50; // @[RegisterRouter.scala:87:24]
wire out_woready_1_51; // @[RegisterRouter.scala:87:24]
wire out_woready_1_52; // @[RegisterRouter.scala:87:24]
wire out_woready_1_53; // @[RegisterRouter.scala:87:24]
wire out_woready_1_54; // @[RegisterRouter.scala:87:24]
wire out_woready_1_55; // @[RegisterRouter.scala:87:24]
wire out_woready_1_56; // @[RegisterRouter.scala:87:24]
wire out_woready_1_57; // @[RegisterRouter.scala:87:24]
wire out_woready_1_58; // @[RegisterRouter.scala:87:24]
wire out_woready_1_59; // @[RegisterRouter.scala:87:24]
wire out_woready_1_60; // @[RegisterRouter.scala:87:24]
wire out_woready_1_61; // @[RegisterRouter.scala:87:24]
wire out_woready_1_62; // @[RegisterRouter.scala:87:24]
wire out_woready_1_63; // @[RegisterRouter.scala:87:24]
wire out_woready_1_64; // @[RegisterRouter.scala:87:24]
wire out_woready_1_65; // @[RegisterRouter.scala:87:24]
wire out_woready_1_66; // @[RegisterRouter.scala:87:24]
wire out_woready_1_67; // @[RegisterRouter.scala:87:24]
wire out_woready_1_68; // @[RegisterRouter.scala:87:24]
wire out_woready_1_69; // @[RegisterRouter.scala:87:24]
wire out_woready_1_70; // @[RegisterRouter.scala:87:24]
wire out_woready_1_71; // @[RegisterRouter.scala:87:24]
wire out_woready_1_72; // @[RegisterRouter.scala:87:24]
wire out_woready_1_73; // @[RegisterRouter.scala:87:24]
wire out_woready_1_74; // @[RegisterRouter.scala:87:24]
wire out_woready_1_75; // @[RegisterRouter.scala:87:24]
wire out_woready_1_76; // @[RegisterRouter.scala:87:24]
wire out_woready_1_77; // @[RegisterRouter.scala:87:24]
wire out_woready_1_78; // @[RegisterRouter.scala:87:24]
wire out_woready_1_79; // @[RegisterRouter.scala:87:24]
wire out_woready_1_80; // @[RegisterRouter.scala:87:24]
wire out_woready_1_81; // @[RegisterRouter.scala:87:24]
wire out_woready_1_82; // @[RegisterRouter.scala:87:24]
wire out_woready_1_83; // @[RegisterRouter.scala:87:24]
wire out_woready_1_84; // @[RegisterRouter.scala:87:24]
wire out_woready_1_85; // @[RegisterRouter.scala:87:24]
wire out_woready_1_86; // @[RegisterRouter.scala:87:24]
wire out_woready_1_87; // @[RegisterRouter.scala:87:24]
wire out_woready_1_88; // @[RegisterRouter.scala:87:24]
wire out_woready_1_89; // @[RegisterRouter.scala:87:24]
wire out_woready_1_90; // @[RegisterRouter.scala:87:24]
wire out_woready_1_91; // @[RegisterRouter.scala:87:24]
wire out_woready_1_92; // @[RegisterRouter.scala:87:24]
wire out_woready_1_93; // @[RegisterRouter.scala:87:24]
wire out_woready_1_94; // @[RegisterRouter.scala:87:24]
wire out_woready_1_95; // @[RegisterRouter.scala:87:24]
wire out_woready_1_96; // @[RegisterRouter.scala:87:24]
wire out_woready_1_97; // @[RegisterRouter.scala:87:24]
wire out_woready_1_98; // @[RegisterRouter.scala:87:24]
wire out_woready_1_99; // @[RegisterRouter.scala:87:24]
wire out_woready_1_100; // @[RegisterRouter.scala:87:24]
wire out_woready_1_101; // @[RegisterRouter.scala:87:24]
wire out_woready_1_102; // @[RegisterRouter.scala:87:24]
wire out_woready_1_103; // @[RegisterRouter.scala:87:24]
wire out_woready_1_104; // @[RegisterRouter.scala:87:24]
wire out_woready_1_105; // @[RegisterRouter.scala:87:24]
wire out_woready_1_106; // @[RegisterRouter.scala:87:24]
wire out_woready_1_107; // @[RegisterRouter.scala:87:24]
wire out_woready_1_108; // @[RegisterRouter.scala:87:24]
wire out_woready_1_109; // @[RegisterRouter.scala:87:24]
wire out_woready_1_110; // @[RegisterRouter.scala:87:24]
wire out_woready_1_111; // @[RegisterRouter.scala:87:24]
wire out_woready_1_112; // @[RegisterRouter.scala:87:24]
wire out_woready_1_113; // @[RegisterRouter.scala:87:24]
wire out_woready_1_114; // @[RegisterRouter.scala:87:24]
wire out_woready_1_115; // @[RegisterRouter.scala:87:24]
wire out_woready_1_116; // @[RegisterRouter.scala:87:24]
wire out_woready_1_117; // @[RegisterRouter.scala:87:24]
wire out_woready_1_118; // @[RegisterRouter.scala:87:24]
wire out_woready_1_119; // @[RegisterRouter.scala:87:24]
wire out_woready_1_120; // @[RegisterRouter.scala:87:24]
wire out_woready_1_121; // @[RegisterRouter.scala:87:24]
wire out_woready_1_122; // @[RegisterRouter.scala:87:24]
wire out_woready_1_123; // @[RegisterRouter.scala:87:24]
wire out_woready_1_124; // @[RegisterRouter.scala:87:24]
wire out_woready_1_125; // @[RegisterRouter.scala:87:24]
wire out_woready_1_126; // @[RegisterRouter.scala:87:24]
wire out_woready_1_127; // @[RegisterRouter.scala:87:24]
wire out_woready_1_128; // @[RegisterRouter.scala:87:24]
wire out_woready_1_129; // @[RegisterRouter.scala:87:24]
wire out_woready_1_130; // @[RegisterRouter.scala:87:24]
wire out_woready_1_131; // @[RegisterRouter.scala:87:24]
wire out_woready_1_132; // @[RegisterRouter.scala:87:24]
wire out_woready_1_133; // @[RegisterRouter.scala:87:24]
wire out_woready_1_134; // @[RegisterRouter.scala:87:24]
wire out_woready_1_135; // @[RegisterRouter.scala:87:24]
wire out_woready_1_136; // @[RegisterRouter.scala:87:24]
wire out_woready_1_137; // @[RegisterRouter.scala:87:24]
wire out_woready_1_138; // @[RegisterRouter.scala:87:24]
wire out_woready_1_139; // @[RegisterRouter.scala:87:24]
wire out_woready_1_140; // @[RegisterRouter.scala:87:24]
wire out_woready_1_141; // @[RegisterRouter.scala:87:24]
wire out_woready_1_142; // @[RegisterRouter.scala:87:24]
wire out_woready_1_143; // @[RegisterRouter.scala:87:24]
wire out_woready_1_144; // @[RegisterRouter.scala:87:24]
wire out_woready_1_145; // @[RegisterRouter.scala:87:24]
wire out_woready_1_146; // @[RegisterRouter.scala:87:24]
wire out_woready_1_147; // @[RegisterRouter.scala:87:24]
wire out_woready_1_148; // @[RegisterRouter.scala:87:24]
wire out_woready_1_149; // @[RegisterRouter.scala:87:24]
wire out_woready_1_150; // @[RegisterRouter.scala:87:24]
wire out_woready_1_151; // @[RegisterRouter.scala:87:24]
wire out_woready_1_152; // @[RegisterRouter.scala:87:24]
wire out_woready_1_153; // @[RegisterRouter.scala:87:24]
wire out_woready_1_154; // @[RegisterRouter.scala:87:24]
wire out_woready_1_155; // @[RegisterRouter.scala:87:24]
wire out_woready_1_156; // @[RegisterRouter.scala:87:24]
wire out_woready_1_157; // @[RegisterRouter.scala:87:24]
wire out_woready_1_158; // @[RegisterRouter.scala:87:24]
wire out_woready_1_159; // @[RegisterRouter.scala:87:24]
wire out_woready_1_160; // @[RegisterRouter.scala:87:24]
wire out_woready_1_161; // @[RegisterRouter.scala:87:24]
wire out_woready_1_162; // @[RegisterRouter.scala:87:24]
wire out_woready_1_163; // @[RegisterRouter.scala:87:24]
wire out_woready_1_164; // @[RegisterRouter.scala:87:24]
wire out_woready_1_165; // @[RegisterRouter.scala:87:24]
wire out_woready_1_166; // @[RegisterRouter.scala:87:24]
wire out_woready_1_167; // @[RegisterRouter.scala:87:24]
wire out_woready_1_168; // @[RegisterRouter.scala:87:24]
wire out_woready_1_169; // @[RegisterRouter.scala:87:24]
wire out_woready_1_170; // @[RegisterRouter.scala:87:24]
wire out_woready_1_171; // @[RegisterRouter.scala:87:24]
wire out_woready_1_172; // @[RegisterRouter.scala:87:24]
wire out_woready_1_173; // @[RegisterRouter.scala:87:24]
wire out_woready_1_174; // @[RegisterRouter.scala:87:24]
wire out_woready_1_175; // @[RegisterRouter.scala:87:24]
wire out_woready_1_176; // @[RegisterRouter.scala:87:24]
wire out_woready_1_177; // @[RegisterRouter.scala:87:24]
wire out_woready_1_178; // @[RegisterRouter.scala:87:24]
wire out_woready_1_179; // @[RegisterRouter.scala:87:24]
wire out_woready_1_180; // @[RegisterRouter.scala:87:24]
wire out_woready_1_181; // @[RegisterRouter.scala:87:24]
wire out_woready_1_182; // @[RegisterRouter.scala:87:24]
wire out_woready_1_183; // @[RegisterRouter.scala:87:24]
wire out_woready_1_184; // @[RegisterRouter.scala:87:24]
wire out_woready_1_185; // @[RegisterRouter.scala:87:24]
wire out_woready_1_186; // @[RegisterRouter.scala:87:24]
wire out_woready_1_187; // @[RegisterRouter.scala:87:24]
wire out_woready_1_188; // @[RegisterRouter.scala:87:24]
wire out_woready_1_189; // @[RegisterRouter.scala:87:24]
wire out_woready_1_190; // @[RegisterRouter.scala:87:24]
wire out_woready_1_191; // @[RegisterRouter.scala:87:24]
wire out_woready_1_192; // @[RegisterRouter.scala:87:24]
wire out_woready_1_193; // @[RegisterRouter.scala:87:24]
wire out_woready_1_194; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_8 = out_front_1_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_9 = out_front_1_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_10 = out_front_1_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_11 = out_front_1_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_12 = out_front_1_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_13 = out_front_1_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_14 = out_front_1_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_15 = out_front_1_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_16 = {8{_out_frontMask_T_8}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_17 = {8{_out_frontMask_T_9}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_18 = {8{_out_frontMask_T_10}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_19 = {8{_out_frontMask_T_11}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_20 = {8{_out_frontMask_T_12}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_21 = {8{_out_frontMask_T_13}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_22 = {8{_out_frontMask_T_14}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_23 = {8{_out_frontMask_T_15}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_17, _out_frontMask_T_16}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_19, _out_frontMask_T_18}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo_1 = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_21, _out_frontMask_T_20}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_23, _out_frontMask_T_22}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi_1 = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask_1 = {out_frontMask_hi_1, out_frontMask_lo_1}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_16 = {8{_out_backMask_T_8}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_17 = {8{_out_backMask_T_9}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_18 = {8{_out_backMask_T_10}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_19 = {8{_out_backMask_T_11}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_20 = {8{_out_backMask_T_12}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_21 = {8{_out_backMask_T_13}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_22 = {8{_out_backMask_T_14}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_23 = {8{_out_backMask_T_15}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_17, _out_backMask_T_16}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_19, _out_backMask_T_18}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo_1 = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_21, _out_backMask_T_20}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_23, _out_backMask_T_22}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi_1 = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask_1 = {out_backMask_hi_1, out_backMask_lo_1}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_150 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_150 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_158 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_158 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_166 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_166 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_174 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_174 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_182 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_182 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_190 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_190 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_198 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_198 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_206 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_206 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_214 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_214 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_222 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_222 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_230 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_230 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_238 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_238 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_246 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_246 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_254 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_254 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_262 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_262 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_273 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_273 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_281 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_281 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_289 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_289 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_297 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_297 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_305 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_305 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_311 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_311 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_321 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_321 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_329 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_329 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_337 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_337 = out_frontMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_150 = |_out_rimask_T_150; // @[RegisterRouter.scala:87:24]
wire out_wimask_150 = &_out_wimask_T_150; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_150 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_150 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_158 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_158 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_166 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_166 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_174 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_174 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_182 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_182 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_190 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_190 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_198 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_198 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_206 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_206 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_214 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_214 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_222 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_222 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_230 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_230 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_238 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_238 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_246 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_246 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_254 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_254 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_262 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_262 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_273 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_273 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_281 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_281 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_289 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_289 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_297 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_297 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_305 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_305 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_311 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_311 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_321 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_321 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_329 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_329 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_337 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_337 = out_backMask_1[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_150 = |_out_romask_T_150; // @[RegisterRouter.scala:87:24]
wire out_womask_150 = &_out_womask_T_150; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_150 = out_rivalid_1_0 & out_rimask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1699 = out_f_rivalid_150; // @[RegisterRouter.scala:87:24]
wire out_f_roready_150 = out_roready_1_0 & out_romask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1700 = out_f_roready_150; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_150 = out_wivalid_1_0 & out_wimask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1701 = out_f_wivalid_150; // @[RegisterRouter.scala:87:24]
wire out_f_woready_150 = out_woready_1_0 & out_womask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1702 = out_f_woready_150; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1698 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1786 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1858 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1946 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2018 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2106 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2178 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2250 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2338 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2426 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2498 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2586 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2658 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2746 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2834 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2933 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3021 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3093 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3165 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3253 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3307 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3397 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3485 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3557 = out_front_1_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_1703 = ~out_rimask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1704 = ~out_wimask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1705 = ~out_romask_150; // @[RegisterRouter.scala:87:24]
wire _out_T_1706 = ~out_womask_150; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1708 = _out_T_1707; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_115 = _out_T_1708; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_151 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_151 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_159 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_159 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_167 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_167 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_175 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_175 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_183 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_183 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_191 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_191 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_199 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_199 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_207 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_207 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_215 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_215 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_223 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_223 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_231 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_231 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_239 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_239 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_247 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_247 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_255 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_255 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_263 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_263 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_274 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_274 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_282 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_282 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_290 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_290 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_298 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_298 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_306 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_306 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_312 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_312 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_322 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_322 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_330 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_330 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_338 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_338 = out_frontMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_151 = |_out_rimask_T_151; // @[RegisterRouter.scala:87:24]
wire out_wimask_151 = &_out_wimask_T_151; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_151 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_151 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_159 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_159 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_167 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_167 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_175 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_175 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_183 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_183 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_191 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_191 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_199 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_199 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_207 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_207 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_215 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_215 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_223 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_223 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_231 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_231 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_239 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_239 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_247 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_247 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_255 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_255 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_263 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_263 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_274 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_274 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_282 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_282 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_290 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_290 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_298 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_298 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_306 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_306 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_312 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_312 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_322 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_322 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_330 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_330 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_338 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_338 = out_backMask_1[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_151 = |_out_romask_T_151; // @[RegisterRouter.scala:87:24]
wire out_womask_151 = &_out_womask_T_151; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_151 = out_rivalid_1_1 & out_rimask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1710 = out_f_rivalid_151; // @[RegisterRouter.scala:87:24]
wire out_f_roready_151 = out_roready_1_1 & out_romask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1711 = out_f_roready_151; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_151 = out_wivalid_1_1 & out_wimask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1712 = out_f_wivalid_151; // @[RegisterRouter.scala:87:24]
wire out_f_woready_151 = out_woready_1_1 & out_womask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1713 = out_f_woready_151; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1709 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1795 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1869 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1955 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2029 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2115 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2187 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2261 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2349 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2435 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2509 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2595 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2669 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2757 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2843 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2944 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3030 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3102 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3176 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3262 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3316 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3408 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3494 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3568 = out_front_1_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_1714 = ~out_rimask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1715 = ~out_wimask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1716 = ~out_romask_151; // @[RegisterRouter.scala:87:24]
wire _out_T_1717 = ~out_womask_151; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_115 = {abstractDataMem_25, _out_prepend_T_115}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1718 = out_prepend_115; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1719 = _out_T_1718; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_116 = _out_T_1719; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_152 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_152 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_160 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_160 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_168 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_168 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_176 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_176 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_184 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_184 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_192 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_192 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_200 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_200 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_208 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_208 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_216 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_216 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_224 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_224 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_232 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_232 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_240 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_240 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_248 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_248 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_256 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_256 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_264 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_264 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_275 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_275 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_283 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_283 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_291 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_291 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_299 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_299 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_307 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_307 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_313 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_313 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_323 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_323 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_331 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_331 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_339 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_339 = out_frontMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_152 = |_out_rimask_T_152; // @[RegisterRouter.scala:87:24]
wire out_wimask_152 = &_out_wimask_T_152; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_152 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_152 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_160 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_160 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_168 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_168 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_176 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_176 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_184 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_184 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_192 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_192 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_200 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_200 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_208 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_208 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_216 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_216 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_224 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_224 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_232 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_232 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_240 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_240 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_248 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_248 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_256 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_256 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_264 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_264 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_275 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_275 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_283 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_283 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_291 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_291 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_299 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_299 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_307 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_307 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_313 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_313 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_323 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_323 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_331 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_331 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_339 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_339 = out_backMask_1[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_152 = |_out_romask_T_152; // @[RegisterRouter.scala:87:24]
wire out_womask_152 = &_out_womask_T_152; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_152 = out_rivalid_1_2 & out_rimask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1721 = out_f_rivalid_152; // @[RegisterRouter.scala:87:24]
wire out_f_roready_152 = out_roready_1_2 & out_romask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1722 = out_f_roready_152; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_152 = out_wivalid_1_2 & out_wimask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1723 = out_f_wivalid_152; // @[RegisterRouter.scala:87:24]
wire out_f_woready_152 = out_woready_1_2 & out_womask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1724 = out_f_woready_152; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1720 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1804 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1880 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1964 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2040 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2124 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2196 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2272 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2360 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2444 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2520 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2604 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2680 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2768 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2852 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2955 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3039 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3111 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3187 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3271 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3325 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3419 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3503 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3579 = out_front_1_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_1725 = ~out_rimask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1726 = ~out_wimask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1727 = ~out_romask_152; // @[RegisterRouter.scala:87:24]
wire _out_T_1728 = ~out_womask_152; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_116 = {abstractDataMem_26, _out_prepend_T_116}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1729 = out_prepend_116; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1730 = _out_T_1729; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_117 = _out_T_1730; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_153 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_153 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_161 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_161 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_169 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_169 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_177 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_177 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_185 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_185 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_193 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_193 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_201 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_201 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_209 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_209 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_217 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_217 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_225 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_225 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_233 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_233 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_241 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_241 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_249 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_249 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_257 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_257 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_265 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_265 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_276 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_276 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_284 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_284 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_292 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_292 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_300 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_300 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_308 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_308 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_314 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_314 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_324 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_324 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_332 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_332 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_340 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_340 = out_frontMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_153 = |_out_rimask_T_153; // @[RegisterRouter.scala:87:24]
wire out_wimask_153 = &_out_wimask_T_153; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_153 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_153 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_161 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_161 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_169 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_169 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_177 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_177 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_185 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_185 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_193 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_193 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_201 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_201 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_209 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_209 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_217 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_217 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_225 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_225 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_233 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_233 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_241 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_241 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_249 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_249 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_257 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_257 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_265 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_265 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_276 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_276 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_284 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_284 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_292 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_292 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_300 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_300 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_308 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_308 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_314 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_314 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_324 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_324 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_332 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_332 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_340 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_340 = out_backMask_1[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_153 = |_out_romask_T_153; // @[RegisterRouter.scala:87:24]
wire out_womask_153 = &_out_womask_T_153; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_153 = out_rivalid_1_3 & out_rimask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1732 = out_f_rivalid_153; // @[RegisterRouter.scala:87:24]
wire out_f_roready_153 = out_roready_1_3 & out_romask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1733 = out_f_roready_153; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_153 = out_wivalid_1_3 & out_wimask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1734 = out_f_wivalid_153; // @[RegisterRouter.scala:87:24]
wire out_f_woready_153 = out_woready_1_3 & out_womask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1735 = out_f_woready_153; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1731 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1813 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1891 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1973 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2051 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2133 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2205 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2283 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2371 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2453 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2531 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2613 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2691 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2779 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2861 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2966 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3048 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3120 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3198 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3280 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3334 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3430 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3512 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3590 = out_front_1_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire _out_T_1736 = ~out_rimask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1737 = ~out_wimask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1738 = ~out_romask_153; // @[RegisterRouter.scala:87:24]
wire _out_T_1739 = ~out_womask_153; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_117 = {abstractDataMem_27, _out_prepend_T_117}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1740 = out_prepend_117; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1741 = _out_T_1740; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_118 = _out_T_1741; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_154 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_154 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_162 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_162 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_170 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_170 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_178 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_178 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_186 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_186 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_194 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_194 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_202 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_202 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_210 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_210 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_218 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_218 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_226 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_226 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_234 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_234 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_242 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_242 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_250 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_250 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_258 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_258 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_266 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_266 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_277 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_277 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_285 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_285 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_293 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_293 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_301 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_301 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_315 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_315 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_325 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_325 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_333 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_333 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_341 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_341 = out_frontMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_154 = |_out_rimask_T_154; // @[RegisterRouter.scala:87:24]
wire out_wimask_154 = &_out_wimask_T_154; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_154 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_154 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_162 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_162 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_170 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_170 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_178 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_178 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_186 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_186 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_194 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_194 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_202 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_202 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_210 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_210 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_218 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_218 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_226 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_226 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_234 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_234 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_242 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_242 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_250 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_250 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_258 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_258 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_266 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_266 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_277 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_277 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_285 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_285 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_293 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_293 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_301 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_301 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_315 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_315 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_325 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_325 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_333 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_333 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_341 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_341 = out_backMask_1[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_154 = |_out_romask_T_154; // @[RegisterRouter.scala:87:24]
wire out_womask_154 = &_out_womask_T_154; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_154 = out_rivalid_1_4 & out_rimask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1743 = out_f_rivalid_154; // @[RegisterRouter.scala:87:24]
wire out_f_roready_154 = out_roready_1_4 & out_romask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1744 = out_f_roready_154; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_154 = out_wivalid_1_4 & out_wimask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1745 = out_f_wivalid_154; // @[RegisterRouter.scala:87:24]
wire out_f_woready_154 = out_woready_1_4 & out_womask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1746 = out_f_woready_154; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1742 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1822 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1902 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1982 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2062 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2142 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2214 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2294 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2382 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2462 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2542 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2622 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2702 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2790 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2870 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2977 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3057 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3129 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3209 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3343 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3441 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3521 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3601 = out_front_1_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_1747 = ~out_rimask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1748 = ~out_wimask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1749 = ~out_romask_154; // @[RegisterRouter.scala:87:24]
wire _out_T_1750 = ~out_womask_154; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_118 = {abstractDataMem_28, _out_prepend_T_118}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1751 = out_prepend_118; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1752 = _out_T_1751; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_119 = _out_T_1752; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_155 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_155 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_163 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_163 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_171 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_171 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_179 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_179 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_187 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_187 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_195 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_195 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_203 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_203 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_211 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_211 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_219 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_219 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_227 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_227 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_235 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_235 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_243 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_243 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_251 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_251 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_259 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_259 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_267 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_267 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_278 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_278 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_286 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_286 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_294 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_294 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_302 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_302 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_316 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_316 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_326 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_326 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_334 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_334 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_342 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_342 = out_frontMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_155 = |_out_rimask_T_155; // @[RegisterRouter.scala:87:24]
wire out_wimask_155 = &_out_wimask_T_155; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_155 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_155 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_163 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_163 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_171 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_171 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_179 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_179 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_187 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_187 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_195 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_195 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_203 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_203 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_211 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_211 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_219 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_219 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_227 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_227 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_235 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_235 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_243 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_243 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_251 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_251 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_259 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_259 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_267 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_267 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_278 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_278 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_286 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_286 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_294 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_294 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_302 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_302 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_316 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_316 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_326 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_326 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_334 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_334 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_342 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_342 = out_backMask_1[47:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_155 = |_out_romask_T_155; // @[RegisterRouter.scala:87:24]
wire out_womask_155 = &_out_womask_T_155; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_155 = out_rivalid_1_5 & out_rimask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1754 = out_f_rivalid_155; // @[RegisterRouter.scala:87:24]
wire out_f_roready_155 = out_roready_1_5 & out_romask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1755 = out_f_roready_155; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_155 = out_wivalid_1_5 & out_wimask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1756 = out_f_wivalid_155; // @[RegisterRouter.scala:87:24]
wire out_f_woready_155 = out_woready_1_5 & out_womask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1757 = out_f_woready_155; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1753 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1831 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1913 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1991 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2073 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2151 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2223 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2305 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2393 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2471 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2553 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2631 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2713 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2801 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2879 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2988 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3066 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3138 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3220 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3352 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3452 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3530 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3612 = out_front_1_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
wire _out_T_1758 = ~out_rimask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1759 = ~out_wimask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1760 = ~out_romask_155; // @[RegisterRouter.scala:87:24]
wire _out_T_1761 = ~out_womask_155; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_119 = {abstractDataMem_29, _out_prepend_T_119}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1762 = out_prepend_119; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1763 = _out_T_1762; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_120 = _out_T_1763; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_156 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_156 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_164 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_164 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_172 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_172 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_180 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_180 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_188 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_188 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_196 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_196 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_204 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_204 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_212 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_212 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_220 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_220 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_228 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_228 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_236 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_236 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_244 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_244 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_252 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_252 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_260 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_260 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_268 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_268 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_279 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_279 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_287 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_287 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_295 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_295 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_303 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_303 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_317 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_317 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_327 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_327 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_335 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_335 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_343 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_343 = out_frontMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_156 = |_out_rimask_T_156; // @[RegisterRouter.scala:87:24]
wire out_wimask_156 = &_out_wimask_T_156; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_156 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_156 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_164 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_164 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_172 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_172 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_180 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_180 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_188 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_188 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_196 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_196 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_204 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_204 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_212 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_212 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_220 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_220 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_228 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_228 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_236 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_236 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_244 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_244 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_252 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_252 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_260 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_260 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_268 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_268 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_279 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_279 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_287 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_287 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_295 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_295 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_303 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_303 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_317 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_317 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_327 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_327 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_335 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_335 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_343 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_343 = out_backMask_1[55:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_156 = |_out_romask_T_156; // @[RegisterRouter.scala:87:24]
wire out_womask_156 = &_out_womask_T_156; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_156 = out_rivalid_1_6 & out_rimask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_1765 = out_f_rivalid_156; // @[RegisterRouter.scala:87:24]
wire out_f_roready_156 = out_roready_1_6 & out_romask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_1766 = out_f_roready_156; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_156 = out_wivalid_1_6 & out_wimask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_1767 = out_f_wivalid_156; // @[RegisterRouter.scala:87:24]
wire out_f_woready_156 = out_woready_1_6 & out_womask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_1768 = out_f_woready_156; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1764 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1840 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1924 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2000 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2084 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2160 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2232 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2316 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2404 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2480 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2564 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2640 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2724 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2812 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2888 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2999 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3075 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3147 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3231 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3361 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3463 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3539 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3623 = out_front_1_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
wire _out_T_1769 = ~out_rimask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_1770 = ~out_wimask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_1771 = ~out_romask_156; // @[RegisterRouter.scala:87:24]
wire _out_T_1772 = ~out_womask_156; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_120 = {abstractDataMem_30, _out_prepend_T_120}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_1773 = out_prepend_120; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_1774 = _out_T_1773; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_121 = _out_T_1774; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_157 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_157 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_165 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_165 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_173 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_173 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_181 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_181 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_189 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_189 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_197 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_197 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_205 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_205 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_213 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_213 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_221 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_221 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_229 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_229 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_237 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_237 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_245 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_245 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_253 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_253 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_261 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_261 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_269 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_269 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_280 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_280 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_288 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_288 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_296 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_296 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_304 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_304 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_318 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_318 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_328 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_328 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_336 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_336 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_344 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_344 = out_frontMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire out_rimask_157 = |_out_rimask_T_157; // @[RegisterRouter.scala:87:24]
wire out_wimask_157 = &_out_wimask_T_157; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_157 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_157 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_165 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_165 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_173 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_173 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_181 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_181 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_189 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_189 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_197 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_197 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_205 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_205 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_213 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_213 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_221 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_221 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_229 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_229 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_237 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_237 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_245 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_245 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_253 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_253 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_261 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_261 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_269 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_269 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_280 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_280 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_288 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_288 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_296 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_296 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_304 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_304 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_318 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_318 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_328 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_328 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_336 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_336 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_344 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_344 = out_backMask_1[63:56]; // @[RegisterRouter.scala:87:24]
wire out_romask_157 = |_out_romask_T_157; // @[RegisterRouter.scala:87:24]
wire out_womask_157 = &_out_womask_T_157; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_157 = out_rivalid_1_7 & out_rimask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_1776 = out_f_rivalid_157; // @[RegisterRouter.scala:87:24]
wire out_f_roready_157 = out_roready_1_7 & out_romask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_1777 = out_f_roready_157; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_157 = out_wivalid_1_7 & out_wimask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_1778 = out_f_wivalid_157; // @[RegisterRouter.scala:87:24]
wire out_f_woready_157 = out_woready_1_7 & out_womask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_1779 = out_f_woready_157; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1775 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1849 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1935 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2009 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2095 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2169 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2241 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2327 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2415 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2489 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2575 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2649 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2735 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2823 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2897 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3010 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3084 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3156 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3242 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3370 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3474 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3548 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3634 = out_front_1_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
wire _out_T_1780 = ~out_rimask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_1781 = ~out_wimask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_1782 = ~out_romask_157; // @[RegisterRouter.scala:87:24]
wire _out_T_1783 = ~out_womask_157; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_121 = {abstractDataMem_31, _out_prepend_T_121}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_1784 = out_prepend_121; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_1785 = _out_T_1784; // @[RegisterRouter.scala:87:24]
wire out_rimask_158 = |_out_rimask_T_158; // @[RegisterRouter.scala:87:24]
wire out_wimask_158 = &_out_wimask_T_158; // @[RegisterRouter.scala:87:24]
wire out_romask_158 = |_out_romask_T_158; // @[RegisterRouter.scala:87:24]
wire out_womask_158 = &_out_womask_T_158; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_158 = out_rivalid_1_8 & out_rimask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_1787 = out_f_rivalid_158; // @[RegisterRouter.scala:87:24]
wire out_f_roready_158 = out_roready_1_8 & out_romask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_1788 = out_f_roready_158; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_158 = out_wivalid_1_8 & out_wimask_158; // @[RegisterRouter.scala:87:24]
wire out_f_woready_158 = out_woready_1_8 & out_womask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_1789 = ~out_rimask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_1790 = ~out_wimask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_1791 = ~out_romask_158; // @[RegisterRouter.scala:87:24]
wire _out_T_1792 = ~out_womask_158; // @[RegisterRouter.scala:87:24]
wire out_rimask_159 = |_out_rimask_T_159; // @[RegisterRouter.scala:87:24]
wire out_wimask_159 = &_out_wimask_T_159; // @[RegisterRouter.scala:87:24]
wire out_romask_159 = |_out_romask_T_159; // @[RegisterRouter.scala:87:24]
wire out_womask_159 = &_out_womask_T_159; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_159 = out_rivalid_1_9 & out_rimask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_1796 = out_f_rivalid_159; // @[RegisterRouter.scala:87:24]
wire out_f_roready_159 = out_roready_1_9 & out_romask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_1797 = out_f_roready_159; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_159 = out_wivalid_1_9 & out_wimask_159; // @[RegisterRouter.scala:87:24]
wire out_f_woready_159 = out_woready_1_9 & out_womask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_1798 = ~out_rimask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_1799 = ~out_wimask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_1800 = ~out_romask_159; // @[RegisterRouter.scala:87:24]
wire _out_T_1801 = ~out_womask_159; // @[RegisterRouter.scala:87:24]
wire out_rimask_160 = |_out_rimask_T_160; // @[RegisterRouter.scala:87:24]
wire out_wimask_160 = &_out_wimask_T_160; // @[RegisterRouter.scala:87:24]
wire out_romask_160 = |_out_romask_T_160; // @[RegisterRouter.scala:87:24]
wire out_womask_160 = &_out_womask_T_160; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_160 = out_rivalid_1_10 & out_rimask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_1805 = out_f_rivalid_160; // @[RegisterRouter.scala:87:24]
wire out_f_roready_160 = out_roready_1_10 & out_romask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_1806 = out_f_roready_160; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_160 = out_wivalid_1_10 & out_wimask_160; // @[RegisterRouter.scala:87:24]
wire out_f_woready_160 = out_woready_1_10 & out_womask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_1807 = ~out_rimask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_1808 = ~out_wimask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_1809 = ~out_romask_160; // @[RegisterRouter.scala:87:24]
wire _out_T_1810 = ~out_womask_160; // @[RegisterRouter.scala:87:24]
wire out_rimask_161 = |_out_rimask_T_161; // @[RegisterRouter.scala:87:24]
wire out_wimask_161 = &_out_wimask_T_161; // @[RegisterRouter.scala:87:24]
wire out_romask_161 = |_out_romask_T_161; // @[RegisterRouter.scala:87:24]
wire out_womask_161 = &_out_womask_T_161; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_161 = out_rivalid_1_11 & out_rimask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_1814 = out_f_rivalid_161; // @[RegisterRouter.scala:87:24]
wire out_f_roready_161 = out_roready_1_11 & out_romask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_1815 = out_f_roready_161; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_161 = out_wivalid_1_11 & out_wimask_161; // @[RegisterRouter.scala:87:24]
wire out_f_woready_161 = out_woready_1_11 & out_womask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_1816 = ~out_rimask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_1817 = ~out_wimask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_1818 = ~out_romask_161; // @[RegisterRouter.scala:87:24]
wire _out_T_1819 = ~out_womask_161; // @[RegisterRouter.scala:87:24]
wire out_rimask_162 = |_out_rimask_T_162; // @[RegisterRouter.scala:87:24]
wire out_wimask_162 = &_out_wimask_T_162; // @[RegisterRouter.scala:87:24]
wire out_romask_162 = |_out_romask_T_162; // @[RegisterRouter.scala:87:24]
wire out_womask_162 = &_out_womask_T_162; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_162 = out_rivalid_1_12 & out_rimask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_1823 = out_f_rivalid_162; // @[RegisterRouter.scala:87:24]
wire out_f_roready_162 = out_roready_1_12 & out_romask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_1824 = out_f_roready_162; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_162 = out_wivalid_1_12 & out_wimask_162; // @[RegisterRouter.scala:87:24]
wire out_f_woready_162 = out_woready_1_12 & out_womask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_1825 = ~out_rimask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_1826 = ~out_wimask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_1827 = ~out_romask_162; // @[RegisterRouter.scala:87:24]
wire _out_T_1828 = ~out_womask_162; // @[RegisterRouter.scala:87:24]
wire out_rimask_163 = |_out_rimask_T_163; // @[RegisterRouter.scala:87:24]
wire out_wimask_163 = &_out_wimask_T_163; // @[RegisterRouter.scala:87:24]
wire out_romask_163 = |_out_romask_T_163; // @[RegisterRouter.scala:87:24]
wire out_womask_163 = &_out_womask_T_163; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_163 = out_rivalid_1_13 & out_rimask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_1832 = out_f_rivalid_163; // @[RegisterRouter.scala:87:24]
wire out_f_roready_163 = out_roready_1_13 & out_romask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_1833 = out_f_roready_163; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_163 = out_wivalid_1_13 & out_wimask_163; // @[RegisterRouter.scala:87:24]
wire out_f_woready_163 = out_woready_1_13 & out_womask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_1834 = ~out_rimask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_1835 = ~out_wimask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_1836 = ~out_romask_163; // @[RegisterRouter.scala:87:24]
wire _out_T_1837 = ~out_womask_163; // @[RegisterRouter.scala:87:24]
wire out_rimask_164 = |_out_rimask_T_164; // @[RegisterRouter.scala:87:24]
wire out_wimask_164 = &_out_wimask_T_164; // @[RegisterRouter.scala:87:24]
wire out_romask_164 = |_out_romask_T_164; // @[RegisterRouter.scala:87:24]
wire out_womask_164 = &_out_womask_T_164; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_164 = out_rivalid_1_14 & out_rimask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_1841 = out_f_rivalid_164; // @[RegisterRouter.scala:87:24]
wire out_f_roready_164 = out_roready_1_14 & out_romask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_1842 = out_f_roready_164; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_164 = out_wivalid_1_14 & out_wimask_164; // @[RegisterRouter.scala:87:24]
wire out_f_woready_164 = out_woready_1_14 & out_womask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_1843 = ~out_rimask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_1844 = ~out_wimask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_1845 = ~out_romask_164; // @[RegisterRouter.scala:87:24]
wire _out_T_1846 = ~out_womask_164; // @[RegisterRouter.scala:87:24]
wire out_rimask_165 = |_out_rimask_T_165; // @[RegisterRouter.scala:87:24]
wire out_wimask_165 = &_out_wimask_T_165; // @[RegisterRouter.scala:87:24]
wire out_romask_165 = |_out_romask_T_165; // @[RegisterRouter.scala:87:24]
wire out_womask_165 = &_out_womask_T_165; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_165 = out_rivalid_1_15 & out_rimask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_1850 = out_f_rivalid_165; // @[RegisterRouter.scala:87:24]
wire out_f_roready_165 = out_roready_1_15 & out_romask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_1851 = out_f_roready_165; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_165 = out_wivalid_1_15 & out_wimask_165; // @[RegisterRouter.scala:87:24]
wire out_f_woready_165 = out_woready_1_15 & out_womask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_1852 = ~out_rimask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_1853 = ~out_wimask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_1854 = ~out_romask_165; // @[RegisterRouter.scala:87:24]
wire _out_T_1855 = ~out_womask_165; // @[RegisterRouter.scala:87:24]
wire out_rimask_166 = |_out_rimask_T_166; // @[RegisterRouter.scala:87:24]
wire out_wimask_166 = &_out_wimask_T_166; // @[RegisterRouter.scala:87:24]
wire out_romask_166 = |_out_romask_T_166; // @[RegisterRouter.scala:87:24]
wire out_womask_166 = &_out_womask_T_166; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_166 = out_rivalid_1_16 & out_rimask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_1859 = out_f_rivalid_166; // @[RegisterRouter.scala:87:24]
wire out_f_roready_166 = out_roready_1_16 & out_romask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_1860 = out_f_roready_166; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_166 = out_wivalid_1_16 & out_wimask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_1861 = out_f_wivalid_166; // @[RegisterRouter.scala:87:24]
wire out_f_woready_166 = out_woready_1_16 & out_womask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_1862 = out_f_woready_166; // @[RegisterRouter.scala:87:24]
wire _out_T_1863 = ~out_rimask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_1864 = ~out_wimask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_1865 = ~out_romask_166; // @[RegisterRouter.scala:87:24]
wire _out_T_1866 = ~out_womask_166; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_1868 = _out_T_1867; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_129 = _out_T_1868; // @[RegisterRouter.scala:87:24]
wire out_rimask_167 = |_out_rimask_T_167; // @[RegisterRouter.scala:87:24]
wire out_wimask_167 = &_out_wimask_T_167; // @[RegisterRouter.scala:87:24]
wire out_romask_167 = |_out_romask_T_167; // @[RegisterRouter.scala:87:24]
wire out_womask_167 = &_out_womask_T_167; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_167 = out_rivalid_1_17 & out_rimask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_1870 = out_f_rivalid_167; // @[RegisterRouter.scala:87:24]
wire out_f_roready_167 = out_roready_1_17 & out_romask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_1871 = out_f_roready_167; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_167 = out_wivalid_1_17 & out_wimask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_1872 = out_f_wivalid_167; // @[RegisterRouter.scala:87:24]
wire out_f_woready_167 = out_woready_1_17 & out_womask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_1873 = out_f_woready_167; // @[RegisterRouter.scala:87:24]
wire _out_T_1874 = ~out_rimask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_1875 = ~out_wimask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_1876 = ~out_romask_167; // @[RegisterRouter.scala:87:24]
wire _out_T_1877 = ~out_womask_167; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_129 = {programBufferMem_49, _out_prepend_T_129}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1878 = out_prepend_129; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_1879 = _out_T_1878; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_130 = _out_T_1879; // @[RegisterRouter.scala:87:24]
wire out_rimask_168 = |_out_rimask_T_168; // @[RegisterRouter.scala:87:24]
wire out_wimask_168 = &_out_wimask_T_168; // @[RegisterRouter.scala:87:24]
wire out_romask_168 = |_out_romask_T_168; // @[RegisterRouter.scala:87:24]
wire out_womask_168 = &_out_womask_T_168; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_168 = out_rivalid_1_18 & out_rimask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_1881 = out_f_rivalid_168; // @[RegisterRouter.scala:87:24]
wire out_f_roready_168 = out_roready_1_18 & out_romask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_1882 = out_f_roready_168; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_168 = out_wivalid_1_18 & out_wimask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_1883 = out_f_wivalid_168; // @[RegisterRouter.scala:87:24]
wire out_f_woready_168 = out_woready_1_18 & out_womask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_1884 = out_f_woready_168; // @[RegisterRouter.scala:87:24]
wire _out_T_1885 = ~out_rimask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_1886 = ~out_wimask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_1887 = ~out_romask_168; // @[RegisterRouter.scala:87:24]
wire _out_T_1888 = ~out_womask_168; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_130 = {programBufferMem_50, _out_prepend_T_130}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1889 = out_prepend_130; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_1890 = _out_T_1889; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_131 = _out_T_1890; // @[RegisterRouter.scala:87:24]
wire out_rimask_169 = |_out_rimask_T_169; // @[RegisterRouter.scala:87:24]
wire out_wimask_169 = &_out_wimask_T_169; // @[RegisterRouter.scala:87:24]
wire out_romask_169 = |_out_romask_T_169; // @[RegisterRouter.scala:87:24]
wire out_womask_169 = &_out_womask_T_169; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_169 = out_rivalid_1_19 & out_rimask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_1892 = out_f_rivalid_169; // @[RegisterRouter.scala:87:24]
wire out_f_roready_169 = out_roready_1_19 & out_romask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_1893 = out_f_roready_169; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_169 = out_wivalid_1_19 & out_wimask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_1894 = out_f_wivalid_169; // @[RegisterRouter.scala:87:24]
wire out_f_woready_169 = out_woready_1_19 & out_womask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_1895 = out_f_woready_169; // @[RegisterRouter.scala:87:24]
wire _out_T_1896 = ~out_rimask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_1897 = ~out_wimask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_1898 = ~out_romask_169; // @[RegisterRouter.scala:87:24]
wire _out_T_1899 = ~out_womask_169; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_131 = {programBufferMem_51, _out_prepend_T_131}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1900 = out_prepend_131; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_1901 = _out_T_1900; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_132 = _out_T_1901; // @[RegisterRouter.scala:87:24]
wire out_rimask_170 = |_out_rimask_T_170; // @[RegisterRouter.scala:87:24]
wire out_wimask_170 = &_out_wimask_T_170; // @[RegisterRouter.scala:87:24]
wire out_romask_170 = |_out_romask_T_170; // @[RegisterRouter.scala:87:24]
wire out_womask_170 = &_out_womask_T_170; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_170 = out_rivalid_1_20 & out_rimask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_1903 = out_f_rivalid_170; // @[RegisterRouter.scala:87:24]
wire out_f_roready_170 = out_roready_1_20 & out_romask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_1904 = out_f_roready_170; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_170 = out_wivalid_1_20 & out_wimask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_1905 = out_f_wivalid_170; // @[RegisterRouter.scala:87:24]
wire out_f_woready_170 = out_woready_1_20 & out_womask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_1906 = out_f_woready_170; // @[RegisterRouter.scala:87:24]
wire _out_T_1907 = ~out_rimask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_1908 = ~out_wimask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_1909 = ~out_romask_170; // @[RegisterRouter.scala:87:24]
wire _out_T_1910 = ~out_womask_170; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_132 = {programBufferMem_52, _out_prepend_T_132}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1911 = out_prepend_132; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_1912 = _out_T_1911; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_133 = _out_T_1912; // @[RegisterRouter.scala:87:24]
wire out_rimask_171 = |_out_rimask_T_171; // @[RegisterRouter.scala:87:24]
wire out_wimask_171 = &_out_wimask_T_171; // @[RegisterRouter.scala:87:24]
wire out_romask_171 = |_out_romask_T_171; // @[RegisterRouter.scala:87:24]
wire out_womask_171 = &_out_womask_T_171; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_171 = out_rivalid_1_21 & out_rimask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_1914 = out_f_rivalid_171; // @[RegisterRouter.scala:87:24]
wire out_f_roready_171 = out_roready_1_21 & out_romask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_1915 = out_f_roready_171; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_171 = out_wivalid_1_21 & out_wimask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_1916 = out_f_wivalid_171; // @[RegisterRouter.scala:87:24]
wire out_f_woready_171 = out_woready_1_21 & out_womask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_1917 = out_f_woready_171; // @[RegisterRouter.scala:87:24]
wire _out_T_1918 = ~out_rimask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_1919 = ~out_wimask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_1920 = ~out_romask_171; // @[RegisterRouter.scala:87:24]
wire _out_T_1921 = ~out_womask_171; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_133 = {programBufferMem_53, _out_prepend_T_133}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1922 = out_prepend_133; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_1923 = _out_T_1922; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_134 = _out_T_1923; // @[RegisterRouter.scala:87:24]
wire out_rimask_172 = |_out_rimask_T_172; // @[RegisterRouter.scala:87:24]
wire out_wimask_172 = &_out_wimask_T_172; // @[RegisterRouter.scala:87:24]
wire out_romask_172 = |_out_romask_T_172; // @[RegisterRouter.scala:87:24]
wire out_womask_172 = &_out_womask_T_172; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_172 = out_rivalid_1_22 & out_rimask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_1925 = out_f_rivalid_172; // @[RegisterRouter.scala:87:24]
wire out_f_roready_172 = out_roready_1_22 & out_romask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_1926 = out_f_roready_172; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_172 = out_wivalid_1_22 & out_wimask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_1927 = out_f_wivalid_172; // @[RegisterRouter.scala:87:24]
wire out_f_woready_172 = out_woready_1_22 & out_womask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_1928 = out_f_woready_172; // @[RegisterRouter.scala:87:24]
wire _out_T_1929 = ~out_rimask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_1930 = ~out_wimask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_1931 = ~out_romask_172; // @[RegisterRouter.scala:87:24]
wire _out_T_1932 = ~out_womask_172; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_134 = {programBufferMem_54, _out_prepend_T_134}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_1933 = out_prepend_134; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_1934 = _out_T_1933; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_135 = _out_T_1934; // @[RegisterRouter.scala:87:24]
wire out_rimask_173 = |_out_rimask_T_173; // @[RegisterRouter.scala:87:24]
wire out_wimask_173 = &_out_wimask_T_173; // @[RegisterRouter.scala:87:24]
wire out_romask_173 = |_out_romask_T_173; // @[RegisterRouter.scala:87:24]
wire out_womask_173 = &_out_womask_T_173; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_173 = out_rivalid_1_23 & out_rimask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_1936 = out_f_rivalid_173; // @[RegisterRouter.scala:87:24]
wire out_f_roready_173 = out_roready_1_23 & out_romask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_1937 = out_f_roready_173; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_173 = out_wivalid_1_23 & out_wimask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_1938 = out_f_wivalid_173; // @[RegisterRouter.scala:87:24]
wire out_f_woready_173 = out_woready_1_23 & out_womask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_1939 = out_f_woready_173; // @[RegisterRouter.scala:87:24]
wire _out_T_1940 = ~out_rimask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_1941 = ~out_wimask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_1942 = ~out_romask_173; // @[RegisterRouter.scala:87:24]
wire _out_T_1943 = ~out_womask_173; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_135 = {programBufferMem_55, _out_prepend_T_135}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_1944 = out_prepend_135; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_1945 = _out_T_1944; // @[RegisterRouter.scala:87:24]
wire out_rimask_174 = |_out_rimask_T_174; // @[RegisterRouter.scala:87:24]
wire out_wimask_174 = &_out_wimask_T_174; // @[RegisterRouter.scala:87:24]
wire out_romask_174 = |_out_romask_T_174; // @[RegisterRouter.scala:87:24]
wire out_womask_174 = &_out_womask_T_174; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_174 = out_rivalid_1_24 & out_rimask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_1947 = out_f_rivalid_174; // @[RegisterRouter.scala:87:24]
wire out_f_roready_174 = out_roready_1_24 & out_romask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_1948 = out_f_roready_174; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_174 = out_wivalid_1_24 & out_wimask_174; // @[RegisterRouter.scala:87:24]
wire out_f_woready_174 = out_woready_1_24 & out_womask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_1949 = ~out_rimask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_1950 = ~out_wimask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_1951 = ~out_romask_174; // @[RegisterRouter.scala:87:24]
wire _out_T_1952 = ~out_womask_174; // @[RegisterRouter.scala:87:24]
wire out_rimask_175 = |_out_rimask_T_175; // @[RegisterRouter.scala:87:24]
wire out_wimask_175 = &_out_wimask_T_175; // @[RegisterRouter.scala:87:24]
wire out_romask_175 = |_out_romask_T_175; // @[RegisterRouter.scala:87:24]
wire out_womask_175 = &_out_womask_T_175; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_175 = out_rivalid_1_25 & out_rimask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_1956 = out_f_rivalid_175; // @[RegisterRouter.scala:87:24]
wire out_f_roready_175 = out_roready_1_25 & out_romask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_1957 = out_f_roready_175; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_175 = out_wivalid_1_25 & out_wimask_175; // @[RegisterRouter.scala:87:24]
wire out_f_woready_175 = out_woready_1_25 & out_womask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_1958 = ~out_rimask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_1959 = ~out_wimask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_1960 = ~out_romask_175; // @[RegisterRouter.scala:87:24]
wire _out_T_1961 = ~out_womask_175; // @[RegisterRouter.scala:87:24]
wire out_rimask_176 = |_out_rimask_T_176; // @[RegisterRouter.scala:87:24]
wire out_wimask_176 = &_out_wimask_T_176; // @[RegisterRouter.scala:87:24]
wire out_romask_176 = |_out_romask_T_176; // @[RegisterRouter.scala:87:24]
wire out_womask_176 = &_out_womask_T_176; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_176 = out_rivalid_1_26 & out_rimask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_1965 = out_f_rivalid_176; // @[RegisterRouter.scala:87:24]
wire out_f_roready_176 = out_roready_1_26 & out_romask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_1966 = out_f_roready_176; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_176 = out_wivalid_1_26 & out_wimask_176; // @[RegisterRouter.scala:87:24]
wire out_f_woready_176 = out_woready_1_26 & out_womask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_1967 = ~out_rimask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_1968 = ~out_wimask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_1969 = ~out_romask_176; // @[RegisterRouter.scala:87:24]
wire _out_T_1970 = ~out_womask_176; // @[RegisterRouter.scala:87:24]
wire out_rimask_177 = |_out_rimask_T_177; // @[RegisterRouter.scala:87:24]
wire out_wimask_177 = &_out_wimask_T_177; // @[RegisterRouter.scala:87:24]
wire out_romask_177 = |_out_romask_T_177; // @[RegisterRouter.scala:87:24]
wire out_womask_177 = &_out_womask_T_177; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_177 = out_rivalid_1_27 & out_rimask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_1974 = out_f_rivalid_177; // @[RegisterRouter.scala:87:24]
wire out_f_roready_177 = out_roready_1_27 & out_romask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_1975 = out_f_roready_177; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_177 = out_wivalid_1_27 & out_wimask_177; // @[RegisterRouter.scala:87:24]
wire out_f_woready_177 = out_woready_1_27 & out_womask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_1976 = ~out_rimask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_1977 = ~out_wimask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_1978 = ~out_romask_177; // @[RegisterRouter.scala:87:24]
wire _out_T_1979 = ~out_womask_177; // @[RegisterRouter.scala:87:24]
wire out_rimask_178 = |_out_rimask_T_178; // @[RegisterRouter.scala:87:24]
wire out_wimask_178 = &_out_wimask_T_178; // @[RegisterRouter.scala:87:24]
wire out_romask_178 = |_out_romask_T_178; // @[RegisterRouter.scala:87:24]
wire out_womask_178 = &_out_womask_T_178; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_178 = out_rivalid_1_28 & out_rimask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_1983 = out_f_rivalid_178; // @[RegisterRouter.scala:87:24]
wire out_f_roready_178 = out_roready_1_28 & out_romask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_1984 = out_f_roready_178; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_178 = out_wivalid_1_28 & out_wimask_178; // @[RegisterRouter.scala:87:24]
wire out_f_woready_178 = out_woready_1_28 & out_womask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_1985 = ~out_rimask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_1986 = ~out_wimask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_1987 = ~out_romask_178; // @[RegisterRouter.scala:87:24]
wire _out_T_1988 = ~out_womask_178; // @[RegisterRouter.scala:87:24]
wire out_rimask_179 = |_out_rimask_T_179; // @[RegisterRouter.scala:87:24]
wire out_wimask_179 = &_out_wimask_T_179; // @[RegisterRouter.scala:87:24]
wire out_romask_179 = |_out_romask_T_179; // @[RegisterRouter.scala:87:24]
wire out_womask_179 = &_out_womask_T_179; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_179 = out_rivalid_1_29 & out_rimask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_1992 = out_f_rivalid_179; // @[RegisterRouter.scala:87:24]
wire out_f_roready_179 = out_roready_1_29 & out_romask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_1993 = out_f_roready_179; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_179 = out_wivalid_1_29 & out_wimask_179; // @[RegisterRouter.scala:87:24]
wire out_f_woready_179 = out_woready_1_29 & out_womask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_1994 = ~out_rimask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_1995 = ~out_wimask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_1996 = ~out_romask_179; // @[RegisterRouter.scala:87:24]
wire _out_T_1997 = ~out_womask_179; // @[RegisterRouter.scala:87:24]
wire out_rimask_180 = |_out_rimask_T_180; // @[RegisterRouter.scala:87:24]
wire out_wimask_180 = &_out_wimask_T_180; // @[RegisterRouter.scala:87:24]
wire out_romask_180 = |_out_romask_T_180; // @[RegisterRouter.scala:87:24]
wire out_womask_180 = &_out_womask_T_180; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_180 = out_rivalid_1_30 & out_rimask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2001 = out_f_rivalid_180; // @[RegisterRouter.scala:87:24]
wire out_f_roready_180 = out_roready_1_30 & out_romask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2002 = out_f_roready_180; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_180 = out_wivalid_1_30 & out_wimask_180; // @[RegisterRouter.scala:87:24]
wire out_f_woready_180 = out_woready_1_30 & out_womask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2003 = ~out_rimask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2004 = ~out_wimask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2005 = ~out_romask_180; // @[RegisterRouter.scala:87:24]
wire _out_T_2006 = ~out_womask_180; // @[RegisterRouter.scala:87:24]
wire out_rimask_181 = |_out_rimask_T_181; // @[RegisterRouter.scala:87:24]
wire out_wimask_181 = &_out_wimask_T_181; // @[RegisterRouter.scala:87:24]
wire out_romask_181 = |_out_romask_T_181; // @[RegisterRouter.scala:87:24]
wire out_womask_181 = &_out_womask_T_181; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_181 = out_rivalid_1_31 & out_rimask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2010 = out_f_rivalid_181; // @[RegisterRouter.scala:87:24]
wire out_f_roready_181 = out_roready_1_31 & out_romask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2011 = out_f_roready_181; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_181 = out_wivalid_1_31 & out_wimask_181; // @[RegisterRouter.scala:87:24]
wire out_f_woready_181 = out_woready_1_31 & out_womask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2012 = ~out_rimask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2013 = ~out_wimask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2014 = ~out_romask_181; // @[RegisterRouter.scala:87:24]
wire _out_T_2015 = ~out_womask_181; // @[RegisterRouter.scala:87:24]
wire out_rimask_182 = |_out_rimask_T_182; // @[RegisterRouter.scala:87:24]
wire out_wimask_182 = &_out_wimask_T_182; // @[RegisterRouter.scala:87:24]
wire out_romask_182 = |_out_romask_T_182; // @[RegisterRouter.scala:87:24]
wire out_womask_182 = &_out_womask_T_182; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_182 = out_rivalid_1_32 & out_rimask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2019 = out_f_rivalid_182; // @[RegisterRouter.scala:87:24]
wire out_f_roready_182 = out_roready_1_32 & out_romask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2020 = out_f_roready_182; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_182 = out_wivalid_1_32 & out_wimask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2021 = out_f_wivalid_182; // @[RegisterRouter.scala:87:24]
wire out_f_woready_182 = out_woready_1_32 & out_womask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2022 = out_f_woready_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2023 = ~out_rimask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2024 = ~out_wimask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2025 = ~out_romask_182; // @[RegisterRouter.scala:87:24]
wire _out_T_2026 = ~out_womask_182; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2028 = _out_T_2027; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_143 = _out_T_2028; // @[RegisterRouter.scala:87:24]
wire out_rimask_183 = |_out_rimask_T_183; // @[RegisterRouter.scala:87:24]
wire out_wimask_183 = &_out_wimask_T_183; // @[RegisterRouter.scala:87:24]
wire out_romask_183 = |_out_romask_T_183; // @[RegisterRouter.scala:87:24]
wire out_womask_183 = &_out_womask_T_183; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_183 = out_rivalid_1_33 & out_rimask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2030 = out_f_rivalid_183; // @[RegisterRouter.scala:87:24]
wire out_f_roready_183 = out_roready_1_33 & out_romask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2031 = out_f_roready_183; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_183 = out_wivalid_1_33 & out_wimask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2032 = out_f_wivalid_183; // @[RegisterRouter.scala:87:24]
wire out_f_woready_183 = out_woready_1_33 & out_womask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2033 = out_f_woready_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2034 = ~out_rimask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2035 = ~out_wimask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2036 = ~out_romask_183; // @[RegisterRouter.scala:87:24]
wire _out_T_2037 = ~out_womask_183; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_143 = {programBufferMem_17, _out_prepend_T_143}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2038 = out_prepend_143; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2039 = _out_T_2038; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_144 = _out_T_2039; // @[RegisterRouter.scala:87:24]
wire out_rimask_184 = |_out_rimask_T_184; // @[RegisterRouter.scala:87:24]
wire out_wimask_184 = &_out_wimask_T_184; // @[RegisterRouter.scala:87:24]
wire out_romask_184 = |_out_romask_T_184; // @[RegisterRouter.scala:87:24]
wire out_womask_184 = &_out_womask_T_184; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_184 = out_rivalid_1_34 & out_rimask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2041 = out_f_rivalid_184; // @[RegisterRouter.scala:87:24]
wire out_f_roready_184 = out_roready_1_34 & out_romask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2042 = out_f_roready_184; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_184 = out_wivalid_1_34 & out_wimask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2043 = out_f_wivalid_184; // @[RegisterRouter.scala:87:24]
wire out_f_woready_184 = out_woready_1_34 & out_womask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2044 = out_f_woready_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2045 = ~out_rimask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2046 = ~out_wimask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2047 = ~out_romask_184; // @[RegisterRouter.scala:87:24]
wire _out_T_2048 = ~out_womask_184; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_144 = {programBufferMem_18, _out_prepend_T_144}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2049 = out_prepend_144; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2050 = _out_T_2049; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_145 = _out_T_2050; // @[RegisterRouter.scala:87:24]
wire out_rimask_185 = |_out_rimask_T_185; // @[RegisterRouter.scala:87:24]
wire out_wimask_185 = &_out_wimask_T_185; // @[RegisterRouter.scala:87:24]
wire out_romask_185 = |_out_romask_T_185; // @[RegisterRouter.scala:87:24]
wire out_womask_185 = &_out_womask_T_185; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_185 = out_rivalid_1_35 & out_rimask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2052 = out_f_rivalid_185; // @[RegisterRouter.scala:87:24]
wire out_f_roready_185 = out_roready_1_35 & out_romask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2053 = out_f_roready_185; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_185 = out_wivalid_1_35 & out_wimask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2054 = out_f_wivalid_185; // @[RegisterRouter.scala:87:24]
wire out_f_woready_185 = out_woready_1_35 & out_womask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2055 = out_f_woready_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2056 = ~out_rimask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2057 = ~out_wimask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2058 = ~out_romask_185; // @[RegisterRouter.scala:87:24]
wire _out_T_2059 = ~out_womask_185; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_145 = {programBufferMem_19, _out_prepend_T_145}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2060 = out_prepend_145; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2061 = _out_T_2060; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_146 = _out_T_2061; // @[RegisterRouter.scala:87:24]
wire out_rimask_186 = |_out_rimask_T_186; // @[RegisterRouter.scala:87:24]
wire out_wimask_186 = &_out_wimask_T_186; // @[RegisterRouter.scala:87:24]
wire out_romask_186 = |_out_romask_T_186; // @[RegisterRouter.scala:87:24]
wire out_womask_186 = &_out_womask_T_186; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_186 = out_rivalid_1_36 & out_rimask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2063 = out_f_rivalid_186; // @[RegisterRouter.scala:87:24]
wire out_f_roready_186 = out_roready_1_36 & out_romask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2064 = out_f_roready_186; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_186 = out_wivalid_1_36 & out_wimask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2065 = out_f_wivalid_186; // @[RegisterRouter.scala:87:24]
wire out_f_woready_186 = out_woready_1_36 & out_womask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2066 = out_f_woready_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2067 = ~out_rimask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2068 = ~out_wimask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2069 = ~out_romask_186; // @[RegisterRouter.scala:87:24]
wire _out_T_2070 = ~out_womask_186; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_146 = {programBufferMem_20, _out_prepend_T_146}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2071 = out_prepend_146; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2072 = _out_T_2071; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_147 = _out_T_2072; // @[RegisterRouter.scala:87:24]
wire out_rimask_187 = |_out_rimask_T_187; // @[RegisterRouter.scala:87:24]
wire out_wimask_187 = &_out_wimask_T_187; // @[RegisterRouter.scala:87:24]
wire out_romask_187 = |_out_romask_T_187; // @[RegisterRouter.scala:87:24]
wire out_womask_187 = &_out_womask_T_187; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_187 = out_rivalid_1_37 & out_rimask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2074 = out_f_rivalid_187; // @[RegisterRouter.scala:87:24]
wire out_f_roready_187 = out_roready_1_37 & out_romask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2075 = out_f_roready_187; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_187 = out_wivalid_1_37 & out_wimask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2076 = out_f_wivalid_187; // @[RegisterRouter.scala:87:24]
wire out_f_woready_187 = out_woready_1_37 & out_womask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2077 = out_f_woready_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2078 = ~out_rimask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2079 = ~out_wimask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2080 = ~out_romask_187; // @[RegisterRouter.scala:87:24]
wire _out_T_2081 = ~out_womask_187; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_147 = {programBufferMem_21, _out_prepend_T_147}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2082 = out_prepend_147; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2083 = _out_T_2082; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_148 = _out_T_2083; // @[RegisterRouter.scala:87:24]
wire out_rimask_188 = |_out_rimask_T_188; // @[RegisterRouter.scala:87:24]
wire out_wimask_188 = &_out_wimask_T_188; // @[RegisterRouter.scala:87:24]
wire out_romask_188 = |_out_romask_T_188; // @[RegisterRouter.scala:87:24]
wire out_womask_188 = &_out_womask_T_188; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_188 = out_rivalid_1_38 & out_rimask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2085 = out_f_rivalid_188; // @[RegisterRouter.scala:87:24]
wire out_f_roready_188 = out_roready_1_38 & out_romask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2086 = out_f_roready_188; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_188 = out_wivalid_1_38 & out_wimask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2087 = out_f_wivalid_188; // @[RegisterRouter.scala:87:24]
wire out_f_woready_188 = out_woready_1_38 & out_womask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2088 = out_f_woready_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2089 = ~out_rimask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2090 = ~out_wimask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2091 = ~out_romask_188; // @[RegisterRouter.scala:87:24]
wire _out_T_2092 = ~out_womask_188; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_148 = {programBufferMem_22, _out_prepend_T_148}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2093 = out_prepend_148; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2094 = _out_T_2093; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_149 = _out_T_2094; // @[RegisterRouter.scala:87:24]
wire out_rimask_189 = |_out_rimask_T_189; // @[RegisterRouter.scala:87:24]
wire out_wimask_189 = &_out_wimask_T_189; // @[RegisterRouter.scala:87:24]
wire out_romask_189 = |_out_romask_T_189; // @[RegisterRouter.scala:87:24]
wire out_womask_189 = &_out_womask_T_189; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_189 = out_rivalid_1_39 & out_rimask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2096 = out_f_rivalid_189; // @[RegisterRouter.scala:87:24]
wire out_f_roready_189 = out_roready_1_39 & out_romask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2097 = out_f_roready_189; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_189 = out_wivalid_1_39 & out_wimask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2098 = out_f_wivalid_189; // @[RegisterRouter.scala:87:24]
wire out_f_woready_189 = out_woready_1_39 & out_womask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2099 = out_f_woready_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2100 = ~out_rimask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2101 = ~out_wimask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2102 = ~out_romask_189; // @[RegisterRouter.scala:87:24]
wire _out_T_2103 = ~out_womask_189; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_149 = {programBufferMem_23, _out_prepend_T_149}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2104 = out_prepend_149; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2105 = _out_T_2104; // @[RegisterRouter.scala:87:24]
wire out_rimask_190 = |_out_rimask_T_190; // @[RegisterRouter.scala:87:24]
wire out_wimask_190 = &_out_wimask_T_190; // @[RegisterRouter.scala:87:24]
wire out_romask_190 = |_out_romask_T_190; // @[RegisterRouter.scala:87:24]
wire out_womask_190 = &_out_womask_T_190; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_190 = out_rivalid_1_40 & out_rimask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2107 = out_f_rivalid_190; // @[RegisterRouter.scala:87:24]
wire out_f_roready_190 = out_roready_1_40 & out_romask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2108 = out_f_roready_190; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_190 = out_wivalid_1_40 & out_wimask_190; // @[RegisterRouter.scala:87:24]
wire out_f_woready_190 = out_woready_1_40 & out_womask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2109 = ~out_rimask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2110 = ~out_wimask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2111 = ~out_romask_190; // @[RegisterRouter.scala:87:24]
wire _out_T_2112 = ~out_womask_190; // @[RegisterRouter.scala:87:24]
wire out_rimask_191 = |_out_rimask_T_191; // @[RegisterRouter.scala:87:24]
wire out_wimask_191 = &_out_wimask_T_191; // @[RegisterRouter.scala:87:24]
wire out_romask_191 = |_out_romask_T_191; // @[RegisterRouter.scala:87:24]
wire out_womask_191 = &_out_womask_T_191; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_191 = out_rivalid_1_41 & out_rimask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2116 = out_f_rivalid_191; // @[RegisterRouter.scala:87:24]
wire out_f_roready_191 = out_roready_1_41 & out_romask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2117 = out_f_roready_191; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_191 = out_wivalid_1_41 & out_wimask_191; // @[RegisterRouter.scala:87:24]
wire out_f_woready_191 = out_woready_1_41 & out_womask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2118 = ~out_rimask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2119 = ~out_wimask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2120 = ~out_romask_191; // @[RegisterRouter.scala:87:24]
wire _out_T_2121 = ~out_womask_191; // @[RegisterRouter.scala:87:24]
wire out_rimask_192 = |_out_rimask_T_192; // @[RegisterRouter.scala:87:24]
wire out_wimask_192 = &_out_wimask_T_192; // @[RegisterRouter.scala:87:24]
wire out_romask_192 = |_out_romask_T_192; // @[RegisterRouter.scala:87:24]
wire out_womask_192 = &_out_womask_T_192; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_192 = out_rivalid_1_42 & out_rimask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2125 = out_f_rivalid_192; // @[RegisterRouter.scala:87:24]
wire out_f_roready_192 = out_roready_1_42 & out_romask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2126 = out_f_roready_192; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_192 = out_wivalid_1_42 & out_wimask_192; // @[RegisterRouter.scala:87:24]
wire out_f_woready_192 = out_woready_1_42 & out_womask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2127 = ~out_rimask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2128 = ~out_wimask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2129 = ~out_romask_192; // @[RegisterRouter.scala:87:24]
wire _out_T_2130 = ~out_womask_192; // @[RegisterRouter.scala:87:24]
wire out_rimask_193 = |_out_rimask_T_193; // @[RegisterRouter.scala:87:24]
wire out_wimask_193 = &_out_wimask_T_193; // @[RegisterRouter.scala:87:24]
wire out_romask_193 = |_out_romask_T_193; // @[RegisterRouter.scala:87:24]
wire out_womask_193 = &_out_womask_T_193; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_193 = out_rivalid_1_43 & out_rimask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2134 = out_f_rivalid_193; // @[RegisterRouter.scala:87:24]
wire out_f_roready_193 = out_roready_1_43 & out_romask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2135 = out_f_roready_193; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_193 = out_wivalid_1_43 & out_wimask_193; // @[RegisterRouter.scala:87:24]
wire out_f_woready_193 = out_woready_1_43 & out_womask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2136 = ~out_rimask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2137 = ~out_wimask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2138 = ~out_romask_193; // @[RegisterRouter.scala:87:24]
wire _out_T_2139 = ~out_womask_193; // @[RegisterRouter.scala:87:24]
wire out_rimask_194 = |_out_rimask_T_194; // @[RegisterRouter.scala:87:24]
wire out_wimask_194 = &_out_wimask_T_194; // @[RegisterRouter.scala:87:24]
wire out_romask_194 = |_out_romask_T_194; // @[RegisterRouter.scala:87:24]
wire out_womask_194 = &_out_womask_T_194; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_194 = out_rivalid_1_44 & out_rimask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2143 = out_f_rivalid_194; // @[RegisterRouter.scala:87:24]
wire out_f_roready_194 = out_roready_1_44 & out_romask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2144 = out_f_roready_194; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_194 = out_wivalid_1_44 & out_wimask_194; // @[RegisterRouter.scala:87:24]
wire out_f_woready_194 = out_woready_1_44 & out_womask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2145 = ~out_rimask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2146 = ~out_wimask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2147 = ~out_romask_194; // @[RegisterRouter.scala:87:24]
wire _out_T_2148 = ~out_womask_194; // @[RegisterRouter.scala:87:24]
wire out_rimask_195 = |_out_rimask_T_195; // @[RegisterRouter.scala:87:24]
wire out_wimask_195 = &_out_wimask_T_195; // @[RegisterRouter.scala:87:24]
wire out_romask_195 = |_out_romask_T_195; // @[RegisterRouter.scala:87:24]
wire out_womask_195 = &_out_womask_T_195; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_195 = out_rivalid_1_45 & out_rimask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2152 = out_f_rivalid_195; // @[RegisterRouter.scala:87:24]
wire out_f_roready_195 = out_roready_1_45 & out_romask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2153 = out_f_roready_195; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_195 = out_wivalid_1_45 & out_wimask_195; // @[RegisterRouter.scala:87:24]
wire out_f_woready_195 = out_woready_1_45 & out_womask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2154 = ~out_rimask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2155 = ~out_wimask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2156 = ~out_romask_195; // @[RegisterRouter.scala:87:24]
wire _out_T_2157 = ~out_womask_195; // @[RegisterRouter.scala:87:24]
wire out_rimask_196 = |_out_rimask_T_196; // @[RegisterRouter.scala:87:24]
wire out_wimask_196 = &_out_wimask_T_196; // @[RegisterRouter.scala:87:24]
wire out_romask_196 = |_out_romask_T_196; // @[RegisterRouter.scala:87:24]
wire out_womask_196 = &_out_womask_T_196; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_196 = out_rivalid_1_46 & out_rimask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2161 = out_f_rivalid_196; // @[RegisterRouter.scala:87:24]
wire out_f_roready_196 = out_roready_1_46 & out_romask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2162 = out_f_roready_196; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_196 = out_wivalid_1_46 & out_wimask_196; // @[RegisterRouter.scala:87:24]
wire out_f_woready_196 = out_woready_1_46 & out_womask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2163 = ~out_rimask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2164 = ~out_wimask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2165 = ~out_romask_196; // @[RegisterRouter.scala:87:24]
wire _out_T_2166 = ~out_womask_196; // @[RegisterRouter.scala:87:24]
wire out_rimask_197 = |_out_rimask_T_197; // @[RegisterRouter.scala:87:24]
wire out_wimask_197 = &_out_wimask_T_197; // @[RegisterRouter.scala:87:24]
wire out_romask_197 = |_out_romask_T_197; // @[RegisterRouter.scala:87:24]
wire out_womask_197 = &_out_womask_T_197; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_197 = out_rivalid_1_47 & out_rimask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2170 = out_f_rivalid_197; // @[RegisterRouter.scala:87:24]
wire out_f_roready_197 = out_roready_1_47 & out_romask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2171 = out_f_roready_197; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_197 = out_wivalid_1_47 & out_wimask_197; // @[RegisterRouter.scala:87:24]
wire out_f_woready_197 = out_woready_1_47 & out_womask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2172 = ~out_rimask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2173 = ~out_wimask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2174 = ~out_romask_197; // @[RegisterRouter.scala:87:24]
wire _out_T_2175 = ~out_womask_197; // @[RegisterRouter.scala:87:24]
wire out_rimask_198 = |_out_rimask_T_198; // @[RegisterRouter.scala:87:24]
wire out_wimask_198 = &_out_wimask_T_198; // @[RegisterRouter.scala:87:24]
wire out_romask_198 = |_out_romask_T_198; // @[RegisterRouter.scala:87:24]
wire out_womask_198 = &_out_womask_T_198; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_198 = out_rivalid_1_48 & out_rimask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2179 = out_f_rivalid_198; // @[RegisterRouter.scala:87:24]
wire out_f_roready_198 = out_roready_1_48 & out_romask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2180 = out_f_roready_198; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_198 = out_wivalid_1_48 & out_wimask_198; // @[RegisterRouter.scala:87:24]
wire out_f_woready_198 = out_woready_1_48 & out_womask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2181 = ~out_rimask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2182 = ~out_wimask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2183 = ~out_romask_198; // @[RegisterRouter.scala:87:24]
wire _out_T_2184 = ~out_womask_198; // @[RegisterRouter.scala:87:24]
wire out_rimask_199 = |_out_rimask_T_199; // @[RegisterRouter.scala:87:24]
wire out_wimask_199 = &_out_wimask_T_199; // @[RegisterRouter.scala:87:24]
wire out_romask_199 = |_out_romask_T_199; // @[RegisterRouter.scala:87:24]
wire out_womask_199 = &_out_womask_T_199; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_199 = out_rivalid_1_49 & out_rimask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2188 = out_f_rivalid_199; // @[RegisterRouter.scala:87:24]
wire out_f_roready_199 = out_roready_1_49 & out_romask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2189 = out_f_roready_199; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_199 = out_wivalid_1_49 & out_wimask_199; // @[RegisterRouter.scala:87:24]
wire out_f_woready_199 = out_woready_1_49 & out_womask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2190 = ~out_rimask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2191 = ~out_wimask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2192 = ~out_romask_199; // @[RegisterRouter.scala:87:24]
wire _out_T_2193 = ~out_womask_199; // @[RegisterRouter.scala:87:24]
wire out_rimask_200 = |_out_rimask_T_200; // @[RegisterRouter.scala:87:24]
wire out_wimask_200 = &_out_wimask_T_200; // @[RegisterRouter.scala:87:24]
wire out_romask_200 = |_out_romask_T_200; // @[RegisterRouter.scala:87:24]
wire out_womask_200 = &_out_womask_T_200; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_200 = out_rivalid_1_50 & out_rimask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2197 = out_f_rivalid_200; // @[RegisterRouter.scala:87:24]
wire out_f_roready_200 = out_roready_1_50 & out_romask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2198 = out_f_roready_200; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_200 = out_wivalid_1_50 & out_wimask_200; // @[RegisterRouter.scala:87:24]
wire out_f_woready_200 = out_woready_1_50 & out_womask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2199 = ~out_rimask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2200 = ~out_wimask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2201 = ~out_romask_200; // @[RegisterRouter.scala:87:24]
wire _out_T_2202 = ~out_womask_200; // @[RegisterRouter.scala:87:24]
wire out_rimask_201 = |_out_rimask_T_201; // @[RegisterRouter.scala:87:24]
wire out_wimask_201 = &_out_wimask_T_201; // @[RegisterRouter.scala:87:24]
wire out_romask_201 = |_out_romask_T_201; // @[RegisterRouter.scala:87:24]
wire out_womask_201 = &_out_womask_T_201; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_201 = out_rivalid_1_51 & out_rimask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2206 = out_f_rivalid_201; // @[RegisterRouter.scala:87:24]
wire out_f_roready_201 = out_roready_1_51 & out_romask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2207 = out_f_roready_201; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_201 = out_wivalid_1_51 & out_wimask_201; // @[RegisterRouter.scala:87:24]
wire out_f_woready_201 = out_woready_1_51 & out_womask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2208 = ~out_rimask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2209 = ~out_wimask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2210 = ~out_romask_201; // @[RegisterRouter.scala:87:24]
wire _out_T_2211 = ~out_womask_201; // @[RegisterRouter.scala:87:24]
wire out_rimask_202 = |_out_rimask_T_202; // @[RegisterRouter.scala:87:24]
wire out_wimask_202 = &_out_wimask_T_202; // @[RegisterRouter.scala:87:24]
wire out_romask_202 = |_out_romask_T_202; // @[RegisterRouter.scala:87:24]
wire out_womask_202 = &_out_womask_T_202; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_202 = out_rivalid_1_52 & out_rimask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2215 = out_f_rivalid_202; // @[RegisterRouter.scala:87:24]
wire out_f_roready_202 = out_roready_1_52 & out_romask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2216 = out_f_roready_202; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_202 = out_wivalid_1_52 & out_wimask_202; // @[RegisterRouter.scala:87:24]
wire out_f_woready_202 = out_woready_1_52 & out_womask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2217 = ~out_rimask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2218 = ~out_wimask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2219 = ~out_romask_202; // @[RegisterRouter.scala:87:24]
wire _out_T_2220 = ~out_womask_202; // @[RegisterRouter.scala:87:24]
wire out_rimask_203 = |_out_rimask_T_203; // @[RegisterRouter.scala:87:24]
wire out_wimask_203 = &_out_wimask_T_203; // @[RegisterRouter.scala:87:24]
wire out_romask_203 = |_out_romask_T_203; // @[RegisterRouter.scala:87:24]
wire out_womask_203 = &_out_womask_T_203; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_203 = out_rivalid_1_53 & out_rimask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2224 = out_f_rivalid_203; // @[RegisterRouter.scala:87:24]
wire out_f_roready_203 = out_roready_1_53 & out_romask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2225 = out_f_roready_203; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_203 = out_wivalid_1_53 & out_wimask_203; // @[RegisterRouter.scala:87:24]
wire out_f_woready_203 = out_woready_1_53 & out_womask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2226 = ~out_rimask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2227 = ~out_wimask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2228 = ~out_romask_203; // @[RegisterRouter.scala:87:24]
wire _out_T_2229 = ~out_womask_203; // @[RegisterRouter.scala:87:24]
wire out_rimask_204 = |_out_rimask_T_204; // @[RegisterRouter.scala:87:24]
wire out_wimask_204 = &_out_wimask_T_204; // @[RegisterRouter.scala:87:24]
wire out_romask_204 = |_out_romask_T_204; // @[RegisterRouter.scala:87:24]
wire out_womask_204 = &_out_womask_T_204; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_204 = out_rivalid_1_54 & out_rimask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2233 = out_f_rivalid_204; // @[RegisterRouter.scala:87:24]
wire out_f_roready_204 = out_roready_1_54 & out_romask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2234 = out_f_roready_204; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_204 = out_wivalid_1_54 & out_wimask_204; // @[RegisterRouter.scala:87:24]
wire out_f_woready_204 = out_woready_1_54 & out_womask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2235 = ~out_rimask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2236 = ~out_wimask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2237 = ~out_romask_204; // @[RegisterRouter.scala:87:24]
wire _out_T_2238 = ~out_womask_204; // @[RegisterRouter.scala:87:24]
wire out_rimask_205 = |_out_rimask_T_205; // @[RegisterRouter.scala:87:24]
wire out_wimask_205 = &_out_wimask_T_205; // @[RegisterRouter.scala:87:24]
wire out_romask_205 = |_out_romask_T_205; // @[RegisterRouter.scala:87:24]
wire out_womask_205 = &_out_womask_T_205; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_205 = out_rivalid_1_55 & out_rimask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2242 = out_f_rivalid_205; // @[RegisterRouter.scala:87:24]
wire out_f_roready_205 = out_roready_1_55 & out_romask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2243 = out_f_roready_205; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_205 = out_wivalid_1_55 & out_wimask_205; // @[RegisterRouter.scala:87:24]
wire out_f_woready_205 = out_woready_1_55 & out_womask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2244 = ~out_rimask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2245 = ~out_wimask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2246 = ~out_romask_205; // @[RegisterRouter.scala:87:24]
wire _out_T_2247 = ~out_womask_205; // @[RegisterRouter.scala:87:24]
wire out_rimask_206 = |_out_rimask_T_206; // @[RegisterRouter.scala:87:24]
wire out_wimask_206 = &_out_wimask_T_206; // @[RegisterRouter.scala:87:24]
wire out_romask_206 = |_out_romask_T_206; // @[RegisterRouter.scala:87:24]
wire out_womask_206 = &_out_womask_T_206; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_206 = out_rivalid_1_56 & out_rimask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2251 = out_f_rivalid_206; // @[RegisterRouter.scala:87:24]
wire out_f_roready_206 = out_roready_1_56 & out_romask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2252 = out_f_roready_206; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_206 = out_wivalid_1_56 & out_wimask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2253 = out_f_wivalid_206; // @[RegisterRouter.scala:87:24]
wire out_f_woready_206 = out_woready_1_56 & out_womask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2254 = out_f_woready_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2255 = ~out_rimask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2256 = ~out_wimask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2257 = ~out_romask_206; // @[RegisterRouter.scala:87:24]
wire _out_T_2258 = ~out_womask_206; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2260 = _out_T_2259; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_164 = _out_T_2260; // @[RegisterRouter.scala:87:24]
wire out_rimask_207 = |_out_rimask_T_207; // @[RegisterRouter.scala:87:24]
wire out_wimask_207 = &_out_wimask_T_207; // @[RegisterRouter.scala:87:24]
wire out_romask_207 = |_out_romask_T_207; // @[RegisterRouter.scala:87:24]
wire out_womask_207 = &_out_womask_T_207; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_207 = out_rivalid_1_57 & out_rimask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2262 = out_f_rivalid_207; // @[RegisterRouter.scala:87:24]
wire out_f_roready_207 = out_roready_1_57 & out_romask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2263 = out_f_roready_207; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_207 = out_wivalid_1_57 & out_wimask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2264 = out_f_wivalid_207; // @[RegisterRouter.scala:87:24]
wire out_f_woready_207 = out_woready_1_57 & out_womask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2265 = out_f_woready_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2266 = ~out_rimask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2267 = ~out_wimask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2268 = ~out_romask_207; // @[RegisterRouter.scala:87:24]
wire _out_T_2269 = ~out_womask_207; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_164 = {abstractDataMem_9, _out_prepend_T_164}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2270 = out_prepend_164; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2271 = _out_T_2270; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_165 = _out_T_2271; // @[RegisterRouter.scala:87:24]
wire out_rimask_208 = |_out_rimask_T_208; // @[RegisterRouter.scala:87:24]
wire out_wimask_208 = &_out_wimask_T_208; // @[RegisterRouter.scala:87:24]
wire out_romask_208 = |_out_romask_T_208; // @[RegisterRouter.scala:87:24]
wire out_womask_208 = &_out_womask_T_208; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_208 = out_rivalid_1_58 & out_rimask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2273 = out_f_rivalid_208; // @[RegisterRouter.scala:87:24]
wire out_f_roready_208 = out_roready_1_58 & out_romask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2274 = out_f_roready_208; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_208 = out_wivalid_1_58 & out_wimask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2275 = out_f_wivalid_208; // @[RegisterRouter.scala:87:24]
wire out_f_woready_208 = out_woready_1_58 & out_womask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2276 = out_f_woready_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2277 = ~out_rimask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2278 = ~out_wimask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2279 = ~out_romask_208; // @[RegisterRouter.scala:87:24]
wire _out_T_2280 = ~out_womask_208; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_165 = {abstractDataMem_10, _out_prepend_T_165}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2281 = out_prepend_165; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2282 = _out_T_2281; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_166 = _out_T_2282; // @[RegisterRouter.scala:87:24]
wire out_rimask_209 = |_out_rimask_T_209; // @[RegisterRouter.scala:87:24]
wire out_wimask_209 = &_out_wimask_T_209; // @[RegisterRouter.scala:87:24]
wire out_romask_209 = |_out_romask_T_209; // @[RegisterRouter.scala:87:24]
wire out_womask_209 = &_out_womask_T_209; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_209 = out_rivalid_1_59 & out_rimask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2284 = out_f_rivalid_209; // @[RegisterRouter.scala:87:24]
wire out_f_roready_209 = out_roready_1_59 & out_romask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2285 = out_f_roready_209; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_209 = out_wivalid_1_59 & out_wimask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2286 = out_f_wivalid_209; // @[RegisterRouter.scala:87:24]
wire out_f_woready_209 = out_woready_1_59 & out_womask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2287 = out_f_woready_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2288 = ~out_rimask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2289 = ~out_wimask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2290 = ~out_romask_209; // @[RegisterRouter.scala:87:24]
wire _out_T_2291 = ~out_womask_209; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_166 = {abstractDataMem_11, _out_prepend_T_166}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2292 = out_prepend_166; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2293 = _out_T_2292; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_167 = _out_T_2293; // @[RegisterRouter.scala:87:24]
wire out_rimask_210 = |_out_rimask_T_210; // @[RegisterRouter.scala:87:24]
wire out_wimask_210 = &_out_wimask_T_210; // @[RegisterRouter.scala:87:24]
wire out_romask_210 = |_out_romask_T_210; // @[RegisterRouter.scala:87:24]
wire out_womask_210 = &_out_womask_T_210; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_210 = out_rivalid_1_60 & out_rimask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2295 = out_f_rivalid_210; // @[RegisterRouter.scala:87:24]
wire out_f_roready_210 = out_roready_1_60 & out_romask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2296 = out_f_roready_210; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_210 = out_wivalid_1_60 & out_wimask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2297 = out_f_wivalid_210; // @[RegisterRouter.scala:87:24]
wire out_f_woready_210 = out_woready_1_60 & out_womask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2298 = out_f_woready_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2299 = ~out_rimask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2300 = ~out_wimask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2301 = ~out_romask_210; // @[RegisterRouter.scala:87:24]
wire _out_T_2302 = ~out_womask_210; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_167 = {abstractDataMem_12, _out_prepend_T_167}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2303 = out_prepend_167; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2304 = _out_T_2303; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_168 = _out_T_2304; // @[RegisterRouter.scala:87:24]
wire out_rimask_211 = |_out_rimask_T_211; // @[RegisterRouter.scala:87:24]
wire out_wimask_211 = &_out_wimask_T_211; // @[RegisterRouter.scala:87:24]
wire out_romask_211 = |_out_romask_T_211; // @[RegisterRouter.scala:87:24]
wire out_womask_211 = &_out_womask_T_211; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_211 = out_rivalid_1_61 & out_rimask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2306 = out_f_rivalid_211; // @[RegisterRouter.scala:87:24]
wire out_f_roready_211 = out_roready_1_61 & out_romask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2307 = out_f_roready_211; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_211 = out_wivalid_1_61 & out_wimask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2308 = out_f_wivalid_211; // @[RegisterRouter.scala:87:24]
wire out_f_woready_211 = out_woready_1_61 & out_womask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2309 = out_f_woready_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2310 = ~out_rimask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2311 = ~out_wimask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2312 = ~out_romask_211; // @[RegisterRouter.scala:87:24]
wire _out_T_2313 = ~out_womask_211; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_168 = {abstractDataMem_13, _out_prepend_T_168}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2314 = out_prepend_168; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2315 = _out_T_2314; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_169 = _out_T_2315; // @[RegisterRouter.scala:87:24]
wire out_rimask_212 = |_out_rimask_T_212; // @[RegisterRouter.scala:87:24]
wire out_wimask_212 = &_out_wimask_T_212; // @[RegisterRouter.scala:87:24]
wire out_romask_212 = |_out_romask_T_212; // @[RegisterRouter.scala:87:24]
wire out_womask_212 = &_out_womask_T_212; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_212 = out_rivalid_1_62 & out_rimask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2317 = out_f_rivalid_212; // @[RegisterRouter.scala:87:24]
wire out_f_roready_212 = out_roready_1_62 & out_romask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2318 = out_f_roready_212; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_212 = out_wivalid_1_62 & out_wimask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2319 = out_f_wivalid_212; // @[RegisterRouter.scala:87:24]
wire out_f_woready_212 = out_woready_1_62 & out_womask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2320 = out_f_woready_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2321 = ~out_rimask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2322 = ~out_wimask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2323 = ~out_romask_212; // @[RegisterRouter.scala:87:24]
wire _out_T_2324 = ~out_womask_212; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_169 = {abstractDataMem_14, _out_prepend_T_169}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2325 = out_prepend_169; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2326 = _out_T_2325; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_170 = _out_T_2326; // @[RegisterRouter.scala:87:24]
wire out_rimask_213 = |_out_rimask_T_213; // @[RegisterRouter.scala:87:24]
wire out_wimask_213 = &_out_wimask_T_213; // @[RegisterRouter.scala:87:24]
wire out_romask_213 = |_out_romask_T_213; // @[RegisterRouter.scala:87:24]
wire out_womask_213 = &_out_womask_T_213; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_213 = out_rivalid_1_63 & out_rimask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2328 = out_f_rivalid_213; // @[RegisterRouter.scala:87:24]
wire out_f_roready_213 = out_roready_1_63 & out_romask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2329 = out_f_roready_213; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_213 = out_wivalid_1_63 & out_wimask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2330 = out_f_wivalid_213; // @[RegisterRouter.scala:87:24]
wire out_f_woready_213 = out_woready_1_63 & out_womask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2331 = out_f_woready_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2332 = ~out_rimask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2333 = ~out_wimask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2334 = ~out_romask_213; // @[RegisterRouter.scala:87:24]
wire _out_T_2335 = ~out_womask_213; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_170 = {abstractDataMem_15, _out_prepend_T_170}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2336 = out_prepend_170; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2337 = _out_T_2336; // @[RegisterRouter.scala:87:24]
wire out_rimask_214 = |_out_rimask_T_214; // @[RegisterRouter.scala:87:24]
wire out_wimask_214 = &_out_wimask_T_214; // @[RegisterRouter.scala:87:24]
wire out_romask_214 = |_out_romask_T_214; // @[RegisterRouter.scala:87:24]
wire out_womask_214 = &_out_womask_T_214; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_214 = out_rivalid_1_64 & out_rimask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2339 = out_f_rivalid_214; // @[RegisterRouter.scala:87:24]
wire out_f_roready_214 = out_roready_1_64 & out_romask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2340 = out_f_roready_214; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_214 = out_wivalid_1_64 & out_wimask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2341 = out_f_wivalid_214; // @[RegisterRouter.scala:87:24]
wire out_f_woready_214 = out_woready_1_64 & out_womask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2342 = out_f_woready_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2343 = ~out_rimask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2344 = ~out_wimask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2345 = ~out_romask_214; // @[RegisterRouter.scala:87:24]
wire _out_T_2346 = ~out_womask_214; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2348 = _out_T_2347; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_171 = _out_T_2348; // @[RegisterRouter.scala:87:24]
wire out_rimask_215 = |_out_rimask_T_215; // @[RegisterRouter.scala:87:24]
wire out_wimask_215 = &_out_wimask_T_215; // @[RegisterRouter.scala:87:24]
wire out_romask_215 = |_out_romask_T_215; // @[RegisterRouter.scala:87:24]
wire out_womask_215 = &_out_womask_T_215; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_215 = out_rivalid_1_65 & out_rimask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2350 = out_f_rivalid_215; // @[RegisterRouter.scala:87:24]
wire out_f_roready_215 = out_roready_1_65 & out_romask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2351 = out_f_roready_215; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_215 = out_wivalid_1_65 & out_wimask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2352 = out_f_wivalid_215; // @[RegisterRouter.scala:87:24]
wire out_f_woready_215 = out_woready_1_65 & out_womask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2353 = out_f_woready_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2354 = ~out_rimask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2355 = ~out_wimask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2356 = ~out_romask_215; // @[RegisterRouter.scala:87:24]
wire _out_T_2357 = ~out_womask_215; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_171 = {abstractDataMem_1, _out_prepend_T_171}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2358 = out_prepend_171; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2359 = _out_T_2358; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_172 = _out_T_2359; // @[RegisterRouter.scala:87:24]
wire out_rimask_216 = |_out_rimask_T_216; // @[RegisterRouter.scala:87:24]
wire out_wimask_216 = &_out_wimask_T_216; // @[RegisterRouter.scala:87:24]
wire out_romask_216 = |_out_romask_T_216; // @[RegisterRouter.scala:87:24]
wire out_womask_216 = &_out_womask_T_216; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_216 = out_rivalid_1_66 & out_rimask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2361 = out_f_rivalid_216; // @[RegisterRouter.scala:87:24]
wire out_f_roready_216 = out_roready_1_66 & out_romask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2362 = out_f_roready_216; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_216 = out_wivalid_1_66 & out_wimask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2363 = out_f_wivalid_216; // @[RegisterRouter.scala:87:24]
wire out_f_woready_216 = out_woready_1_66 & out_womask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2364 = out_f_woready_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2365 = ~out_rimask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2366 = ~out_wimask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2367 = ~out_romask_216; // @[RegisterRouter.scala:87:24]
wire _out_T_2368 = ~out_womask_216; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_172 = {abstractDataMem_2, _out_prepend_T_172}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2369 = out_prepend_172; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2370 = _out_T_2369; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_173 = _out_T_2370; // @[RegisterRouter.scala:87:24]
wire out_rimask_217 = |_out_rimask_T_217; // @[RegisterRouter.scala:87:24]
wire out_wimask_217 = &_out_wimask_T_217; // @[RegisterRouter.scala:87:24]
wire out_romask_217 = |_out_romask_T_217; // @[RegisterRouter.scala:87:24]
wire out_womask_217 = &_out_womask_T_217; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_217 = out_rivalid_1_67 & out_rimask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2372 = out_f_rivalid_217; // @[RegisterRouter.scala:87:24]
wire out_f_roready_217 = out_roready_1_67 & out_romask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2373 = out_f_roready_217; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_217 = out_wivalid_1_67 & out_wimask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2374 = out_f_wivalid_217; // @[RegisterRouter.scala:87:24]
wire out_f_woready_217 = out_woready_1_67 & out_womask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2375 = out_f_woready_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2376 = ~out_rimask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2377 = ~out_wimask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2378 = ~out_romask_217; // @[RegisterRouter.scala:87:24]
wire _out_T_2379 = ~out_womask_217; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_173 = {abstractDataMem_3, _out_prepend_T_173}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2380 = out_prepend_173; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2381 = _out_T_2380; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_174 = _out_T_2381; // @[RegisterRouter.scala:87:24]
wire out_rimask_218 = |_out_rimask_T_218; // @[RegisterRouter.scala:87:24]
wire out_wimask_218 = &_out_wimask_T_218; // @[RegisterRouter.scala:87:24]
wire out_romask_218 = |_out_romask_T_218; // @[RegisterRouter.scala:87:24]
wire out_womask_218 = &_out_womask_T_218; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_218 = out_rivalid_1_68 & out_rimask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2383 = out_f_rivalid_218; // @[RegisterRouter.scala:87:24]
wire out_f_roready_218 = out_roready_1_68 & out_romask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2384 = out_f_roready_218; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_218 = out_wivalid_1_68 & out_wimask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2385 = out_f_wivalid_218; // @[RegisterRouter.scala:87:24]
wire out_f_woready_218 = out_woready_1_68 & out_womask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2386 = out_f_woready_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2387 = ~out_rimask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2388 = ~out_wimask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2389 = ~out_romask_218; // @[RegisterRouter.scala:87:24]
wire _out_T_2390 = ~out_womask_218; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_174 = {abstractDataMem_4, _out_prepend_T_174}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2391 = out_prepend_174; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2392 = _out_T_2391; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_175 = _out_T_2392; // @[RegisterRouter.scala:87:24]
wire out_rimask_219 = |_out_rimask_T_219; // @[RegisterRouter.scala:87:24]
wire out_wimask_219 = &_out_wimask_T_219; // @[RegisterRouter.scala:87:24]
wire out_romask_219 = |_out_romask_T_219; // @[RegisterRouter.scala:87:24]
wire out_womask_219 = &_out_womask_T_219; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_219 = out_rivalid_1_69 & out_rimask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2394 = out_f_rivalid_219; // @[RegisterRouter.scala:87:24]
wire out_f_roready_219 = out_roready_1_69 & out_romask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2395 = out_f_roready_219; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_219 = out_wivalid_1_69 & out_wimask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2396 = out_f_wivalid_219; // @[RegisterRouter.scala:87:24]
wire out_f_woready_219 = out_woready_1_69 & out_womask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2397 = out_f_woready_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2398 = ~out_rimask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2399 = ~out_wimask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2400 = ~out_romask_219; // @[RegisterRouter.scala:87:24]
wire _out_T_2401 = ~out_womask_219; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_175 = {abstractDataMem_5, _out_prepend_T_175}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2402 = out_prepend_175; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2403 = _out_T_2402; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_176 = _out_T_2403; // @[RegisterRouter.scala:87:24]
wire out_rimask_220 = |_out_rimask_T_220; // @[RegisterRouter.scala:87:24]
wire out_wimask_220 = &_out_wimask_T_220; // @[RegisterRouter.scala:87:24]
wire out_romask_220 = |_out_romask_T_220; // @[RegisterRouter.scala:87:24]
wire out_womask_220 = &_out_womask_T_220; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_220 = out_rivalid_1_70 & out_rimask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2405 = out_f_rivalid_220; // @[RegisterRouter.scala:87:24]
wire out_f_roready_220 = out_roready_1_70 & out_romask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2406 = out_f_roready_220; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_220 = out_wivalid_1_70 & out_wimask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2407 = out_f_wivalid_220; // @[RegisterRouter.scala:87:24]
wire out_f_woready_220 = out_woready_1_70 & out_womask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2408 = out_f_woready_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2409 = ~out_rimask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2410 = ~out_wimask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2411 = ~out_romask_220; // @[RegisterRouter.scala:87:24]
wire _out_T_2412 = ~out_womask_220; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_176 = {abstractDataMem_6, _out_prepend_T_176}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2413 = out_prepend_176; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2414 = _out_T_2413; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_177 = _out_T_2414; // @[RegisterRouter.scala:87:24]
wire out_rimask_221 = |_out_rimask_T_221; // @[RegisterRouter.scala:87:24]
wire out_wimask_221 = &_out_wimask_T_221; // @[RegisterRouter.scala:87:24]
wire out_romask_221 = |_out_romask_T_221; // @[RegisterRouter.scala:87:24]
wire out_womask_221 = &_out_womask_T_221; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_221 = out_rivalid_1_71 & out_rimask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2416 = out_f_rivalid_221; // @[RegisterRouter.scala:87:24]
wire out_f_roready_221 = out_roready_1_71 & out_romask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2417 = out_f_roready_221; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_221 = out_wivalid_1_71 & out_wimask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2418 = out_f_wivalid_221; // @[RegisterRouter.scala:87:24]
wire out_f_woready_221 = out_woready_1_71 & out_womask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2419 = out_f_woready_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2420 = ~out_rimask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2421 = ~out_wimask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2422 = ~out_romask_221; // @[RegisterRouter.scala:87:24]
wire _out_T_2423 = ~out_womask_221; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_177 = {abstractDataMem_7, _out_prepend_T_177}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2424 = out_prepend_177; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2425 = _out_T_2424; // @[RegisterRouter.scala:87:24]
wire out_rimask_222 = |_out_rimask_T_222; // @[RegisterRouter.scala:87:24]
wire out_wimask_222 = &_out_wimask_T_222; // @[RegisterRouter.scala:87:24]
wire out_romask_222 = |_out_romask_T_222; // @[RegisterRouter.scala:87:24]
wire out_womask_222 = &_out_womask_T_222; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_222 = out_rivalid_1_72 & out_rimask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2427 = out_f_rivalid_222; // @[RegisterRouter.scala:87:24]
wire out_f_roready_222 = out_roready_1_72 & out_romask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2428 = out_f_roready_222; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_222 = out_wivalid_1_72 & out_wimask_222; // @[RegisterRouter.scala:87:24]
wire out_f_woready_222 = out_woready_1_72 & out_womask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2429 = ~out_rimask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2430 = ~out_wimask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2431 = ~out_romask_222; // @[RegisterRouter.scala:87:24]
wire _out_T_2432 = ~out_womask_222; // @[RegisterRouter.scala:87:24]
wire out_rimask_223 = |_out_rimask_T_223; // @[RegisterRouter.scala:87:24]
wire out_wimask_223 = &_out_wimask_T_223; // @[RegisterRouter.scala:87:24]
wire out_romask_223 = |_out_romask_T_223; // @[RegisterRouter.scala:87:24]
wire out_womask_223 = &_out_womask_T_223; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_223 = out_rivalid_1_73 & out_rimask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2436 = out_f_rivalid_223; // @[RegisterRouter.scala:87:24]
wire out_f_roready_223 = out_roready_1_73 & out_romask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2437 = out_f_roready_223; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_223 = out_wivalid_1_73 & out_wimask_223; // @[RegisterRouter.scala:87:24]
wire out_f_woready_223 = out_woready_1_73 & out_womask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2438 = ~out_rimask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2439 = ~out_wimask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2440 = ~out_romask_223; // @[RegisterRouter.scala:87:24]
wire _out_T_2441 = ~out_womask_223; // @[RegisterRouter.scala:87:24]
wire out_rimask_224 = |_out_rimask_T_224; // @[RegisterRouter.scala:87:24]
wire out_wimask_224 = &_out_wimask_T_224; // @[RegisterRouter.scala:87:24]
wire out_romask_224 = |_out_romask_T_224; // @[RegisterRouter.scala:87:24]
wire out_womask_224 = &_out_womask_T_224; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_224 = out_rivalid_1_74 & out_rimask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2445 = out_f_rivalid_224; // @[RegisterRouter.scala:87:24]
wire out_f_roready_224 = out_roready_1_74 & out_romask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2446 = out_f_roready_224; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_224 = out_wivalid_1_74 & out_wimask_224; // @[RegisterRouter.scala:87:24]
wire out_f_woready_224 = out_woready_1_74 & out_womask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2447 = ~out_rimask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2448 = ~out_wimask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2449 = ~out_romask_224; // @[RegisterRouter.scala:87:24]
wire _out_T_2450 = ~out_womask_224; // @[RegisterRouter.scala:87:24]
wire out_rimask_225 = |_out_rimask_T_225; // @[RegisterRouter.scala:87:24]
wire out_wimask_225 = &_out_wimask_T_225; // @[RegisterRouter.scala:87:24]
wire out_romask_225 = |_out_romask_T_225; // @[RegisterRouter.scala:87:24]
wire out_womask_225 = &_out_womask_T_225; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_225 = out_rivalid_1_75 & out_rimask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2454 = out_f_rivalid_225; // @[RegisterRouter.scala:87:24]
wire out_f_roready_225 = out_roready_1_75 & out_romask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2455 = out_f_roready_225; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_225 = out_wivalid_1_75 & out_wimask_225; // @[RegisterRouter.scala:87:24]
wire out_f_woready_225 = out_woready_1_75 & out_womask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2456 = ~out_rimask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2457 = ~out_wimask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2458 = ~out_romask_225; // @[RegisterRouter.scala:87:24]
wire _out_T_2459 = ~out_womask_225; // @[RegisterRouter.scala:87:24]
wire out_rimask_226 = |_out_rimask_T_226; // @[RegisterRouter.scala:87:24]
wire out_wimask_226 = &_out_wimask_T_226; // @[RegisterRouter.scala:87:24]
wire out_romask_226 = |_out_romask_T_226; // @[RegisterRouter.scala:87:24]
wire out_womask_226 = &_out_womask_T_226; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_226 = out_rivalid_1_76 & out_rimask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2463 = out_f_rivalid_226; // @[RegisterRouter.scala:87:24]
wire out_f_roready_226 = out_roready_1_76 & out_romask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2464 = out_f_roready_226; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_226 = out_wivalid_1_76 & out_wimask_226; // @[RegisterRouter.scala:87:24]
wire out_f_woready_226 = out_woready_1_76 & out_womask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2465 = ~out_rimask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2466 = ~out_wimask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2467 = ~out_romask_226; // @[RegisterRouter.scala:87:24]
wire _out_T_2468 = ~out_womask_226; // @[RegisterRouter.scala:87:24]
wire out_rimask_227 = |_out_rimask_T_227; // @[RegisterRouter.scala:87:24]
wire out_wimask_227 = &_out_wimask_T_227; // @[RegisterRouter.scala:87:24]
wire out_romask_227 = |_out_romask_T_227; // @[RegisterRouter.scala:87:24]
wire out_womask_227 = &_out_womask_T_227; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_227 = out_rivalid_1_77 & out_rimask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2472 = out_f_rivalid_227; // @[RegisterRouter.scala:87:24]
wire out_f_roready_227 = out_roready_1_77 & out_romask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2473 = out_f_roready_227; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_227 = out_wivalid_1_77 & out_wimask_227; // @[RegisterRouter.scala:87:24]
wire out_f_woready_227 = out_woready_1_77 & out_womask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2474 = ~out_rimask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2475 = ~out_wimask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2476 = ~out_romask_227; // @[RegisterRouter.scala:87:24]
wire _out_T_2477 = ~out_womask_227; // @[RegisterRouter.scala:87:24]
wire out_rimask_228 = |_out_rimask_T_228; // @[RegisterRouter.scala:87:24]
wire out_wimask_228 = &_out_wimask_T_228; // @[RegisterRouter.scala:87:24]
wire out_romask_228 = |_out_romask_T_228; // @[RegisterRouter.scala:87:24]
wire out_womask_228 = &_out_womask_T_228; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_228 = out_rivalid_1_78 & out_rimask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2481 = out_f_rivalid_228; // @[RegisterRouter.scala:87:24]
wire out_f_roready_228 = out_roready_1_78 & out_romask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2482 = out_f_roready_228; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_228 = out_wivalid_1_78 & out_wimask_228; // @[RegisterRouter.scala:87:24]
wire out_f_woready_228 = out_woready_1_78 & out_womask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2483 = ~out_rimask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2484 = ~out_wimask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2485 = ~out_romask_228; // @[RegisterRouter.scala:87:24]
wire _out_T_2486 = ~out_womask_228; // @[RegisterRouter.scala:87:24]
wire out_rimask_229 = |_out_rimask_T_229; // @[RegisterRouter.scala:87:24]
wire out_wimask_229 = &_out_wimask_T_229; // @[RegisterRouter.scala:87:24]
wire out_romask_229 = |_out_romask_T_229; // @[RegisterRouter.scala:87:24]
wire out_womask_229 = &_out_womask_T_229; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_229 = out_rivalid_1_79 & out_rimask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2490 = out_f_rivalid_229; // @[RegisterRouter.scala:87:24]
wire out_f_roready_229 = out_roready_1_79 & out_romask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2491 = out_f_roready_229; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_229 = out_wivalid_1_79 & out_wimask_229; // @[RegisterRouter.scala:87:24]
wire out_f_woready_229 = out_woready_1_79 & out_womask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2492 = ~out_rimask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2493 = ~out_wimask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2494 = ~out_romask_229; // @[RegisterRouter.scala:87:24]
wire _out_T_2495 = ~out_womask_229; // @[RegisterRouter.scala:87:24]
wire out_rimask_230 = |_out_rimask_T_230; // @[RegisterRouter.scala:87:24]
wire out_wimask_230 = &_out_wimask_T_230; // @[RegisterRouter.scala:87:24]
wire out_romask_230 = |_out_romask_T_230; // @[RegisterRouter.scala:87:24]
wire out_womask_230 = &_out_womask_T_230; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_230 = out_rivalid_1_80 & out_rimask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2499 = out_f_rivalid_230; // @[RegisterRouter.scala:87:24]
wire out_f_roready_230 = out_roready_1_80 & out_romask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2500 = out_f_roready_230; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_230 = out_wivalid_1_80 & out_wimask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2501 = out_f_wivalid_230; // @[RegisterRouter.scala:87:24]
wire out_f_woready_230 = out_woready_1_80 & out_womask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2502 = out_f_woready_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2503 = ~out_rimask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2504 = ~out_wimask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2505 = ~out_romask_230; // @[RegisterRouter.scala:87:24]
wire _out_T_2506 = ~out_womask_230; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2508 = _out_T_2507; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_185 = _out_T_2508; // @[RegisterRouter.scala:87:24]
wire out_rimask_231 = |_out_rimask_T_231; // @[RegisterRouter.scala:87:24]
wire out_wimask_231 = &_out_wimask_T_231; // @[RegisterRouter.scala:87:24]
wire out_romask_231 = |_out_romask_T_231; // @[RegisterRouter.scala:87:24]
wire out_womask_231 = &_out_womask_T_231; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_231 = out_rivalid_1_81 & out_rimask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2510 = out_f_rivalid_231; // @[RegisterRouter.scala:87:24]
wire out_f_roready_231 = out_roready_1_81 & out_romask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2511 = out_f_roready_231; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_231 = out_wivalid_1_81 & out_wimask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2512 = out_f_wivalid_231; // @[RegisterRouter.scala:87:24]
wire out_f_woready_231 = out_woready_1_81 & out_womask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2513 = out_f_woready_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2514 = ~out_rimask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2515 = ~out_wimask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2516 = ~out_romask_231; // @[RegisterRouter.scala:87:24]
wire _out_T_2517 = ~out_womask_231; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_185 = {programBufferMem_1, _out_prepend_T_185}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2518 = out_prepend_185; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2519 = _out_T_2518; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_186 = _out_T_2519; // @[RegisterRouter.scala:87:24]
wire out_rimask_232 = |_out_rimask_T_232; // @[RegisterRouter.scala:87:24]
wire out_wimask_232 = &_out_wimask_T_232; // @[RegisterRouter.scala:87:24]
wire out_romask_232 = |_out_romask_T_232; // @[RegisterRouter.scala:87:24]
wire out_womask_232 = &_out_womask_T_232; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_232 = out_rivalid_1_82 & out_rimask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2521 = out_f_rivalid_232; // @[RegisterRouter.scala:87:24]
wire out_f_roready_232 = out_roready_1_82 & out_romask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2522 = out_f_roready_232; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_232 = out_wivalid_1_82 & out_wimask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2523 = out_f_wivalid_232; // @[RegisterRouter.scala:87:24]
wire out_f_woready_232 = out_woready_1_82 & out_womask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2524 = out_f_woready_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2525 = ~out_rimask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2526 = ~out_wimask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2527 = ~out_romask_232; // @[RegisterRouter.scala:87:24]
wire _out_T_2528 = ~out_womask_232; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_186 = {programBufferMem_2, _out_prepend_T_186}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2529 = out_prepend_186; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2530 = _out_T_2529; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_187 = _out_T_2530; // @[RegisterRouter.scala:87:24]
wire out_rimask_233 = |_out_rimask_T_233; // @[RegisterRouter.scala:87:24]
wire out_wimask_233 = &_out_wimask_T_233; // @[RegisterRouter.scala:87:24]
wire out_romask_233 = |_out_romask_T_233; // @[RegisterRouter.scala:87:24]
wire out_womask_233 = &_out_womask_T_233; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_233 = out_rivalid_1_83 & out_rimask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2532 = out_f_rivalid_233; // @[RegisterRouter.scala:87:24]
wire out_f_roready_233 = out_roready_1_83 & out_romask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2533 = out_f_roready_233; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_233 = out_wivalid_1_83 & out_wimask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2534 = out_f_wivalid_233; // @[RegisterRouter.scala:87:24]
wire out_f_woready_233 = out_woready_1_83 & out_womask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2535 = out_f_woready_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2536 = ~out_rimask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2537 = ~out_wimask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2538 = ~out_romask_233; // @[RegisterRouter.scala:87:24]
wire _out_T_2539 = ~out_womask_233; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_187 = {programBufferMem_3, _out_prepend_T_187}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2540 = out_prepend_187; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2541 = _out_T_2540; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_188 = _out_T_2541; // @[RegisterRouter.scala:87:24]
wire out_rimask_234 = |_out_rimask_T_234; // @[RegisterRouter.scala:87:24]
wire out_wimask_234 = &_out_wimask_T_234; // @[RegisterRouter.scala:87:24]
wire out_romask_234 = |_out_romask_T_234; // @[RegisterRouter.scala:87:24]
wire out_womask_234 = &_out_womask_T_234; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_234 = out_rivalid_1_84 & out_rimask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2543 = out_f_rivalid_234; // @[RegisterRouter.scala:87:24]
wire out_f_roready_234 = out_roready_1_84 & out_romask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2544 = out_f_roready_234; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_234 = out_wivalid_1_84 & out_wimask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2545 = out_f_wivalid_234; // @[RegisterRouter.scala:87:24]
wire out_f_woready_234 = out_woready_1_84 & out_womask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2546 = out_f_woready_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2547 = ~out_rimask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2548 = ~out_wimask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2549 = ~out_romask_234; // @[RegisterRouter.scala:87:24]
wire _out_T_2550 = ~out_womask_234; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_188 = {programBufferMem_4, _out_prepend_T_188}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2551 = out_prepend_188; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2552 = _out_T_2551; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_189 = _out_T_2552; // @[RegisterRouter.scala:87:24]
wire out_rimask_235 = |_out_rimask_T_235; // @[RegisterRouter.scala:87:24]
wire out_wimask_235 = &_out_wimask_T_235; // @[RegisterRouter.scala:87:24]
wire out_romask_235 = |_out_romask_T_235; // @[RegisterRouter.scala:87:24]
wire out_womask_235 = &_out_womask_T_235; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_235 = out_rivalid_1_85 & out_rimask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2554 = out_f_rivalid_235; // @[RegisterRouter.scala:87:24]
wire out_f_roready_235 = out_roready_1_85 & out_romask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2555 = out_f_roready_235; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_235 = out_wivalid_1_85 & out_wimask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2556 = out_f_wivalid_235; // @[RegisterRouter.scala:87:24]
wire out_f_woready_235 = out_woready_1_85 & out_womask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2557 = out_f_woready_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2558 = ~out_rimask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2559 = ~out_wimask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2560 = ~out_romask_235; // @[RegisterRouter.scala:87:24]
wire _out_T_2561 = ~out_womask_235; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_189 = {programBufferMem_5, _out_prepend_T_189}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2562 = out_prepend_189; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2563 = _out_T_2562; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_190 = _out_T_2563; // @[RegisterRouter.scala:87:24]
wire out_rimask_236 = |_out_rimask_T_236; // @[RegisterRouter.scala:87:24]
wire out_wimask_236 = &_out_wimask_T_236; // @[RegisterRouter.scala:87:24]
wire out_romask_236 = |_out_romask_T_236; // @[RegisterRouter.scala:87:24]
wire out_womask_236 = &_out_womask_T_236; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_236 = out_rivalid_1_86 & out_rimask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2565 = out_f_rivalid_236; // @[RegisterRouter.scala:87:24]
wire out_f_roready_236 = out_roready_1_86 & out_romask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2566 = out_f_roready_236; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_236 = out_wivalid_1_86 & out_wimask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2567 = out_f_wivalid_236; // @[RegisterRouter.scala:87:24]
wire out_f_woready_236 = out_woready_1_86 & out_womask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2568 = out_f_woready_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2569 = ~out_rimask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2570 = ~out_wimask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2571 = ~out_romask_236; // @[RegisterRouter.scala:87:24]
wire _out_T_2572 = ~out_womask_236; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_190 = {programBufferMem_6, _out_prepend_T_190}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2573 = out_prepend_190; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2574 = _out_T_2573; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_191 = _out_T_2574; // @[RegisterRouter.scala:87:24]
wire out_rimask_237 = |_out_rimask_T_237; // @[RegisterRouter.scala:87:24]
wire out_wimask_237 = &_out_wimask_T_237; // @[RegisterRouter.scala:87:24]
wire out_romask_237 = |_out_romask_T_237; // @[RegisterRouter.scala:87:24]
wire out_womask_237 = &_out_womask_T_237; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_237 = out_rivalid_1_87 & out_rimask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2576 = out_f_rivalid_237; // @[RegisterRouter.scala:87:24]
wire out_f_roready_237 = out_roready_1_87 & out_romask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2577 = out_f_roready_237; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_237 = out_wivalid_1_87 & out_wimask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2578 = out_f_wivalid_237; // @[RegisterRouter.scala:87:24]
wire out_f_woready_237 = out_woready_1_87 & out_womask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2579 = out_f_woready_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2580 = ~out_rimask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2581 = ~out_wimask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2582 = ~out_romask_237; // @[RegisterRouter.scala:87:24]
wire _out_T_2583 = ~out_womask_237; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_191 = {programBufferMem_7, _out_prepend_T_191}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2584 = out_prepend_191; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2585 = _out_T_2584; // @[RegisterRouter.scala:87:24]
wire out_rimask_238 = |_out_rimask_T_238; // @[RegisterRouter.scala:87:24]
wire out_wimask_238 = &_out_wimask_T_238; // @[RegisterRouter.scala:87:24]
wire out_romask_238 = |_out_romask_T_238; // @[RegisterRouter.scala:87:24]
wire out_womask_238 = &_out_womask_T_238; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_238 = out_rivalid_1_88 & out_rimask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2587 = out_f_rivalid_238; // @[RegisterRouter.scala:87:24]
wire out_f_roready_238 = out_roready_1_88 & out_romask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2588 = out_f_roready_238; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_238 = out_wivalid_1_88 & out_wimask_238; // @[RegisterRouter.scala:87:24]
wire out_f_woready_238 = out_woready_1_88 & out_womask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2589 = ~out_rimask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2590 = ~out_wimask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2591 = ~out_romask_238; // @[RegisterRouter.scala:87:24]
wire _out_T_2592 = ~out_womask_238; // @[RegisterRouter.scala:87:24]
wire out_rimask_239 = |_out_rimask_T_239; // @[RegisterRouter.scala:87:24]
wire out_wimask_239 = &_out_wimask_T_239; // @[RegisterRouter.scala:87:24]
wire out_romask_239 = |_out_romask_T_239; // @[RegisterRouter.scala:87:24]
wire out_womask_239 = &_out_womask_T_239; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_239 = out_rivalid_1_89 & out_rimask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2596 = out_f_rivalid_239; // @[RegisterRouter.scala:87:24]
wire out_f_roready_239 = out_roready_1_89 & out_romask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2597 = out_f_roready_239; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_239 = out_wivalid_1_89 & out_wimask_239; // @[RegisterRouter.scala:87:24]
wire out_f_woready_239 = out_woready_1_89 & out_womask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2598 = ~out_rimask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2599 = ~out_wimask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2600 = ~out_romask_239; // @[RegisterRouter.scala:87:24]
wire _out_T_2601 = ~out_womask_239; // @[RegisterRouter.scala:87:24]
wire out_rimask_240 = |_out_rimask_T_240; // @[RegisterRouter.scala:87:24]
wire out_wimask_240 = &_out_wimask_T_240; // @[RegisterRouter.scala:87:24]
wire out_romask_240 = |_out_romask_T_240; // @[RegisterRouter.scala:87:24]
wire out_womask_240 = &_out_womask_T_240; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_240 = out_rivalid_1_90 & out_rimask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2605 = out_f_rivalid_240; // @[RegisterRouter.scala:87:24]
wire out_f_roready_240 = out_roready_1_90 & out_romask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2606 = out_f_roready_240; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_240 = out_wivalid_1_90 & out_wimask_240; // @[RegisterRouter.scala:87:24]
wire out_f_woready_240 = out_woready_1_90 & out_womask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2607 = ~out_rimask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2608 = ~out_wimask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2609 = ~out_romask_240; // @[RegisterRouter.scala:87:24]
wire _out_T_2610 = ~out_womask_240; // @[RegisterRouter.scala:87:24]
wire out_rimask_241 = |_out_rimask_T_241; // @[RegisterRouter.scala:87:24]
wire out_wimask_241 = &_out_wimask_T_241; // @[RegisterRouter.scala:87:24]
wire out_romask_241 = |_out_romask_T_241; // @[RegisterRouter.scala:87:24]
wire out_womask_241 = &_out_womask_T_241; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_241 = out_rivalid_1_91 & out_rimask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2614 = out_f_rivalid_241; // @[RegisterRouter.scala:87:24]
wire out_f_roready_241 = out_roready_1_91 & out_romask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2615 = out_f_roready_241; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_241 = out_wivalid_1_91 & out_wimask_241; // @[RegisterRouter.scala:87:24]
wire out_f_woready_241 = out_woready_1_91 & out_womask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2616 = ~out_rimask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2617 = ~out_wimask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2618 = ~out_romask_241; // @[RegisterRouter.scala:87:24]
wire _out_T_2619 = ~out_womask_241; // @[RegisterRouter.scala:87:24]
wire out_rimask_242 = |_out_rimask_T_242; // @[RegisterRouter.scala:87:24]
wire out_wimask_242 = &_out_wimask_T_242; // @[RegisterRouter.scala:87:24]
wire out_romask_242 = |_out_romask_T_242; // @[RegisterRouter.scala:87:24]
wire out_womask_242 = &_out_womask_T_242; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_242 = out_rivalid_1_92 & out_rimask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2623 = out_f_rivalid_242; // @[RegisterRouter.scala:87:24]
wire out_f_roready_242 = out_roready_1_92 & out_romask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2624 = out_f_roready_242; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_242 = out_wivalid_1_92 & out_wimask_242; // @[RegisterRouter.scala:87:24]
wire out_f_woready_242 = out_woready_1_92 & out_womask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2625 = ~out_rimask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2626 = ~out_wimask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2627 = ~out_romask_242; // @[RegisterRouter.scala:87:24]
wire _out_T_2628 = ~out_womask_242; // @[RegisterRouter.scala:87:24]
wire out_rimask_243 = |_out_rimask_T_243; // @[RegisterRouter.scala:87:24]
wire out_wimask_243 = &_out_wimask_T_243; // @[RegisterRouter.scala:87:24]
wire out_romask_243 = |_out_romask_T_243; // @[RegisterRouter.scala:87:24]
wire out_womask_243 = &_out_womask_T_243; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_243 = out_rivalid_1_93 & out_rimask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2632 = out_f_rivalid_243; // @[RegisterRouter.scala:87:24]
wire out_f_roready_243 = out_roready_1_93 & out_romask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2633 = out_f_roready_243; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_243 = out_wivalid_1_93 & out_wimask_243; // @[RegisterRouter.scala:87:24]
wire out_f_woready_243 = out_woready_1_93 & out_womask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2634 = ~out_rimask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2635 = ~out_wimask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2636 = ~out_romask_243; // @[RegisterRouter.scala:87:24]
wire _out_T_2637 = ~out_womask_243; // @[RegisterRouter.scala:87:24]
wire out_rimask_244 = |_out_rimask_T_244; // @[RegisterRouter.scala:87:24]
wire out_wimask_244 = &_out_wimask_T_244; // @[RegisterRouter.scala:87:24]
wire out_romask_244 = |_out_romask_T_244; // @[RegisterRouter.scala:87:24]
wire out_womask_244 = &_out_womask_T_244; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_244 = out_rivalid_1_94 & out_rimask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2641 = out_f_rivalid_244; // @[RegisterRouter.scala:87:24]
wire out_f_roready_244 = out_roready_1_94 & out_romask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2642 = out_f_roready_244; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_244 = out_wivalid_1_94 & out_wimask_244; // @[RegisterRouter.scala:87:24]
wire out_f_woready_244 = out_woready_1_94 & out_womask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2643 = ~out_rimask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2644 = ~out_wimask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2645 = ~out_romask_244; // @[RegisterRouter.scala:87:24]
wire _out_T_2646 = ~out_womask_244; // @[RegisterRouter.scala:87:24]
wire out_rimask_245 = |_out_rimask_T_245; // @[RegisterRouter.scala:87:24]
wire out_wimask_245 = &_out_wimask_T_245; // @[RegisterRouter.scala:87:24]
wire out_romask_245 = |_out_romask_T_245; // @[RegisterRouter.scala:87:24]
wire out_womask_245 = &_out_womask_T_245; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_245 = out_rivalid_1_95 & out_rimask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2650 = out_f_rivalid_245; // @[RegisterRouter.scala:87:24]
wire out_f_roready_245 = out_roready_1_95 & out_romask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2651 = out_f_roready_245; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_245 = out_wivalid_1_95 & out_wimask_245; // @[RegisterRouter.scala:87:24]
wire out_f_woready_245 = out_woready_1_95 & out_womask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2652 = ~out_rimask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2653 = ~out_wimask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2654 = ~out_romask_245; // @[RegisterRouter.scala:87:24]
wire _out_T_2655 = ~out_womask_245; // @[RegisterRouter.scala:87:24]
wire out_rimask_246 = |_out_rimask_T_246; // @[RegisterRouter.scala:87:24]
wire out_wimask_246 = &_out_wimask_T_246; // @[RegisterRouter.scala:87:24]
wire out_romask_246 = |_out_romask_T_246; // @[RegisterRouter.scala:87:24]
wire out_womask_246 = &_out_womask_T_246; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_246 = out_rivalid_1_96 & out_rimask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2659 = out_f_rivalid_246; // @[RegisterRouter.scala:87:24]
wire out_f_roready_246 = out_roready_1_96 & out_romask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2660 = out_f_roready_246; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_246 = out_wivalid_1_96 & out_wimask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2661 = out_f_wivalid_246; // @[RegisterRouter.scala:87:24]
wire out_f_woready_246 = out_woready_1_96 & out_womask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2662 = out_f_woready_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2663 = ~out_rimask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2664 = ~out_wimask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2665 = ~out_romask_246; // @[RegisterRouter.scala:87:24]
wire _out_T_2666 = ~out_womask_246; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2668 = _out_T_2667; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_199 = _out_T_2668; // @[RegisterRouter.scala:87:24]
wire out_rimask_247 = |_out_rimask_T_247; // @[RegisterRouter.scala:87:24]
wire out_wimask_247 = &_out_wimask_T_247; // @[RegisterRouter.scala:87:24]
wire out_romask_247 = |_out_romask_T_247; // @[RegisterRouter.scala:87:24]
wire out_womask_247 = &_out_womask_T_247; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_247 = out_rivalid_1_97 & out_rimask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2670 = out_f_rivalid_247; // @[RegisterRouter.scala:87:24]
wire out_f_roready_247 = out_roready_1_97 & out_romask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2671 = out_f_roready_247; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_247 = out_wivalid_1_97 & out_wimask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2672 = out_f_wivalid_247; // @[RegisterRouter.scala:87:24]
wire out_f_woready_247 = out_woready_1_97 & out_womask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2673 = out_f_woready_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2674 = ~out_rimask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2675 = ~out_wimask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2676 = ~out_romask_247; // @[RegisterRouter.scala:87:24]
wire _out_T_2677 = ~out_womask_247; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_199 = {programBufferMem_25, _out_prepend_T_199}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2678 = out_prepend_199; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2679 = _out_T_2678; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_200 = _out_T_2679; // @[RegisterRouter.scala:87:24]
wire out_rimask_248 = |_out_rimask_T_248; // @[RegisterRouter.scala:87:24]
wire out_wimask_248 = &_out_wimask_T_248; // @[RegisterRouter.scala:87:24]
wire out_romask_248 = |_out_romask_T_248; // @[RegisterRouter.scala:87:24]
wire out_womask_248 = &_out_womask_T_248; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_248 = out_rivalid_1_98 & out_rimask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2681 = out_f_rivalid_248; // @[RegisterRouter.scala:87:24]
wire out_f_roready_248 = out_roready_1_98 & out_romask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2682 = out_f_roready_248; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_248 = out_wivalid_1_98 & out_wimask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2683 = out_f_wivalid_248; // @[RegisterRouter.scala:87:24]
wire out_f_woready_248 = out_woready_1_98 & out_womask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2684 = out_f_woready_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2685 = ~out_rimask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2686 = ~out_wimask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2687 = ~out_romask_248; // @[RegisterRouter.scala:87:24]
wire _out_T_2688 = ~out_womask_248; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_200 = {programBufferMem_26, _out_prepend_T_200}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2689 = out_prepend_200; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2690 = _out_T_2689; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_201 = _out_T_2690; // @[RegisterRouter.scala:87:24]
wire out_rimask_249 = |_out_rimask_T_249; // @[RegisterRouter.scala:87:24]
wire out_wimask_249 = &_out_wimask_T_249; // @[RegisterRouter.scala:87:24]
wire out_romask_249 = |_out_romask_T_249; // @[RegisterRouter.scala:87:24]
wire out_womask_249 = &_out_womask_T_249; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_249 = out_rivalid_1_99 & out_rimask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2692 = out_f_rivalid_249; // @[RegisterRouter.scala:87:24]
wire out_f_roready_249 = out_roready_1_99 & out_romask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2693 = out_f_roready_249; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_249 = out_wivalid_1_99 & out_wimask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2694 = out_f_wivalid_249; // @[RegisterRouter.scala:87:24]
wire out_f_woready_249 = out_woready_1_99 & out_womask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2695 = out_f_woready_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2696 = ~out_rimask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2697 = ~out_wimask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2698 = ~out_romask_249; // @[RegisterRouter.scala:87:24]
wire _out_T_2699 = ~out_womask_249; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_201 = {programBufferMem_27, _out_prepend_T_201}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2700 = out_prepend_201; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2701 = _out_T_2700; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_202 = _out_T_2701; // @[RegisterRouter.scala:87:24]
wire out_rimask_250 = |_out_rimask_T_250; // @[RegisterRouter.scala:87:24]
wire out_wimask_250 = &_out_wimask_T_250; // @[RegisterRouter.scala:87:24]
wire out_romask_250 = |_out_romask_T_250; // @[RegisterRouter.scala:87:24]
wire out_womask_250 = &_out_womask_T_250; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_250 = out_rivalid_1_100 & out_rimask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2703 = out_f_rivalid_250; // @[RegisterRouter.scala:87:24]
wire out_f_roready_250 = out_roready_1_100 & out_romask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2704 = out_f_roready_250; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_250 = out_wivalid_1_100 & out_wimask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2705 = out_f_wivalid_250; // @[RegisterRouter.scala:87:24]
wire out_f_woready_250 = out_woready_1_100 & out_womask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2706 = out_f_woready_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2707 = ~out_rimask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2708 = ~out_wimask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2709 = ~out_romask_250; // @[RegisterRouter.scala:87:24]
wire _out_T_2710 = ~out_womask_250; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_202 = {programBufferMem_28, _out_prepend_T_202}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2711 = out_prepend_202; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2712 = _out_T_2711; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_203 = _out_T_2712; // @[RegisterRouter.scala:87:24]
wire out_rimask_251 = |_out_rimask_T_251; // @[RegisterRouter.scala:87:24]
wire out_wimask_251 = &_out_wimask_T_251; // @[RegisterRouter.scala:87:24]
wire out_romask_251 = |_out_romask_T_251; // @[RegisterRouter.scala:87:24]
wire out_womask_251 = &_out_womask_T_251; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_251 = out_rivalid_1_101 & out_rimask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2714 = out_f_rivalid_251; // @[RegisterRouter.scala:87:24]
wire out_f_roready_251 = out_roready_1_101 & out_romask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2715 = out_f_roready_251; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_251 = out_wivalid_1_101 & out_wimask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2716 = out_f_wivalid_251; // @[RegisterRouter.scala:87:24]
wire out_f_woready_251 = out_woready_1_101 & out_womask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2717 = out_f_woready_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2718 = ~out_rimask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2719 = ~out_wimask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2720 = ~out_romask_251; // @[RegisterRouter.scala:87:24]
wire _out_T_2721 = ~out_womask_251; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_203 = {programBufferMem_29, _out_prepend_T_203}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2722 = out_prepend_203; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2723 = _out_T_2722; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_204 = _out_T_2723; // @[RegisterRouter.scala:87:24]
wire out_rimask_252 = |_out_rimask_T_252; // @[RegisterRouter.scala:87:24]
wire out_wimask_252 = &_out_wimask_T_252; // @[RegisterRouter.scala:87:24]
wire out_romask_252 = |_out_romask_T_252; // @[RegisterRouter.scala:87:24]
wire out_womask_252 = &_out_womask_T_252; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_252 = out_rivalid_1_102 & out_rimask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2725 = out_f_rivalid_252; // @[RegisterRouter.scala:87:24]
wire out_f_roready_252 = out_roready_1_102 & out_romask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2726 = out_f_roready_252; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_252 = out_wivalid_1_102 & out_wimask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2727 = out_f_wivalid_252; // @[RegisterRouter.scala:87:24]
wire out_f_woready_252 = out_woready_1_102 & out_womask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2728 = out_f_woready_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2729 = ~out_rimask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2730 = ~out_wimask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2731 = ~out_romask_252; // @[RegisterRouter.scala:87:24]
wire _out_T_2732 = ~out_womask_252; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_204 = {programBufferMem_30, _out_prepend_T_204}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2733 = out_prepend_204; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2734 = _out_T_2733; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_205 = _out_T_2734; // @[RegisterRouter.scala:87:24]
wire out_rimask_253 = |_out_rimask_T_253; // @[RegisterRouter.scala:87:24]
wire out_wimask_253 = &_out_wimask_T_253; // @[RegisterRouter.scala:87:24]
wire out_romask_253 = |_out_romask_T_253; // @[RegisterRouter.scala:87:24]
wire out_womask_253 = &_out_womask_T_253; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_253 = out_rivalid_1_103 & out_rimask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2736 = out_f_rivalid_253; // @[RegisterRouter.scala:87:24]
wire out_f_roready_253 = out_roready_1_103 & out_romask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2737 = out_f_roready_253; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_253 = out_wivalid_1_103 & out_wimask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2738 = out_f_wivalid_253; // @[RegisterRouter.scala:87:24]
wire out_f_woready_253 = out_woready_1_103 & out_womask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2739 = out_f_woready_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2740 = ~out_rimask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2741 = ~out_wimask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2742 = ~out_romask_253; // @[RegisterRouter.scala:87:24]
wire _out_T_2743 = ~out_womask_253; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_205 = {programBufferMem_31, _out_prepend_T_205}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2744 = out_prepend_205; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2745 = _out_T_2744; // @[RegisterRouter.scala:87:24]
wire out_rimask_254 = |_out_rimask_T_254; // @[RegisterRouter.scala:87:24]
wire out_wimask_254 = &_out_wimask_T_254; // @[RegisterRouter.scala:87:24]
wire out_romask_254 = |_out_romask_T_254; // @[RegisterRouter.scala:87:24]
wire out_womask_254 = &_out_womask_T_254; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_254 = out_rivalid_1_104 & out_rimask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2747 = out_f_rivalid_254; // @[RegisterRouter.scala:87:24]
wire out_f_roready_254 = out_roready_1_104 & out_romask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2748 = out_f_roready_254; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_254 = out_wivalid_1_104 & out_wimask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2749 = out_f_wivalid_254; // @[RegisterRouter.scala:87:24]
wire out_f_woready_254 = out_woready_1_104 & out_womask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2750 = out_f_woready_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2751 = ~out_rimask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2752 = ~out_wimask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2753 = ~out_romask_254; // @[RegisterRouter.scala:87:24]
wire _out_T_2754 = ~out_womask_254; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2756 = _out_T_2755; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_206 = _out_T_2756; // @[RegisterRouter.scala:87:24]
wire out_rimask_255 = |_out_rimask_T_255; // @[RegisterRouter.scala:87:24]
wire out_wimask_255 = &_out_wimask_T_255; // @[RegisterRouter.scala:87:24]
wire out_romask_255 = |_out_romask_T_255; // @[RegisterRouter.scala:87:24]
wire out_womask_255 = &_out_womask_T_255; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_255 = out_rivalid_1_105 & out_rimask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2758 = out_f_rivalid_255; // @[RegisterRouter.scala:87:24]
wire out_f_roready_255 = out_roready_1_105 & out_romask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2759 = out_f_roready_255; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_255 = out_wivalid_1_105 & out_wimask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2760 = out_f_wivalid_255; // @[RegisterRouter.scala:87:24]
wire out_f_woready_255 = out_woready_1_105 & out_womask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2761 = out_f_woready_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2762 = ~out_rimask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2763 = ~out_wimask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2764 = ~out_romask_255; // @[RegisterRouter.scala:87:24]
wire _out_T_2765 = ~out_womask_255; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_206 = {programBufferMem_57, _out_prepend_T_206}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2766 = out_prepend_206; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2767 = _out_T_2766; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_207 = _out_T_2767; // @[RegisterRouter.scala:87:24]
wire out_rimask_256 = |_out_rimask_T_256; // @[RegisterRouter.scala:87:24]
wire out_wimask_256 = &_out_wimask_T_256; // @[RegisterRouter.scala:87:24]
wire out_romask_256 = |_out_romask_T_256; // @[RegisterRouter.scala:87:24]
wire out_womask_256 = &_out_womask_T_256; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_256 = out_rivalid_1_106 & out_rimask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2769 = out_f_rivalid_256; // @[RegisterRouter.scala:87:24]
wire out_f_roready_256 = out_roready_1_106 & out_romask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2770 = out_f_roready_256; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_256 = out_wivalid_1_106 & out_wimask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2771 = out_f_wivalid_256; // @[RegisterRouter.scala:87:24]
wire out_f_woready_256 = out_woready_1_106 & out_womask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2772 = out_f_woready_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2773 = ~out_rimask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2774 = ~out_wimask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2775 = ~out_romask_256; // @[RegisterRouter.scala:87:24]
wire _out_T_2776 = ~out_womask_256; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_207 = {programBufferMem_58, _out_prepend_T_207}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2777 = out_prepend_207; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2778 = _out_T_2777; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_208 = _out_T_2778; // @[RegisterRouter.scala:87:24]
wire out_rimask_257 = |_out_rimask_T_257; // @[RegisterRouter.scala:87:24]
wire out_wimask_257 = &_out_wimask_T_257; // @[RegisterRouter.scala:87:24]
wire out_romask_257 = |_out_romask_T_257; // @[RegisterRouter.scala:87:24]
wire out_womask_257 = &_out_womask_T_257; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_257 = out_rivalid_1_107 & out_rimask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2780 = out_f_rivalid_257; // @[RegisterRouter.scala:87:24]
wire out_f_roready_257 = out_roready_1_107 & out_romask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2781 = out_f_roready_257; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_257 = out_wivalid_1_107 & out_wimask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2782 = out_f_wivalid_257; // @[RegisterRouter.scala:87:24]
wire out_f_woready_257 = out_woready_1_107 & out_womask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2783 = out_f_woready_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2784 = ~out_rimask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2785 = ~out_wimask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2786 = ~out_romask_257; // @[RegisterRouter.scala:87:24]
wire _out_T_2787 = ~out_womask_257; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_208 = {programBufferMem_59, _out_prepend_T_208}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2788 = out_prepend_208; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2789 = _out_T_2788; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_209 = _out_T_2789; // @[RegisterRouter.scala:87:24]
wire out_rimask_258 = |_out_rimask_T_258; // @[RegisterRouter.scala:87:24]
wire out_wimask_258 = &_out_wimask_T_258; // @[RegisterRouter.scala:87:24]
wire out_romask_258 = |_out_romask_T_258; // @[RegisterRouter.scala:87:24]
wire out_womask_258 = &_out_womask_T_258; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_258 = out_rivalid_1_108 & out_rimask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2791 = out_f_rivalid_258; // @[RegisterRouter.scala:87:24]
wire out_f_roready_258 = out_roready_1_108 & out_romask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2792 = out_f_roready_258; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_258 = out_wivalid_1_108 & out_wimask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2793 = out_f_wivalid_258; // @[RegisterRouter.scala:87:24]
wire out_f_woready_258 = out_woready_1_108 & out_womask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2794 = out_f_woready_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2795 = ~out_rimask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2796 = ~out_wimask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2797 = ~out_romask_258; // @[RegisterRouter.scala:87:24]
wire _out_T_2798 = ~out_womask_258; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_209 = {programBufferMem_60, _out_prepend_T_209}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2799 = out_prepend_209; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2800 = _out_T_2799; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_210 = _out_T_2800; // @[RegisterRouter.scala:87:24]
wire out_rimask_259 = |_out_rimask_T_259; // @[RegisterRouter.scala:87:24]
wire out_wimask_259 = &_out_wimask_T_259; // @[RegisterRouter.scala:87:24]
wire out_romask_259 = |_out_romask_T_259; // @[RegisterRouter.scala:87:24]
wire out_womask_259 = &_out_womask_T_259; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_259 = out_rivalid_1_109 & out_rimask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2802 = out_f_rivalid_259; // @[RegisterRouter.scala:87:24]
wire out_f_roready_259 = out_roready_1_109 & out_romask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2803 = out_f_roready_259; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_259 = out_wivalid_1_109 & out_wimask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2804 = out_f_wivalid_259; // @[RegisterRouter.scala:87:24]
wire out_f_woready_259 = out_woready_1_109 & out_womask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2805 = out_f_woready_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2806 = ~out_rimask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2807 = ~out_wimask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2808 = ~out_romask_259; // @[RegisterRouter.scala:87:24]
wire _out_T_2809 = ~out_womask_259; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_210 = {programBufferMem_61, _out_prepend_T_210}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2810 = out_prepend_210; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2811 = _out_T_2810; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_211 = _out_T_2811; // @[RegisterRouter.scala:87:24]
wire out_rimask_260 = |_out_rimask_T_260; // @[RegisterRouter.scala:87:24]
wire out_wimask_260 = &_out_wimask_T_260; // @[RegisterRouter.scala:87:24]
wire out_romask_260 = |_out_romask_T_260; // @[RegisterRouter.scala:87:24]
wire out_womask_260 = &_out_womask_T_260; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_260 = out_rivalid_1_110 & out_rimask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2813 = out_f_rivalid_260; // @[RegisterRouter.scala:87:24]
wire out_f_roready_260 = out_roready_1_110 & out_romask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2814 = out_f_roready_260; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_260 = out_wivalid_1_110 & out_wimask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2815 = out_f_wivalid_260; // @[RegisterRouter.scala:87:24]
wire out_f_woready_260 = out_woready_1_110 & out_womask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2816 = out_f_woready_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2817 = ~out_rimask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2818 = ~out_wimask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2819 = ~out_romask_260; // @[RegisterRouter.scala:87:24]
wire _out_T_2820 = ~out_womask_260; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_211 = {programBufferMem_62, _out_prepend_T_211}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2821 = out_prepend_211; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_2822 = _out_T_2821; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_212 = _out_T_2822; // @[RegisterRouter.scala:87:24]
wire out_rimask_261 = |_out_rimask_T_261; // @[RegisterRouter.scala:87:24]
wire out_wimask_261 = &_out_wimask_T_261; // @[RegisterRouter.scala:87:24]
wire out_romask_261 = |_out_romask_T_261; // @[RegisterRouter.scala:87:24]
wire out_womask_261 = &_out_womask_T_261; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_261 = out_rivalid_1_111 & out_rimask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2824 = out_f_rivalid_261; // @[RegisterRouter.scala:87:24]
wire out_f_roready_261 = out_roready_1_111 & out_romask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2825 = out_f_roready_261; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_261 = out_wivalid_1_111 & out_wimask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2826 = out_f_wivalid_261; // @[RegisterRouter.scala:87:24]
wire out_f_woready_261 = out_woready_1_111 & out_womask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2827 = out_f_woready_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2828 = ~out_rimask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2829 = ~out_wimask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2830 = ~out_romask_261; // @[RegisterRouter.scala:87:24]
wire _out_T_2831 = ~out_womask_261; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_212 = {programBufferMem_63, _out_prepend_T_212}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2832 = out_prepend_212; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_2833 = _out_T_2832; // @[RegisterRouter.scala:87:24]
wire out_rimask_262 = |_out_rimask_T_262; // @[RegisterRouter.scala:87:24]
wire out_wimask_262 = &_out_wimask_T_262; // @[RegisterRouter.scala:87:24]
wire out_romask_262 = |_out_romask_T_262; // @[RegisterRouter.scala:87:24]
wire out_womask_262 = &_out_womask_T_262; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_262 = out_rivalid_1_112 & out_rimask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2835 = out_f_rivalid_262; // @[RegisterRouter.scala:87:24]
wire out_f_roready_262 = out_roready_1_112 & out_romask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2836 = out_f_roready_262; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_262 = out_wivalid_1_112 & out_wimask_262; // @[RegisterRouter.scala:87:24]
wire out_f_woready_262 = out_woready_1_112 & out_womask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2837 = ~out_rimask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2838 = ~out_wimask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2839 = ~out_romask_262; // @[RegisterRouter.scala:87:24]
wire _out_T_2840 = ~out_womask_262; // @[RegisterRouter.scala:87:24]
wire out_rimask_263 = |_out_rimask_T_263; // @[RegisterRouter.scala:87:24]
wire out_wimask_263 = &_out_wimask_T_263; // @[RegisterRouter.scala:87:24]
wire out_romask_263 = |_out_romask_T_263; // @[RegisterRouter.scala:87:24]
wire out_womask_263 = &_out_womask_T_263; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_263 = out_rivalid_1_113 & out_rimask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2844 = out_f_rivalid_263; // @[RegisterRouter.scala:87:24]
wire out_f_roready_263 = out_roready_1_113 & out_romask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2845 = out_f_roready_263; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_263 = out_wivalid_1_113 & out_wimask_263; // @[RegisterRouter.scala:87:24]
wire out_f_woready_263 = out_woready_1_113 & out_womask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2846 = ~out_rimask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2847 = ~out_wimask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2848 = ~out_romask_263; // @[RegisterRouter.scala:87:24]
wire _out_T_2849 = ~out_womask_263; // @[RegisterRouter.scala:87:24]
wire out_rimask_264 = |_out_rimask_T_264; // @[RegisterRouter.scala:87:24]
wire out_wimask_264 = &_out_wimask_T_264; // @[RegisterRouter.scala:87:24]
wire out_romask_264 = |_out_romask_T_264; // @[RegisterRouter.scala:87:24]
wire out_womask_264 = &_out_womask_T_264; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_264 = out_rivalid_1_114 & out_rimask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_2853 = out_f_rivalid_264; // @[RegisterRouter.scala:87:24]
wire out_f_roready_264 = out_roready_1_114 & out_romask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_2854 = out_f_roready_264; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_264 = out_wivalid_1_114 & out_wimask_264; // @[RegisterRouter.scala:87:24]
wire out_f_woready_264 = out_woready_1_114 & out_womask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_2855 = ~out_rimask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_2856 = ~out_wimask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_2857 = ~out_romask_264; // @[RegisterRouter.scala:87:24]
wire _out_T_2858 = ~out_womask_264; // @[RegisterRouter.scala:87:24]
wire out_rimask_265 = |_out_rimask_T_265; // @[RegisterRouter.scala:87:24]
wire out_wimask_265 = &_out_wimask_T_265; // @[RegisterRouter.scala:87:24]
wire out_romask_265 = |_out_romask_T_265; // @[RegisterRouter.scala:87:24]
wire out_womask_265 = &_out_womask_T_265; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_265 = out_rivalid_1_115 & out_rimask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_2862 = out_f_rivalid_265; // @[RegisterRouter.scala:87:24]
wire out_f_roready_265 = out_roready_1_115 & out_romask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_2863 = out_f_roready_265; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_265 = out_wivalid_1_115 & out_wimask_265; // @[RegisterRouter.scala:87:24]
wire out_f_woready_265 = out_woready_1_115 & out_womask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_2864 = ~out_rimask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_2865 = ~out_wimask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_2866 = ~out_romask_265; // @[RegisterRouter.scala:87:24]
wire _out_T_2867 = ~out_womask_265; // @[RegisterRouter.scala:87:24]
wire out_rimask_266 = |_out_rimask_T_266; // @[RegisterRouter.scala:87:24]
wire out_wimask_266 = &_out_wimask_T_266; // @[RegisterRouter.scala:87:24]
wire out_romask_266 = |_out_romask_T_266; // @[RegisterRouter.scala:87:24]
wire out_womask_266 = &_out_womask_T_266; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_266 = out_rivalid_1_116 & out_rimask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_2871 = out_f_rivalid_266; // @[RegisterRouter.scala:87:24]
wire out_f_roready_266 = out_roready_1_116 & out_romask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_2872 = out_f_roready_266; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_266 = out_wivalid_1_116 & out_wimask_266; // @[RegisterRouter.scala:87:24]
wire out_f_woready_266 = out_woready_1_116 & out_womask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_2873 = ~out_rimask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_2874 = ~out_wimask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_2875 = ~out_romask_266; // @[RegisterRouter.scala:87:24]
wire _out_T_2876 = ~out_womask_266; // @[RegisterRouter.scala:87:24]
wire out_rimask_267 = |_out_rimask_T_267; // @[RegisterRouter.scala:87:24]
wire out_wimask_267 = &_out_wimask_T_267; // @[RegisterRouter.scala:87:24]
wire out_romask_267 = |_out_romask_T_267; // @[RegisterRouter.scala:87:24]
wire out_womask_267 = &_out_womask_T_267; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_267 = out_rivalid_1_117 & out_rimask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_2880 = out_f_rivalid_267; // @[RegisterRouter.scala:87:24]
wire out_f_roready_267 = out_roready_1_117 & out_romask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_2881 = out_f_roready_267; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_267 = out_wivalid_1_117 & out_wimask_267; // @[RegisterRouter.scala:87:24]
wire out_f_woready_267 = out_woready_1_117 & out_womask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_2882 = ~out_rimask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_2883 = ~out_wimask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_2884 = ~out_romask_267; // @[RegisterRouter.scala:87:24]
wire _out_T_2885 = ~out_womask_267; // @[RegisterRouter.scala:87:24]
wire out_rimask_268 = |_out_rimask_T_268; // @[RegisterRouter.scala:87:24]
wire out_wimask_268 = &_out_wimask_T_268; // @[RegisterRouter.scala:87:24]
wire out_romask_268 = |_out_romask_T_268; // @[RegisterRouter.scala:87:24]
wire out_womask_268 = &_out_womask_T_268; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_268 = out_rivalid_1_118 & out_rimask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_2889 = out_f_rivalid_268; // @[RegisterRouter.scala:87:24]
wire out_f_roready_268 = out_roready_1_118 & out_romask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_2890 = out_f_roready_268; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_268 = out_wivalid_1_118 & out_wimask_268; // @[RegisterRouter.scala:87:24]
wire out_f_woready_268 = out_woready_1_118 & out_womask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_2891 = ~out_rimask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_2892 = ~out_wimask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_2893 = ~out_romask_268; // @[RegisterRouter.scala:87:24]
wire _out_T_2894 = ~out_womask_268; // @[RegisterRouter.scala:87:24]
wire out_rimask_269 = |_out_rimask_T_269; // @[RegisterRouter.scala:87:24]
wire out_wimask_269 = &_out_wimask_T_269; // @[RegisterRouter.scala:87:24]
wire out_romask_269 = |_out_romask_T_269; // @[RegisterRouter.scala:87:24]
wire out_womask_269 = &_out_womask_T_269; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_269 = out_rivalid_1_119 & out_rimask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_2898 = out_f_rivalid_269; // @[RegisterRouter.scala:87:24]
wire out_f_roready_269 = out_roready_1_119 & out_romask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_2899 = out_f_roready_269; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_269 = out_wivalid_1_119 & out_wimask_269; // @[RegisterRouter.scala:87:24]
wire out_f_woready_269 = out_woready_1_119 & out_womask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_2900 = ~out_rimask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_2901 = ~out_wimask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_2902 = ~out_romask_269; // @[RegisterRouter.scala:87:24]
wire _out_T_2903 = ~out_womask_269; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_rimask_T_270 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_wimask_T_270 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_rimask_T_309 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_wimask_T_309 = out_frontMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_270 = |_out_rimask_T_270; // @[RegisterRouter.scala:87:24]
wire out_wimask_270 = &_out_wimask_T_270; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_romask_T_270 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_womask_T_270 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_romask_T_309 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_womask_T_309 = out_backMask_1[9:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_270 = |_out_romask_T_270; // @[RegisterRouter.scala:87:24]
wire out_womask_270 = &_out_womask_T_270; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_270 = out_rivalid_1_120 & out_rimask_270; // @[RegisterRouter.scala:87:24]
wire out_f_roready_270 = out_roready_1_120 & out_romask_270; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_270 = out_wivalid_1_120 & out_wimask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_2907 = out_f_wivalid_270; // @[RegisterRouter.scala:87:24]
assign out_f_woready_270 = out_woready_1_120 & out_womask_270; // @[RegisterRouter.scala:87:24]
assign hartResumingWrEn = out_f_woready_270; // @[RegisterRouter.scala:87:24]
wire _out_T_2908 = out_f_woready_270; // @[RegisterRouter.scala:87:24]
assign _out_T_2906 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24]
assign _out_T_3289 = out_front_1_bits_data[9:0]; // @[RegisterRouter.scala:87:24]
assign hartResumingId = _out_T_2906; // @[RegisterRouter.scala:87:24]
wire _out_T_2909 = ~out_rimask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_2910 = ~out_wimask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_2911 = ~out_romask_270; // @[RegisterRouter.scala:87:24]
wire _out_T_2912 = ~out_womask_270; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_rimask_T_271 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_wimask_T_271 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_rimask_T_310 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_wimask_T_310 = out_frontMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_271 = |_out_rimask_T_271; // @[RegisterRouter.scala:87:24]
wire out_wimask_271 = &_out_wimask_T_271; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_romask_T_271 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_womask_T_271 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_romask_T_310 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire [9:0] _out_womask_T_310 = out_backMask_1[41:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_271 = |_out_romask_T_271; // @[RegisterRouter.scala:87:24]
wire out_womask_271 = &_out_womask_T_271; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_271 = out_rivalid_1_121 & out_rimask_271; // @[RegisterRouter.scala:87:24]
wire out_f_roready_271 = out_roready_1_121 & out_romask_271; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_271 = out_wivalid_1_121 & out_wimask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_2916 = out_f_wivalid_271; // @[RegisterRouter.scala:87:24]
assign out_f_woready_271 = out_woready_1_121 & out_womask_271; // @[RegisterRouter.scala:87:24]
assign hartExceptionWrEn = out_f_woready_271; // @[RegisterRouter.scala:87:24]
wire _out_T_2917 = out_f_woready_271; // @[RegisterRouter.scala:87:24]
assign _out_T_2915 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24]
assign _out_T_3298 = out_front_1_bits_data[41:32]; // @[RegisterRouter.scala:87:24]
assign hartExceptionId = _out_T_2915; // @[RegisterRouter.scala:87:24]
wire _out_T_2918 = ~out_rimask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_2919 = ~out_wimask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_2920 = ~out_romask_271; // @[RegisterRouter.scala:87:24]
wire _out_T_2921 = ~out_womask_271; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_272 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_272 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_319 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_319 = out_frontMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_272 = |_out_rimask_T_272; // @[RegisterRouter.scala:87:24]
wire out_wimask_272 = &_out_wimask_T_272; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_272 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_272 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_319 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_319 = out_backMask_1[31:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_272 = |_out_romask_T_272; // @[RegisterRouter.scala:87:24]
wire out_womask_272 = &_out_womask_T_272; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_272 = out_rivalid_1_122 & out_rimask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_2925 = out_f_rivalid_272; // @[RegisterRouter.scala:87:24]
wire out_f_roready_272 = out_roready_1_122 & out_romask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_2926 = out_f_roready_272; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_272 = out_wivalid_1_122 & out_wimask_272; // @[RegisterRouter.scala:87:24]
wire out_f_woready_272 = out_woready_1_122 & out_womask_272; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2924 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3379 = out_front_1_bits_data[31:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_2927 = ~out_rimask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_2928 = ~out_wimask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_2929 = ~out_romask_272; // @[RegisterRouter.scala:87:24]
wire _out_T_2930 = ~out_womask_272; // @[RegisterRouter.scala:87:24]
wire out_rimask_273 = |_out_rimask_T_273; // @[RegisterRouter.scala:87:24]
wire out_wimask_273 = &_out_wimask_T_273; // @[RegisterRouter.scala:87:24]
wire out_romask_273 = |_out_romask_T_273; // @[RegisterRouter.scala:87:24]
wire out_womask_273 = &_out_womask_T_273; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_273 = out_rivalid_1_123 & out_rimask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_2934 = out_f_rivalid_273; // @[RegisterRouter.scala:87:24]
wire out_f_roready_273 = out_roready_1_123 & out_romask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_2935 = out_f_roready_273; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_273 = out_wivalid_1_123 & out_wimask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_2936 = out_f_wivalid_273; // @[RegisterRouter.scala:87:24]
wire out_f_woready_273 = out_woready_1_123 & out_womask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_2937 = out_f_woready_273; // @[RegisterRouter.scala:87:24]
wire _out_T_2938 = ~out_rimask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_2939 = ~out_wimask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_2940 = ~out_romask_273; // @[RegisterRouter.scala:87:24]
wire _out_T_2941 = ~out_womask_273; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2943 = _out_T_2942; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_221 = _out_T_2943; // @[RegisterRouter.scala:87:24]
wire out_rimask_274 = |_out_rimask_T_274; // @[RegisterRouter.scala:87:24]
wire out_wimask_274 = &_out_wimask_T_274; // @[RegisterRouter.scala:87:24]
wire out_romask_274 = |_out_romask_T_274; // @[RegisterRouter.scala:87:24]
wire out_womask_274 = &_out_womask_T_274; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_274 = out_rivalid_1_124 & out_rimask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_2945 = out_f_rivalid_274; // @[RegisterRouter.scala:87:24]
wire out_f_roready_274 = out_roready_1_124 & out_romask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_2946 = out_f_roready_274; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_274 = out_wivalid_1_124 & out_wimask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_2947 = out_f_wivalid_274; // @[RegisterRouter.scala:87:24]
wire out_f_woready_274 = out_woready_1_124 & out_womask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_2948 = out_f_woready_274; // @[RegisterRouter.scala:87:24]
wire _out_T_2949 = ~out_rimask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_2950 = ~out_wimask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_2951 = ~out_romask_274; // @[RegisterRouter.scala:87:24]
wire _out_T_2952 = ~out_womask_274; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_221 = {programBufferMem_41, _out_prepend_T_221}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2953 = out_prepend_221; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_2954 = _out_T_2953; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_222 = _out_T_2954; // @[RegisterRouter.scala:87:24]
wire out_rimask_275 = |_out_rimask_T_275; // @[RegisterRouter.scala:87:24]
wire out_wimask_275 = &_out_wimask_T_275; // @[RegisterRouter.scala:87:24]
wire out_romask_275 = |_out_romask_T_275; // @[RegisterRouter.scala:87:24]
wire out_womask_275 = &_out_womask_T_275; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_275 = out_rivalid_1_125 & out_rimask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_2956 = out_f_rivalid_275; // @[RegisterRouter.scala:87:24]
wire out_f_roready_275 = out_roready_1_125 & out_romask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_2957 = out_f_roready_275; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_275 = out_wivalid_1_125 & out_wimask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_2958 = out_f_wivalid_275; // @[RegisterRouter.scala:87:24]
wire out_f_woready_275 = out_woready_1_125 & out_womask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_2959 = out_f_woready_275; // @[RegisterRouter.scala:87:24]
wire _out_T_2960 = ~out_rimask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_2961 = ~out_wimask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_2962 = ~out_romask_275; // @[RegisterRouter.scala:87:24]
wire _out_T_2963 = ~out_womask_275; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_222 = {programBufferMem_42, _out_prepend_T_222}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2964 = out_prepend_222; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_2965 = _out_T_2964; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_223 = _out_T_2965; // @[RegisterRouter.scala:87:24]
wire out_rimask_276 = |_out_rimask_T_276; // @[RegisterRouter.scala:87:24]
wire out_wimask_276 = &_out_wimask_T_276; // @[RegisterRouter.scala:87:24]
wire out_romask_276 = |_out_romask_T_276; // @[RegisterRouter.scala:87:24]
wire out_womask_276 = &_out_womask_T_276; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_276 = out_rivalid_1_126 & out_rimask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_2967 = out_f_rivalid_276; // @[RegisterRouter.scala:87:24]
wire out_f_roready_276 = out_roready_1_126 & out_romask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_2968 = out_f_roready_276; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_276 = out_wivalid_1_126 & out_wimask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_2969 = out_f_wivalid_276; // @[RegisterRouter.scala:87:24]
wire out_f_woready_276 = out_woready_1_126 & out_womask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_2970 = out_f_woready_276; // @[RegisterRouter.scala:87:24]
wire _out_T_2971 = ~out_rimask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_2972 = ~out_wimask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_2973 = ~out_romask_276; // @[RegisterRouter.scala:87:24]
wire _out_T_2974 = ~out_womask_276; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_223 = {programBufferMem_43, _out_prepend_T_223}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2975 = out_prepend_223; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_2976 = _out_T_2975; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_224 = _out_T_2976; // @[RegisterRouter.scala:87:24]
wire out_rimask_277 = |_out_rimask_T_277; // @[RegisterRouter.scala:87:24]
wire out_wimask_277 = &_out_wimask_T_277; // @[RegisterRouter.scala:87:24]
wire out_romask_277 = |_out_romask_T_277; // @[RegisterRouter.scala:87:24]
wire out_womask_277 = &_out_womask_T_277; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_277 = out_rivalid_1_127 & out_rimask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_2978 = out_f_rivalid_277; // @[RegisterRouter.scala:87:24]
wire out_f_roready_277 = out_roready_1_127 & out_romask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_2979 = out_f_roready_277; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_277 = out_wivalid_1_127 & out_wimask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_2980 = out_f_wivalid_277; // @[RegisterRouter.scala:87:24]
wire out_f_woready_277 = out_woready_1_127 & out_womask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_2981 = out_f_woready_277; // @[RegisterRouter.scala:87:24]
wire _out_T_2982 = ~out_rimask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_2983 = ~out_wimask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_2984 = ~out_romask_277; // @[RegisterRouter.scala:87:24]
wire _out_T_2985 = ~out_womask_277; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_224 = {programBufferMem_44, _out_prepend_T_224}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2986 = out_prepend_224; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_2987 = _out_T_2986; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_225 = _out_T_2987; // @[RegisterRouter.scala:87:24]
wire out_rimask_278 = |_out_rimask_T_278; // @[RegisterRouter.scala:87:24]
wire out_wimask_278 = &_out_wimask_T_278; // @[RegisterRouter.scala:87:24]
wire out_romask_278 = |_out_romask_T_278; // @[RegisterRouter.scala:87:24]
wire out_womask_278 = &_out_womask_T_278; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_278 = out_rivalid_1_128 & out_rimask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_2989 = out_f_rivalid_278; // @[RegisterRouter.scala:87:24]
wire out_f_roready_278 = out_roready_1_128 & out_romask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_2990 = out_f_roready_278; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_278 = out_wivalid_1_128 & out_wimask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_2991 = out_f_wivalid_278; // @[RegisterRouter.scala:87:24]
wire out_f_woready_278 = out_woready_1_128 & out_womask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_2992 = out_f_woready_278; // @[RegisterRouter.scala:87:24]
wire _out_T_2993 = ~out_rimask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_2994 = ~out_wimask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_2995 = ~out_romask_278; // @[RegisterRouter.scala:87:24]
wire _out_T_2996 = ~out_womask_278; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_225 = {programBufferMem_45, _out_prepend_T_225}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2997 = out_prepend_225; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_2998 = _out_T_2997; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_226 = _out_T_2998; // @[RegisterRouter.scala:87:24]
wire out_rimask_279 = |_out_rimask_T_279; // @[RegisterRouter.scala:87:24]
wire out_wimask_279 = &_out_wimask_T_279; // @[RegisterRouter.scala:87:24]
wire out_romask_279 = |_out_romask_T_279; // @[RegisterRouter.scala:87:24]
wire out_womask_279 = &_out_womask_T_279; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_279 = out_rivalid_1_129 & out_rimask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3000 = out_f_rivalid_279; // @[RegisterRouter.scala:87:24]
wire out_f_roready_279 = out_roready_1_129 & out_romask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3001 = out_f_roready_279; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_279 = out_wivalid_1_129 & out_wimask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3002 = out_f_wivalid_279; // @[RegisterRouter.scala:87:24]
wire out_f_woready_279 = out_woready_1_129 & out_womask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3003 = out_f_woready_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3004 = ~out_rimask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3005 = ~out_wimask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3006 = ~out_romask_279; // @[RegisterRouter.scala:87:24]
wire _out_T_3007 = ~out_womask_279; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_226 = {programBufferMem_46, _out_prepend_T_226}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3008 = out_prepend_226; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3009 = _out_T_3008; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_227 = _out_T_3009; // @[RegisterRouter.scala:87:24]
wire out_rimask_280 = |_out_rimask_T_280; // @[RegisterRouter.scala:87:24]
wire out_wimask_280 = &_out_wimask_T_280; // @[RegisterRouter.scala:87:24]
wire out_romask_280 = |_out_romask_T_280; // @[RegisterRouter.scala:87:24]
wire out_womask_280 = &_out_womask_T_280; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_280 = out_rivalid_1_130 & out_rimask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3011 = out_f_rivalid_280; // @[RegisterRouter.scala:87:24]
wire out_f_roready_280 = out_roready_1_130 & out_romask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3012 = out_f_roready_280; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_280 = out_wivalid_1_130 & out_wimask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3013 = out_f_wivalid_280; // @[RegisterRouter.scala:87:24]
wire out_f_woready_280 = out_woready_1_130 & out_womask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3014 = out_f_woready_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3015 = ~out_rimask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3016 = ~out_wimask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3017 = ~out_romask_280; // @[RegisterRouter.scala:87:24]
wire _out_T_3018 = ~out_womask_280; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_227 = {programBufferMem_47, _out_prepend_T_227}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3019 = out_prepend_227; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3020 = _out_T_3019; // @[RegisterRouter.scala:87:24]
wire out_rimask_281 = |_out_rimask_T_281; // @[RegisterRouter.scala:87:24]
wire out_wimask_281 = &_out_wimask_T_281; // @[RegisterRouter.scala:87:24]
wire out_romask_281 = |_out_romask_T_281; // @[RegisterRouter.scala:87:24]
wire out_womask_281 = &_out_womask_T_281; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_281 = out_rivalid_1_131 & out_rimask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3022 = out_f_rivalid_281; // @[RegisterRouter.scala:87:24]
wire out_f_roready_281 = out_roready_1_131 & out_romask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3023 = out_f_roready_281; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_281 = out_wivalid_1_131 & out_wimask_281; // @[RegisterRouter.scala:87:24]
wire out_f_woready_281 = out_woready_1_131 & out_womask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3024 = ~out_rimask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3025 = ~out_wimask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3026 = ~out_romask_281; // @[RegisterRouter.scala:87:24]
wire _out_T_3027 = ~out_womask_281; // @[RegisterRouter.scala:87:24]
wire out_rimask_282 = |_out_rimask_T_282; // @[RegisterRouter.scala:87:24]
wire out_wimask_282 = &_out_wimask_T_282; // @[RegisterRouter.scala:87:24]
wire out_romask_282 = |_out_romask_T_282; // @[RegisterRouter.scala:87:24]
wire out_womask_282 = &_out_womask_T_282; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_282 = out_rivalid_1_132 & out_rimask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3031 = out_f_rivalid_282; // @[RegisterRouter.scala:87:24]
wire out_f_roready_282 = out_roready_1_132 & out_romask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3032 = out_f_roready_282; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_282 = out_wivalid_1_132 & out_wimask_282; // @[RegisterRouter.scala:87:24]
wire out_f_woready_282 = out_woready_1_132 & out_womask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3033 = ~out_rimask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3034 = ~out_wimask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3035 = ~out_romask_282; // @[RegisterRouter.scala:87:24]
wire _out_T_3036 = ~out_womask_282; // @[RegisterRouter.scala:87:24]
wire out_rimask_283 = |_out_rimask_T_283; // @[RegisterRouter.scala:87:24]
wire out_wimask_283 = &_out_wimask_T_283; // @[RegisterRouter.scala:87:24]
wire out_romask_283 = |_out_romask_T_283; // @[RegisterRouter.scala:87:24]
wire out_womask_283 = &_out_womask_T_283; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_283 = out_rivalid_1_133 & out_rimask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3040 = out_f_rivalid_283; // @[RegisterRouter.scala:87:24]
wire out_f_roready_283 = out_roready_1_133 & out_romask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3041 = out_f_roready_283; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_283 = out_wivalid_1_133 & out_wimask_283; // @[RegisterRouter.scala:87:24]
wire out_f_woready_283 = out_woready_1_133 & out_womask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3042 = ~out_rimask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3043 = ~out_wimask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3044 = ~out_romask_283; // @[RegisterRouter.scala:87:24]
wire _out_T_3045 = ~out_womask_283; // @[RegisterRouter.scala:87:24]
wire out_rimask_284 = |_out_rimask_T_284; // @[RegisterRouter.scala:87:24]
wire out_wimask_284 = &_out_wimask_T_284; // @[RegisterRouter.scala:87:24]
wire out_romask_284 = |_out_romask_T_284; // @[RegisterRouter.scala:87:24]
wire out_womask_284 = &_out_womask_T_284; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_284 = out_rivalid_1_134 & out_rimask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3049 = out_f_rivalid_284; // @[RegisterRouter.scala:87:24]
wire out_f_roready_284 = out_roready_1_134 & out_romask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3050 = out_f_roready_284; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_284 = out_wivalid_1_134 & out_wimask_284; // @[RegisterRouter.scala:87:24]
wire out_f_woready_284 = out_woready_1_134 & out_womask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3051 = ~out_rimask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3052 = ~out_wimask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3053 = ~out_romask_284; // @[RegisterRouter.scala:87:24]
wire _out_T_3054 = ~out_womask_284; // @[RegisterRouter.scala:87:24]
wire out_rimask_285 = |_out_rimask_T_285; // @[RegisterRouter.scala:87:24]
wire out_wimask_285 = &_out_wimask_T_285; // @[RegisterRouter.scala:87:24]
wire out_romask_285 = |_out_romask_T_285; // @[RegisterRouter.scala:87:24]
wire out_womask_285 = &_out_womask_T_285; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_285 = out_rivalid_1_135 & out_rimask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3058 = out_f_rivalid_285; // @[RegisterRouter.scala:87:24]
wire out_f_roready_285 = out_roready_1_135 & out_romask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3059 = out_f_roready_285; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_285 = out_wivalid_1_135 & out_wimask_285; // @[RegisterRouter.scala:87:24]
wire out_f_woready_285 = out_woready_1_135 & out_womask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3060 = ~out_rimask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3061 = ~out_wimask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3062 = ~out_romask_285; // @[RegisterRouter.scala:87:24]
wire _out_T_3063 = ~out_womask_285; // @[RegisterRouter.scala:87:24]
wire out_rimask_286 = |_out_rimask_T_286; // @[RegisterRouter.scala:87:24]
wire out_wimask_286 = &_out_wimask_T_286; // @[RegisterRouter.scala:87:24]
wire out_romask_286 = |_out_romask_T_286; // @[RegisterRouter.scala:87:24]
wire out_womask_286 = &_out_womask_T_286; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_286 = out_rivalid_1_136 & out_rimask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3067 = out_f_rivalid_286; // @[RegisterRouter.scala:87:24]
wire out_f_roready_286 = out_roready_1_136 & out_romask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3068 = out_f_roready_286; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_286 = out_wivalid_1_136 & out_wimask_286; // @[RegisterRouter.scala:87:24]
wire out_f_woready_286 = out_woready_1_136 & out_womask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3069 = ~out_rimask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3070 = ~out_wimask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3071 = ~out_romask_286; // @[RegisterRouter.scala:87:24]
wire _out_T_3072 = ~out_womask_286; // @[RegisterRouter.scala:87:24]
wire out_rimask_287 = |_out_rimask_T_287; // @[RegisterRouter.scala:87:24]
wire out_wimask_287 = &_out_wimask_T_287; // @[RegisterRouter.scala:87:24]
wire out_romask_287 = |_out_romask_T_287; // @[RegisterRouter.scala:87:24]
wire out_womask_287 = &_out_womask_T_287; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_287 = out_rivalid_1_137 & out_rimask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3076 = out_f_rivalid_287; // @[RegisterRouter.scala:87:24]
wire out_f_roready_287 = out_roready_1_137 & out_romask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3077 = out_f_roready_287; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_287 = out_wivalid_1_137 & out_wimask_287; // @[RegisterRouter.scala:87:24]
wire out_f_woready_287 = out_woready_1_137 & out_womask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3078 = ~out_rimask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3079 = ~out_wimask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3080 = ~out_romask_287; // @[RegisterRouter.scala:87:24]
wire _out_T_3081 = ~out_womask_287; // @[RegisterRouter.scala:87:24]
wire out_rimask_288 = |_out_rimask_T_288; // @[RegisterRouter.scala:87:24]
wire out_wimask_288 = &_out_wimask_T_288; // @[RegisterRouter.scala:87:24]
wire out_romask_288 = |_out_romask_T_288; // @[RegisterRouter.scala:87:24]
wire out_womask_288 = &_out_womask_T_288; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_288 = out_rivalid_1_138 & out_rimask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3085 = out_f_rivalid_288; // @[RegisterRouter.scala:87:24]
wire out_f_roready_288 = out_roready_1_138 & out_romask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3086 = out_f_roready_288; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_288 = out_wivalid_1_138 & out_wimask_288; // @[RegisterRouter.scala:87:24]
wire out_f_woready_288 = out_woready_1_138 & out_womask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3087 = ~out_rimask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3088 = ~out_wimask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3089 = ~out_romask_288; // @[RegisterRouter.scala:87:24]
wire _out_T_3090 = ~out_womask_288; // @[RegisterRouter.scala:87:24]
wire out_rimask_289 = |_out_rimask_T_289; // @[RegisterRouter.scala:87:24]
wire out_wimask_289 = &_out_wimask_T_289; // @[RegisterRouter.scala:87:24]
wire out_romask_289 = |_out_romask_T_289; // @[RegisterRouter.scala:87:24]
wire out_womask_289 = &_out_womask_T_289; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_289 = out_rivalid_1_139 & out_rimask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3094 = out_f_rivalid_289; // @[RegisterRouter.scala:87:24]
wire out_f_roready_289 = out_roready_1_139 & out_romask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3095 = out_f_roready_289; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_289 = out_wivalid_1_139 & out_wimask_289; // @[RegisterRouter.scala:87:24]
wire out_f_woready_289 = out_woready_1_139 & out_womask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3096 = ~out_rimask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3097 = ~out_wimask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3098 = ~out_romask_289; // @[RegisterRouter.scala:87:24]
wire _out_T_3099 = ~out_womask_289; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3101 = _out_T_3100; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_235 = _out_T_3101; // @[RegisterRouter.scala:87:24]
wire out_rimask_290 = |_out_rimask_T_290; // @[RegisterRouter.scala:87:24]
wire out_wimask_290 = &_out_wimask_T_290; // @[RegisterRouter.scala:87:24]
wire out_romask_290 = |_out_romask_T_290; // @[RegisterRouter.scala:87:24]
wire out_womask_290 = &_out_womask_T_290; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_290 = out_rivalid_1_140 & out_rimask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3103 = out_f_rivalid_290; // @[RegisterRouter.scala:87:24]
wire out_f_roready_290 = out_roready_1_140 & out_romask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3104 = out_f_roready_290; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_290 = out_wivalid_1_140 & out_wimask_290; // @[RegisterRouter.scala:87:24]
wire out_f_woready_290 = out_woready_1_140 & out_womask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3105 = ~out_rimask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3106 = ~out_wimask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3107 = ~out_romask_290; // @[RegisterRouter.scala:87:24]
wire _out_T_3108 = ~out_womask_290; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_235 = {hi_2, flags_1_go, _out_prepend_T_235}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3109 = out_prepend_235; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3110 = _out_T_3109; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_236 = _out_T_3110; // @[RegisterRouter.scala:87:24]
wire out_rimask_291 = |_out_rimask_T_291; // @[RegisterRouter.scala:87:24]
wire out_wimask_291 = &_out_wimask_T_291; // @[RegisterRouter.scala:87:24]
wire out_romask_291 = |_out_romask_T_291; // @[RegisterRouter.scala:87:24]
wire out_womask_291 = &_out_womask_T_291; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_291 = out_rivalid_1_141 & out_rimask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3112 = out_f_rivalid_291; // @[RegisterRouter.scala:87:24]
wire out_f_roready_291 = out_roready_1_141 & out_romask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3113 = out_f_roready_291; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_291 = out_wivalid_1_141 & out_wimask_291; // @[RegisterRouter.scala:87:24]
wire out_f_woready_291 = out_woready_1_141 & out_womask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3114 = ~out_rimask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3115 = ~out_wimask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3116 = ~out_romask_291; // @[RegisterRouter.scala:87:24]
wire _out_T_3117 = ~out_womask_291; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_236 = {hi_3, flags_2_go, _out_prepend_T_236}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3118 = out_prepend_236; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3119 = _out_T_3118; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_237 = _out_T_3119; // @[RegisterRouter.scala:87:24]
wire out_rimask_292 = |_out_rimask_T_292; // @[RegisterRouter.scala:87:24]
wire out_wimask_292 = &_out_wimask_T_292; // @[RegisterRouter.scala:87:24]
wire out_romask_292 = |_out_romask_T_292; // @[RegisterRouter.scala:87:24]
wire out_womask_292 = &_out_womask_T_292; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_292 = out_rivalid_1_142 & out_rimask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3121 = out_f_rivalid_292; // @[RegisterRouter.scala:87:24]
wire out_f_roready_292 = out_roready_1_142 & out_romask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3122 = out_f_roready_292; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_292 = out_wivalid_1_142 & out_wimask_292; // @[RegisterRouter.scala:87:24]
wire out_f_woready_292 = out_woready_1_142 & out_womask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3123 = ~out_rimask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3124 = ~out_wimask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3125 = ~out_romask_292; // @[RegisterRouter.scala:87:24]
wire _out_T_3126 = ~out_womask_292; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_237 = {hi_4, flags_3_go, _out_prepend_T_237}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3127 = out_prepend_237; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3128 = _out_T_3127; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_238 = _out_T_3128; // @[RegisterRouter.scala:87:24]
wire out_rimask_293 = |_out_rimask_T_293; // @[RegisterRouter.scala:87:24]
wire out_wimask_293 = &_out_wimask_T_293; // @[RegisterRouter.scala:87:24]
wire out_romask_293 = |_out_romask_T_293; // @[RegisterRouter.scala:87:24]
wire out_womask_293 = &_out_womask_T_293; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_293 = out_rivalid_1_143 & out_rimask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3130 = out_f_rivalid_293; // @[RegisterRouter.scala:87:24]
wire out_f_roready_293 = out_roready_1_143 & out_romask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3131 = out_f_roready_293; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_293 = out_wivalid_1_143 & out_wimask_293; // @[RegisterRouter.scala:87:24]
wire out_f_woready_293 = out_woready_1_143 & out_womask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3132 = ~out_rimask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3133 = ~out_wimask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3134 = ~out_romask_293; // @[RegisterRouter.scala:87:24]
wire _out_T_3135 = ~out_womask_293; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_238 = {hi_5, flags_4_go, _out_prepend_T_238}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3136 = out_prepend_238; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3137 = _out_T_3136; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_239 = _out_T_3137; // @[RegisterRouter.scala:87:24]
wire out_rimask_294 = |_out_rimask_T_294; // @[RegisterRouter.scala:87:24]
wire out_wimask_294 = &_out_wimask_T_294; // @[RegisterRouter.scala:87:24]
wire out_romask_294 = |_out_romask_T_294; // @[RegisterRouter.scala:87:24]
wire out_womask_294 = &_out_womask_T_294; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_294 = out_rivalid_1_144 & out_rimask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3139 = out_f_rivalid_294; // @[RegisterRouter.scala:87:24]
wire out_f_roready_294 = out_roready_1_144 & out_romask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3140 = out_f_roready_294; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_294 = out_wivalid_1_144 & out_wimask_294; // @[RegisterRouter.scala:87:24]
wire out_f_woready_294 = out_woready_1_144 & out_womask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3141 = ~out_rimask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3142 = ~out_wimask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3143 = ~out_romask_294; // @[RegisterRouter.scala:87:24]
wire _out_T_3144 = ~out_womask_294; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_239 = {hi_6, flags_5_go, _out_prepend_T_239}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3145 = out_prepend_239; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3146 = _out_T_3145; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_240 = _out_T_3146; // @[RegisterRouter.scala:87:24]
wire out_rimask_295 = |_out_rimask_T_295; // @[RegisterRouter.scala:87:24]
wire out_wimask_295 = &_out_wimask_T_295; // @[RegisterRouter.scala:87:24]
wire out_romask_295 = |_out_romask_T_295; // @[RegisterRouter.scala:87:24]
wire out_womask_295 = &_out_womask_T_295; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_295 = out_rivalid_1_145 & out_rimask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3148 = out_f_rivalid_295; // @[RegisterRouter.scala:87:24]
wire out_f_roready_295 = out_roready_1_145 & out_romask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3149 = out_f_roready_295; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_295 = out_wivalid_1_145 & out_wimask_295; // @[RegisterRouter.scala:87:24]
wire out_f_woready_295 = out_woready_1_145 & out_womask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3150 = ~out_rimask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3151 = ~out_wimask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3152 = ~out_romask_295; // @[RegisterRouter.scala:87:24]
wire _out_T_3153 = ~out_womask_295; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_240 = {hi_7, flags_6_go, _out_prepend_T_240}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3154 = out_prepend_240; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3155 = _out_T_3154; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_241 = _out_T_3155; // @[RegisterRouter.scala:87:24]
wire out_rimask_296 = |_out_rimask_T_296; // @[RegisterRouter.scala:87:24]
wire out_wimask_296 = &_out_wimask_T_296; // @[RegisterRouter.scala:87:24]
wire out_romask_296 = |_out_romask_T_296; // @[RegisterRouter.scala:87:24]
wire out_womask_296 = &_out_womask_T_296; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_296 = out_rivalid_1_146 & out_rimask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3157 = out_f_rivalid_296; // @[RegisterRouter.scala:87:24]
wire out_f_roready_296 = out_roready_1_146 & out_romask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3158 = out_f_roready_296; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_296 = out_wivalid_1_146 & out_wimask_296; // @[RegisterRouter.scala:87:24]
wire out_f_woready_296 = out_woready_1_146 & out_womask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3159 = ~out_rimask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3160 = ~out_wimask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3161 = ~out_romask_296; // @[RegisterRouter.scala:87:24]
wire _out_T_3162 = ~out_womask_296; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_241 = {hi_8, flags_7_go, _out_prepend_T_241}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3163 = out_prepend_241; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3164 = _out_T_3163; // @[RegisterRouter.scala:87:24]
wire out_rimask_297 = |_out_rimask_T_297; // @[RegisterRouter.scala:87:24]
wire out_wimask_297 = &_out_wimask_T_297; // @[RegisterRouter.scala:87:24]
wire out_romask_297 = |_out_romask_T_297; // @[RegisterRouter.scala:87:24]
wire out_womask_297 = &_out_womask_T_297; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_297 = out_rivalid_1_147 & out_rimask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3166 = out_f_rivalid_297; // @[RegisterRouter.scala:87:24]
wire out_f_roready_297 = out_roready_1_147 & out_romask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3167 = out_f_roready_297; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_297 = out_wivalid_1_147 & out_wimask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3168 = out_f_wivalid_297; // @[RegisterRouter.scala:87:24]
wire out_f_woready_297 = out_woready_1_147 & out_womask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3169 = out_f_woready_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3170 = ~out_rimask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3171 = ~out_wimask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3172 = ~out_romask_297; // @[RegisterRouter.scala:87:24]
wire _out_T_3173 = ~out_womask_297; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3175 = _out_T_3174; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_242 = _out_T_3175; // @[RegisterRouter.scala:87:24]
wire out_rimask_298 = |_out_rimask_T_298; // @[RegisterRouter.scala:87:24]
wire out_wimask_298 = &_out_wimask_T_298; // @[RegisterRouter.scala:87:24]
wire out_romask_298 = |_out_romask_T_298; // @[RegisterRouter.scala:87:24]
wire out_womask_298 = &_out_womask_T_298; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_298 = out_rivalid_1_148 & out_rimask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3177 = out_f_rivalid_298; // @[RegisterRouter.scala:87:24]
wire out_f_roready_298 = out_roready_1_148 & out_romask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3178 = out_f_roready_298; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_298 = out_wivalid_1_148 & out_wimask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3179 = out_f_wivalid_298; // @[RegisterRouter.scala:87:24]
wire out_f_woready_298 = out_woready_1_148 & out_womask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3180 = out_f_woready_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3181 = ~out_rimask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3182 = ~out_wimask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3183 = ~out_romask_298; // @[RegisterRouter.scala:87:24]
wire _out_T_3184 = ~out_womask_298; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_242 = {programBufferMem_9, _out_prepend_T_242}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3185 = out_prepend_242; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3186 = _out_T_3185; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_243 = _out_T_3186; // @[RegisterRouter.scala:87:24]
wire out_rimask_299 = |_out_rimask_T_299; // @[RegisterRouter.scala:87:24]
wire out_wimask_299 = &_out_wimask_T_299; // @[RegisterRouter.scala:87:24]
wire out_romask_299 = |_out_romask_T_299; // @[RegisterRouter.scala:87:24]
wire out_womask_299 = &_out_womask_T_299; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_299 = out_rivalid_1_149 & out_rimask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3188 = out_f_rivalid_299; // @[RegisterRouter.scala:87:24]
wire out_f_roready_299 = out_roready_1_149 & out_romask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3189 = out_f_roready_299; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_299 = out_wivalid_1_149 & out_wimask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3190 = out_f_wivalid_299; // @[RegisterRouter.scala:87:24]
wire out_f_woready_299 = out_woready_1_149 & out_womask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3191 = out_f_woready_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3192 = ~out_rimask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3193 = ~out_wimask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3194 = ~out_romask_299; // @[RegisterRouter.scala:87:24]
wire _out_T_3195 = ~out_womask_299; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_243 = {programBufferMem_10, _out_prepend_T_243}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3196 = out_prepend_243; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3197 = _out_T_3196; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_244 = _out_T_3197; // @[RegisterRouter.scala:87:24]
wire out_rimask_300 = |_out_rimask_T_300; // @[RegisterRouter.scala:87:24]
wire out_wimask_300 = &_out_wimask_T_300; // @[RegisterRouter.scala:87:24]
wire out_romask_300 = |_out_romask_T_300; // @[RegisterRouter.scala:87:24]
wire out_womask_300 = &_out_womask_T_300; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_300 = out_rivalid_1_150 & out_rimask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3199 = out_f_rivalid_300; // @[RegisterRouter.scala:87:24]
wire out_f_roready_300 = out_roready_1_150 & out_romask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3200 = out_f_roready_300; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_300 = out_wivalid_1_150 & out_wimask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3201 = out_f_wivalid_300; // @[RegisterRouter.scala:87:24]
wire out_f_woready_300 = out_woready_1_150 & out_womask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3202 = out_f_woready_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3203 = ~out_rimask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3204 = ~out_wimask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3205 = ~out_romask_300; // @[RegisterRouter.scala:87:24]
wire _out_T_3206 = ~out_womask_300; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_244 = {programBufferMem_11, _out_prepend_T_244}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3207 = out_prepend_244; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3208 = _out_T_3207; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_245 = _out_T_3208; // @[RegisterRouter.scala:87:24]
wire out_rimask_301 = |_out_rimask_T_301; // @[RegisterRouter.scala:87:24]
wire out_wimask_301 = &_out_wimask_T_301; // @[RegisterRouter.scala:87:24]
wire out_romask_301 = |_out_romask_T_301; // @[RegisterRouter.scala:87:24]
wire out_womask_301 = &_out_womask_T_301; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_301 = out_rivalid_1_151 & out_rimask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3210 = out_f_rivalid_301; // @[RegisterRouter.scala:87:24]
wire out_f_roready_301 = out_roready_1_151 & out_romask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3211 = out_f_roready_301; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_301 = out_wivalid_1_151 & out_wimask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3212 = out_f_wivalid_301; // @[RegisterRouter.scala:87:24]
wire out_f_woready_301 = out_woready_1_151 & out_womask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3213 = out_f_woready_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3214 = ~out_rimask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3215 = ~out_wimask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3216 = ~out_romask_301; // @[RegisterRouter.scala:87:24]
wire _out_T_3217 = ~out_womask_301; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_245 = {programBufferMem_12, _out_prepend_T_245}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3218 = out_prepend_245; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3219 = _out_T_3218; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_246 = _out_T_3219; // @[RegisterRouter.scala:87:24]
wire out_rimask_302 = |_out_rimask_T_302; // @[RegisterRouter.scala:87:24]
wire out_wimask_302 = &_out_wimask_T_302; // @[RegisterRouter.scala:87:24]
wire out_romask_302 = |_out_romask_T_302; // @[RegisterRouter.scala:87:24]
wire out_womask_302 = &_out_womask_T_302; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_302 = out_rivalid_1_152 & out_rimask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3221 = out_f_rivalid_302; // @[RegisterRouter.scala:87:24]
wire out_f_roready_302 = out_roready_1_152 & out_romask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3222 = out_f_roready_302; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_302 = out_wivalid_1_152 & out_wimask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3223 = out_f_wivalid_302; // @[RegisterRouter.scala:87:24]
wire out_f_woready_302 = out_woready_1_152 & out_womask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3224 = out_f_woready_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3225 = ~out_rimask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3226 = ~out_wimask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3227 = ~out_romask_302; // @[RegisterRouter.scala:87:24]
wire _out_T_3228 = ~out_womask_302; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_246 = {programBufferMem_13, _out_prepend_T_246}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3229 = out_prepend_246; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3230 = _out_T_3229; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_247 = _out_T_3230; // @[RegisterRouter.scala:87:24]
wire out_rimask_303 = |_out_rimask_T_303; // @[RegisterRouter.scala:87:24]
wire out_wimask_303 = &_out_wimask_T_303; // @[RegisterRouter.scala:87:24]
wire out_romask_303 = |_out_romask_T_303; // @[RegisterRouter.scala:87:24]
wire out_womask_303 = &_out_womask_T_303; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_303 = out_rivalid_1_153 & out_rimask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3232 = out_f_rivalid_303; // @[RegisterRouter.scala:87:24]
wire out_f_roready_303 = out_roready_1_153 & out_romask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3233 = out_f_roready_303; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_303 = out_wivalid_1_153 & out_wimask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3234 = out_f_wivalid_303; // @[RegisterRouter.scala:87:24]
wire out_f_woready_303 = out_woready_1_153 & out_womask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3235 = out_f_woready_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3236 = ~out_rimask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3237 = ~out_wimask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3238 = ~out_romask_303; // @[RegisterRouter.scala:87:24]
wire _out_T_3239 = ~out_womask_303; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_247 = {programBufferMem_14, _out_prepend_T_247}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3240 = out_prepend_247; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3241 = _out_T_3240; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_248 = _out_T_3241; // @[RegisterRouter.scala:87:24]
wire out_rimask_304 = |_out_rimask_T_304; // @[RegisterRouter.scala:87:24]
wire out_wimask_304 = &_out_wimask_T_304; // @[RegisterRouter.scala:87:24]
wire out_romask_304 = |_out_romask_T_304; // @[RegisterRouter.scala:87:24]
wire out_womask_304 = &_out_womask_T_304; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_304 = out_rivalid_1_154 & out_rimask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3243 = out_f_rivalid_304; // @[RegisterRouter.scala:87:24]
wire out_f_roready_304 = out_roready_1_154 & out_romask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3244 = out_f_roready_304; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_304 = out_wivalid_1_154 & out_wimask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3245 = out_f_wivalid_304; // @[RegisterRouter.scala:87:24]
wire out_f_woready_304 = out_woready_1_154 & out_womask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3246 = out_f_woready_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3247 = ~out_rimask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3248 = ~out_wimask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3249 = ~out_romask_304; // @[RegisterRouter.scala:87:24]
wire _out_T_3250 = ~out_womask_304; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_248 = {programBufferMem_15, _out_prepend_T_248}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3251 = out_prepend_248; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3252 = _out_T_3251; // @[RegisterRouter.scala:87:24]
wire out_rimask_305 = |_out_rimask_T_305; // @[RegisterRouter.scala:87:24]
wire out_wimask_305 = &_out_wimask_T_305; // @[RegisterRouter.scala:87:24]
wire out_romask_305 = |_out_romask_T_305; // @[RegisterRouter.scala:87:24]
wire out_womask_305 = &_out_womask_T_305; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_305 = out_rivalid_1_155 & out_rimask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3254 = out_f_rivalid_305; // @[RegisterRouter.scala:87:24]
wire out_f_roready_305 = out_roready_1_155 & out_romask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3255 = out_f_roready_305; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_305 = out_wivalid_1_155 & out_wimask_305; // @[RegisterRouter.scala:87:24]
wire out_f_woready_305 = out_woready_1_155 & out_womask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3256 = ~out_rimask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3257 = ~out_wimask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3258 = ~out_romask_305; // @[RegisterRouter.scala:87:24]
wire _out_T_3259 = ~out_womask_305; // @[RegisterRouter.scala:87:24]
wire out_rimask_306 = |_out_rimask_T_306; // @[RegisterRouter.scala:87:24]
wire out_wimask_306 = &_out_wimask_T_306; // @[RegisterRouter.scala:87:24]
wire out_romask_306 = |_out_romask_T_306; // @[RegisterRouter.scala:87:24]
wire out_womask_306 = &_out_womask_T_306; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_306 = out_rivalid_1_156 & out_rimask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3263 = out_f_rivalid_306; // @[RegisterRouter.scala:87:24]
wire out_f_roready_306 = out_roready_1_156 & out_romask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3264 = out_f_roready_306; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_306 = out_wivalid_1_156 & out_wimask_306; // @[RegisterRouter.scala:87:24]
wire out_f_woready_306 = out_woready_1_156 & out_womask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3265 = ~out_rimask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3266 = ~out_wimask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3267 = ~out_romask_306; // @[RegisterRouter.scala:87:24]
wire _out_T_3268 = ~out_womask_306; // @[RegisterRouter.scala:87:24]
wire out_rimask_307 = |_out_rimask_T_307; // @[RegisterRouter.scala:87:24]
wire out_wimask_307 = &_out_wimask_T_307; // @[RegisterRouter.scala:87:24]
wire out_romask_307 = |_out_romask_T_307; // @[RegisterRouter.scala:87:24]
wire out_womask_307 = &_out_womask_T_307; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_307 = out_rivalid_1_157 & out_rimask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3272 = out_f_rivalid_307; // @[RegisterRouter.scala:87:24]
wire out_f_roready_307 = out_roready_1_157 & out_romask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3273 = out_f_roready_307; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_307 = out_wivalid_1_157 & out_wimask_307; // @[RegisterRouter.scala:87:24]
wire out_f_woready_307 = out_woready_1_157 & out_womask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3274 = ~out_rimask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3275 = ~out_wimask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3276 = ~out_romask_307; // @[RegisterRouter.scala:87:24]
wire _out_T_3277 = ~out_womask_307; // @[RegisterRouter.scala:87:24]
wire out_rimask_308 = |_out_rimask_T_308; // @[RegisterRouter.scala:87:24]
wire out_wimask_308 = &_out_wimask_T_308; // @[RegisterRouter.scala:87:24]
wire out_romask_308 = |_out_romask_T_308; // @[RegisterRouter.scala:87:24]
wire out_womask_308 = &_out_womask_T_308; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_308 = out_rivalid_1_158 & out_rimask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3281 = out_f_rivalid_308; // @[RegisterRouter.scala:87:24]
wire out_f_roready_308 = out_roready_1_158 & out_romask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3282 = out_f_roready_308; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_308 = out_wivalid_1_158 & out_wimask_308; // @[RegisterRouter.scala:87:24]
wire out_f_woready_308 = out_woready_1_158 & out_womask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3283 = ~out_rimask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3284 = ~out_wimask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3285 = ~out_romask_308; // @[RegisterRouter.scala:87:24]
wire _out_T_3286 = ~out_womask_308; // @[RegisterRouter.scala:87:24]
wire out_rimask_309 = |_out_rimask_T_309; // @[RegisterRouter.scala:87:24]
wire out_wimask_309 = &_out_wimask_T_309; // @[RegisterRouter.scala:87:24]
wire out_romask_309 = |_out_romask_T_309; // @[RegisterRouter.scala:87:24]
wire out_womask_309 = &_out_womask_T_309; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_309 = out_rivalid_1_159 & out_rimask_309; // @[RegisterRouter.scala:87:24]
wire out_f_roready_309 = out_roready_1_159 & out_romask_309; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_309 = out_wivalid_1_159 & out_wimask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3290 = out_f_wivalid_309; // @[RegisterRouter.scala:87:24]
assign out_f_woready_309 = out_woready_1_159 & out_womask_309; // @[RegisterRouter.scala:87:24]
assign hartHaltedWrEn = out_f_woready_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3291 = out_f_woready_309; // @[RegisterRouter.scala:87:24]
assign hartHaltedId = _out_T_3289; // @[RegisterRouter.scala:87:24]
wire _out_T_3292 = ~out_rimask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3293 = ~out_wimask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3294 = ~out_romask_309; // @[RegisterRouter.scala:87:24]
wire _out_T_3295 = ~out_womask_309; // @[RegisterRouter.scala:87:24]
wire out_rimask_310 = |_out_rimask_T_310; // @[RegisterRouter.scala:87:24]
wire out_wimask_310 = &_out_wimask_T_310; // @[RegisterRouter.scala:87:24]
wire out_romask_310 = |_out_romask_T_310; // @[RegisterRouter.scala:87:24]
wire out_womask_310 = &_out_womask_T_310; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_310 = out_rivalid_1_160 & out_rimask_310; // @[RegisterRouter.scala:87:24]
wire out_f_roready_310 = out_roready_1_160 & out_romask_310; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_310 = out_wivalid_1_160 & out_wimask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3299 = out_f_wivalid_310; // @[RegisterRouter.scala:87:24]
assign out_f_woready_310 = out_woready_1_160 & out_womask_310; // @[RegisterRouter.scala:87:24]
assign hartGoingWrEn = out_f_woready_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3300 = out_f_woready_310; // @[RegisterRouter.scala:87:24]
assign hartGoingId = _out_T_3298; // @[RegisterRouter.scala:87:24]
wire _out_T_3301 = ~out_rimask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3302 = ~out_wimask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3303 = ~out_romask_310; // @[RegisterRouter.scala:87:24]
wire _out_T_3304 = ~out_womask_310; // @[RegisterRouter.scala:87:24]
wire out_rimask_311 = |_out_rimask_T_311; // @[RegisterRouter.scala:87:24]
wire out_wimask_311 = &_out_wimask_T_311; // @[RegisterRouter.scala:87:24]
wire out_romask_311 = |_out_romask_T_311; // @[RegisterRouter.scala:87:24]
wire out_womask_311 = &_out_womask_T_311; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_311 = out_rivalid_1_161 & out_rimask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3308 = out_f_rivalid_311; // @[RegisterRouter.scala:87:24]
wire out_f_roready_311 = out_roready_1_161 & out_romask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3309 = out_f_roready_311; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_311 = out_wivalid_1_161 & out_wimask_311; // @[RegisterRouter.scala:87:24]
wire out_f_woready_311 = out_woready_1_161 & out_womask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3310 = ~out_rimask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3311 = ~out_wimask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3312 = ~out_romask_311; // @[RegisterRouter.scala:87:24]
wire _out_T_3313 = ~out_womask_311; // @[RegisterRouter.scala:87:24]
wire out_rimask_312 = |_out_rimask_T_312; // @[RegisterRouter.scala:87:24]
wire out_wimask_312 = &_out_wimask_T_312; // @[RegisterRouter.scala:87:24]
wire out_romask_312 = |_out_romask_T_312; // @[RegisterRouter.scala:87:24]
wire out_womask_312 = &_out_womask_T_312; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_312 = out_rivalid_1_162 & out_rimask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3317 = out_f_rivalid_312; // @[RegisterRouter.scala:87:24]
wire out_f_roready_312 = out_roready_1_162 & out_romask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3318 = out_f_roready_312; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_312 = out_wivalid_1_162 & out_wimask_312; // @[RegisterRouter.scala:87:24]
wire out_f_woready_312 = out_woready_1_162 & out_womask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3319 = ~out_rimask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3320 = ~out_wimask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3321 = ~out_romask_312; // @[RegisterRouter.scala:87:24]
wire _out_T_3322 = ~out_womask_312; // @[RegisterRouter.scala:87:24]
wire out_rimask_313 = |_out_rimask_T_313; // @[RegisterRouter.scala:87:24]
wire out_wimask_313 = &_out_wimask_T_313; // @[RegisterRouter.scala:87:24]
wire out_romask_313 = |_out_romask_T_313; // @[RegisterRouter.scala:87:24]
wire out_womask_313 = &_out_womask_T_313; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_313 = out_rivalid_1_163 & out_rimask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3326 = out_f_rivalid_313; // @[RegisterRouter.scala:87:24]
wire out_f_roready_313 = out_roready_1_163 & out_romask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3327 = out_f_roready_313; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_313 = out_wivalid_1_163 & out_wimask_313; // @[RegisterRouter.scala:87:24]
wire out_f_woready_313 = out_woready_1_163 & out_womask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3328 = ~out_rimask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3329 = ~out_wimask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3330 = ~out_romask_313; // @[RegisterRouter.scala:87:24]
wire _out_T_3331 = ~out_womask_313; // @[RegisterRouter.scala:87:24]
wire out_rimask_314 = |_out_rimask_T_314; // @[RegisterRouter.scala:87:24]
wire out_wimask_314 = &_out_wimask_T_314; // @[RegisterRouter.scala:87:24]
wire out_romask_314 = |_out_romask_T_314; // @[RegisterRouter.scala:87:24]
wire out_womask_314 = &_out_womask_T_314; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_314 = out_rivalid_1_164 & out_rimask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3335 = out_f_rivalid_314; // @[RegisterRouter.scala:87:24]
wire out_f_roready_314 = out_roready_1_164 & out_romask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3336 = out_f_roready_314; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_314 = out_wivalid_1_164 & out_wimask_314; // @[RegisterRouter.scala:87:24]
wire out_f_woready_314 = out_woready_1_164 & out_womask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3337 = ~out_rimask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3338 = ~out_wimask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3339 = ~out_romask_314; // @[RegisterRouter.scala:87:24]
wire _out_T_3340 = ~out_womask_314; // @[RegisterRouter.scala:87:24]
wire out_rimask_315 = |_out_rimask_T_315; // @[RegisterRouter.scala:87:24]
wire out_wimask_315 = &_out_wimask_T_315; // @[RegisterRouter.scala:87:24]
wire out_romask_315 = |_out_romask_T_315; // @[RegisterRouter.scala:87:24]
wire out_womask_315 = &_out_womask_T_315; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_315 = out_rivalid_1_165 & out_rimask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3344 = out_f_rivalid_315; // @[RegisterRouter.scala:87:24]
wire out_f_roready_315 = out_roready_1_165 & out_romask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3345 = out_f_roready_315; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_315 = out_wivalid_1_165 & out_wimask_315; // @[RegisterRouter.scala:87:24]
wire out_f_woready_315 = out_woready_1_165 & out_womask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3346 = ~out_rimask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3347 = ~out_wimask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3348 = ~out_romask_315; // @[RegisterRouter.scala:87:24]
wire _out_T_3349 = ~out_womask_315; // @[RegisterRouter.scala:87:24]
wire out_rimask_316 = |_out_rimask_T_316; // @[RegisterRouter.scala:87:24]
wire out_wimask_316 = &_out_wimask_T_316; // @[RegisterRouter.scala:87:24]
wire out_romask_316 = |_out_romask_T_316; // @[RegisterRouter.scala:87:24]
wire out_womask_316 = &_out_womask_T_316; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_316 = out_rivalid_1_166 & out_rimask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3353 = out_f_rivalid_316; // @[RegisterRouter.scala:87:24]
wire out_f_roready_316 = out_roready_1_166 & out_romask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3354 = out_f_roready_316; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_316 = out_wivalid_1_166 & out_wimask_316; // @[RegisterRouter.scala:87:24]
wire out_f_woready_316 = out_woready_1_166 & out_womask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3355 = ~out_rimask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3356 = ~out_wimask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3357 = ~out_romask_316; // @[RegisterRouter.scala:87:24]
wire _out_T_3358 = ~out_womask_316; // @[RegisterRouter.scala:87:24]
wire out_rimask_317 = |_out_rimask_T_317; // @[RegisterRouter.scala:87:24]
wire out_wimask_317 = &_out_wimask_T_317; // @[RegisterRouter.scala:87:24]
wire out_romask_317 = |_out_romask_T_317; // @[RegisterRouter.scala:87:24]
wire out_womask_317 = &_out_womask_T_317; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_317 = out_rivalid_1_167 & out_rimask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3362 = out_f_rivalid_317; // @[RegisterRouter.scala:87:24]
wire out_f_roready_317 = out_roready_1_167 & out_romask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3363 = out_f_roready_317; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_317 = out_wivalid_1_167 & out_wimask_317; // @[RegisterRouter.scala:87:24]
wire out_f_woready_317 = out_woready_1_167 & out_womask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3364 = ~out_rimask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3365 = ~out_wimask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3366 = ~out_romask_317; // @[RegisterRouter.scala:87:24]
wire _out_T_3367 = ~out_womask_317; // @[RegisterRouter.scala:87:24]
wire out_rimask_318 = |_out_rimask_T_318; // @[RegisterRouter.scala:87:24]
wire out_wimask_318 = &_out_wimask_T_318; // @[RegisterRouter.scala:87:24]
wire out_romask_318 = |_out_romask_T_318; // @[RegisterRouter.scala:87:24]
wire out_womask_318 = &_out_womask_T_318; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_318 = out_rivalid_1_168 & out_rimask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3371 = out_f_rivalid_318; // @[RegisterRouter.scala:87:24]
wire out_f_roready_318 = out_roready_1_168 & out_romask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3372 = out_f_roready_318; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_318 = out_wivalid_1_168 & out_wimask_318; // @[RegisterRouter.scala:87:24]
wire out_f_woready_318 = out_woready_1_168 & out_womask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3373 = ~out_rimask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3374 = ~out_wimask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3375 = ~out_romask_318; // @[RegisterRouter.scala:87:24]
wire _out_T_3376 = ~out_womask_318; // @[RegisterRouter.scala:87:24]
wire out_rimask_319 = |_out_rimask_T_319; // @[RegisterRouter.scala:87:24]
wire out_wimask_319 = &_out_wimask_T_319; // @[RegisterRouter.scala:87:24]
wire out_romask_319 = |_out_romask_T_319; // @[RegisterRouter.scala:87:24]
wire out_womask_319 = &_out_womask_T_319; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_319 = out_rivalid_1_169 & out_rimask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3380 = out_f_rivalid_319; // @[RegisterRouter.scala:87:24]
wire out_f_roready_319 = out_roready_1_169 & out_romask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3381 = out_f_roready_319; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_319 = out_wivalid_1_169 & out_wimask_319; // @[RegisterRouter.scala:87:24]
wire out_f_woready_319 = out_woready_1_169 & out_womask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3382 = ~out_rimask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3383 = ~out_wimask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3384 = ~out_romask_319; // @[RegisterRouter.scala:87:24]
wire _out_T_3385 = ~out_womask_319; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3387 = _out_T_3386; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_260 = _out_T_3387; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_320 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_320 = out_frontMask_1[63:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_320 = |_out_rimask_T_320; // @[RegisterRouter.scala:87:24]
wire out_wimask_320 = &_out_wimask_T_320; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_320 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_320 = out_backMask_1[63:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_320 = |_out_romask_T_320; // @[RegisterRouter.scala:87:24]
wire out_womask_320 = &_out_womask_T_320; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_320 = out_rivalid_1_170 & out_rimask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3389 = out_f_rivalid_320; // @[RegisterRouter.scala:87:24]
wire out_f_roready_320 = out_roready_1_170 & out_romask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3390 = out_f_roready_320; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_320 = out_wivalid_1_170 & out_wimask_320; // @[RegisterRouter.scala:87:24]
wire out_f_woready_320 = out_woready_1_170 & out_womask_320; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3388 = out_front_1_bits_data[63:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_3391 = ~out_rimask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3392 = ~out_wimask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3393 = ~out_romask_320; // @[RegisterRouter.scala:87:24]
wire _out_T_3394 = ~out_womask_320; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_260 = {abstractGeneratedMem_1, _out_prepend_T_260}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3395 = out_prepend_260; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3396 = _out_T_3395; // @[RegisterRouter.scala:87:24]
wire out_rimask_321 = |_out_rimask_T_321; // @[RegisterRouter.scala:87:24]
wire out_wimask_321 = &_out_wimask_T_321; // @[RegisterRouter.scala:87:24]
wire out_romask_321 = |_out_romask_T_321; // @[RegisterRouter.scala:87:24]
wire out_womask_321 = &_out_womask_T_321; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_321 = out_rivalid_1_171 & out_rimask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3398 = out_f_rivalid_321; // @[RegisterRouter.scala:87:24]
wire out_f_roready_321 = out_roready_1_171 & out_romask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3399 = out_f_roready_321; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_321 = out_wivalid_1_171 & out_wimask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3400 = out_f_wivalid_321; // @[RegisterRouter.scala:87:24]
wire out_f_woready_321 = out_woready_1_171 & out_womask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3401 = out_f_woready_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3402 = ~out_rimask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3403 = ~out_wimask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3404 = ~out_romask_321; // @[RegisterRouter.scala:87:24]
wire _out_T_3405 = ~out_womask_321; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3407 = _out_T_3406; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_261 = _out_T_3407; // @[RegisterRouter.scala:87:24]
wire out_rimask_322 = |_out_rimask_T_322; // @[RegisterRouter.scala:87:24]
wire out_wimask_322 = &_out_wimask_T_322; // @[RegisterRouter.scala:87:24]
wire out_romask_322 = |_out_romask_T_322; // @[RegisterRouter.scala:87:24]
wire out_womask_322 = &_out_womask_T_322; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_322 = out_rivalid_1_172 & out_rimask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3409 = out_f_rivalid_322; // @[RegisterRouter.scala:87:24]
wire out_f_roready_322 = out_roready_1_172 & out_romask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3410 = out_f_roready_322; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_322 = out_wivalid_1_172 & out_wimask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3411 = out_f_wivalid_322; // @[RegisterRouter.scala:87:24]
wire out_f_woready_322 = out_woready_1_172 & out_womask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3412 = out_f_woready_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3413 = ~out_rimask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3414 = ~out_wimask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3415 = ~out_romask_322; // @[RegisterRouter.scala:87:24]
wire _out_T_3416 = ~out_womask_322; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_261 = {programBufferMem_33, _out_prepend_T_261}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3417 = out_prepend_261; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3418 = _out_T_3417; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_262 = _out_T_3418; // @[RegisterRouter.scala:87:24]
wire out_rimask_323 = |_out_rimask_T_323; // @[RegisterRouter.scala:87:24]
wire out_wimask_323 = &_out_wimask_T_323; // @[RegisterRouter.scala:87:24]
wire out_romask_323 = |_out_romask_T_323; // @[RegisterRouter.scala:87:24]
wire out_womask_323 = &_out_womask_T_323; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_323 = out_rivalid_1_173 & out_rimask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3420 = out_f_rivalid_323; // @[RegisterRouter.scala:87:24]
wire out_f_roready_323 = out_roready_1_173 & out_romask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3421 = out_f_roready_323; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_323 = out_wivalid_1_173 & out_wimask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3422 = out_f_wivalid_323; // @[RegisterRouter.scala:87:24]
wire out_f_woready_323 = out_woready_1_173 & out_womask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3423 = out_f_woready_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3424 = ~out_rimask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3425 = ~out_wimask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3426 = ~out_romask_323; // @[RegisterRouter.scala:87:24]
wire _out_T_3427 = ~out_womask_323; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_262 = {programBufferMem_34, _out_prepend_T_262}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3428 = out_prepend_262; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3429 = _out_T_3428; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_263 = _out_T_3429; // @[RegisterRouter.scala:87:24]
wire out_rimask_324 = |_out_rimask_T_324; // @[RegisterRouter.scala:87:24]
wire out_wimask_324 = &_out_wimask_T_324; // @[RegisterRouter.scala:87:24]
wire out_romask_324 = |_out_romask_T_324; // @[RegisterRouter.scala:87:24]
wire out_womask_324 = &_out_womask_T_324; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_324 = out_rivalid_1_174 & out_rimask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3431 = out_f_rivalid_324; // @[RegisterRouter.scala:87:24]
wire out_f_roready_324 = out_roready_1_174 & out_romask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3432 = out_f_roready_324; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_324 = out_wivalid_1_174 & out_wimask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3433 = out_f_wivalid_324; // @[RegisterRouter.scala:87:24]
wire out_f_woready_324 = out_woready_1_174 & out_womask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3434 = out_f_woready_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3435 = ~out_rimask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3436 = ~out_wimask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3437 = ~out_romask_324; // @[RegisterRouter.scala:87:24]
wire _out_T_3438 = ~out_womask_324; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_263 = {programBufferMem_35, _out_prepend_T_263}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3439 = out_prepend_263; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3440 = _out_T_3439; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_264 = _out_T_3440; // @[RegisterRouter.scala:87:24]
wire out_rimask_325 = |_out_rimask_T_325; // @[RegisterRouter.scala:87:24]
wire out_wimask_325 = &_out_wimask_T_325; // @[RegisterRouter.scala:87:24]
wire out_romask_325 = |_out_romask_T_325; // @[RegisterRouter.scala:87:24]
wire out_womask_325 = &_out_womask_T_325; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_325 = out_rivalid_1_175 & out_rimask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3442 = out_f_rivalid_325; // @[RegisterRouter.scala:87:24]
wire out_f_roready_325 = out_roready_1_175 & out_romask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3443 = out_f_roready_325; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_325 = out_wivalid_1_175 & out_wimask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3444 = out_f_wivalid_325; // @[RegisterRouter.scala:87:24]
wire out_f_woready_325 = out_woready_1_175 & out_womask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3445 = out_f_woready_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3446 = ~out_rimask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3447 = ~out_wimask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3448 = ~out_romask_325; // @[RegisterRouter.scala:87:24]
wire _out_T_3449 = ~out_womask_325; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_264 = {programBufferMem_36, _out_prepend_T_264}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3450 = out_prepend_264; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3451 = _out_T_3450; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_265 = _out_T_3451; // @[RegisterRouter.scala:87:24]
wire out_rimask_326 = |_out_rimask_T_326; // @[RegisterRouter.scala:87:24]
wire out_wimask_326 = &_out_wimask_T_326; // @[RegisterRouter.scala:87:24]
wire out_romask_326 = |_out_romask_T_326; // @[RegisterRouter.scala:87:24]
wire out_womask_326 = &_out_womask_T_326; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_326 = out_rivalid_1_176 & out_rimask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3453 = out_f_rivalid_326; // @[RegisterRouter.scala:87:24]
wire out_f_roready_326 = out_roready_1_176 & out_romask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3454 = out_f_roready_326; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_326 = out_wivalid_1_176 & out_wimask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3455 = out_f_wivalid_326; // @[RegisterRouter.scala:87:24]
wire out_f_woready_326 = out_woready_1_176 & out_womask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3456 = out_f_woready_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3457 = ~out_rimask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3458 = ~out_wimask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3459 = ~out_romask_326; // @[RegisterRouter.scala:87:24]
wire _out_T_3460 = ~out_womask_326; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_265 = {programBufferMem_37, _out_prepend_T_265}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3461 = out_prepend_265; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3462 = _out_T_3461; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_266 = _out_T_3462; // @[RegisterRouter.scala:87:24]
wire out_rimask_327 = |_out_rimask_T_327; // @[RegisterRouter.scala:87:24]
wire out_wimask_327 = &_out_wimask_T_327; // @[RegisterRouter.scala:87:24]
wire out_romask_327 = |_out_romask_T_327; // @[RegisterRouter.scala:87:24]
wire out_womask_327 = &_out_womask_T_327; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_327 = out_rivalid_1_177 & out_rimask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3464 = out_f_rivalid_327; // @[RegisterRouter.scala:87:24]
wire out_f_roready_327 = out_roready_1_177 & out_romask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3465 = out_f_roready_327; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_327 = out_wivalid_1_177 & out_wimask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3466 = out_f_wivalid_327; // @[RegisterRouter.scala:87:24]
wire out_f_woready_327 = out_woready_1_177 & out_womask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3467 = out_f_woready_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3468 = ~out_rimask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3469 = ~out_wimask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3470 = ~out_romask_327; // @[RegisterRouter.scala:87:24]
wire _out_T_3471 = ~out_womask_327; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_266 = {programBufferMem_38, _out_prepend_T_266}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3472 = out_prepend_266; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3473 = _out_T_3472; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_267 = _out_T_3473; // @[RegisterRouter.scala:87:24]
wire out_rimask_328 = |_out_rimask_T_328; // @[RegisterRouter.scala:87:24]
wire out_wimask_328 = &_out_wimask_T_328; // @[RegisterRouter.scala:87:24]
wire out_romask_328 = |_out_romask_T_328; // @[RegisterRouter.scala:87:24]
wire out_womask_328 = &_out_womask_T_328; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_328 = out_rivalid_1_178 & out_rimask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3475 = out_f_rivalid_328; // @[RegisterRouter.scala:87:24]
wire out_f_roready_328 = out_roready_1_178 & out_romask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3476 = out_f_roready_328; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_328 = out_wivalid_1_178 & out_wimask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3477 = out_f_wivalid_328; // @[RegisterRouter.scala:87:24]
wire out_f_woready_328 = out_woready_1_178 & out_womask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3478 = out_f_woready_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3479 = ~out_rimask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3480 = ~out_wimask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3481 = ~out_romask_328; // @[RegisterRouter.scala:87:24]
wire _out_T_3482 = ~out_womask_328; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_267 = {programBufferMem_39, _out_prepend_T_267}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3483 = out_prepend_267; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3484 = _out_T_3483; // @[RegisterRouter.scala:87:24]
wire out_rimask_329 = |_out_rimask_T_329; // @[RegisterRouter.scala:87:24]
wire out_wimask_329 = &_out_wimask_T_329; // @[RegisterRouter.scala:87:24]
wire out_romask_329 = |_out_romask_T_329; // @[RegisterRouter.scala:87:24]
wire out_womask_329 = &_out_womask_T_329; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_329 = out_rivalid_1_179 & out_rimask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3486 = out_f_rivalid_329; // @[RegisterRouter.scala:87:24]
wire out_f_roready_329 = out_roready_1_179 & out_romask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3487 = out_f_roready_329; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_329 = out_wivalid_1_179 & out_wimask_329; // @[RegisterRouter.scala:87:24]
wire out_f_woready_329 = out_woready_1_179 & out_womask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3488 = ~out_rimask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3489 = ~out_wimask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3490 = ~out_romask_329; // @[RegisterRouter.scala:87:24]
wire _out_T_3491 = ~out_womask_329; // @[RegisterRouter.scala:87:24]
wire out_rimask_330 = |_out_rimask_T_330; // @[RegisterRouter.scala:87:24]
wire out_wimask_330 = &_out_wimask_T_330; // @[RegisterRouter.scala:87:24]
wire out_romask_330 = |_out_romask_T_330; // @[RegisterRouter.scala:87:24]
wire out_womask_330 = &_out_womask_T_330; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_330 = out_rivalid_1_180 & out_rimask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3495 = out_f_rivalid_330; // @[RegisterRouter.scala:87:24]
wire out_f_roready_330 = out_roready_1_180 & out_romask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3496 = out_f_roready_330; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_330 = out_wivalid_1_180 & out_wimask_330; // @[RegisterRouter.scala:87:24]
wire out_f_woready_330 = out_woready_1_180 & out_womask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3497 = ~out_rimask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3498 = ~out_wimask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3499 = ~out_romask_330; // @[RegisterRouter.scala:87:24]
wire _out_T_3500 = ~out_womask_330; // @[RegisterRouter.scala:87:24]
wire out_rimask_331 = |_out_rimask_T_331; // @[RegisterRouter.scala:87:24]
wire out_wimask_331 = &_out_wimask_T_331; // @[RegisterRouter.scala:87:24]
wire out_romask_331 = |_out_romask_T_331; // @[RegisterRouter.scala:87:24]
wire out_womask_331 = &_out_womask_T_331; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_331 = out_rivalid_1_181 & out_rimask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3504 = out_f_rivalid_331; // @[RegisterRouter.scala:87:24]
wire out_f_roready_331 = out_roready_1_181 & out_romask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3505 = out_f_roready_331; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_331 = out_wivalid_1_181 & out_wimask_331; // @[RegisterRouter.scala:87:24]
wire out_f_woready_331 = out_woready_1_181 & out_womask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3506 = ~out_rimask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3507 = ~out_wimask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3508 = ~out_romask_331; // @[RegisterRouter.scala:87:24]
wire _out_T_3509 = ~out_womask_331; // @[RegisterRouter.scala:87:24]
wire out_rimask_332 = |_out_rimask_T_332; // @[RegisterRouter.scala:87:24]
wire out_wimask_332 = &_out_wimask_T_332; // @[RegisterRouter.scala:87:24]
wire out_romask_332 = |_out_romask_T_332; // @[RegisterRouter.scala:87:24]
wire out_womask_332 = &_out_womask_T_332; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_332 = out_rivalid_1_182 & out_rimask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3513 = out_f_rivalid_332; // @[RegisterRouter.scala:87:24]
wire out_f_roready_332 = out_roready_1_182 & out_romask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3514 = out_f_roready_332; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_332 = out_wivalid_1_182 & out_wimask_332; // @[RegisterRouter.scala:87:24]
wire out_f_woready_332 = out_woready_1_182 & out_womask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3515 = ~out_rimask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3516 = ~out_wimask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3517 = ~out_romask_332; // @[RegisterRouter.scala:87:24]
wire _out_T_3518 = ~out_womask_332; // @[RegisterRouter.scala:87:24]
wire out_rimask_333 = |_out_rimask_T_333; // @[RegisterRouter.scala:87:24]
wire out_wimask_333 = &_out_wimask_T_333; // @[RegisterRouter.scala:87:24]
wire out_romask_333 = |_out_romask_T_333; // @[RegisterRouter.scala:87:24]
wire out_womask_333 = &_out_womask_T_333; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_333 = out_rivalid_1_183 & out_rimask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3522 = out_f_rivalid_333; // @[RegisterRouter.scala:87:24]
wire out_f_roready_333 = out_roready_1_183 & out_romask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3523 = out_f_roready_333; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_333 = out_wivalid_1_183 & out_wimask_333; // @[RegisterRouter.scala:87:24]
wire out_f_woready_333 = out_woready_1_183 & out_womask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3524 = ~out_rimask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3525 = ~out_wimask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3526 = ~out_romask_333; // @[RegisterRouter.scala:87:24]
wire _out_T_3527 = ~out_womask_333; // @[RegisterRouter.scala:87:24]
wire out_rimask_334 = |_out_rimask_T_334; // @[RegisterRouter.scala:87:24]
wire out_wimask_334 = &_out_wimask_T_334; // @[RegisterRouter.scala:87:24]
wire out_romask_334 = |_out_romask_T_334; // @[RegisterRouter.scala:87:24]
wire out_womask_334 = &_out_womask_T_334; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_334 = out_rivalid_1_184 & out_rimask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3531 = out_f_rivalid_334; // @[RegisterRouter.scala:87:24]
wire out_f_roready_334 = out_roready_1_184 & out_romask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3532 = out_f_roready_334; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_334 = out_wivalid_1_184 & out_wimask_334; // @[RegisterRouter.scala:87:24]
wire out_f_woready_334 = out_woready_1_184 & out_womask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3533 = ~out_rimask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3534 = ~out_wimask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3535 = ~out_romask_334; // @[RegisterRouter.scala:87:24]
wire _out_T_3536 = ~out_womask_334; // @[RegisterRouter.scala:87:24]
wire out_rimask_335 = |_out_rimask_T_335; // @[RegisterRouter.scala:87:24]
wire out_wimask_335 = &_out_wimask_T_335; // @[RegisterRouter.scala:87:24]
wire out_romask_335 = |_out_romask_T_335; // @[RegisterRouter.scala:87:24]
wire out_womask_335 = &_out_womask_T_335; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_335 = out_rivalid_1_185 & out_rimask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3540 = out_f_rivalid_335; // @[RegisterRouter.scala:87:24]
wire out_f_roready_335 = out_roready_1_185 & out_romask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3541 = out_f_roready_335; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_335 = out_wivalid_1_185 & out_wimask_335; // @[RegisterRouter.scala:87:24]
wire out_f_woready_335 = out_woready_1_185 & out_womask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3542 = ~out_rimask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3543 = ~out_wimask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3544 = ~out_romask_335; // @[RegisterRouter.scala:87:24]
wire _out_T_3545 = ~out_womask_335; // @[RegisterRouter.scala:87:24]
wire out_rimask_336 = |_out_rimask_T_336; // @[RegisterRouter.scala:87:24]
wire out_wimask_336 = &_out_wimask_T_336; // @[RegisterRouter.scala:87:24]
wire out_romask_336 = |_out_romask_T_336; // @[RegisterRouter.scala:87:24]
wire out_womask_336 = &_out_womask_T_336; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_336 = out_rivalid_1_186 & out_rimask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3549 = out_f_rivalid_336; // @[RegisterRouter.scala:87:24]
wire out_f_roready_336 = out_roready_1_186 & out_romask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3550 = out_f_roready_336; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_336 = out_wivalid_1_186 & out_wimask_336; // @[RegisterRouter.scala:87:24]
wire out_f_woready_336 = out_woready_1_186 & out_womask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3551 = ~out_rimask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3552 = ~out_wimask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3553 = ~out_romask_336; // @[RegisterRouter.scala:87:24]
wire _out_T_3554 = ~out_womask_336; // @[RegisterRouter.scala:87:24]
wire out_rimask_337 = |_out_rimask_T_337; // @[RegisterRouter.scala:87:24]
wire out_wimask_337 = &_out_wimask_T_337; // @[RegisterRouter.scala:87:24]
wire out_romask_337 = |_out_romask_T_337; // @[RegisterRouter.scala:87:24]
wire out_womask_337 = &_out_womask_T_337; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_337 = out_rivalid_1_187 & out_rimask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3558 = out_f_rivalid_337; // @[RegisterRouter.scala:87:24]
wire out_f_roready_337 = out_roready_1_187 & out_romask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3559 = out_f_roready_337; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_337 = out_wivalid_1_187 & out_wimask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3560 = out_f_wivalid_337; // @[RegisterRouter.scala:87:24]
wire out_f_woready_337 = out_woready_1_187 & out_womask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3561 = out_f_woready_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3562 = ~out_rimask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3563 = ~out_wimask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3564 = ~out_romask_337; // @[RegisterRouter.scala:87:24]
wire _out_T_3565 = ~out_womask_337; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_3567 = _out_T_3566; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T_275 = _out_T_3567; // @[RegisterRouter.scala:87:24]
wire out_rimask_338 = |_out_rimask_T_338; // @[RegisterRouter.scala:87:24]
wire out_wimask_338 = &_out_wimask_T_338; // @[RegisterRouter.scala:87:24]
wire out_romask_338 = |_out_romask_T_338; // @[RegisterRouter.scala:87:24]
wire out_womask_338 = &_out_womask_T_338; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_338 = out_rivalid_1_188 & out_rimask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3569 = out_f_rivalid_338; // @[RegisterRouter.scala:87:24]
wire out_f_roready_338 = out_roready_1_188 & out_romask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3570 = out_f_roready_338; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_338 = out_wivalid_1_188 & out_wimask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3571 = out_f_wivalid_338; // @[RegisterRouter.scala:87:24]
wire out_f_woready_338 = out_woready_1_188 & out_womask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3572 = out_f_woready_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3573 = ~out_rimask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3574 = ~out_wimask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3575 = ~out_romask_338; // @[RegisterRouter.scala:87:24]
wire _out_T_3576 = ~out_womask_338; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_275 = {abstractDataMem_17, _out_prepend_T_275}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3577 = out_prepend_275; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_3578 = _out_T_3577; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_276 = _out_T_3578; // @[RegisterRouter.scala:87:24]
wire out_rimask_339 = |_out_rimask_T_339; // @[RegisterRouter.scala:87:24]
wire out_wimask_339 = &_out_wimask_T_339; // @[RegisterRouter.scala:87:24]
wire out_romask_339 = |_out_romask_T_339; // @[RegisterRouter.scala:87:24]
wire out_womask_339 = &_out_womask_T_339; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_339 = out_rivalid_1_189 & out_rimask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3580 = out_f_rivalid_339; // @[RegisterRouter.scala:87:24]
wire out_f_roready_339 = out_roready_1_189 & out_romask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3581 = out_f_roready_339; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_339 = out_wivalid_1_189 & out_wimask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3582 = out_f_wivalid_339; // @[RegisterRouter.scala:87:24]
wire out_f_woready_339 = out_woready_1_189 & out_womask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3583 = out_f_woready_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3584 = ~out_rimask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3585 = ~out_wimask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3586 = ~out_romask_339; // @[RegisterRouter.scala:87:24]
wire _out_T_3587 = ~out_womask_339; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_276 = {abstractDataMem_18, _out_prepend_T_276}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3588 = out_prepend_276; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_3589 = _out_T_3588; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_277 = _out_T_3589; // @[RegisterRouter.scala:87:24]
wire out_rimask_340 = |_out_rimask_T_340; // @[RegisterRouter.scala:87:24]
wire out_wimask_340 = &_out_wimask_T_340; // @[RegisterRouter.scala:87:24]
wire out_romask_340 = |_out_romask_T_340; // @[RegisterRouter.scala:87:24]
wire out_womask_340 = &_out_womask_T_340; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_340 = out_rivalid_1_190 & out_rimask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3591 = out_f_rivalid_340; // @[RegisterRouter.scala:87:24]
wire out_f_roready_340 = out_roready_1_190 & out_romask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3592 = out_f_roready_340; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_340 = out_wivalid_1_190 & out_wimask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3593 = out_f_wivalid_340; // @[RegisterRouter.scala:87:24]
wire out_f_woready_340 = out_woready_1_190 & out_womask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3594 = out_f_woready_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3595 = ~out_rimask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3596 = ~out_wimask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3597 = ~out_romask_340; // @[RegisterRouter.scala:87:24]
wire _out_T_3598 = ~out_womask_340; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_277 = {abstractDataMem_19, _out_prepend_T_277}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3599 = out_prepend_277; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_3600 = _out_T_3599; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_278 = _out_T_3600; // @[RegisterRouter.scala:87:24]
wire out_rimask_341 = |_out_rimask_T_341; // @[RegisterRouter.scala:87:24]
wire out_wimask_341 = &_out_wimask_T_341; // @[RegisterRouter.scala:87:24]
wire out_romask_341 = |_out_romask_T_341; // @[RegisterRouter.scala:87:24]
wire out_womask_341 = &_out_womask_T_341; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_341 = out_rivalid_1_191 & out_rimask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3602 = out_f_rivalid_341; // @[RegisterRouter.scala:87:24]
wire out_f_roready_341 = out_roready_1_191 & out_romask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3603 = out_f_roready_341; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_341 = out_wivalid_1_191 & out_wimask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3604 = out_f_wivalid_341; // @[RegisterRouter.scala:87:24]
wire out_f_woready_341 = out_woready_1_191 & out_womask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3605 = out_f_woready_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3606 = ~out_rimask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3607 = ~out_wimask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3608 = ~out_romask_341; // @[RegisterRouter.scala:87:24]
wire _out_T_3609 = ~out_womask_341; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_278 = {abstractDataMem_20, _out_prepend_T_278}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3610 = out_prepend_278; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_3611 = _out_T_3610; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_279 = _out_T_3611; // @[RegisterRouter.scala:87:24]
wire out_rimask_342 = |_out_rimask_T_342; // @[RegisterRouter.scala:87:24]
wire out_wimask_342 = &_out_wimask_T_342; // @[RegisterRouter.scala:87:24]
wire out_romask_342 = |_out_romask_T_342; // @[RegisterRouter.scala:87:24]
wire out_womask_342 = &_out_womask_T_342; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_342 = out_rivalid_1_192 & out_rimask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3613 = out_f_rivalid_342; // @[RegisterRouter.scala:87:24]
wire out_f_roready_342 = out_roready_1_192 & out_romask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3614 = out_f_roready_342; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_342 = out_wivalid_1_192 & out_wimask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3615 = out_f_wivalid_342; // @[RegisterRouter.scala:87:24]
wire out_f_woready_342 = out_woready_1_192 & out_womask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3616 = out_f_woready_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3617 = ~out_rimask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3618 = ~out_wimask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3619 = ~out_romask_342; // @[RegisterRouter.scala:87:24]
wire _out_T_3620 = ~out_womask_342; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_279 = {abstractDataMem_21, _out_prepend_T_279}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3621 = out_prepend_279; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_3622 = _out_T_3621; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_280 = _out_T_3622; // @[RegisterRouter.scala:87:24]
wire out_rimask_343 = |_out_rimask_T_343; // @[RegisterRouter.scala:87:24]
wire out_wimask_343 = &_out_wimask_T_343; // @[RegisterRouter.scala:87:24]
wire out_romask_343 = |_out_romask_T_343; // @[RegisterRouter.scala:87:24]
wire out_womask_343 = &_out_womask_T_343; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_343 = out_rivalid_1_193 & out_rimask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3624 = out_f_rivalid_343; // @[RegisterRouter.scala:87:24]
wire out_f_roready_343 = out_roready_1_193 & out_romask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3625 = out_f_roready_343; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_343 = out_wivalid_1_193 & out_wimask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3626 = out_f_wivalid_343; // @[RegisterRouter.scala:87:24]
wire out_f_woready_343 = out_woready_1_193 & out_womask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3627 = out_f_woready_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3628 = ~out_rimask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3629 = ~out_wimask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3630 = ~out_romask_343; // @[RegisterRouter.scala:87:24]
wire _out_T_3631 = ~out_womask_343; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_280 = {abstractDataMem_22, _out_prepend_T_280}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3632 = out_prepend_280; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_3633 = _out_T_3632; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_281 = _out_T_3633; // @[RegisterRouter.scala:87:24]
wire out_rimask_344 = |_out_rimask_T_344; // @[RegisterRouter.scala:87:24]
wire out_wimask_344 = &_out_wimask_T_344; // @[RegisterRouter.scala:87:24]
wire out_romask_344 = |_out_romask_T_344; // @[RegisterRouter.scala:87:24]
wire out_womask_344 = &_out_womask_T_344; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_344 = out_rivalid_1_194 & out_rimask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3635 = out_f_rivalid_344; // @[RegisterRouter.scala:87:24]
wire out_f_roready_344 = out_roready_1_194 & out_romask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3636 = out_f_roready_344; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_344 = out_wivalid_1_194 & out_wimask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3637 = out_f_wivalid_344; // @[RegisterRouter.scala:87:24]
wire out_f_woready_344 = out_woready_1_194 & out_womask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3638 = out_f_woready_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3639 = ~out_rimask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3640 = ~out_wimask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3641 = ~out_romask_344; // @[RegisterRouter.scala:87:24]
wire _out_T_3642 = ~out_womask_344; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_281 = {abstractDataMem_23, _out_prepend_T_281}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3643 = out_prepend_281; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_3644 = _out_T_3643; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = out_front_1_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = out_front_1_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_9 = out_front_1_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_10 = out_front_1_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_11 = out_front_1_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_12 = out_front_1_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_13 = out_front_1_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_14 = out_front_1_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_15 = out_front_1_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_lo_lo = {_out_iindex_T_8, _out_iindex_T_7}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_lo_hi_1 = {_out_iindex_T_10, _out_iindex_T_9}; // @[RegisterRouter.scala:87:24]
wire [3:0] out_iindex_lo_1 = {out_iindex_lo_hi_1, out_iindex_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_hi_lo = {_out_iindex_T_13, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex_hi_hi_1 = {_out_iindex_T_15, _out_iindex_T_14}; // @[RegisterRouter.scala:87:24]
wire [3:0] out_iindex_hi_1 = {out_iindex_hi_hi_1, out_iindex_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] out_iindex_1 = {out_iindex_hi_1, out_iindex_lo_1}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_lo_lo = {_out_oindex_T_8, _out_oindex_T_7}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_lo_hi_1 = {_out_oindex_T_10, _out_oindex_T_9}; // @[RegisterRouter.scala:87:24]
wire [3:0] out_oindex_lo_1 = {out_oindex_lo_hi_1, out_oindex_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_hi_lo = {_out_oindex_T_13, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex_hi_hi_1 = {_out_oindex_T_15, _out_oindex_T_14}; // @[RegisterRouter.scala:87:24]
wire [3:0] out_oindex_hi_1 = {out_oindex_hi_hi_1, out_oindex_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] out_oindex_1 = {out_oindex_hi_1, out_oindex_lo_1}; // @[RegisterRouter.scala:87:24]
wire [255:0] _out_frontSel_T_1 = 256'h1 << out_iindex_1; // @[OneHot.scala:58:35]
wire out_frontSel_0_1 = _out_frontSel_T_1[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1_1 = _out_frontSel_T_1[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2_1 = _out_frontSel_T_1[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3_1 = _out_frontSel_T_1[3]; // @[OneHot.scala:58:35]
wire out_frontSel_4_1 = _out_frontSel_T_1[4]; // @[OneHot.scala:58:35]
wire out_frontSel_5_1 = _out_frontSel_T_1[5]; // @[OneHot.scala:58:35]
wire out_frontSel_6_1 = _out_frontSel_T_1[6]; // @[OneHot.scala:58:35]
wire out_frontSel_7_1 = _out_frontSel_T_1[7]; // @[OneHot.scala:58:35]
wire out_frontSel_8_1 = _out_frontSel_T_1[8]; // @[OneHot.scala:58:35]
wire out_frontSel_9_1 = _out_frontSel_T_1[9]; // @[OneHot.scala:58:35]
wire out_frontSel_10_1 = _out_frontSel_T_1[10]; // @[OneHot.scala:58:35]
wire out_frontSel_11_1 = _out_frontSel_T_1[11]; // @[OneHot.scala:58:35]
wire out_frontSel_12_1 = _out_frontSel_T_1[12]; // @[OneHot.scala:58:35]
wire out_frontSel_13_1 = _out_frontSel_T_1[13]; // @[OneHot.scala:58:35]
wire out_frontSel_14_1 = _out_frontSel_T_1[14]; // @[OneHot.scala:58:35]
wire out_frontSel_15_1 = _out_frontSel_T_1[15]; // @[OneHot.scala:58:35]
wire out_frontSel_16_1 = _out_frontSel_T_1[16]; // @[OneHot.scala:58:35]
wire out_frontSel_17_1 = _out_frontSel_T_1[17]; // @[OneHot.scala:58:35]
wire out_frontSel_18_1 = _out_frontSel_T_1[18]; // @[OneHot.scala:58:35]
wire out_frontSel_19_1 = _out_frontSel_T_1[19]; // @[OneHot.scala:58:35]
wire out_frontSel_20_1 = _out_frontSel_T_1[20]; // @[OneHot.scala:58:35]
wire out_frontSel_21_1 = _out_frontSel_T_1[21]; // @[OneHot.scala:58:35]
wire out_frontSel_22_1 = _out_frontSel_T_1[22]; // @[OneHot.scala:58:35]
wire out_frontSel_23_1 = _out_frontSel_T_1[23]; // @[OneHot.scala:58:35]
wire out_frontSel_24_1 = _out_frontSel_T_1[24]; // @[OneHot.scala:58:35]
wire out_frontSel_25_1 = _out_frontSel_T_1[25]; // @[OneHot.scala:58:35]
wire out_frontSel_26_1 = _out_frontSel_T_1[26]; // @[OneHot.scala:58:35]
wire out_frontSel_27_1 = _out_frontSel_T_1[27]; // @[OneHot.scala:58:35]
wire out_frontSel_28_1 = _out_frontSel_T_1[28]; // @[OneHot.scala:58:35]
wire out_frontSel_29_1 = _out_frontSel_T_1[29]; // @[OneHot.scala:58:35]
wire out_frontSel_30_1 = _out_frontSel_T_1[30]; // @[OneHot.scala:58:35]
wire out_frontSel_31_1 = _out_frontSel_T_1[31]; // @[OneHot.scala:58:35]
wire out_frontSel_32_1 = _out_frontSel_T_1[32]; // @[OneHot.scala:58:35]
wire out_frontSel_33_1 = _out_frontSel_T_1[33]; // @[OneHot.scala:58:35]
wire out_frontSel_34_1 = _out_frontSel_T_1[34]; // @[OneHot.scala:58:35]
wire out_frontSel_35_1 = _out_frontSel_T_1[35]; // @[OneHot.scala:58:35]
wire out_frontSel_36_1 = _out_frontSel_T_1[36]; // @[OneHot.scala:58:35]
wire out_frontSel_37_1 = _out_frontSel_T_1[37]; // @[OneHot.scala:58:35]
wire out_frontSel_38_1 = _out_frontSel_T_1[38]; // @[OneHot.scala:58:35]
wire out_frontSel_39_1 = _out_frontSel_T_1[39]; // @[OneHot.scala:58:35]
wire out_frontSel_40_1 = _out_frontSel_T_1[40]; // @[OneHot.scala:58:35]
wire out_frontSel_41_1 = _out_frontSel_T_1[41]; // @[OneHot.scala:58:35]
wire out_frontSel_42_1 = _out_frontSel_T_1[42]; // @[OneHot.scala:58:35]
wire out_frontSel_43_1 = _out_frontSel_T_1[43]; // @[OneHot.scala:58:35]
wire out_frontSel_44_1 = _out_frontSel_T_1[44]; // @[OneHot.scala:58:35]
wire out_frontSel_45_1 = _out_frontSel_T_1[45]; // @[OneHot.scala:58:35]
wire out_frontSel_46_1 = _out_frontSel_T_1[46]; // @[OneHot.scala:58:35]
wire out_frontSel_47_1 = _out_frontSel_T_1[47]; // @[OneHot.scala:58:35]
wire out_frontSel_48_1 = _out_frontSel_T_1[48]; // @[OneHot.scala:58:35]
wire out_frontSel_49_1 = _out_frontSel_T_1[49]; // @[OneHot.scala:58:35]
wire out_frontSel_50_1 = _out_frontSel_T_1[50]; // @[OneHot.scala:58:35]
wire out_frontSel_51_1 = _out_frontSel_T_1[51]; // @[OneHot.scala:58:35]
wire out_frontSel_52_1 = _out_frontSel_T_1[52]; // @[OneHot.scala:58:35]
wire out_frontSel_53_1 = _out_frontSel_T_1[53]; // @[OneHot.scala:58:35]
wire out_frontSel_54_1 = _out_frontSel_T_1[54]; // @[OneHot.scala:58:35]
wire out_frontSel_55_1 = _out_frontSel_T_1[55]; // @[OneHot.scala:58:35]
wire out_frontSel_56_1 = _out_frontSel_T_1[56]; // @[OneHot.scala:58:35]
wire out_frontSel_57_1 = _out_frontSel_T_1[57]; // @[OneHot.scala:58:35]
wire out_frontSel_58_1 = _out_frontSel_T_1[58]; // @[OneHot.scala:58:35]
wire out_frontSel_59_1 = _out_frontSel_T_1[59]; // @[OneHot.scala:58:35]
wire out_frontSel_60_1 = _out_frontSel_T_1[60]; // @[OneHot.scala:58:35]
wire out_frontSel_61_1 = _out_frontSel_T_1[61]; // @[OneHot.scala:58:35]
wire out_frontSel_62_1 = _out_frontSel_T_1[62]; // @[OneHot.scala:58:35]
wire out_frontSel_63_1 = _out_frontSel_T_1[63]; // @[OneHot.scala:58:35]
wire out_frontSel_64 = _out_frontSel_T_1[64]; // @[OneHot.scala:58:35]
wire out_frontSel_65 = _out_frontSel_T_1[65]; // @[OneHot.scala:58:35]
wire out_frontSel_66 = _out_frontSel_T_1[66]; // @[OneHot.scala:58:35]
wire out_frontSel_67 = _out_frontSel_T_1[67]; // @[OneHot.scala:58:35]
wire out_frontSel_68 = _out_frontSel_T_1[68]; // @[OneHot.scala:58:35]
wire out_frontSel_69 = _out_frontSel_T_1[69]; // @[OneHot.scala:58:35]
wire out_frontSel_70 = _out_frontSel_T_1[70]; // @[OneHot.scala:58:35]
wire out_frontSel_71 = _out_frontSel_T_1[71]; // @[OneHot.scala:58:35]
wire out_frontSel_72 = _out_frontSel_T_1[72]; // @[OneHot.scala:58:35]
wire out_frontSel_73 = _out_frontSel_T_1[73]; // @[OneHot.scala:58:35]
wire out_frontSel_74 = _out_frontSel_T_1[74]; // @[OneHot.scala:58:35]
wire out_frontSel_75 = _out_frontSel_T_1[75]; // @[OneHot.scala:58:35]
wire out_frontSel_76 = _out_frontSel_T_1[76]; // @[OneHot.scala:58:35]
wire out_frontSel_77 = _out_frontSel_T_1[77]; // @[OneHot.scala:58:35]
wire out_frontSel_78 = _out_frontSel_T_1[78]; // @[OneHot.scala:58:35]
wire out_frontSel_79 = _out_frontSel_T_1[79]; // @[OneHot.scala:58:35]
wire out_frontSel_80 = _out_frontSel_T_1[80]; // @[OneHot.scala:58:35]
wire out_frontSel_81 = _out_frontSel_T_1[81]; // @[OneHot.scala:58:35]
wire out_frontSel_82 = _out_frontSel_T_1[82]; // @[OneHot.scala:58:35]
wire out_frontSel_83 = _out_frontSel_T_1[83]; // @[OneHot.scala:58:35]
wire out_frontSel_84 = _out_frontSel_T_1[84]; // @[OneHot.scala:58:35]
wire out_frontSel_85 = _out_frontSel_T_1[85]; // @[OneHot.scala:58:35]
wire out_frontSel_86 = _out_frontSel_T_1[86]; // @[OneHot.scala:58:35]
wire out_frontSel_87 = _out_frontSel_T_1[87]; // @[OneHot.scala:58:35]
wire out_frontSel_88 = _out_frontSel_T_1[88]; // @[OneHot.scala:58:35]
wire out_frontSel_89 = _out_frontSel_T_1[89]; // @[OneHot.scala:58:35]
wire out_frontSel_90 = _out_frontSel_T_1[90]; // @[OneHot.scala:58:35]
wire out_frontSel_91 = _out_frontSel_T_1[91]; // @[OneHot.scala:58:35]
wire out_frontSel_92 = _out_frontSel_T_1[92]; // @[OneHot.scala:58:35]
wire out_frontSel_93 = _out_frontSel_T_1[93]; // @[OneHot.scala:58:35]
wire out_frontSel_94 = _out_frontSel_T_1[94]; // @[OneHot.scala:58:35]
wire out_frontSel_95 = _out_frontSel_T_1[95]; // @[OneHot.scala:58:35]
wire out_frontSel_96 = _out_frontSel_T_1[96]; // @[OneHot.scala:58:35]
wire out_frontSel_97 = _out_frontSel_T_1[97]; // @[OneHot.scala:58:35]
wire out_frontSel_98 = _out_frontSel_T_1[98]; // @[OneHot.scala:58:35]
wire out_frontSel_99 = _out_frontSel_T_1[99]; // @[OneHot.scala:58:35]
wire out_frontSel_100 = _out_frontSel_T_1[100]; // @[OneHot.scala:58:35]
wire out_frontSel_101 = _out_frontSel_T_1[101]; // @[OneHot.scala:58:35]
wire out_frontSel_102 = _out_frontSel_T_1[102]; // @[OneHot.scala:58:35]
wire out_frontSel_103 = _out_frontSel_T_1[103]; // @[OneHot.scala:58:35]
wire out_frontSel_104 = _out_frontSel_T_1[104]; // @[OneHot.scala:58:35]
wire out_frontSel_105 = _out_frontSel_T_1[105]; // @[OneHot.scala:58:35]
wire out_frontSel_106 = _out_frontSel_T_1[106]; // @[OneHot.scala:58:35]
wire out_frontSel_107 = _out_frontSel_T_1[107]; // @[OneHot.scala:58:35]
wire out_frontSel_108 = _out_frontSel_T_1[108]; // @[OneHot.scala:58:35]
wire out_frontSel_109 = _out_frontSel_T_1[109]; // @[OneHot.scala:58:35]
wire out_frontSel_110 = _out_frontSel_T_1[110]; // @[OneHot.scala:58:35]
wire out_frontSel_111 = _out_frontSel_T_1[111]; // @[OneHot.scala:58:35]
wire out_frontSel_112 = _out_frontSel_T_1[112]; // @[OneHot.scala:58:35]
wire out_frontSel_113 = _out_frontSel_T_1[113]; // @[OneHot.scala:58:35]
wire out_frontSel_114 = _out_frontSel_T_1[114]; // @[OneHot.scala:58:35]
wire out_frontSel_115 = _out_frontSel_T_1[115]; // @[OneHot.scala:58:35]
wire out_frontSel_116 = _out_frontSel_T_1[116]; // @[OneHot.scala:58:35]
wire out_frontSel_117 = _out_frontSel_T_1[117]; // @[OneHot.scala:58:35]
wire out_frontSel_118 = _out_frontSel_T_1[118]; // @[OneHot.scala:58:35]
wire out_frontSel_119 = _out_frontSel_T_1[119]; // @[OneHot.scala:58:35]
wire out_frontSel_120 = _out_frontSel_T_1[120]; // @[OneHot.scala:58:35]
wire out_frontSel_121 = _out_frontSel_T_1[121]; // @[OneHot.scala:58:35]
wire out_frontSel_122 = _out_frontSel_T_1[122]; // @[OneHot.scala:58:35]
wire out_frontSel_123 = _out_frontSel_T_1[123]; // @[OneHot.scala:58:35]
wire out_frontSel_124 = _out_frontSel_T_1[124]; // @[OneHot.scala:58:35]
wire out_frontSel_125 = _out_frontSel_T_1[125]; // @[OneHot.scala:58:35]
wire out_frontSel_126 = _out_frontSel_T_1[126]; // @[OneHot.scala:58:35]
wire out_frontSel_127 = _out_frontSel_T_1[127]; // @[OneHot.scala:58:35]
wire out_frontSel_128 = _out_frontSel_T_1[128]; // @[OneHot.scala:58:35]
wire out_frontSel_129 = _out_frontSel_T_1[129]; // @[OneHot.scala:58:35]
wire out_frontSel_130 = _out_frontSel_T_1[130]; // @[OneHot.scala:58:35]
wire out_frontSel_131 = _out_frontSel_T_1[131]; // @[OneHot.scala:58:35]
wire out_frontSel_132 = _out_frontSel_T_1[132]; // @[OneHot.scala:58:35]
wire out_frontSel_133 = _out_frontSel_T_1[133]; // @[OneHot.scala:58:35]
wire out_frontSel_134 = _out_frontSel_T_1[134]; // @[OneHot.scala:58:35]
wire out_frontSel_135 = _out_frontSel_T_1[135]; // @[OneHot.scala:58:35]
wire out_frontSel_136 = _out_frontSel_T_1[136]; // @[OneHot.scala:58:35]
wire out_frontSel_137 = _out_frontSel_T_1[137]; // @[OneHot.scala:58:35]
wire out_frontSel_138 = _out_frontSel_T_1[138]; // @[OneHot.scala:58:35]
wire out_frontSel_139 = _out_frontSel_T_1[139]; // @[OneHot.scala:58:35]
wire out_frontSel_140 = _out_frontSel_T_1[140]; // @[OneHot.scala:58:35]
wire out_frontSel_141 = _out_frontSel_T_1[141]; // @[OneHot.scala:58:35]
wire out_frontSel_142 = _out_frontSel_T_1[142]; // @[OneHot.scala:58:35]
wire out_frontSel_143 = _out_frontSel_T_1[143]; // @[OneHot.scala:58:35]
wire out_frontSel_144 = _out_frontSel_T_1[144]; // @[OneHot.scala:58:35]
wire out_frontSel_145 = _out_frontSel_T_1[145]; // @[OneHot.scala:58:35]
wire out_frontSel_146 = _out_frontSel_T_1[146]; // @[OneHot.scala:58:35]
wire out_frontSel_147 = _out_frontSel_T_1[147]; // @[OneHot.scala:58:35]
wire out_frontSel_148 = _out_frontSel_T_1[148]; // @[OneHot.scala:58:35]
wire out_frontSel_149 = _out_frontSel_T_1[149]; // @[OneHot.scala:58:35]
wire out_frontSel_150 = _out_frontSel_T_1[150]; // @[OneHot.scala:58:35]
wire out_frontSel_151 = _out_frontSel_T_1[151]; // @[OneHot.scala:58:35]
wire out_frontSel_152 = _out_frontSel_T_1[152]; // @[OneHot.scala:58:35]
wire out_frontSel_153 = _out_frontSel_T_1[153]; // @[OneHot.scala:58:35]
wire out_frontSel_154 = _out_frontSel_T_1[154]; // @[OneHot.scala:58:35]
wire out_frontSel_155 = _out_frontSel_T_1[155]; // @[OneHot.scala:58:35]
wire out_frontSel_156 = _out_frontSel_T_1[156]; // @[OneHot.scala:58:35]
wire out_frontSel_157 = _out_frontSel_T_1[157]; // @[OneHot.scala:58:35]
wire out_frontSel_158 = _out_frontSel_T_1[158]; // @[OneHot.scala:58:35]
wire out_frontSel_159 = _out_frontSel_T_1[159]; // @[OneHot.scala:58:35]
wire out_frontSel_160 = _out_frontSel_T_1[160]; // @[OneHot.scala:58:35]
wire out_frontSel_161 = _out_frontSel_T_1[161]; // @[OneHot.scala:58:35]
wire out_frontSel_162 = _out_frontSel_T_1[162]; // @[OneHot.scala:58:35]
wire out_frontSel_163 = _out_frontSel_T_1[163]; // @[OneHot.scala:58:35]
wire out_frontSel_164 = _out_frontSel_T_1[164]; // @[OneHot.scala:58:35]
wire out_frontSel_165 = _out_frontSel_T_1[165]; // @[OneHot.scala:58:35]
wire out_frontSel_166 = _out_frontSel_T_1[166]; // @[OneHot.scala:58:35]
wire out_frontSel_167 = _out_frontSel_T_1[167]; // @[OneHot.scala:58:35]
wire out_frontSel_168 = _out_frontSel_T_1[168]; // @[OneHot.scala:58:35]
wire out_frontSel_169 = _out_frontSel_T_1[169]; // @[OneHot.scala:58:35]
wire out_frontSel_170 = _out_frontSel_T_1[170]; // @[OneHot.scala:58:35]
wire out_frontSel_171 = _out_frontSel_T_1[171]; // @[OneHot.scala:58:35]
wire out_frontSel_172 = _out_frontSel_T_1[172]; // @[OneHot.scala:58:35]
wire out_frontSel_173 = _out_frontSel_T_1[173]; // @[OneHot.scala:58:35]
wire out_frontSel_174 = _out_frontSel_T_1[174]; // @[OneHot.scala:58:35]
wire out_frontSel_175 = _out_frontSel_T_1[175]; // @[OneHot.scala:58:35]
wire out_frontSel_176 = _out_frontSel_T_1[176]; // @[OneHot.scala:58:35]
wire out_frontSel_177 = _out_frontSel_T_1[177]; // @[OneHot.scala:58:35]
wire out_frontSel_178 = _out_frontSel_T_1[178]; // @[OneHot.scala:58:35]
wire out_frontSel_179 = _out_frontSel_T_1[179]; // @[OneHot.scala:58:35]
wire out_frontSel_180 = _out_frontSel_T_1[180]; // @[OneHot.scala:58:35]
wire out_frontSel_181 = _out_frontSel_T_1[181]; // @[OneHot.scala:58:35]
wire out_frontSel_182 = _out_frontSel_T_1[182]; // @[OneHot.scala:58:35]
wire out_frontSel_183 = _out_frontSel_T_1[183]; // @[OneHot.scala:58:35]
wire out_frontSel_184 = _out_frontSel_T_1[184]; // @[OneHot.scala:58:35]
wire out_frontSel_185 = _out_frontSel_T_1[185]; // @[OneHot.scala:58:35]
wire out_frontSel_186 = _out_frontSel_T_1[186]; // @[OneHot.scala:58:35]
wire out_frontSel_187 = _out_frontSel_T_1[187]; // @[OneHot.scala:58:35]
wire out_frontSel_188 = _out_frontSel_T_1[188]; // @[OneHot.scala:58:35]
wire out_frontSel_189 = _out_frontSel_T_1[189]; // @[OneHot.scala:58:35]
wire out_frontSel_190 = _out_frontSel_T_1[190]; // @[OneHot.scala:58:35]
wire out_frontSel_191 = _out_frontSel_T_1[191]; // @[OneHot.scala:58:35]
wire out_frontSel_192 = _out_frontSel_T_1[192]; // @[OneHot.scala:58:35]
wire out_frontSel_193 = _out_frontSel_T_1[193]; // @[OneHot.scala:58:35]
wire out_frontSel_194 = _out_frontSel_T_1[194]; // @[OneHot.scala:58:35]
wire out_frontSel_195 = _out_frontSel_T_1[195]; // @[OneHot.scala:58:35]
wire out_frontSel_196 = _out_frontSel_T_1[196]; // @[OneHot.scala:58:35]
wire out_frontSel_197 = _out_frontSel_T_1[197]; // @[OneHot.scala:58:35]
wire out_frontSel_198 = _out_frontSel_T_1[198]; // @[OneHot.scala:58:35]
wire out_frontSel_199 = _out_frontSel_T_1[199]; // @[OneHot.scala:58:35]
wire out_frontSel_200 = _out_frontSel_T_1[200]; // @[OneHot.scala:58:35]
wire out_frontSel_201 = _out_frontSel_T_1[201]; // @[OneHot.scala:58:35]
wire out_frontSel_202 = _out_frontSel_T_1[202]; // @[OneHot.scala:58:35]
wire out_frontSel_203 = _out_frontSel_T_1[203]; // @[OneHot.scala:58:35]
wire out_frontSel_204 = _out_frontSel_T_1[204]; // @[OneHot.scala:58:35]
wire out_frontSel_205 = _out_frontSel_T_1[205]; // @[OneHot.scala:58:35]
wire out_frontSel_206 = _out_frontSel_T_1[206]; // @[OneHot.scala:58:35]
wire out_frontSel_207 = _out_frontSel_T_1[207]; // @[OneHot.scala:58:35]
wire out_frontSel_208 = _out_frontSel_T_1[208]; // @[OneHot.scala:58:35]
wire out_frontSel_209 = _out_frontSel_T_1[209]; // @[OneHot.scala:58:35]
wire out_frontSel_210 = _out_frontSel_T_1[210]; // @[OneHot.scala:58:35]
wire out_frontSel_211 = _out_frontSel_T_1[211]; // @[OneHot.scala:58:35]
wire out_frontSel_212 = _out_frontSel_T_1[212]; // @[OneHot.scala:58:35]
wire out_frontSel_213 = _out_frontSel_T_1[213]; // @[OneHot.scala:58:35]
wire out_frontSel_214 = _out_frontSel_T_1[214]; // @[OneHot.scala:58:35]
wire out_frontSel_215 = _out_frontSel_T_1[215]; // @[OneHot.scala:58:35]
wire out_frontSel_216 = _out_frontSel_T_1[216]; // @[OneHot.scala:58:35]
wire out_frontSel_217 = _out_frontSel_T_1[217]; // @[OneHot.scala:58:35]
wire out_frontSel_218 = _out_frontSel_T_1[218]; // @[OneHot.scala:58:35]
wire out_frontSel_219 = _out_frontSel_T_1[219]; // @[OneHot.scala:58:35]
wire out_frontSel_220 = _out_frontSel_T_1[220]; // @[OneHot.scala:58:35]
wire out_frontSel_221 = _out_frontSel_T_1[221]; // @[OneHot.scala:58:35]
wire out_frontSel_222 = _out_frontSel_T_1[222]; // @[OneHot.scala:58:35]
wire out_frontSel_223 = _out_frontSel_T_1[223]; // @[OneHot.scala:58:35]
wire out_frontSel_224 = _out_frontSel_T_1[224]; // @[OneHot.scala:58:35]
wire out_frontSel_225 = _out_frontSel_T_1[225]; // @[OneHot.scala:58:35]
wire out_frontSel_226 = _out_frontSel_T_1[226]; // @[OneHot.scala:58:35]
wire out_frontSel_227 = _out_frontSel_T_1[227]; // @[OneHot.scala:58:35]
wire out_frontSel_228 = _out_frontSel_T_1[228]; // @[OneHot.scala:58:35]
wire out_frontSel_229 = _out_frontSel_T_1[229]; // @[OneHot.scala:58:35]
wire out_frontSel_230 = _out_frontSel_T_1[230]; // @[OneHot.scala:58:35]
wire out_frontSel_231 = _out_frontSel_T_1[231]; // @[OneHot.scala:58:35]
wire out_frontSel_232 = _out_frontSel_T_1[232]; // @[OneHot.scala:58:35]
wire out_frontSel_233 = _out_frontSel_T_1[233]; // @[OneHot.scala:58:35]
wire out_frontSel_234 = _out_frontSel_T_1[234]; // @[OneHot.scala:58:35]
wire out_frontSel_235 = _out_frontSel_T_1[235]; // @[OneHot.scala:58:35]
wire out_frontSel_236 = _out_frontSel_T_1[236]; // @[OneHot.scala:58:35]
wire out_frontSel_237 = _out_frontSel_T_1[237]; // @[OneHot.scala:58:35]
wire out_frontSel_238 = _out_frontSel_T_1[238]; // @[OneHot.scala:58:35]
wire out_frontSel_239 = _out_frontSel_T_1[239]; // @[OneHot.scala:58:35]
wire out_frontSel_240 = _out_frontSel_T_1[240]; // @[OneHot.scala:58:35]
wire out_frontSel_241 = _out_frontSel_T_1[241]; // @[OneHot.scala:58:35]
wire out_frontSel_242 = _out_frontSel_T_1[242]; // @[OneHot.scala:58:35]
wire out_frontSel_243 = _out_frontSel_T_1[243]; // @[OneHot.scala:58:35]
wire out_frontSel_244 = _out_frontSel_T_1[244]; // @[OneHot.scala:58:35]
wire out_frontSel_245 = _out_frontSel_T_1[245]; // @[OneHot.scala:58:35]
wire out_frontSel_246 = _out_frontSel_T_1[246]; // @[OneHot.scala:58:35]
wire out_frontSel_247 = _out_frontSel_T_1[247]; // @[OneHot.scala:58:35]
wire out_frontSel_248 = _out_frontSel_T_1[248]; // @[OneHot.scala:58:35]
wire out_frontSel_249 = _out_frontSel_T_1[249]; // @[OneHot.scala:58:35]
wire out_frontSel_250 = _out_frontSel_T_1[250]; // @[OneHot.scala:58:35]
wire out_frontSel_251 = _out_frontSel_T_1[251]; // @[OneHot.scala:58:35]
wire out_frontSel_252 = _out_frontSel_T_1[252]; // @[OneHot.scala:58:35]
wire out_frontSel_253 = _out_frontSel_T_1[253]; // @[OneHot.scala:58:35]
wire out_frontSel_254 = _out_frontSel_T_1[254]; // @[OneHot.scala:58:35]
wire out_frontSel_255 = _out_frontSel_T_1[255]; // @[OneHot.scala:58:35]
wire [255:0] _out_backSel_T_1 = 256'h1 << out_oindex_1; // @[OneHot.scala:58:35]
wire out_backSel_0_1 = _out_backSel_T_1[0]; // @[OneHot.scala:58:35]
wire out_backSel_1_1 = _out_backSel_T_1[1]; // @[OneHot.scala:58:35]
wire out_backSel_2_1 = _out_backSel_T_1[2]; // @[OneHot.scala:58:35]
wire out_backSel_3_1 = _out_backSel_T_1[3]; // @[OneHot.scala:58:35]
wire out_backSel_4_1 = _out_backSel_T_1[4]; // @[OneHot.scala:58:35]
wire out_backSel_5_1 = _out_backSel_T_1[5]; // @[OneHot.scala:58:35]
wire out_backSel_6_1 = _out_backSel_T_1[6]; // @[OneHot.scala:58:35]
wire out_backSel_7_1 = _out_backSel_T_1[7]; // @[OneHot.scala:58:35]
wire out_backSel_8_1 = _out_backSel_T_1[8]; // @[OneHot.scala:58:35]
wire out_backSel_9_1 = _out_backSel_T_1[9]; // @[OneHot.scala:58:35]
wire out_backSel_10_1 = _out_backSel_T_1[10]; // @[OneHot.scala:58:35]
wire out_backSel_11_1 = _out_backSel_T_1[11]; // @[OneHot.scala:58:35]
wire out_backSel_12_1 = _out_backSel_T_1[12]; // @[OneHot.scala:58:35]
wire out_backSel_13_1 = _out_backSel_T_1[13]; // @[OneHot.scala:58:35]
wire out_backSel_14_1 = _out_backSel_T_1[14]; // @[OneHot.scala:58:35]
wire out_backSel_15_1 = _out_backSel_T_1[15]; // @[OneHot.scala:58:35]
wire out_backSel_16_1 = _out_backSel_T_1[16]; // @[OneHot.scala:58:35]
wire out_backSel_17_1 = _out_backSel_T_1[17]; // @[OneHot.scala:58:35]
wire out_backSel_18_1 = _out_backSel_T_1[18]; // @[OneHot.scala:58:35]
wire out_backSel_19_1 = _out_backSel_T_1[19]; // @[OneHot.scala:58:35]
wire out_backSel_20_1 = _out_backSel_T_1[20]; // @[OneHot.scala:58:35]
wire out_backSel_21_1 = _out_backSel_T_1[21]; // @[OneHot.scala:58:35]
wire out_backSel_22_1 = _out_backSel_T_1[22]; // @[OneHot.scala:58:35]
wire out_backSel_23_1 = _out_backSel_T_1[23]; // @[OneHot.scala:58:35]
wire out_backSel_24_1 = _out_backSel_T_1[24]; // @[OneHot.scala:58:35]
wire out_backSel_25_1 = _out_backSel_T_1[25]; // @[OneHot.scala:58:35]
wire out_backSel_26_1 = _out_backSel_T_1[26]; // @[OneHot.scala:58:35]
wire out_backSel_27_1 = _out_backSel_T_1[27]; // @[OneHot.scala:58:35]
wire out_backSel_28_1 = _out_backSel_T_1[28]; // @[OneHot.scala:58:35]
wire out_backSel_29_1 = _out_backSel_T_1[29]; // @[OneHot.scala:58:35]
wire out_backSel_30_1 = _out_backSel_T_1[30]; // @[OneHot.scala:58:35]
wire out_backSel_31_1 = _out_backSel_T_1[31]; // @[OneHot.scala:58:35]
wire out_backSel_32_1 = _out_backSel_T_1[32]; // @[OneHot.scala:58:35]
wire out_backSel_33_1 = _out_backSel_T_1[33]; // @[OneHot.scala:58:35]
wire out_backSel_34_1 = _out_backSel_T_1[34]; // @[OneHot.scala:58:35]
wire out_backSel_35_1 = _out_backSel_T_1[35]; // @[OneHot.scala:58:35]
wire out_backSel_36_1 = _out_backSel_T_1[36]; // @[OneHot.scala:58:35]
wire out_backSel_37_1 = _out_backSel_T_1[37]; // @[OneHot.scala:58:35]
wire out_backSel_38_1 = _out_backSel_T_1[38]; // @[OneHot.scala:58:35]
wire out_backSel_39_1 = _out_backSel_T_1[39]; // @[OneHot.scala:58:35]
wire out_backSel_40_1 = _out_backSel_T_1[40]; // @[OneHot.scala:58:35]
wire out_backSel_41_1 = _out_backSel_T_1[41]; // @[OneHot.scala:58:35]
wire out_backSel_42_1 = _out_backSel_T_1[42]; // @[OneHot.scala:58:35]
wire out_backSel_43_1 = _out_backSel_T_1[43]; // @[OneHot.scala:58:35]
wire out_backSel_44_1 = _out_backSel_T_1[44]; // @[OneHot.scala:58:35]
wire out_backSel_45_1 = _out_backSel_T_1[45]; // @[OneHot.scala:58:35]
wire out_backSel_46_1 = _out_backSel_T_1[46]; // @[OneHot.scala:58:35]
wire out_backSel_47_1 = _out_backSel_T_1[47]; // @[OneHot.scala:58:35]
wire out_backSel_48_1 = _out_backSel_T_1[48]; // @[OneHot.scala:58:35]
wire out_backSel_49_1 = _out_backSel_T_1[49]; // @[OneHot.scala:58:35]
wire out_backSel_50_1 = _out_backSel_T_1[50]; // @[OneHot.scala:58:35]
wire out_backSel_51_1 = _out_backSel_T_1[51]; // @[OneHot.scala:58:35]
wire out_backSel_52_1 = _out_backSel_T_1[52]; // @[OneHot.scala:58:35]
wire out_backSel_53_1 = _out_backSel_T_1[53]; // @[OneHot.scala:58:35]
wire out_backSel_54_1 = _out_backSel_T_1[54]; // @[OneHot.scala:58:35]
wire out_backSel_55_1 = _out_backSel_T_1[55]; // @[OneHot.scala:58:35]
wire out_backSel_56_1 = _out_backSel_T_1[56]; // @[OneHot.scala:58:35]
wire out_backSel_57_1 = _out_backSel_T_1[57]; // @[OneHot.scala:58:35]
wire out_backSel_58_1 = _out_backSel_T_1[58]; // @[OneHot.scala:58:35]
wire out_backSel_59_1 = _out_backSel_T_1[59]; // @[OneHot.scala:58:35]
wire out_backSel_60_1 = _out_backSel_T_1[60]; // @[OneHot.scala:58:35]
wire out_backSel_61_1 = _out_backSel_T_1[61]; // @[OneHot.scala:58:35]
wire out_backSel_62_1 = _out_backSel_T_1[62]; // @[OneHot.scala:58:35]
wire out_backSel_63_1 = _out_backSel_T_1[63]; // @[OneHot.scala:58:35]
wire out_backSel_64 = _out_backSel_T_1[64]; // @[OneHot.scala:58:35]
wire out_backSel_65 = _out_backSel_T_1[65]; // @[OneHot.scala:58:35]
wire out_backSel_66 = _out_backSel_T_1[66]; // @[OneHot.scala:58:35]
wire out_backSel_67 = _out_backSel_T_1[67]; // @[OneHot.scala:58:35]
wire out_backSel_68 = _out_backSel_T_1[68]; // @[OneHot.scala:58:35]
wire out_backSel_69 = _out_backSel_T_1[69]; // @[OneHot.scala:58:35]
wire out_backSel_70 = _out_backSel_T_1[70]; // @[OneHot.scala:58:35]
wire out_backSel_71 = _out_backSel_T_1[71]; // @[OneHot.scala:58:35]
wire out_backSel_72 = _out_backSel_T_1[72]; // @[OneHot.scala:58:35]
wire out_backSel_73 = _out_backSel_T_1[73]; // @[OneHot.scala:58:35]
wire out_backSel_74 = _out_backSel_T_1[74]; // @[OneHot.scala:58:35]
wire out_backSel_75 = _out_backSel_T_1[75]; // @[OneHot.scala:58:35]
wire out_backSel_76 = _out_backSel_T_1[76]; // @[OneHot.scala:58:35]
wire out_backSel_77 = _out_backSel_T_1[77]; // @[OneHot.scala:58:35]
wire out_backSel_78 = _out_backSel_T_1[78]; // @[OneHot.scala:58:35]
wire out_backSel_79 = _out_backSel_T_1[79]; // @[OneHot.scala:58:35]
wire out_backSel_80 = _out_backSel_T_1[80]; // @[OneHot.scala:58:35]
wire out_backSel_81 = _out_backSel_T_1[81]; // @[OneHot.scala:58:35]
wire out_backSel_82 = _out_backSel_T_1[82]; // @[OneHot.scala:58:35]
wire out_backSel_83 = _out_backSel_T_1[83]; // @[OneHot.scala:58:35]
wire out_backSel_84 = _out_backSel_T_1[84]; // @[OneHot.scala:58:35]
wire out_backSel_85 = _out_backSel_T_1[85]; // @[OneHot.scala:58:35]
wire out_backSel_86 = _out_backSel_T_1[86]; // @[OneHot.scala:58:35]
wire out_backSel_87 = _out_backSel_T_1[87]; // @[OneHot.scala:58:35]
wire out_backSel_88 = _out_backSel_T_1[88]; // @[OneHot.scala:58:35]
wire out_backSel_89 = _out_backSel_T_1[89]; // @[OneHot.scala:58:35]
wire out_backSel_90 = _out_backSel_T_1[90]; // @[OneHot.scala:58:35]
wire out_backSel_91 = _out_backSel_T_1[91]; // @[OneHot.scala:58:35]
wire out_backSel_92 = _out_backSel_T_1[92]; // @[OneHot.scala:58:35]
wire out_backSel_93 = _out_backSel_T_1[93]; // @[OneHot.scala:58:35]
wire out_backSel_94 = _out_backSel_T_1[94]; // @[OneHot.scala:58:35]
wire out_backSel_95 = _out_backSel_T_1[95]; // @[OneHot.scala:58:35]
wire out_backSel_96 = _out_backSel_T_1[96]; // @[OneHot.scala:58:35]
wire out_backSel_97 = _out_backSel_T_1[97]; // @[OneHot.scala:58:35]
wire out_backSel_98 = _out_backSel_T_1[98]; // @[OneHot.scala:58:35]
wire out_backSel_99 = _out_backSel_T_1[99]; // @[OneHot.scala:58:35]
wire out_backSel_100 = _out_backSel_T_1[100]; // @[OneHot.scala:58:35]
wire out_backSel_101 = _out_backSel_T_1[101]; // @[OneHot.scala:58:35]
wire out_backSel_102 = _out_backSel_T_1[102]; // @[OneHot.scala:58:35]
wire out_backSel_103 = _out_backSel_T_1[103]; // @[OneHot.scala:58:35]
wire out_backSel_104 = _out_backSel_T_1[104]; // @[OneHot.scala:58:35]
wire out_backSel_105 = _out_backSel_T_1[105]; // @[OneHot.scala:58:35]
wire out_backSel_106 = _out_backSel_T_1[106]; // @[OneHot.scala:58:35]
wire out_backSel_107 = _out_backSel_T_1[107]; // @[OneHot.scala:58:35]
wire out_backSel_108 = _out_backSel_T_1[108]; // @[OneHot.scala:58:35]
wire out_backSel_109 = _out_backSel_T_1[109]; // @[OneHot.scala:58:35]
wire out_backSel_110 = _out_backSel_T_1[110]; // @[OneHot.scala:58:35]
wire out_backSel_111 = _out_backSel_T_1[111]; // @[OneHot.scala:58:35]
wire out_backSel_112 = _out_backSel_T_1[112]; // @[OneHot.scala:58:35]
wire out_backSel_113 = _out_backSel_T_1[113]; // @[OneHot.scala:58:35]
wire out_backSel_114 = _out_backSel_T_1[114]; // @[OneHot.scala:58:35]
wire out_backSel_115 = _out_backSel_T_1[115]; // @[OneHot.scala:58:35]
wire out_backSel_116 = _out_backSel_T_1[116]; // @[OneHot.scala:58:35]
wire out_backSel_117 = _out_backSel_T_1[117]; // @[OneHot.scala:58:35]
wire out_backSel_118 = _out_backSel_T_1[118]; // @[OneHot.scala:58:35]
wire out_backSel_119 = _out_backSel_T_1[119]; // @[OneHot.scala:58:35]
wire out_backSel_120 = _out_backSel_T_1[120]; // @[OneHot.scala:58:35]
wire out_backSel_121 = _out_backSel_T_1[121]; // @[OneHot.scala:58:35]
wire out_backSel_122 = _out_backSel_T_1[122]; // @[OneHot.scala:58:35]
wire out_backSel_123 = _out_backSel_T_1[123]; // @[OneHot.scala:58:35]
wire out_backSel_124 = _out_backSel_T_1[124]; // @[OneHot.scala:58:35]
wire out_backSel_125 = _out_backSel_T_1[125]; // @[OneHot.scala:58:35]
wire out_backSel_126 = _out_backSel_T_1[126]; // @[OneHot.scala:58:35]
wire out_backSel_127 = _out_backSel_T_1[127]; // @[OneHot.scala:58:35]
wire out_backSel_128 = _out_backSel_T_1[128]; // @[OneHot.scala:58:35]
wire out_backSel_129 = _out_backSel_T_1[129]; // @[OneHot.scala:58:35]
wire out_backSel_130 = _out_backSel_T_1[130]; // @[OneHot.scala:58:35]
wire out_backSel_131 = _out_backSel_T_1[131]; // @[OneHot.scala:58:35]
wire out_backSel_132 = _out_backSel_T_1[132]; // @[OneHot.scala:58:35]
wire out_backSel_133 = _out_backSel_T_1[133]; // @[OneHot.scala:58:35]
wire out_backSel_134 = _out_backSel_T_1[134]; // @[OneHot.scala:58:35]
wire out_backSel_135 = _out_backSel_T_1[135]; // @[OneHot.scala:58:35]
wire out_backSel_136 = _out_backSel_T_1[136]; // @[OneHot.scala:58:35]
wire out_backSel_137 = _out_backSel_T_1[137]; // @[OneHot.scala:58:35]
wire out_backSel_138 = _out_backSel_T_1[138]; // @[OneHot.scala:58:35]
wire out_backSel_139 = _out_backSel_T_1[139]; // @[OneHot.scala:58:35]
wire out_backSel_140 = _out_backSel_T_1[140]; // @[OneHot.scala:58:35]
wire out_backSel_141 = _out_backSel_T_1[141]; // @[OneHot.scala:58:35]
wire out_backSel_142 = _out_backSel_T_1[142]; // @[OneHot.scala:58:35]
wire out_backSel_143 = _out_backSel_T_1[143]; // @[OneHot.scala:58:35]
wire out_backSel_144 = _out_backSel_T_1[144]; // @[OneHot.scala:58:35]
wire out_backSel_145 = _out_backSel_T_1[145]; // @[OneHot.scala:58:35]
wire out_backSel_146 = _out_backSel_T_1[146]; // @[OneHot.scala:58:35]
wire out_backSel_147 = _out_backSel_T_1[147]; // @[OneHot.scala:58:35]
wire out_backSel_148 = _out_backSel_T_1[148]; // @[OneHot.scala:58:35]
wire out_backSel_149 = _out_backSel_T_1[149]; // @[OneHot.scala:58:35]
wire out_backSel_150 = _out_backSel_T_1[150]; // @[OneHot.scala:58:35]
wire out_backSel_151 = _out_backSel_T_1[151]; // @[OneHot.scala:58:35]
wire out_backSel_152 = _out_backSel_T_1[152]; // @[OneHot.scala:58:35]
wire out_backSel_153 = _out_backSel_T_1[153]; // @[OneHot.scala:58:35]
wire out_backSel_154 = _out_backSel_T_1[154]; // @[OneHot.scala:58:35]
wire out_backSel_155 = _out_backSel_T_1[155]; // @[OneHot.scala:58:35]
wire out_backSel_156 = _out_backSel_T_1[156]; // @[OneHot.scala:58:35]
wire out_backSel_157 = _out_backSel_T_1[157]; // @[OneHot.scala:58:35]
wire out_backSel_158 = _out_backSel_T_1[158]; // @[OneHot.scala:58:35]
wire out_backSel_159 = _out_backSel_T_1[159]; // @[OneHot.scala:58:35]
wire out_backSel_160 = _out_backSel_T_1[160]; // @[OneHot.scala:58:35]
wire out_backSel_161 = _out_backSel_T_1[161]; // @[OneHot.scala:58:35]
wire out_backSel_162 = _out_backSel_T_1[162]; // @[OneHot.scala:58:35]
wire out_backSel_163 = _out_backSel_T_1[163]; // @[OneHot.scala:58:35]
wire out_backSel_164 = _out_backSel_T_1[164]; // @[OneHot.scala:58:35]
wire out_backSel_165 = _out_backSel_T_1[165]; // @[OneHot.scala:58:35]
wire out_backSel_166 = _out_backSel_T_1[166]; // @[OneHot.scala:58:35]
wire out_backSel_167 = _out_backSel_T_1[167]; // @[OneHot.scala:58:35]
wire out_backSel_168 = _out_backSel_T_1[168]; // @[OneHot.scala:58:35]
wire out_backSel_169 = _out_backSel_T_1[169]; // @[OneHot.scala:58:35]
wire out_backSel_170 = _out_backSel_T_1[170]; // @[OneHot.scala:58:35]
wire out_backSel_171 = _out_backSel_T_1[171]; // @[OneHot.scala:58:35]
wire out_backSel_172 = _out_backSel_T_1[172]; // @[OneHot.scala:58:35]
wire out_backSel_173 = _out_backSel_T_1[173]; // @[OneHot.scala:58:35]
wire out_backSel_174 = _out_backSel_T_1[174]; // @[OneHot.scala:58:35]
wire out_backSel_175 = _out_backSel_T_1[175]; // @[OneHot.scala:58:35]
wire out_backSel_176 = _out_backSel_T_1[176]; // @[OneHot.scala:58:35]
wire out_backSel_177 = _out_backSel_T_1[177]; // @[OneHot.scala:58:35]
wire out_backSel_178 = _out_backSel_T_1[178]; // @[OneHot.scala:58:35]
wire out_backSel_179 = _out_backSel_T_1[179]; // @[OneHot.scala:58:35]
wire out_backSel_180 = _out_backSel_T_1[180]; // @[OneHot.scala:58:35]
wire out_backSel_181 = _out_backSel_T_1[181]; // @[OneHot.scala:58:35]
wire out_backSel_182 = _out_backSel_T_1[182]; // @[OneHot.scala:58:35]
wire out_backSel_183 = _out_backSel_T_1[183]; // @[OneHot.scala:58:35]
wire out_backSel_184 = _out_backSel_T_1[184]; // @[OneHot.scala:58:35]
wire out_backSel_185 = _out_backSel_T_1[185]; // @[OneHot.scala:58:35]
wire out_backSel_186 = _out_backSel_T_1[186]; // @[OneHot.scala:58:35]
wire out_backSel_187 = _out_backSel_T_1[187]; // @[OneHot.scala:58:35]
wire out_backSel_188 = _out_backSel_T_1[188]; // @[OneHot.scala:58:35]
wire out_backSel_189 = _out_backSel_T_1[189]; // @[OneHot.scala:58:35]
wire out_backSel_190 = _out_backSel_T_1[190]; // @[OneHot.scala:58:35]
wire out_backSel_191 = _out_backSel_T_1[191]; // @[OneHot.scala:58:35]
wire out_backSel_192 = _out_backSel_T_1[192]; // @[OneHot.scala:58:35]
wire out_backSel_193 = _out_backSel_T_1[193]; // @[OneHot.scala:58:35]
wire out_backSel_194 = _out_backSel_T_1[194]; // @[OneHot.scala:58:35]
wire out_backSel_195 = _out_backSel_T_1[195]; // @[OneHot.scala:58:35]
wire out_backSel_196 = _out_backSel_T_1[196]; // @[OneHot.scala:58:35]
wire out_backSel_197 = _out_backSel_T_1[197]; // @[OneHot.scala:58:35]
wire out_backSel_198 = _out_backSel_T_1[198]; // @[OneHot.scala:58:35]
wire out_backSel_199 = _out_backSel_T_1[199]; // @[OneHot.scala:58:35]
wire out_backSel_200 = _out_backSel_T_1[200]; // @[OneHot.scala:58:35]
wire out_backSel_201 = _out_backSel_T_1[201]; // @[OneHot.scala:58:35]
wire out_backSel_202 = _out_backSel_T_1[202]; // @[OneHot.scala:58:35]
wire out_backSel_203 = _out_backSel_T_1[203]; // @[OneHot.scala:58:35]
wire out_backSel_204 = _out_backSel_T_1[204]; // @[OneHot.scala:58:35]
wire out_backSel_205 = _out_backSel_T_1[205]; // @[OneHot.scala:58:35]
wire out_backSel_206 = _out_backSel_T_1[206]; // @[OneHot.scala:58:35]
wire out_backSel_207 = _out_backSel_T_1[207]; // @[OneHot.scala:58:35]
wire out_backSel_208 = _out_backSel_T_1[208]; // @[OneHot.scala:58:35]
wire out_backSel_209 = _out_backSel_T_1[209]; // @[OneHot.scala:58:35]
wire out_backSel_210 = _out_backSel_T_1[210]; // @[OneHot.scala:58:35]
wire out_backSel_211 = _out_backSel_T_1[211]; // @[OneHot.scala:58:35]
wire out_backSel_212 = _out_backSel_T_1[212]; // @[OneHot.scala:58:35]
wire out_backSel_213 = _out_backSel_T_1[213]; // @[OneHot.scala:58:35]
wire out_backSel_214 = _out_backSel_T_1[214]; // @[OneHot.scala:58:35]
wire out_backSel_215 = _out_backSel_T_1[215]; // @[OneHot.scala:58:35]
wire out_backSel_216 = _out_backSel_T_1[216]; // @[OneHot.scala:58:35]
wire out_backSel_217 = _out_backSel_T_1[217]; // @[OneHot.scala:58:35]
wire out_backSel_218 = _out_backSel_T_1[218]; // @[OneHot.scala:58:35]
wire out_backSel_219 = _out_backSel_T_1[219]; // @[OneHot.scala:58:35]
wire out_backSel_220 = _out_backSel_T_1[220]; // @[OneHot.scala:58:35]
wire out_backSel_221 = _out_backSel_T_1[221]; // @[OneHot.scala:58:35]
wire out_backSel_222 = _out_backSel_T_1[222]; // @[OneHot.scala:58:35]
wire out_backSel_223 = _out_backSel_T_1[223]; // @[OneHot.scala:58:35]
wire out_backSel_224 = _out_backSel_T_1[224]; // @[OneHot.scala:58:35]
wire out_backSel_225 = _out_backSel_T_1[225]; // @[OneHot.scala:58:35]
wire out_backSel_226 = _out_backSel_T_1[226]; // @[OneHot.scala:58:35]
wire out_backSel_227 = _out_backSel_T_1[227]; // @[OneHot.scala:58:35]
wire out_backSel_228 = _out_backSel_T_1[228]; // @[OneHot.scala:58:35]
wire out_backSel_229 = _out_backSel_T_1[229]; // @[OneHot.scala:58:35]
wire out_backSel_230 = _out_backSel_T_1[230]; // @[OneHot.scala:58:35]
wire out_backSel_231 = _out_backSel_T_1[231]; // @[OneHot.scala:58:35]
wire out_backSel_232 = _out_backSel_T_1[232]; // @[OneHot.scala:58:35]
wire out_backSel_233 = _out_backSel_T_1[233]; // @[OneHot.scala:58:35]
wire out_backSel_234 = _out_backSel_T_1[234]; // @[OneHot.scala:58:35]
wire out_backSel_235 = _out_backSel_T_1[235]; // @[OneHot.scala:58:35]
wire out_backSel_236 = _out_backSel_T_1[236]; // @[OneHot.scala:58:35]
wire out_backSel_237 = _out_backSel_T_1[237]; // @[OneHot.scala:58:35]
wire out_backSel_238 = _out_backSel_T_1[238]; // @[OneHot.scala:58:35]
wire out_backSel_239 = _out_backSel_T_1[239]; // @[OneHot.scala:58:35]
wire out_backSel_240 = _out_backSel_T_1[240]; // @[OneHot.scala:58:35]
wire out_backSel_241 = _out_backSel_T_1[241]; // @[OneHot.scala:58:35]
wire out_backSel_242 = _out_backSel_T_1[242]; // @[OneHot.scala:58:35]
wire out_backSel_243 = _out_backSel_T_1[243]; // @[OneHot.scala:58:35]
wire out_backSel_244 = _out_backSel_T_1[244]; // @[OneHot.scala:58:35]
wire out_backSel_245 = _out_backSel_T_1[245]; // @[OneHot.scala:58:35]
wire out_backSel_246 = _out_backSel_T_1[246]; // @[OneHot.scala:58:35]
wire out_backSel_247 = _out_backSel_T_1[247]; // @[OneHot.scala:58:35]
wire out_backSel_248 = _out_backSel_T_1[248]; // @[OneHot.scala:58:35]
wire out_backSel_249 = _out_backSel_T_1[249]; // @[OneHot.scala:58:35]
wire out_backSel_250 = _out_backSel_T_1[250]; // @[OneHot.scala:58:35]
wire out_backSel_251 = _out_backSel_T_1[251]; // @[OneHot.scala:58:35]
wire out_backSel_252 = _out_backSel_T_1[252]; // @[OneHot.scala:58:35]
wire out_backSel_253 = _out_backSel_T_1[253]; // @[OneHot.scala:58:35]
wire out_backSel_254 = _out_backSel_T_1[254]; // @[OneHot.scala:58:35]
wire out_backSel_255 = _out_backSel_T_1[255]; // @[OneHot.scala:58:35]
wire _GEN_37 = in_1_valid & out_front_1_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T_259; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_259 = _GEN_37; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_260; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_260 = _GEN_37; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_260 = _out_rifireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_261 = _out_rifireMux_T_260 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_262 = _out_rifireMux_T_261 & _out_T_1686; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_159 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_160 = _out_rifireMux_T_262; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_263 = ~_out_T_1686; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_265 = _out_rifireMux_T_260 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_266 = _out_rifireMux_T_265 & _out_T_1672; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_120 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_121 = _out_rifireMux_T_266; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_267 = ~_out_T_1672; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_269 = _out_rifireMux_T_260 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_270 = _out_rifireMux_T_269; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_273 = _out_rifireMux_T_260 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_274 = _out_rifireMux_T_273; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_277 = _out_rifireMux_T_260 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_278 = _out_rifireMux_T_277; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_281 = _out_rifireMux_T_260 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_282 = _out_rifireMux_T_281; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_285 = _out_rifireMux_T_260 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_286 = _out_rifireMux_T_285; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_289 = _out_rifireMux_T_260 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_290 = _out_rifireMux_T_289; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_293 = _out_rifireMux_T_260 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_294 = _out_rifireMux_T_293; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_297 = _out_rifireMux_T_260 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_298 = _out_rifireMux_T_297; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_301 = _out_rifireMux_T_260 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_302 = _out_rifireMux_T_301; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_305 = _out_rifireMux_T_260 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_306 = _out_rifireMux_T_305; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_309 = _out_rifireMux_T_260 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_310 = _out_rifireMux_T_309; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_313 = _out_rifireMux_T_260 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_314 = _out_rifireMux_T_313; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_317 = _out_rifireMux_T_260 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_318 = _out_rifireMux_T_317; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_321 = _out_rifireMux_T_260 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_322 = _out_rifireMux_T_321; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_325 = _out_rifireMux_T_260 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_326 = _out_rifireMux_T_325; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_329 = _out_rifireMux_T_260 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_330 = _out_rifireMux_T_329; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_333 = _out_rifireMux_T_260 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_334 = _out_rifireMux_T_333; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_337 = _out_rifireMux_T_260 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_338 = _out_rifireMux_T_337; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_341 = _out_rifireMux_T_260 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_342 = _out_rifireMux_T_341; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_345 = _out_rifireMux_T_260 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_346 = _out_rifireMux_T_345; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_349 = _out_rifireMux_T_260 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_350 = _out_rifireMux_T_349; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_353 = _out_rifireMux_T_260 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_354 = _out_rifireMux_T_353; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_357 = _out_rifireMux_T_260 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_358 = _out_rifireMux_T_357; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_361 = _out_rifireMux_T_260 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_362 = _out_rifireMux_T_361; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_365 = _out_rifireMux_T_260 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_366 = _out_rifireMux_T_365; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_369 = _out_rifireMux_T_260 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_370 = _out_rifireMux_T_369; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_373 = _out_rifireMux_T_260 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_374 = _out_rifireMux_T_373; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_377 = _out_rifireMux_T_260 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_378 = _out_rifireMux_T_377; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_381 = _out_rifireMux_T_260 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_382 = _out_rifireMux_T_381; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_385 = _out_rifireMux_T_260 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_386 = _out_rifireMux_T_385; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_389 = _out_rifireMux_T_260 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_390 = _out_rifireMux_T_389 & _out_T_1674; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_122 = _out_rifireMux_T_390; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_391 = ~_out_T_1674; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_393 = _out_rifireMux_T_260 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_394 = _out_rifireMux_T_393; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_397 = _out_rifireMux_T_260 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_398 = _out_rifireMux_T_397; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_401 = _out_rifireMux_T_260 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_402 = _out_rifireMux_T_401; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_405 = _out_rifireMux_T_260 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_406 = _out_rifireMux_T_405; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_409 = _out_rifireMux_T_260 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_410 = _out_rifireMux_T_409; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_413 = _out_rifireMux_T_260 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_414 = _out_rifireMux_T_413; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_417 = _out_rifireMux_T_260 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_418 = _out_rifireMux_T_417 & _out_T_1690; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_169 = _out_rifireMux_T_418; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_170 = _out_rifireMux_T_418; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_419 = ~_out_T_1690; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_421 = _out_rifireMux_T_260 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_422 = _out_rifireMux_T_421 & _out_T_1662; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_80 = _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_81 = _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_82 = _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_83 = _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_84 = _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_85 = _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_86 = _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_87 = _out_rifireMux_T_422; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_423 = ~_out_T_1662; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_425 = _out_rifireMux_T_260 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_426 = _out_rifireMux_T_425 & _out_T_1682; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_147 = _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_148 = _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_149 = _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_150 = _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_151 = _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_152 = _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_153 = _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_154 = _out_rifireMux_T_426; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_427 = ~_out_T_1682; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_429 = _out_rifireMux_T_260 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_430 = _out_rifireMux_T_429 & _out_T_1650; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_32 = _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_33 = _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_34 = _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_35 = _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_36 = _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_37 = _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_38 = _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_39 = _out_rifireMux_T_430; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_431 = ~_out_T_1650; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_433 = _out_rifireMux_T_260 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_434 = _out_rifireMux_T_433 & _out_T_1666; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_96 = _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_97 = _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_98 = _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_99 = _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_100 = _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_101 = _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_102 = _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_103 = _out_rifireMux_T_434; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_435 = ~_out_T_1666; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_437 = _out_rifireMux_T_260 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_438 = _out_rifireMux_T_437 & _out_T_1692; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_171 = _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_172 = _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_173 = _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_174 = _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_175 = _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_176 = _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_177 = _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_178 = _out_rifireMux_T_438; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_439 = ~_out_T_1692; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_441 = _out_rifireMux_T_260 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_442 = _out_rifireMux_T_441 & _out_T_1676; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_123 = _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_124 = _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_125 = _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_126 = _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_127 = _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_128 = _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_129 = _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_130 = _out_rifireMux_T_442; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_443 = ~_out_T_1676; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_445 = _out_rifireMux_T_260 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_446 = _out_rifireMux_T_445 & _out_T_1646; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_16 = _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_17 = _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_18 = _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_19 = _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_20 = _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_21 = _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_22 = _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_23 = _out_rifireMux_T_446; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_447 = ~_out_T_1646; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_449 = _out_rifireMux_T_260 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_450 = _out_rifireMux_T_449 & _out_T_1668; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_104 = _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_105 = _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_106 = _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_107 = _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_108 = _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_109 = _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_110 = _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_111 = _out_rifireMux_T_450; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_451 = ~_out_T_1668; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_453 = _out_rifireMux_T_260 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_454 = _out_rifireMux_T_453 & _out_T_1658; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_64 = _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_65 = _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_66 = _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_67 = _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_68 = _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_69 = _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_70 = _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_71 = _out_rifireMux_T_454; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_455 = ~_out_T_1658; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_457 = _out_rifireMux_T_260 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_458 = _out_rifireMux_T_457 & _out_T_1656; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_56 = _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_57 = _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_58 = _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_59 = _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_60 = _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_61 = _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_62 = _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_63 = _out_rifireMux_T_458; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_459 = ~_out_T_1656; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_461 = _out_rifireMux_T_260 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_462 = _out_rifireMux_T_461 & _out_T_1696; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_187 = _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_188 = _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_189 = _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_190 = _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_191 = _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_192 = _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_193 = _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_194 = _out_rifireMux_T_462; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_463 = ~_out_T_1696; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_465 = _out_rifireMux_T_260 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_466 = _out_rifireMux_T_465 & _out_T_1642; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_0 = _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_1 = _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_2 = _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_3 = _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_4 = _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_5 = _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_6 = _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_7 = _out_rifireMux_T_466; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_467 = ~_out_T_1642; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_469 = _out_rifireMux_T_260 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_470 = _out_rifireMux_T_469; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_473 = _out_rifireMux_T_260 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_474 = _out_rifireMux_T_473; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_477 = _out_rifireMux_T_260 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_478 = _out_rifireMux_T_477; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_481 = _out_rifireMux_T_260 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_482 = _out_rifireMux_T_481; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_485 = _out_rifireMux_T_260 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_486 = _out_rifireMux_T_485; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_489 = _out_rifireMux_T_260 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_490 = _out_rifireMux_T_489; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_493 = _out_rifireMux_T_260 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_494 = _out_rifireMux_T_493; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_497 = _out_rifireMux_T_260 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_498 = _out_rifireMux_T_497; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_501 = _out_rifireMux_T_260 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_502 = _out_rifireMux_T_501; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_505 = _out_rifireMux_T_260 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_506 = _out_rifireMux_T_505; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_509 = _out_rifireMux_T_260 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_510 = _out_rifireMux_T_509; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_513 = _out_rifireMux_T_260 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_514 = _out_rifireMux_T_513; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_517 = _out_rifireMux_T_260 & out_frontSel_64; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_518 = _out_rifireMux_T_517 & _out_T_1680; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_139 = _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_140 = _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_141 = _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_142 = _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_143 = _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_144 = _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_145 = _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_146 = _out_rifireMux_T_518; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_519 = ~_out_T_1680; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_521 = _out_rifireMux_T_260 & out_frontSel_65; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_522 = _out_rifireMux_T_521; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_525 = _out_rifireMux_T_260 & out_frontSel_66; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_526 = _out_rifireMux_T_525; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_529 = _out_rifireMux_T_260 & out_frontSel_67; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_530 = _out_rifireMux_T_529; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_533 = _out_rifireMux_T_260 & out_frontSel_68; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_534 = _out_rifireMux_T_533; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_537 = _out_rifireMux_T_260 & out_frontSel_69; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_538 = _out_rifireMux_T_537; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_541 = _out_rifireMux_T_260 & out_frontSel_70; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_542 = _out_rifireMux_T_541; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_545 = _out_rifireMux_T_260 & out_frontSel_71; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_546 = _out_rifireMux_T_545; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_549 = _out_rifireMux_T_260 & out_frontSel_72; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_550 = _out_rifireMux_T_549; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_553 = _out_rifireMux_T_260 & out_frontSel_73; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_554 = _out_rifireMux_T_553; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_557 = _out_rifireMux_T_260 & out_frontSel_74; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_558 = _out_rifireMux_T_557; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_561 = _out_rifireMux_T_260 & out_frontSel_75; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_562 = _out_rifireMux_T_561; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_565 = _out_rifireMux_T_260 & out_frontSel_76; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_566 = _out_rifireMux_T_565; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_569 = _out_rifireMux_T_260 & out_frontSel_77; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_570 = _out_rifireMux_T_569; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_573 = _out_rifireMux_T_260 & out_frontSel_78; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_574 = _out_rifireMux_T_573; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_577 = _out_rifireMux_T_260 & out_frontSel_79; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_578 = _out_rifireMux_T_577; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_581 = _out_rifireMux_T_260 & out_frontSel_80; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_582 = _out_rifireMux_T_581; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_585 = _out_rifireMux_T_260 & out_frontSel_81; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_586 = _out_rifireMux_T_585; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_589 = _out_rifireMux_T_260 & out_frontSel_82; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_590 = _out_rifireMux_T_589; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_593 = _out_rifireMux_T_260 & out_frontSel_83; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_594 = _out_rifireMux_T_593; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_597 = _out_rifireMux_T_260 & out_frontSel_84; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_598 = _out_rifireMux_T_597; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_601 = _out_rifireMux_T_260 & out_frontSel_85; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_602 = _out_rifireMux_T_601; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_605 = _out_rifireMux_T_260 & out_frontSel_86; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_606 = _out_rifireMux_T_605; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_609 = _out_rifireMux_T_260 & out_frontSel_87; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_610 = _out_rifireMux_T_609; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_613 = _out_rifireMux_T_260 & out_frontSel_88; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_614 = _out_rifireMux_T_613; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_617 = _out_rifireMux_T_260 & out_frontSel_89; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_618 = _out_rifireMux_T_617; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_621 = _out_rifireMux_T_260 & out_frontSel_90; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_622 = _out_rifireMux_T_621; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_625 = _out_rifireMux_T_260 & out_frontSel_91; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_626 = _out_rifireMux_T_625; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_629 = _out_rifireMux_T_260 & out_frontSel_92; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_630 = _out_rifireMux_T_629; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_633 = _out_rifireMux_T_260 & out_frontSel_93; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_634 = _out_rifireMux_T_633; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_637 = _out_rifireMux_T_260 & out_frontSel_94; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_638 = _out_rifireMux_T_637; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_641 = _out_rifireMux_T_260 & out_frontSel_95; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_642 = _out_rifireMux_T_641; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_645 = _out_rifireMux_T_260 & out_frontSel_96; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_646 = _out_rifireMux_T_645; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_649 = _out_rifireMux_T_260 & out_frontSel_97; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_650 = _out_rifireMux_T_649; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_653 = _out_rifireMux_T_260 & out_frontSel_98; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_654 = _out_rifireMux_T_653; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_657 = _out_rifireMux_T_260 & out_frontSel_99; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_658 = _out_rifireMux_T_657; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_661 = _out_rifireMux_T_260 & out_frontSel_100; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_662 = _out_rifireMux_T_661; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_665 = _out_rifireMux_T_260 & out_frontSel_101; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_666 = _out_rifireMux_T_665; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_669 = _out_rifireMux_T_260 & out_frontSel_102; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_670 = _out_rifireMux_T_669; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_673 = _out_rifireMux_T_260 & out_frontSel_103; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_674 = _out_rifireMux_T_673; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_677 = _out_rifireMux_T_260 & out_frontSel_104; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_678 = _out_rifireMux_T_677; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_681 = _out_rifireMux_T_260 & out_frontSel_105; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_682 = _out_rifireMux_T_681; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_685 = _out_rifireMux_T_260 & out_frontSel_106; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_686 = _out_rifireMux_T_685; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_689 = _out_rifireMux_T_260 & out_frontSel_107; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_690 = _out_rifireMux_T_689; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_693 = _out_rifireMux_T_260 & out_frontSel_108; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_694 = _out_rifireMux_T_693; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_697 = _out_rifireMux_T_260 & out_frontSel_109; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_698 = _out_rifireMux_T_697; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_701 = _out_rifireMux_T_260 & out_frontSel_110; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_702 = _out_rifireMux_T_701; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_705 = _out_rifireMux_T_260 & out_frontSel_111; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_706 = _out_rifireMux_T_705; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_709 = _out_rifireMux_T_260 & out_frontSel_112; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_710 = _out_rifireMux_T_709; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_713 = _out_rifireMux_T_260 & out_frontSel_113; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_714 = _out_rifireMux_T_713; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_717 = _out_rifireMux_T_260 & out_frontSel_114; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_718 = _out_rifireMux_T_717; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_721 = _out_rifireMux_T_260 & out_frontSel_115; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_722 = _out_rifireMux_T_721; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_725 = _out_rifireMux_T_260 & out_frontSel_116; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_726 = _out_rifireMux_T_725; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_729 = _out_rifireMux_T_260 & out_frontSel_117; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_730 = _out_rifireMux_T_729; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_733 = _out_rifireMux_T_260 & out_frontSel_118; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_734 = _out_rifireMux_T_733; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_737 = _out_rifireMux_T_260 & out_frontSel_119; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_738 = _out_rifireMux_T_737; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_741 = _out_rifireMux_T_260 & out_frontSel_120; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_742 = _out_rifireMux_T_741; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_745 = _out_rifireMux_T_260 & out_frontSel_121; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_746 = _out_rifireMux_T_745; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_749 = _out_rifireMux_T_260 & out_frontSel_122; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_750 = _out_rifireMux_T_749; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_753 = _out_rifireMux_T_260 & out_frontSel_123; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_754 = _out_rifireMux_T_753; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_757 = _out_rifireMux_T_260 & out_frontSel_124; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_758 = _out_rifireMux_T_757; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_761 = _out_rifireMux_T_260 & out_frontSel_125; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_762 = _out_rifireMux_T_761; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_765 = _out_rifireMux_T_260 & out_frontSel_126; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_766 = _out_rifireMux_T_765; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_769 = _out_rifireMux_T_260 & out_frontSel_127; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_770 = _out_rifireMux_T_769; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_773 = _out_rifireMux_T_260 & out_frontSel_128; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_774 = _out_rifireMux_T_773 & _out_T_1678; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_131 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_132 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_133 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_134 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_135 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_136 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_137 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_138 = _out_rifireMux_T_774; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_775 = ~_out_T_1678; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_777 = _out_rifireMux_T_260 & out_frontSel_129; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_778 = _out_rifireMux_T_777 & _out_T_1644; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_8 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_9 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_10 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_11 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_12 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_13 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_14 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_15 = _out_rifireMux_T_778; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_779 = ~_out_T_1644; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_781 = _out_rifireMux_T_260 & out_frontSel_130; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_782 = _out_rifireMux_T_781 & _out_T_1694; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_179 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_180 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_181 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_182 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_183 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_184 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_185 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_186 = _out_rifireMux_T_782; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_783 = ~_out_T_1694; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_785 = _out_rifireMux_T_260 & out_frontSel_131; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_786 = _out_rifireMux_T_785 & _out_T_1654; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_48 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_49 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_50 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_51 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_52 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_53 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_54 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_55 = _out_rifireMux_T_786; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_787 = ~_out_T_1654; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_789 = _out_rifireMux_T_260 & out_frontSel_132; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_790 = _out_rifireMux_T_789 & _out_T_1670; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_112 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_113 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_114 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_115 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_116 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_117 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_118 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_119 = _out_rifireMux_T_790; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_791 = ~_out_T_1670; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_793 = _out_rifireMux_T_260 & out_frontSel_133; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_794 = _out_rifireMux_T_793 & _out_T_1648; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_24 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_25 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_26 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_27 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_28 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_29 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_30 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_31 = _out_rifireMux_T_794; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_795 = ~_out_T_1648; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_797 = _out_rifireMux_T_260 & out_frontSel_134; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_798 = _out_rifireMux_T_797 & _out_T_1664; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_88 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_89 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_90 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_91 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_92 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_93 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_94 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_95 = _out_rifireMux_T_798; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_799 = ~_out_T_1664; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_801 = _out_rifireMux_T_260 & out_frontSel_135; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_802 = _out_rifireMux_T_801 & _out_T_1660; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_72 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_73 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_74 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_75 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_76 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_77 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_78 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_79 = _out_rifireMux_T_802; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_803 = ~_out_T_1660; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_805 = _out_rifireMux_T_260 & out_frontSel_136; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_806 = _out_rifireMux_T_805 & _out_T_1688; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_161 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_162 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_163 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_164 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_165 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_166 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_167 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_168 = _out_rifireMux_T_806; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_807 = ~_out_T_1688; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_809 = _out_rifireMux_T_260 & out_frontSel_137; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_810 = _out_rifireMux_T_809 & _out_T_1652; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_40 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_41 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_42 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_43 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_44 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_45 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_46 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_47 = _out_rifireMux_T_810; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_811 = ~_out_T_1652; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_813 = _out_rifireMux_T_260 & out_frontSel_138; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_814 = _out_rifireMux_T_813 & _out_T_1684; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_155 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_156 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_157 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1_158 = _out_rifireMux_T_814; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_815 = ~_out_T_1684; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_817 = _out_rifireMux_T_260 & out_frontSel_139; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_818 = _out_rifireMux_T_817; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_821 = _out_rifireMux_T_260 & out_frontSel_140; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_822 = _out_rifireMux_T_821; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_825 = _out_rifireMux_T_260 & out_frontSel_141; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_826 = _out_rifireMux_T_825; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_829 = _out_rifireMux_T_260 & out_frontSel_142; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_830 = _out_rifireMux_T_829; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_833 = _out_rifireMux_T_260 & out_frontSel_143; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_834 = _out_rifireMux_T_833; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_837 = _out_rifireMux_T_260 & out_frontSel_144; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_838 = _out_rifireMux_T_837; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_841 = _out_rifireMux_T_260 & out_frontSel_145; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_842 = _out_rifireMux_T_841; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_845 = _out_rifireMux_T_260 & out_frontSel_146; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_846 = _out_rifireMux_T_845; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_849 = _out_rifireMux_T_260 & out_frontSel_147; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_850 = _out_rifireMux_T_849; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_853 = _out_rifireMux_T_260 & out_frontSel_148; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_854 = _out_rifireMux_T_853; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_857 = _out_rifireMux_T_260 & out_frontSel_149; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_858 = _out_rifireMux_T_857; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_861 = _out_rifireMux_T_260 & out_frontSel_150; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_862 = _out_rifireMux_T_861; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_865 = _out_rifireMux_T_260 & out_frontSel_151; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_866 = _out_rifireMux_T_865; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_869 = _out_rifireMux_T_260 & out_frontSel_152; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_870 = _out_rifireMux_T_869; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_873 = _out_rifireMux_T_260 & out_frontSel_153; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_874 = _out_rifireMux_T_873; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_877 = _out_rifireMux_T_260 & out_frontSel_154; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_878 = _out_rifireMux_T_877; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_881 = _out_rifireMux_T_260 & out_frontSel_155; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_882 = _out_rifireMux_T_881; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_885 = _out_rifireMux_T_260 & out_frontSel_156; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_886 = _out_rifireMux_T_885; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_889 = _out_rifireMux_T_260 & out_frontSel_157; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_890 = _out_rifireMux_T_889; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_893 = _out_rifireMux_T_260 & out_frontSel_158; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_894 = _out_rifireMux_T_893; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_897 = _out_rifireMux_T_260 & out_frontSel_159; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_898 = _out_rifireMux_T_897; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_901 = _out_rifireMux_T_260 & out_frontSel_160; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_902 = _out_rifireMux_T_901; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_905 = _out_rifireMux_T_260 & out_frontSel_161; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_906 = _out_rifireMux_T_905; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_909 = _out_rifireMux_T_260 & out_frontSel_162; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_910 = _out_rifireMux_T_909; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_913 = _out_rifireMux_T_260 & out_frontSel_163; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_914 = _out_rifireMux_T_913; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_917 = _out_rifireMux_T_260 & out_frontSel_164; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_918 = _out_rifireMux_T_917; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_921 = _out_rifireMux_T_260 & out_frontSel_165; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_922 = _out_rifireMux_T_921; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_925 = _out_rifireMux_T_260 & out_frontSel_166; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_926 = _out_rifireMux_T_925; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_929 = _out_rifireMux_T_260 & out_frontSel_167; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_930 = _out_rifireMux_T_929; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_933 = _out_rifireMux_T_260 & out_frontSel_168; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_934 = _out_rifireMux_T_933; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_937 = _out_rifireMux_T_260 & out_frontSel_169; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_938 = _out_rifireMux_T_937; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_941 = _out_rifireMux_T_260 & out_frontSel_170; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_942 = _out_rifireMux_T_941; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_945 = _out_rifireMux_T_260 & out_frontSel_171; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_946 = _out_rifireMux_T_945; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_949 = _out_rifireMux_T_260 & out_frontSel_172; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_950 = _out_rifireMux_T_949; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_953 = _out_rifireMux_T_260 & out_frontSel_173; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_954 = _out_rifireMux_T_953; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_957 = _out_rifireMux_T_260 & out_frontSel_174; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_958 = _out_rifireMux_T_957; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_961 = _out_rifireMux_T_260 & out_frontSel_175; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_962 = _out_rifireMux_T_961; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_965 = _out_rifireMux_T_260 & out_frontSel_176; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_966 = _out_rifireMux_T_965; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_969 = _out_rifireMux_T_260 & out_frontSel_177; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_970 = _out_rifireMux_T_969; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_973 = _out_rifireMux_T_260 & out_frontSel_178; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_974 = _out_rifireMux_T_973; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_977 = _out_rifireMux_T_260 & out_frontSel_179; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_978 = _out_rifireMux_T_977; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_981 = _out_rifireMux_T_260 & out_frontSel_180; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_982 = _out_rifireMux_T_981; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_985 = _out_rifireMux_T_260 & out_frontSel_181; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_986 = _out_rifireMux_T_985; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_989 = _out_rifireMux_T_260 & out_frontSel_182; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_990 = _out_rifireMux_T_989; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_993 = _out_rifireMux_T_260 & out_frontSel_183; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_994 = _out_rifireMux_T_993; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_997 = _out_rifireMux_T_260 & out_frontSel_184; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_998 = _out_rifireMux_T_997; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1001 = _out_rifireMux_T_260 & out_frontSel_185; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1002 = _out_rifireMux_T_1001; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1005 = _out_rifireMux_T_260 & out_frontSel_186; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1006 = _out_rifireMux_T_1005; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1009 = _out_rifireMux_T_260 & out_frontSel_187; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1010 = _out_rifireMux_T_1009; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1013 = _out_rifireMux_T_260 & out_frontSel_188; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1014 = _out_rifireMux_T_1013; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1017 = _out_rifireMux_T_260 & out_frontSel_189; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1018 = _out_rifireMux_T_1017; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1021 = _out_rifireMux_T_260 & out_frontSel_190; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1022 = _out_rifireMux_T_1021; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1025 = _out_rifireMux_T_260 & out_frontSel_191; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1026 = _out_rifireMux_T_1025; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1029 = _out_rifireMux_T_260 & out_frontSel_192; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1030 = _out_rifireMux_T_1029; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1033 = _out_rifireMux_T_260 & out_frontSel_193; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1034 = _out_rifireMux_T_1033; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1037 = _out_rifireMux_T_260 & out_frontSel_194; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1038 = _out_rifireMux_T_1037; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1041 = _out_rifireMux_T_260 & out_frontSel_195; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1042 = _out_rifireMux_T_1041; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1045 = _out_rifireMux_T_260 & out_frontSel_196; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1046 = _out_rifireMux_T_1045; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1049 = _out_rifireMux_T_260 & out_frontSel_197; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1050 = _out_rifireMux_T_1049; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1053 = _out_rifireMux_T_260 & out_frontSel_198; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1054 = _out_rifireMux_T_1053; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1057 = _out_rifireMux_T_260 & out_frontSel_199; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1058 = _out_rifireMux_T_1057; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1061 = _out_rifireMux_T_260 & out_frontSel_200; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1062 = _out_rifireMux_T_1061; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1065 = _out_rifireMux_T_260 & out_frontSel_201; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1066 = _out_rifireMux_T_1065; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1069 = _out_rifireMux_T_260 & out_frontSel_202; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1070 = _out_rifireMux_T_1069; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1073 = _out_rifireMux_T_260 & out_frontSel_203; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1074 = _out_rifireMux_T_1073; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1077 = _out_rifireMux_T_260 & out_frontSel_204; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1078 = _out_rifireMux_T_1077; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1081 = _out_rifireMux_T_260 & out_frontSel_205; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1082 = _out_rifireMux_T_1081; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1085 = _out_rifireMux_T_260 & out_frontSel_206; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1086 = _out_rifireMux_T_1085; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1089 = _out_rifireMux_T_260 & out_frontSel_207; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1090 = _out_rifireMux_T_1089; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1093 = _out_rifireMux_T_260 & out_frontSel_208; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1094 = _out_rifireMux_T_1093; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1097 = _out_rifireMux_T_260 & out_frontSel_209; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1098 = _out_rifireMux_T_1097; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1101 = _out_rifireMux_T_260 & out_frontSel_210; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1102 = _out_rifireMux_T_1101; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1105 = _out_rifireMux_T_260 & out_frontSel_211; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1106 = _out_rifireMux_T_1105; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1109 = _out_rifireMux_T_260 & out_frontSel_212; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1110 = _out_rifireMux_T_1109; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1113 = _out_rifireMux_T_260 & out_frontSel_213; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1114 = _out_rifireMux_T_1113; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1117 = _out_rifireMux_T_260 & out_frontSel_214; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1118 = _out_rifireMux_T_1117; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1121 = _out_rifireMux_T_260 & out_frontSel_215; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1122 = _out_rifireMux_T_1121; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1125 = _out_rifireMux_T_260 & out_frontSel_216; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1126 = _out_rifireMux_T_1125; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1129 = _out_rifireMux_T_260 & out_frontSel_217; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1130 = _out_rifireMux_T_1129; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1133 = _out_rifireMux_T_260 & out_frontSel_218; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1134 = _out_rifireMux_T_1133; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1137 = _out_rifireMux_T_260 & out_frontSel_219; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1138 = _out_rifireMux_T_1137; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1141 = _out_rifireMux_T_260 & out_frontSel_220; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1142 = _out_rifireMux_T_1141; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1145 = _out_rifireMux_T_260 & out_frontSel_221; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1146 = _out_rifireMux_T_1145; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1149 = _out_rifireMux_T_260 & out_frontSel_222; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1150 = _out_rifireMux_T_1149; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1153 = _out_rifireMux_T_260 & out_frontSel_223; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1154 = _out_rifireMux_T_1153; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1157 = _out_rifireMux_T_260 & out_frontSel_224; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1158 = _out_rifireMux_T_1157; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1161 = _out_rifireMux_T_260 & out_frontSel_225; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1162 = _out_rifireMux_T_1161; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1165 = _out_rifireMux_T_260 & out_frontSel_226; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1166 = _out_rifireMux_T_1165; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1169 = _out_rifireMux_T_260 & out_frontSel_227; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1170 = _out_rifireMux_T_1169; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1173 = _out_rifireMux_T_260 & out_frontSel_228; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1174 = _out_rifireMux_T_1173; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1177 = _out_rifireMux_T_260 & out_frontSel_229; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1178 = _out_rifireMux_T_1177; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1181 = _out_rifireMux_T_260 & out_frontSel_230; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1182 = _out_rifireMux_T_1181; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1185 = _out_rifireMux_T_260 & out_frontSel_231; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1186 = _out_rifireMux_T_1185; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1189 = _out_rifireMux_T_260 & out_frontSel_232; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1190 = _out_rifireMux_T_1189; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1193 = _out_rifireMux_T_260 & out_frontSel_233; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1194 = _out_rifireMux_T_1193; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1197 = _out_rifireMux_T_260 & out_frontSel_234; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1198 = _out_rifireMux_T_1197; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1201 = _out_rifireMux_T_260 & out_frontSel_235; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1202 = _out_rifireMux_T_1201; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1205 = _out_rifireMux_T_260 & out_frontSel_236; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1206 = _out_rifireMux_T_1205; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1209 = _out_rifireMux_T_260 & out_frontSel_237; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1210 = _out_rifireMux_T_1209; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1213 = _out_rifireMux_T_260 & out_frontSel_238; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1214 = _out_rifireMux_T_1213; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1217 = _out_rifireMux_T_260 & out_frontSel_239; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1218 = _out_rifireMux_T_1217; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1221 = _out_rifireMux_T_260 & out_frontSel_240; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1222 = _out_rifireMux_T_1221; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1225 = _out_rifireMux_T_260 & out_frontSel_241; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1226 = _out_rifireMux_T_1225; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1229 = _out_rifireMux_T_260 & out_frontSel_242; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1230 = _out_rifireMux_T_1229; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1233 = _out_rifireMux_T_260 & out_frontSel_243; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1234 = _out_rifireMux_T_1233; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1237 = _out_rifireMux_T_260 & out_frontSel_244; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1238 = _out_rifireMux_T_1237; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1241 = _out_rifireMux_T_260 & out_frontSel_245; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1242 = _out_rifireMux_T_1241; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1245 = _out_rifireMux_T_260 & out_frontSel_246; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1246 = _out_rifireMux_T_1245; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1249 = _out_rifireMux_T_260 & out_frontSel_247; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1250 = _out_rifireMux_T_1249; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1253 = _out_rifireMux_T_260 & out_frontSel_248; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1254 = _out_rifireMux_T_1253; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1257 = _out_rifireMux_T_260 & out_frontSel_249; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1258 = _out_rifireMux_T_1257; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1261 = _out_rifireMux_T_260 & out_frontSel_250; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1262 = _out_rifireMux_T_1261; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1265 = _out_rifireMux_T_260 & out_frontSel_251; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1266 = _out_rifireMux_T_1265; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1269 = _out_rifireMux_T_260 & out_frontSel_252; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1270 = _out_rifireMux_T_1269; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1273 = _out_rifireMux_T_260 & out_frontSel_253; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1274 = _out_rifireMux_T_1273; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1277 = _out_rifireMux_T_260 & out_frontSel_254; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1278 = _out_rifireMux_T_1277; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1281 = _out_rifireMux_T_260 & out_frontSel_255; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1282 = _out_rifireMux_T_1281; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_262 = _out_wifireMux_T_260 & _out_wifireMux_T_261; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_263 = _out_wifireMux_T_262 & out_frontSel_0_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_264 = _out_wifireMux_T_263 & _out_T_1686; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_159 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_160 = _out_wifireMux_T_264; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_265 = ~_out_T_1686; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_267 = _out_wifireMux_T_262 & out_frontSel_1_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_268 = _out_wifireMux_T_267 & _out_T_1672; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_120 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_121 = _out_wifireMux_T_268; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_269 = ~_out_T_1672; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_271 = _out_wifireMux_T_262 & out_frontSel_2_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_272 = _out_wifireMux_T_271; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_275 = _out_wifireMux_T_262 & out_frontSel_3_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_276 = _out_wifireMux_T_275; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_279 = _out_wifireMux_T_262 & out_frontSel_4_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_280 = _out_wifireMux_T_279; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_283 = _out_wifireMux_T_262 & out_frontSel_5_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_284 = _out_wifireMux_T_283; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_287 = _out_wifireMux_T_262 & out_frontSel_6_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_288 = _out_wifireMux_T_287; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_291 = _out_wifireMux_T_262 & out_frontSel_7_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_292 = _out_wifireMux_T_291; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_295 = _out_wifireMux_T_262 & out_frontSel_8_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_296 = _out_wifireMux_T_295; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_299 = _out_wifireMux_T_262 & out_frontSel_9_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_300 = _out_wifireMux_T_299; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_303 = _out_wifireMux_T_262 & out_frontSel_10_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_304 = _out_wifireMux_T_303; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_307 = _out_wifireMux_T_262 & out_frontSel_11_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_308 = _out_wifireMux_T_307; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_311 = _out_wifireMux_T_262 & out_frontSel_12_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_312 = _out_wifireMux_T_311; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_315 = _out_wifireMux_T_262 & out_frontSel_13_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_316 = _out_wifireMux_T_315; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_319 = _out_wifireMux_T_262 & out_frontSel_14_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_320 = _out_wifireMux_T_319; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_323 = _out_wifireMux_T_262 & out_frontSel_15_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_324 = _out_wifireMux_T_323; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_327 = _out_wifireMux_T_262 & out_frontSel_16_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_328 = _out_wifireMux_T_327; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_331 = _out_wifireMux_T_262 & out_frontSel_17_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_332 = _out_wifireMux_T_331; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_335 = _out_wifireMux_T_262 & out_frontSel_18_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_336 = _out_wifireMux_T_335; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_339 = _out_wifireMux_T_262 & out_frontSel_19_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_340 = _out_wifireMux_T_339; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_343 = _out_wifireMux_T_262 & out_frontSel_20_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_344 = _out_wifireMux_T_343; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_347 = _out_wifireMux_T_262 & out_frontSel_21_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_348 = _out_wifireMux_T_347; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_351 = _out_wifireMux_T_262 & out_frontSel_22_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_352 = _out_wifireMux_T_351; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_355 = _out_wifireMux_T_262 & out_frontSel_23_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_356 = _out_wifireMux_T_355; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_359 = _out_wifireMux_T_262 & out_frontSel_24_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_360 = _out_wifireMux_T_359; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_363 = _out_wifireMux_T_262 & out_frontSel_25_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_364 = _out_wifireMux_T_363; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_367 = _out_wifireMux_T_262 & out_frontSel_26_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_368 = _out_wifireMux_T_367; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_371 = _out_wifireMux_T_262 & out_frontSel_27_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_372 = _out_wifireMux_T_371; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_375 = _out_wifireMux_T_262 & out_frontSel_28_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_376 = _out_wifireMux_T_375; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_379 = _out_wifireMux_T_262 & out_frontSel_29_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_380 = _out_wifireMux_T_379; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_383 = _out_wifireMux_T_262 & out_frontSel_30_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_384 = _out_wifireMux_T_383; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_387 = _out_wifireMux_T_262 & out_frontSel_31_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_388 = _out_wifireMux_T_387; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_391 = _out_wifireMux_T_262 & out_frontSel_32_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_392 = _out_wifireMux_T_391 & _out_T_1674; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_122 = _out_wifireMux_T_392; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_393 = ~_out_T_1674; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_395 = _out_wifireMux_T_262 & out_frontSel_33_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_396 = _out_wifireMux_T_395; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_399 = _out_wifireMux_T_262 & out_frontSel_34_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_400 = _out_wifireMux_T_399; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_403 = _out_wifireMux_T_262 & out_frontSel_35_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_404 = _out_wifireMux_T_403; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_407 = _out_wifireMux_T_262 & out_frontSel_36_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_408 = _out_wifireMux_T_407; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_411 = _out_wifireMux_T_262 & out_frontSel_37_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_412 = _out_wifireMux_T_411; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_415 = _out_wifireMux_T_262 & out_frontSel_38_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_416 = _out_wifireMux_T_415; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_419 = _out_wifireMux_T_262 & out_frontSel_39_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_420 = _out_wifireMux_T_419 & _out_T_1690; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_169 = _out_wifireMux_T_420; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_170 = _out_wifireMux_T_420; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_421 = ~_out_T_1690; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_423 = _out_wifireMux_T_262 & out_frontSel_40_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_424 = _out_wifireMux_T_423 & _out_T_1662; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_80 = _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_81 = _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_82 = _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_83 = _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_84 = _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_85 = _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_86 = _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_87 = _out_wifireMux_T_424; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_425 = ~_out_T_1662; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_427 = _out_wifireMux_T_262 & out_frontSel_41_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_428 = _out_wifireMux_T_427 & _out_T_1682; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_147 = _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_148 = _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_149 = _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_150 = _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_151 = _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_152 = _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_153 = _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_154 = _out_wifireMux_T_428; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_429 = ~_out_T_1682; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_431 = _out_wifireMux_T_262 & out_frontSel_42_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_432 = _out_wifireMux_T_431 & _out_T_1650; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_32 = _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_33 = _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_34 = _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_35 = _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_36 = _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_37 = _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_38 = _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_39 = _out_wifireMux_T_432; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_433 = ~_out_T_1650; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_435 = _out_wifireMux_T_262 & out_frontSel_43_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_436 = _out_wifireMux_T_435 & _out_T_1666; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_96 = _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_97 = _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_98 = _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_99 = _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_100 = _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_101 = _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_102 = _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_103 = _out_wifireMux_T_436; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_437 = ~_out_T_1666; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_439 = _out_wifireMux_T_262 & out_frontSel_44_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_440 = _out_wifireMux_T_439 & _out_T_1692; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_171 = _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_172 = _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_173 = _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_174 = _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_175 = _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_176 = _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_177 = _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_178 = _out_wifireMux_T_440; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_441 = ~_out_T_1692; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_443 = _out_wifireMux_T_262 & out_frontSel_45_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_444 = _out_wifireMux_T_443 & _out_T_1676; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_123 = _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_124 = _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_125 = _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_126 = _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_127 = _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_128 = _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_129 = _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_130 = _out_wifireMux_T_444; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_445 = ~_out_T_1676; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_447 = _out_wifireMux_T_262 & out_frontSel_46_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_448 = _out_wifireMux_T_447 & _out_T_1646; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_16 = _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_17 = _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_18 = _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_19 = _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_20 = _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_21 = _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_22 = _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_23 = _out_wifireMux_T_448; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_449 = ~_out_T_1646; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_451 = _out_wifireMux_T_262 & out_frontSel_47_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_452 = _out_wifireMux_T_451 & _out_T_1668; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_104 = _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_105 = _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_106 = _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_107 = _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_108 = _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_109 = _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_110 = _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_111 = _out_wifireMux_T_452; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_453 = ~_out_T_1668; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_455 = _out_wifireMux_T_262 & out_frontSel_48_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_456 = _out_wifireMux_T_455 & _out_T_1658; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_64 = _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_65 = _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_66 = _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_67 = _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_68 = _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_69 = _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_70 = _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_71 = _out_wifireMux_T_456; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_457 = ~_out_T_1658; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_459 = _out_wifireMux_T_262 & out_frontSel_49_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_460 = _out_wifireMux_T_459 & _out_T_1656; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_56 = _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_57 = _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_58 = _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_59 = _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_60 = _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_61 = _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_62 = _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_63 = _out_wifireMux_T_460; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_461 = ~_out_T_1656; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_463 = _out_wifireMux_T_262 & out_frontSel_50_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_464 = _out_wifireMux_T_463 & _out_T_1696; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_187 = _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_188 = _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_189 = _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_190 = _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_191 = _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_192 = _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_193 = _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_194 = _out_wifireMux_T_464; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_465 = ~_out_T_1696; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_467 = _out_wifireMux_T_262 & out_frontSel_51_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_468 = _out_wifireMux_T_467 & _out_T_1642; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_0 = _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_1 = _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_2 = _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_3 = _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_4 = _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_5 = _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_6 = _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_7 = _out_wifireMux_T_468; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_469 = ~_out_T_1642; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_471 = _out_wifireMux_T_262 & out_frontSel_52_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_472 = _out_wifireMux_T_471; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_475 = _out_wifireMux_T_262 & out_frontSel_53_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_476 = _out_wifireMux_T_475; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_479 = _out_wifireMux_T_262 & out_frontSel_54_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_480 = _out_wifireMux_T_479; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_483 = _out_wifireMux_T_262 & out_frontSel_55_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_484 = _out_wifireMux_T_483; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_487 = _out_wifireMux_T_262 & out_frontSel_56_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_488 = _out_wifireMux_T_487; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_491 = _out_wifireMux_T_262 & out_frontSel_57_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_492 = _out_wifireMux_T_491; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_495 = _out_wifireMux_T_262 & out_frontSel_58_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_496 = _out_wifireMux_T_495; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_499 = _out_wifireMux_T_262 & out_frontSel_59_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_500 = _out_wifireMux_T_499; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_503 = _out_wifireMux_T_262 & out_frontSel_60_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_504 = _out_wifireMux_T_503; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_507 = _out_wifireMux_T_262 & out_frontSel_61_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_508 = _out_wifireMux_T_507; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_511 = _out_wifireMux_T_262 & out_frontSel_62_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_512 = _out_wifireMux_T_511; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_515 = _out_wifireMux_T_262 & out_frontSel_63_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_516 = _out_wifireMux_T_515; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_519 = _out_wifireMux_T_262 & out_frontSel_64; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_520 = _out_wifireMux_T_519 & _out_T_1680; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_139 = _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_140 = _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_141 = _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_142 = _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_143 = _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_144 = _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_145 = _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_146 = _out_wifireMux_T_520; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_521 = ~_out_T_1680; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_523 = _out_wifireMux_T_262 & out_frontSel_65; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_524 = _out_wifireMux_T_523; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_527 = _out_wifireMux_T_262 & out_frontSel_66; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_528 = _out_wifireMux_T_527; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_531 = _out_wifireMux_T_262 & out_frontSel_67; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_532 = _out_wifireMux_T_531; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_535 = _out_wifireMux_T_262 & out_frontSel_68; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_536 = _out_wifireMux_T_535; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_539 = _out_wifireMux_T_262 & out_frontSel_69; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_540 = _out_wifireMux_T_539; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_543 = _out_wifireMux_T_262 & out_frontSel_70; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_544 = _out_wifireMux_T_543; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_547 = _out_wifireMux_T_262 & out_frontSel_71; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_548 = _out_wifireMux_T_547; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_551 = _out_wifireMux_T_262 & out_frontSel_72; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_552 = _out_wifireMux_T_551; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_555 = _out_wifireMux_T_262 & out_frontSel_73; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_556 = _out_wifireMux_T_555; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_559 = _out_wifireMux_T_262 & out_frontSel_74; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_560 = _out_wifireMux_T_559; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_563 = _out_wifireMux_T_262 & out_frontSel_75; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_564 = _out_wifireMux_T_563; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_567 = _out_wifireMux_T_262 & out_frontSel_76; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_568 = _out_wifireMux_T_567; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_571 = _out_wifireMux_T_262 & out_frontSel_77; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_572 = _out_wifireMux_T_571; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_575 = _out_wifireMux_T_262 & out_frontSel_78; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_576 = _out_wifireMux_T_575; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_579 = _out_wifireMux_T_262 & out_frontSel_79; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_580 = _out_wifireMux_T_579; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_583 = _out_wifireMux_T_262 & out_frontSel_80; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_584 = _out_wifireMux_T_583; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_587 = _out_wifireMux_T_262 & out_frontSel_81; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_588 = _out_wifireMux_T_587; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_591 = _out_wifireMux_T_262 & out_frontSel_82; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_592 = _out_wifireMux_T_591; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_595 = _out_wifireMux_T_262 & out_frontSel_83; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_596 = _out_wifireMux_T_595; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_599 = _out_wifireMux_T_262 & out_frontSel_84; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_600 = _out_wifireMux_T_599; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_603 = _out_wifireMux_T_262 & out_frontSel_85; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_604 = _out_wifireMux_T_603; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_607 = _out_wifireMux_T_262 & out_frontSel_86; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_608 = _out_wifireMux_T_607; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_611 = _out_wifireMux_T_262 & out_frontSel_87; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_612 = _out_wifireMux_T_611; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_615 = _out_wifireMux_T_262 & out_frontSel_88; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_616 = _out_wifireMux_T_615; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_619 = _out_wifireMux_T_262 & out_frontSel_89; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_620 = _out_wifireMux_T_619; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_623 = _out_wifireMux_T_262 & out_frontSel_90; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_624 = _out_wifireMux_T_623; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_627 = _out_wifireMux_T_262 & out_frontSel_91; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_628 = _out_wifireMux_T_627; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_631 = _out_wifireMux_T_262 & out_frontSel_92; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_632 = _out_wifireMux_T_631; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_635 = _out_wifireMux_T_262 & out_frontSel_93; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_636 = _out_wifireMux_T_635; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_639 = _out_wifireMux_T_262 & out_frontSel_94; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_640 = _out_wifireMux_T_639; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_643 = _out_wifireMux_T_262 & out_frontSel_95; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_644 = _out_wifireMux_T_643; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_647 = _out_wifireMux_T_262 & out_frontSel_96; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_648 = _out_wifireMux_T_647; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_651 = _out_wifireMux_T_262 & out_frontSel_97; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_652 = _out_wifireMux_T_651; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_655 = _out_wifireMux_T_262 & out_frontSel_98; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_656 = _out_wifireMux_T_655; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_659 = _out_wifireMux_T_262 & out_frontSel_99; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_660 = _out_wifireMux_T_659; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_663 = _out_wifireMux_T_262 & out_frontSel_100; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_664 = _out_wifireMux_T_663; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_667 = _out_wifireMux_T_262 & out_frontSel_101; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_668 = _out_wifireMux_T_667; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_671 = _out_wifireMux_T_262 & out_frontSel_102; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_672 = _out_wifireMux_T_671; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_675 = _out_wifireMux_T_262 & out_frontSel_103; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_676 = _out_wifireMux_T_675; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_679 = _out_wifireMux_T_262 & out_frontSel_104; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_680 = _out_wifireMux_T_679; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_683 = _out_wifireMux_T_262 & out_frontSel_105; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_684 = _out_wifireMux_T_683; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_687 = _out_wifireMux_T_262 & out_frontSel_106; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_688 = _out_wifireMux_T_687; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_691 = _out_wifireMux_T_262 & out_frontSel_107; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_692 = _out_wifireMux_T_691; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_695 = _out_wifireMux_T_262 & out_frontSel_108; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_696 = _out_wifireMux_T_695; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_699 = _out_wifireMux_T_262 & out_frontSel_109; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_700 = _out_wifireMux_T_699; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_703 = _out_wifireMux_T_262 & out_frontSel_110; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_704 = _out_wifireMux_T_703; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_707 = _out_wifireMux_T_262 & out_frontSel_111; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_708 = _out_wifireMux_T_707; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_711 = _out_wifireMux_T_262 & out_frontSel_112; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_712 = _out_wifireMux_T_711; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_715 = _out_wifireMux_T_262 & out_frontSel_113; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_716 = _out_wifireMux_T_715; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_719 = _out_wifireMux_T_262 & out_frontSel_114; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_720 = _out_wifireMux_T_719; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_723 = _out_wifireMux_T_262 & out_frontSel_115; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_724 = _out_wifireMux_T_723; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_727 = _out_wifireMux_T_262 & out_frontSel_116; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_728 = _out_wifireMux_T_727; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_731 = _out_wifireMux_T_262 & out_frontSel_117; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_732 = _out_wifireMux_T_731; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_735 = _out_wifireMux_T_262 & out_frontSel_118; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_736 = _out_wifireMux_T_735; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_739 = _out_wifireMux_T_262 & out_frontSel_119; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_740 = _out_wifireMux_T_739; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_743 = _out_wifireMux_T_262 & out_frontSel_120; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_744 = _out_wifireMux_T_743; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_747 = _out_wifireMux_T_262 & out_frontSel_121; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_748 = _out_wifireMux_T_747; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_751 = _out_wifireMux_T_262 & out_frontSel_122; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_752 = _out_wifireMux_T_751; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_755 = _out_wifireMux_T_262 & out_frontSel_123; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_756 = _out_wifireMux_T_755; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_759 = _out_wifireMux_T_262 & out_frontSel_124; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_760 = _out_wifireMux_T_759; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_763 = _out_wifireMux_T_262 & out_frontSel_125; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_764 = _out_wifireMux_T_763; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_767 = _out_wifireMux_T_262 & out_frontSel_126; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_768 = _out_wifireMux_T_767; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_771 = _out_wifireMux_T_262 & out_frontSel_127; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_772 = _out_wifireMux_T_771; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_775 = _out_wifireMux_T_262 & out_frontSel_128; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_776 = _out_wifireMux_T_775 & _out_T_1678; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_131 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_132 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_133 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_134 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_135 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_136 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_137 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_138 = _out_wifireMux_T_776; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_777 = ~_out_T_1678; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_779 = _out_wifireMux_T_262 & out_frontSel_129; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_780 = _out_wifireMux_T_779 & _out_T_1644; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_8 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_9 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_10 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_11 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_12 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_13 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_14 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_15 = _out_wifireMux_T_780; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_781 = ~_out_T_1644; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_783 = _out_wifireMux_T_262 & out_frontSel_130; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_784 = _out_wifireMux_T_783 & _out_T_1694; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_179 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_180 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_181 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_182 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_183 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_184 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_185 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_186 = _out_wifireMux_T_784; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_785 = ~_out_T_1694; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_787 = _out_wifireMux_T_262 & out_frontSel_131; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_788 = _out_wifireMux_T_787 & _out_T_1654; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_48 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_49 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_50 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_51 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_52 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_53 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_54 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_55 = _out_wifireMux_T_788; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_789 = ~_out_T_1654; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_791 = _out_wifireMux_T_262 & out_frontSel_132; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_792 = _out_wifireMux_T_791 & _out_T_1670; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_112 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_113 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_114 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_115 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_116 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_117 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_118 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_119 = _out_wifireMux_T_792; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_793 = ~_out_T_1670; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_795 = _out_wifireMux_T_262 & out_frontSel_133; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_796 = _out_wifireMux_T_795 & _out_T_1648; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_24 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_25 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_26 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_27 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_28 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_29 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_30 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_31 = _out_wifireMux_T_796; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_797 = ~_out_T_1648; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_799 = _out_wifireMux_T_262 & out_frontSel_134; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_800 = _out_wifireMux_T_799 & _out_T_1664; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_88 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_89 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_90 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_91 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_92 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_93 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_94 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_95 = _out_wifireMux_T_800; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_801 = ~_out_T_1664; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_803 = _out_wifireMux_T_262 & out_frontSel_135; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_804 = _out_wifireMux_T_803 & _out_T_1660; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_72 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_73 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_74 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_75 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_76 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_77 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_78 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_79 = _out_wifireMux_T_804; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_805 = ~_out_T_1660; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_807 = _out_wifireMux_T_262 & out_frontSel_136; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_808 = _out_wifireMux_T_807 & _out_T_1688; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_161 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_162 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_163 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_164 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_165 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_166 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_167 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_168 = _out_wifireMux_T_808; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_809 = ~_out_T_1688; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_811 = _out_wifireMux_T_262 & out_frontSel_137; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_812 = _out_wifireMux_T_811 & _out_T_1652; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_40 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_41 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_42 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_43 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_44 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_45 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_46 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_47 = _out_wifireMux_T_812; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_813 = ~_out_T_1652; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_815 = _out_wifireMux_T_262 & out_frontSel_138; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_816 = _out_wifireMux_T_815 & _out_T_1684; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_155 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_156 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_157 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1_158 = _out_wifireMux_T_816; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_817 = ~_out_T_1684; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_819 = _out_wifireMux_T_262 & out_frontSel_139; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_820 = _out_wifireMux_T_819; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_823 = _out_wifireMux_T_262 & out_frontSel_140; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_824 = _out_wifireMux_T_823; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_827 = _out_wifireMux_T_262 & out_frontSel_141; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_828 = _out_wifireMux_T_827; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_831 = _out_wifireMux_T_262 & out_frontSel_142; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_832 = _out_wifireMux_T_831; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_835 = _out_wifireMux_T_262 & out_frontSel_143; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_836 = _out_wifireMux_T_835; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_839 = _out_wifireMux_T_262 & out_frontSel_144; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_840 = _out_wifireMux_T_839; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_843 = _out_wifireMux_T_262 & out_frontSel_145; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_844 = _out_wifireMux_T_843; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_847 = _out_wifireMux_T_262 & out_frontSel_146; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_848 = _out_wifireMux_T_847; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_851 = _out_wifireMux_T_262 & out_frontSel_147; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_852 = _out_wifireMux_T_851; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_855 = _out_wifireMux_T_262 & out_frontSel_148; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_856 = _out_wifireMux_T_855; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_859 = _out_wifireMux_T_262 & out_frontSel_149; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_860 = _out_wifireMux_T_859; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_863 = _out_wifireMux_T_262 & out_frontSel_150; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_864 = _out_wifireMux_T_863; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_867 = _out_wifireMux_T_262 & out_frontSel_151; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_868 = _out_wifireMux_T_867; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_871 = _out_wifireMux_T_262 & out_frontSel_152; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_872 = _out_wifireMux_T_871; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_875 = _out_wifireMux_T_262 & out_frontSel_153; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_876 = _out_wifireMux_T_875; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_879 = _out_wifireMux_T_262 & out_frontSel_154; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_880 = _out_wifireMux_T_879; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_883 = _out_wifireMux_T_262 & out_frontSel_155; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_884 = _out_wifireMux_T_883; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_887 = _out_wifireMux_T_262 & out_frontSel_156; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_888 = _out_wifireMux_T_887; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_891 = _out_wifireMux_T_262 & out_frontSel_157; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_892 = _out_wifireMux_T_891; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_895 = _out_wifireMux_T_262 & out_frontSel_158; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_896 = _out_wifireMux_T_895; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_899 = _out_wifireMux_T_262 & out_frontSel_159; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_900 = _out_wifireMux_T_899; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_903 = _out_wifireMux_T_262 & out_frontSel_160; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_904 = _out_wifireMux_T_903; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_907 = _out_wifireMux_T_262 & out_frontSel_161; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_908 = _out_wifireMux_T_907; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_911 = _out_wifireMux_T_262 & out_frontSel_162; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_912 = _out_wifireMux_T_911; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_915 = _out_wifireMux_T_262 & out_frontSel_163; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_916 = _out_wifireMux_T_915; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_919 = _out_wifireMux_T_262 & out_frontSel_164; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_920 = _out_wifireMux_T_919; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_923 = _out_wifireMux_T_262 & out_frontSel_165; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_924 = _out_wifireMux_T_923; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_927 = _out_wifireMux_T_262 & out_frontSel_166; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_928 = _out_wifireMux_T_927; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_931 = _out_wifireMux_T_262 & out_frontSel_167; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_932 = _out_wifireMux_T_931; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_935 = _out_wifireMux_T_262 & out_frontSel_168; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_936 = _out_wifireMux_T_935; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_939 = _out_wifireMux_T_262 & out_frontSel_169; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_940 = _out_wifireMux_T_939; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_943 = _out_wifireMux_T_262 & out_frontSel_170; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_944 = _out_wifireMux_T_943; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_947 = _out_wifireMux_T_262 & out_frontSel_171; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_948 = _out_wifireMux_T_947; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_951 = _out_wifireMux_T_262 & out_frontSel_172; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_952 = _out_wifireMux_T_951; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_955 = _out_wifireMux_T_262 & out_frontSel_173; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_956 = _out_wifireMux_T_955; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_959 = _out_wifireMux_T_262 & out_frontSel_174; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_960 = _out_wifireMux_T_959; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_963 = _out_wifireMux_T_262 & out_frontSel_175; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_964 = _out_wifireMux_T_963; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_967 = _out_wifireMux_T_262 & out_frontSel_176; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_968 = _out_wifireMux_T_967; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_971 = _out_wifireMux_T_262 & out_frontSel_177; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_972 = _out_wifireMux_T_971; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_975 = _out_wifireMux_T_262 & out_frontSel_178; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_976 = _out_wifireMux_T_975; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_979 = _out_wifireMux_T_262 & out_frontSel_179; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_980 = _out_wifireMux_T_979; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_983 = _out_wifireMux_T_262 & out_frontSel_180; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_984 = _out_wifireMux_T_983; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_987 = _out_wifireMux_T_262 & out_frontSel_181; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_988 = _out_wifireMux_T_987; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_991 = _out_wifireMux_T_262 & out_frontSel_182; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_992 = _out_wifireMux_T_991; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_995 = _out_wifireMux_T_262 & out_frontSel_183; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_996 = _out_wifireMux_T_995; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_999 = _out_wifireMux_T_262 & out_frontSel_184; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1000 = _out_wifireMux_T_999; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1003 = _out_wifireMux_T_262 & out_frontSel_185; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1004 = _out_wifireMux_T_1003; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1007 = _out_wifireMux_T_262 & out_frontSel_186; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1008 = _out_wifireMux_T_1007; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1011 = _out_wifireMux_T_262 & out_frontSel_187; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1012 = _out_wifireMux_T_1011; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1015 = _out_wifireMux_T_262 & out_frontSel_188; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1016 = _out_wifireMux_T_1015; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1019 = _out_wifireMux_T_262 & out_frontSel_189; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1020 = _out_wifireMux_T_1019; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1023 = _out_wifireMux_T_262 & out_frontSel_190; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1024 = _out_wifireMux_T_1023; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1027 = _out_wifireMux_T_262 & out_frontSel_191; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1028 = _out_wifireMux_T_1027; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1031 = _out_wifireMux_T_262 & out_frontSel_192; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1032 = _out_wifireMux_T_1031; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1035 = _out_wifireMux_T_262 & out_frontSel_193; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1036 = _out_wifireMux_T_1035; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1039 = _out_wifireMux_T_262 & out_frontSel_194; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1040 = _out_wifireMux_T_1039; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1043 = _out_wifireMux_T_262 & out_frontSel_195; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1044 = _out_wifireMux_T_1043; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1047 = _out_wifireMux_T_262 & out_frontSel_196; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1048 = _out_wifireMux_T_1047; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1051 = _out_wifireMux_T_262 & out_frontSel_197; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1052 = _out_wifireMux_T_1051; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1055 = _out_wifireMux_T_262 & out_frontSel_198; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1056 = _out_wifireMux_T_1055; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1059 = _out_wifireMux_T_262 & out_frontSel_199; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1060 = _out_wifireMux_T_1059; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1063 = _out_wifireMux_T_262 & out_frontSel_200; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1064 = _out_wifireMux_T_1063; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1067 = _out_wifireMux_T_262 & out_frontSel_201; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1068 = _out_wifireMux_T_1067; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1071 = _out_wifireMux_T_262 & out_frontSel_202; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1072 = _out_wifireMux_T_1071; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1075 = _out_wifireMux_T_262 & out_frontSel_203; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1076 = _out_wifireMux_T_1075; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1079 = _out_wifireMux_T_262 & out_frontSel_204; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1080 = _out_wifireMux_T_1079; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1083 = _out_wifireMux_T_262 & out_frontSel_205; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1084 = _out_wifireMux_T_1083; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1087 = _out_wifireMux_T_262 & out_frontSel_206; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1088 = _out_wifireMux_T_1087; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1091 = _out_wifireMux_T_262 & out_frontSel_207; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1092 = _out_wifireMux_T_1091; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1095 = _out_wifireMux_T_262 & out_frontSel_208; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1096 = _out_wifireMux_T_1095; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1099 = _out_wifireMux_T_262 & out_frontSel_209; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1100 = _out_wifireMux_T_1099; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1103 = _out_wifireMux_T_262 & out_frontSel_210; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1104 = _out_wifireMux_T_1103; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1107 = _out_wifireMux_T_262 & out_frontSel_211; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1108 = _out_wifireMux_T_1107; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1111 = _out_wifireMux_T_262 & out_frontSel_212; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1112 = _out_wifireMux_T_1111; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1115 = _out_wifireMux_T_262 & out_frontSel_213; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1116 = _out_wifireMux_T_1115; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1119 = _out_wifireMux_T_262 & out_frontSel_214; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1120 = _out_wifireMux_T_1119; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1123 = _out_wifireMux_T_262 & out_frontSel_215; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1124 = _out_wifireMux_T_1123; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1127 = _out_wifireMux_T_262 & out_frontSel_216; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1128 = _out_wifireMux_T_1127; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1131 = _out_wifireMux_T_262 & out_frontSel_217; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1132 = _out_wifireMux_T_1131; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1135 = _out_wifireMux_T_262 & out_frontSel_218; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1136 = _out_wifireMux_T_1135; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1139 = _out_wifireMux_T_262 & out_frontSel_219; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1140 = _out_wifireMux_T_1139; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1143 = _out_wifireMux_T_262 & out_frontSel_220; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1144 = _out_wifireMux_T_1143; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1147 = _out_wifireMux_T_262 & out_frontSel_221; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1148 = _out_wifireMux_T_1147; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1151 = _out_wifireMux_T_262 & out_frontSel_222; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1152 = _out_wifireMux_T_1151; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1155 = _out_wifireMux_T_262 & out_frontSel_223; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1156 = _out_wifireMux_T_1155; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1159 = _out_wifireMux_T_262 & out_frontSel_224; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1160 = _out_wifireMux_T_1159; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1163 = _out_wifireMux_T_262 & out_frontSel_225; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1164 = _out_wifireMux_T_1163; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1167 = _out_wifireMux_T_262 & out_frontSel_226; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1168 = _out_wifireMux_T_1167; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1171 = _out_wifireMux_T_262 & out_frontSel_227; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1172 = _out_wifireMux_T_1171; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1175 = _out_wifireMux_T_262 & out_frontSel_228; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1176 = _out_wifireMux_T_1175; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1179 = _out_wifireMux_T_262 & out_frontSel_229; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1180 = _out_wifireMux_T_1179; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1183 = _out_wifireMux_T_262 & out_frontSel_230; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1184 = _out_wifireMux_T_1183; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1187 = _out_wifireMux_T_262 & out_frontSel_231; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1188 = _out_wifireMux_T_1187; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1191 = _out_wifireMux_T_262 & out_frontSel_232; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1192 = _out_wifireMux_T_1191; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1195 = _out_wifireMux_T_262 & out_frontSel_233; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1196 = _out_wifireMux_T_1195; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1199 = _out_wifireMux_T_262 & out_frontSel_234; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1200 = _out_wifireMux_T_1199; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1203 = _out_wifireMux_T_262 & out_frontSel_235; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1204 = _out_wifireMux_T_1203; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1207 = _out_wifireMux_T_262 & out_frontSel_236; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1208 = _out_wifireMux_T_1207; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1211 = _out_wifireMux_T_262 & out_frontSel_237; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1212 = _out_wifireMux_T_1211; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1215 = _out_wifireMux_T_262 & out_frontSel_238; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1216 = _out_wifireMux_T_1215; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1219 = _out_wifireMux_T_262 & out_frontSel_239; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1220 = _out_wifireMux_T_1219; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1223 = _out_wifireMux_T_262 & out_frontSel_240; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1224 = _out_wifireMux_T_1223; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1227 = _out_wifireMux_T_262 & out_frontSel_241; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1228 = _out_wifireMux_T_1227; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1231 = _out_wifireMux_T_262 & out_frontSel_242; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1232 = _out_wifireMux_T_1231; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1235 = _out_wifireMux_T_262 & out_frontSel_243; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1236 = _out_wifireMux_T_1235; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1239 = _out_wifireMux_T_262 & out_frontSel_244; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1240 = _out_wifireMux_T_1239; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1243 = _out_wifireMux_T_262 & out_frontSel_245; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1244 = _out_wifireMux_T_1243; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1247 = _out_wifireMux_T_262 & out_frontSel_246; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1248 = _out_wifireMux_T_1247; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1251 = _out_wifireMux_T_262 & out_frontSel_247; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1252 = _out_wifireMux_T_1251; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1255 = _out_wifireMux_T_262 & out_frontSel_248; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1256 = _out_wifireMux_T_1255; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1259 = _out_wifireMux_T_262 & out_frontSel_249; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1260 = _out_wifireMux_T_1259; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1263 = _out_wifireMux_T_262 & out_frontSel_250; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1264 = _out_wifireMux_T_1263; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1267 = _out_wifireMux_T_262 & out_frontSel_251; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1268 = _out_wifireMux_T_1267; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1271 = _out_wifireMux_T_262 & out_frontSel_252; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1272 = _out_wifireMux_T_1271; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1275 = _out_wifireMux_T_262 & out_frontSel_253; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1276 = _out_wifireMux_T_1275; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1279 = _out_wifireMux_T_262 & out_frontSel_254; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1280 = _out_wifireMux_T_1279; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1283 = _out_wifireMux_T_262 & out_frontSel_255; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1284 = _out_wifireMux_T_1283; // @[RegisterRouter.scala:87:24]
wire _GEN_38 = out_front_1_valid & out_1_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_259; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_259 = _GEN_38; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_260; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_260 = _GEN_38; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_260 = _out_rofireMux_T_259 & out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_261 = _out_rofireMux_T_260 & out_backSel_0_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_262 = _out_rofireMux_T_261 & _out_T_1687; // @[RegisterRouter.scala:87:24]
assign out_roready_1_159 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
assign out_roready_1_160 = _out_rofireMux_T_262; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_263 = ~_out_T_1687; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_265 = _out_rofireMux_T_260 & out_backSel_1_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_266 = _out_rofireMux_T_265 & _out_T_1673; // @[RegisterRouter.scala:87:24]
assign out_roready_1_120 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
assign out_roready_1_121 = _out_rofireMux_T_266; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_267 = ~_out_T_1673; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_269 = _out_rofireMux_T_260 & out_backSel_2_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_270 = _out_rofireMux_T_269; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_273 = _out_rofireMux_T_260 & out_backSel_3_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_274 = _out_rofireMux_T_273; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_277 = _out_rofireMux_T_260 & out_backSel_4_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_278 = _out_rofireMux_T_277; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_281 = _out_rofireMux_T_260 & out_backSel_5_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_282 = _out_rofireMux_T_281; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_285 = _out_rofireMux_T_260 & out_backSel_6_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_286 = _out_rofireMux_T_285; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_289 = _out_rofireMux_T_260 & out_backSel_7_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_290 = _out_rofireMux_T_289; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_293 = _out_rofireMux_T_260 & out_backSel_8_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_294 = _out_rofireMux_T_293; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_297 = _out_rofireMux_T_260 & out_backSel_9_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_298 = _out_rofireMux_T_297; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_301 = _out_rofireMux_T_260 & out_backSel_10_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_302 = _out_rofireMux_T_301; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_305 = _out_rofireMux_T_260 & out_backSel_11_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_306 = _out_rofireMux_T_305; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_309 = _out_rofireMux_T_260 & out_backSel_12_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_310 = _out_rofireMux_T_309; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_313 = _out_rofireMux_T_260 & out_backSel_13_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_314 = _out_rofireMux_T_313; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_317 = _out_rofireMux_T_260 & out_backSel_14_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_318 = _out_rofireMux_T_317; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_321 = _out_rofireMux_T_260 & out_backSel_15_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_322 = _out_rofireMux_T_321; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_325 = _out_rofireMux_T_260 & out_backSel_16_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_326 = _out_rofireMux_T_325; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_329 = _out_rofireMux_T_260 & out_backSel_17_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_330 = _out_rofireMux_T_329; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_333 = _out_rofireMux_T_260 & out_backSel_18_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_334 = _out_rofireMux_T_333; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_337 = _out_rofireMux_T_260 & out_backSel_19_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_338 = _out_rofireMux_T_337; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_341 = _out_rofireMux_T_260 & out_backSel_20_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_342 = _out_rofireMux_T_341; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_345 = _out_rofireMux_T_260 & out_backSel_21_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_346 = _out_rofireMux_T_345; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_349 = _out_rofireMux_T_260 & out_backSel_22_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_350 = _out_rofireMux_T_349; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_353 = _out_rofireMux_T_260 & out_backSel_23_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_354 = _out_rofireMux_T_353; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_357 = _out_rofireMux_T_260 & out_backSel_24_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_358 = _out_rofireMux_T_357; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_361 = _out_rofireMux_T_260 & out_backSel_25_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_362 = _out_rofireMux_T_361; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_365 = _out_rofireMux_T_260 & out_backSel_26_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_366 = _out_rofireMux_T_365; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_369 = _out_rofireMux_T_260 & out_backSel_27_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_370 = _out_rofireMux_T_369; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_373 = _out_rofireMux_T_260 & out_backSel_28_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_374 = _out_rofireMux_T_373; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_377 = _out_rofireMux_T_260 & out_backSel_29_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_378 = _out_rofireMux_T_377; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_381 = _out_rofireMux_T_260 & out_backSel_30_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_382 = _out_rofireMux_T_381; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_385 = _out_rofireMux_T_260 & out_backSel_31_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_386 = _out_rofireMux_T_385; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_389 = _out_rofireMux_T_260 & out_backSel_32_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_390 = _out_rofireMux_T_389 & _out_T_1675; // @[RegisterRouter.scala:87:24]
assign out_roready_1_122 = _out_rofireMux_T_390; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_391 = ~_out_T_1675; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_393 = _out_rofireMux_T_260 & out_backSel_33_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_394 = _out_rofireMux_T_393; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_397 = _out_rofireMux_T_260 & out_backSel_34_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_398 = _out_rofireMux_T_397; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_401 = _out_rofireMux_T_260 & out_backSel_35_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_402 = _out_rofireMux_T_401; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_405 = _out_rofireMux_T_260 & out_backSel_36_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_406 = _out_rofireMux_T_405; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_409 = _out_rofireMux_T_260 & out_backSel_37_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_410 = _out_rofireMux_T_409; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_413 = _out_rofireMux_T_260 & out_backSel_38_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_414 = _out_rofireMux_T_413; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_417 = _out_rofireMux_T_260 & out_backSel_39_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_418 = _out_rofireMux_T_417 & _out_T_1691; // @[RegisterRouter.scala:87:24]
assign out_roready_1_169 = _out_rofireMux_T_418; // @[RegisterRouter.scala:87:24]
assign out_roready_1_170 = _out_rofireMux_T_418; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_419 = ~_out_T_1691; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_421 = _out_rofireMux_T_260 & out_backSel_40_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_422 = _out_rofireMux_T_421 & _out_T_1663; // @[RegisterRouter.scala:87:24]
assign out_roready_1_80 = _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_roready_1_81 = _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_roready_1_82 = _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_roready_1_83 = _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_roready_1_84 = _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_roready_1_85 = _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_roready_1_86 = _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
assign out_roready_1_87 = _out_rofireMux_T_422; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_423 = ~_out_T_1663; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_425 = _out_rofireMux_T_260 & out_backSel_41_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_426 = _out_rofireMux_T_425 & _out_T_1683; // @[RegisterRouter.scala:87:24]
assign out_roready_1_147 = _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_roready_1_148 = _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_roready_1_149 = _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_roready_1_150 = _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_roready_1_151 = _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_roready_1_152 = _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_roready_1_153 = _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
assign out_roready_1_154 = _out_rofireMux_T_426; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_427 = ~_out_T_1683; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_429 = _out_rofireMux_T_260 & out_backSel_42_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_430 = _out_rofireMux_T_429 & _out_T_1651; // @[RegisterRouter.scala:87:24]
assign out_roready_1_32 = _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_roready_1_33 = _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_roready_1_34 = _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_roready_1_35 = _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_roready_1_36 = _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_roready_1_37 = _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_roready_1_38 = _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
assign out_roready_1_39 = _out_rofireMux_T_430; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_431 = ~_out_T_1651; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_433 = _out_rofireMux_T_260 & out_backSel_43_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_434 = _out_rofireMux_T_433 & _out_T_1667; // @[RegisterRouter.scala:87:24]
assign out_roready_1_96 = _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_roready_1_97 = _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_roready_1_98 = _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_roready_1_99 = _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_roready_1_100 = _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_roready_1_101 = _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_roready_1_102 = _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
assign out_roready_1_103 = _out_rofireMux_T_434; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_435 = ~_out_T_1667; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_437 = _out_rofireMux_T_260 & out_backSel_44_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_438 = _out_rofireMux_T_437 & _out_T_1693; // @[RegisterRouter.scala:87:24]
assign out_roready_1_171 = _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_roready_1_172 = _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_roready_1_173 = _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_roready_1_174 = _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_roready_1_175 = _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_roready_1_176 = _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_roready_1_177 = _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
assign out_roready_1_178 = _out_rofireMux_T_438; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_439 = ~_out_T_1693; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_441 = _out_rofireMux_T_260 & out_backSel_45_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_442 = _out_rofireMux_T_441 & _out_T_1677; // @[RegisterRouter.scala:87:24]
assign out_roready_1_123 = _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_roready_1_124 = _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_roready_1_125 = _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_roready_1_126 = _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_roready_1_127 = _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_roready_1_128 = _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_roready_1_129 = _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
assign out_roready_1_130 = _out_rofireMux_T_442; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_443 = ~_out_T_1677; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_445 = _out_rofireMux_T_260 & out_backSel_46_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_446 = _out_rofireMux_T_445 & _out_T_1647; // @[RegisterRouter.scala:87:24]
assign out_roready_1_16 = _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_roready_1_17 = _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_roready_1_18 = _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_roready_1_19 = _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_roready_1_20 = _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_roready_1_21 = _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_roready_1_22 = _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
assign out_roready_1_23 = _out_rofireMux_T_446; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_447 = ~_out_T_1647; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_449 = _out_rofireMux_T_260 & out_backSel_47_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_450 = _out_rofireMux_T_449 & _out_T_1669; // @[RegisterRouter.scala:87:24]
assign out_roready_1_104 = _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_roready_1_105 = _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_roready_1_106 = _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_roready_1_107 = _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_roready_1_108 = _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_roready_1_109 = _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_roready_1_110 = _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
assign out_roready_1_111 = _out_rofireMux_T_450; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_451 = ~_out_T_1669; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_453 = _out_rofireMux_T_260 & out_backSel_48_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_454 = _out_rofireMux_T_453 & _out_T_1659; // @[RegisterRouter.scala:87:24]
assign out_roready_1_64 = _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_roready_1_65 = _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_roready_1_66 = _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_roready_1_67 = _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_roready_1_68 = _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_roready_1_69 = _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_roready_1_70 = _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
assign out_roready_1_71 = _out_rofireMux_T_454; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_455 = ~_out_T_1659; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_457 = _out_rofireMux_T_260 & out_backSel_49_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_458 = _out_rofireMux_T_457 & _out_T_1657; // @[RegisterRouter.scala:87:24]
assign out_roready_1_56 = _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_roready_1_57 = _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_roready_1_58 = _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_roready_1_59 = _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_roready_1_60 = _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_roready_1_61 = _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_roready_1_62 = _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
assign out_roready_1_63 = _out_rofireMux_T_458; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_459 = ~_out_T_1657; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_461 = _out_rofireMux_T_260 & out_backSel_50_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_462 = _out_rofireMux_T_461 & _out_T_1697; // @[RegisterRouter.scala:87:24]
assign out_roready_1_187 = _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_roready_1_188 = _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_roready_1_189 = _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_roready_1_190 = _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_roready_1_191 = _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_roready_1_192 = _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_roready_1_193 = _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
assign out_roready_1_194 = _out_rofireMux_T_462; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_463 = ~_out_T_1697; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_465 = _out_rofireMux_T_260 & out_backSel_51_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_466 = _out_rofireMux_T_465 & _out_T_1643; // @[RegisterRouter.scala:87:24]
assign out_roready_1_0 = _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_roready_1_1 = _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_roready_1_2 = _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_roready_1_3 = _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_roready_1_4 = _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_roready_1_5 = _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_roready_1_6 = _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
assign out_roready_1_7 = _out_rofireMux_T_466; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_467 = ~_out_T_1643; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_469 = _out_rofireMux_T_260 & out_backSel_52_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_470 = _out_rofireMux_T_469; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_473 = _out_rofireMux_T_260 & out_backSel_53_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_474 = _out_rofireMux_T_473; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_477 = _out_rofireMux_T_260 & out_backSel_54_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_478 = _out_rofireMux_T_477; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_481 = _out_rofireMux_T_260 & out_backSel_55_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_482 = _out_rofireMux_T_481; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_485 = _out_rofireMux_T_260 & out_backSel_56_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_486 = _out_rofireMux_T_485; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_489 = _out_rofireMux_T_260 & out_backSel_57_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_490 = _out_rofireMux_T_489; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_493 = _out_rofireMux_T_260 & out_backSel_58_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_494 = _out_rofireMux_T_493; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_497 = _out_rofireMux_T_260 & out_backSel_59_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_498 = _out_rofireMux_T_497; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_501 = _out_rofireMux_T_260 & out_backSel_60_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_502 = _out_rofireMux_T_501; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_505 = _out_rofireMux_T_260 & out_backSel_61_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_506 = _out_rofireMux_T_505; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_509 = _out_rofireMux_T_260 & out_backSel_62_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_510 = _out_rofireMux_T_509; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_513 = _out_rofireMux_T_260 & out_backSel_63_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_514 = _out_rofireMux_T_513; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_517 = _out_rofireMux_T_260 & out_backSel_64; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_518 = _out_rofireMux_T_517 & _out_T_1681; // @[RegisterRouter.scala:87:24]
assign out_roready_1_139 = _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_roready_1_140 = _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_roready_1_141 = _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_roready_1_142 = _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_roready_1_143 = _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_roready_1_144 = _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_roready_1_145 = _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
assign out_roready_1_146 = _out_rofireMux_T_518; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_519 = ~_out_T_1681; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_521 = _out_rofireMux_T_260 & out_backSel_65; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_522 = _out_rofireMux_T_521; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_525 = _out_rofireMux_T_260 & out_backSel_66; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_526 = _out_rofireMux_T_525; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_529 = _out_rofireMux_T_260 & out_backSel_67; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_530 = _out_rofireMux_T_529; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_533 = _out_rofireMux_T_260 & out_backSel_68; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_534 = _out_rofireMux_T_533; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_537 = _out_rofireMux_T_260 & out_backSel_69; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_538 = _out_rofireMux_T_537; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_541 = _out_rofireMux_T_260 & out_backSel_70; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_542 = _out_rofireMux_T_541; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_545 = _out_rofireMux_T_260 & out_backSel_71; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_546 = _out_rofireMux_T_545; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_549 = _out_rofireMux_T_260 & out_backSel_72; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_550 = _out_rofireMux_T_549; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_553 = _out_rofireMux_T_260 & out_backSel_73; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_554 = _out_rofireMux_T_553; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_557 = _out_rofireMux_T_260 & out_backSel_74; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_558 = _out_rofireMux_T_557; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_561 = _out_rofireMux_T_260 & out_backSel_75; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_562 = _out_rofireMux_T_561; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_565 = _out_rofireMux_T_260 & out_backSel_76; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_566 = _out_rofireMux_T_565; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_569 = _out_rofireMux_T_260 & out_backSel_77; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_570 = _out_rofireMux_T_569; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_573 = _out_rofireMux_T_260 & out_backSel_78; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_574 = _out_rofireMux_T_573; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_577 = _out_rofireMux_T_260 & out_backSel_79; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_578 = _out_rofireMux_T_577; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_581 = _out_rofireMux_T_260 & out_backSel_80; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_582 = _out_rofireMux_T_581; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_585 = _out_rofireMux_T_260 & out_backSel_81; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_586 = _out_rofireMux_T_585; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_589 = _out_rofireMux_T_260 & out_backSel_82; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_590 = _out_rofireMux_T_589; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_593 = _out_rofireMux_T_260 & out_backSel_83; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_594 = _out_rofireMux_T_593; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_597 = _out_rofireMux_T_260 & out_backSel_84; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_598 = _out_rofireMux_T_597; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_601 = _out_rofireMux_T_260 & out_backSel_85; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_602 = _out_rofireMux_T_601; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_605 = _out_rofireMux_T_260 & out_backSel_86; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_606 = _out_rofireMux_T_605; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_609 = _out_rofireMux_T_260 & out_backSel_87; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_610 = _out_rofireMux_T_609; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_613 = _out_rofireMux_T_260 & out_backSel_88; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_614 = _out_rofireMux_T_613; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_617 = _out_rofireMux_T_260 & out_backSel_89; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_618 = _out_rofireMux_T_617; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_621 = _out_rofireMux_T_260 & out_backSel_90; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_622 = _out_rofireMux_T_621; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_625 = _out_rofireMux_T_260 & out_backSel_91; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_626 = _out_rofireMux_T_625; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_629 = _out_rofireMux_T_260 & out_backSel_92; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_630 = _out_rofireMux_T_629; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_633 = _out_rofireMux_T_260 & out_backSel_93; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_634 = _out_rofireMux_T_633; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_637 = _out_rofireMux_T_260 & out_backSel_94; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_638 = _out_rofireMux_T_637; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_641 = _out_rofireMux_T_260 & out_backSel_95; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_642 = _out_rofireMux_T_641; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_645 = _out_rofireMux_T_260 & out_backSel_96; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_646 = _out_rofireMux_T_645; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_649 = _out_rofireMux_T_260 & out_backSel_97; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_650 = _out_rofireMux_T_649; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_653 = _out_rofireMux_T_260 & out_backSel_98; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_654 = _out_rofireMux_T_653; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_657 = _out_rofireMux_T_260 & out_backSel_99; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_658 = _out_rofireMux_T_657; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_661 = _out_rofireMux_T_260 & out_backSel_100; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_662 = _out_rofireMux_T_661; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_665 = _out_rofireMux_T_260 & out_backSel_101; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_666 = _out_rofireMux_T_665; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_669 = _out_rofireMux_T_260 & out_backSel_102; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_670 = _out_rofireMux_T_669; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_673 = _out_rofireMux_T_260 & out_backSel_103; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_674 = _out_rofireMux_T_673; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_677 = _out_rofireMux_T_260 & out_backSel_104; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_678 = _out_rofireMux_T_677; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_681 = _out_rofireMux_T_260 & out_backSel_105; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_682 = _out_rofireMux_T_681; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_685 = _out_rofireMux_T_260 & out_backSel_106; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_686 = _out_rofireMux_T_685; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_689 = _out_rofireMux_T_260 & out_backSel_107; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_690 = _out_rofireMux_T_689; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_693 = _out_rofireMux_T_260 & out_backSel_108; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_694 = _out_rofireMux_T_693; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_697 = _out_rofireMux_T_260 & out_backSel_109; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_698 = _out_rofireMux_T_697; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_701 = _out_rofireMux_T_260 & out_backSel_110; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_702 = _out_rofireMux_T_701; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_705 = _out_rofireMux_T_260 & out_backSel_111; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_706 = _out_rofireMux_T_705; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_709 = _out_rofireMux_T_260 & out_backSel_112; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_710 = _out_rofireMux_T_709; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_713 = _out_rofireMux_T_260 & out_backSel_113; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_714 = _out_rofireMux_T_713; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_717 = _out_rofireMux_T_260 & out_backSel_114; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_718 = _out_rofireMux_T_717; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_721 = _out_rofireMux_T_260 & out_backSel_115; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_722 = _out_rofireMux_T_721; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_725 = _out_rofireMux_T_260 & out_backSel_116; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_726 = _out_rofireMux_T_725; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_729 = _out_rofireMux_T_260 & out_backSel_117; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_730 = _out_rofireMux_T_729; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_733 = _out_rofireMux_T_260 & out_backSel_118; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_734 = _out_rofireMux_T_733; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_737 = _out_rofireMux_T_260 & out_backSel_119; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_738 = _out_rofireMux_T_737; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_741 = _out_rofireMux_T_260 & out_backSel_120; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_742 = _out_rofireMux_T_741; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_745 = _out_rofireMux_T_260 & out_backSel_121; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_746 = _out_rofireMux_T_745; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_749 = _out_rofireMux_T_260 & out_backSel_122; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_750 = _out_rofireMux_T_749; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_753 = _out_rofireMux_T_260 & out_backSel_123; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_754 = _out_rofireMux_T_753; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_757 = _out_rofireMux_T_260 & out_backSel_124; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_758 = _out_rofireMux_T_757; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_761 = _out_rofireMux_T_260 & out_backSel_125; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_762 = _out_rofireMux_T_761; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_765 = _out_rofireMux_T_260 & out_backSel_126; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_766 = _out_rofireMux_T_765; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_769 = _out_rofireMux_T_260 & out_backSel_127; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_770 = _out_rofireMux_T_769; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_773 = _out_rofireMux_T_260 & out_backSel_128; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_774 = _out_rofireMux_T_773 & _out_T_1679; // @[RegisterRouter.scala:87:24]
assign out_roready_1_131 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_132 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_133 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_134 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_135 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_136 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_137 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
assign out_roready_1_138 = _out_rofireMux_T_774; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_775 = ~_out_T_1679; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_777 = _out_rofireMux_T_260 & out_backSel_129; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_778 = _out_rofireMux_T_777 & _out_T_1645; // @[RegisterRouter.scala:87:24]
assign out_roready_1_8 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_9 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_10 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_11 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_12 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_13 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_14 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
assign out_roready_1_15 = _out_rofireMux_T_778; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_779 = ~_out_T_1645; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_781 = _out_rofireMux_T_260 & out_backSel_130; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_782 = _out_rofireMux_T_781 & _out_T_1695; // @[RegisterRouter.scala:87:24]
assign out_roready_1_179 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_180 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_181 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_182 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_183 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_184 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_185 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
assign out_roready_1_186 = _out_rofireMux_T_782; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_783 = ~_out_T_1695; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_785 = _out_rofireMux_T_260 & out_backSel_131; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_786 = _out_rofireMux_T_785 & _out_T_1655; // @[RegisterRouter.scala:87:24]
assign out_roready_1_48 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_49 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_50 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_51 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_52 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_53 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_54 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
assign out_roready_1_55 = _out_rofireMux_T_786; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_787 = ~_out_T_1655; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_789 = _out_rofireMux_T_260 & out_backSel_132; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_790 = _out_rofireMux_T_789 & _out_T_1671; // @[RegisterRouter.scala:87:24]
assign out_roready_1_112 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_113 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_114 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_115 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_116 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_117 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_118 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
assign out_roready_1_119 = _out_rofireMux_T_790; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_791 = ~_out_T_1671; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_793 = _out_rofireMux_T_260 & out_backSel_133; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_794 = _out_rofireMux_T_793 & _out_T_1649; // @[RegisterRouter.scala:87:24]
assign out_roready_1_24 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_25 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_26 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_27 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_28 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_29 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_30 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
assign out_roready_1_31 = _out_rofireMux_T_794; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_795 = ~_out_T_1649; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_797 = _out_rofireMux_T_260 & out_backSel_134; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_798 = _out_rofireMux_T_797 & _out_T_1665; // @[RegisterRouter.scala:87:24]
assign out_roready_1_88 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_89 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_90 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_91 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_92 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_93 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_94 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
assign out_roready_1_95 = _out_rofireMux_T_798; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_799 = ~_out_T_1665; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_801 = _out_rofireMux_T_260 & out_backSel_135; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_802 = _out_rofireMux_T_801 & _out_T_1661; // @[RegisterRouter.scala:87:24]
assign out_roready_1_72 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_73 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_74 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_75 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_76 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_77 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_78 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
assign out_roready_1_79 = _out_rofireMux_T_802; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_803 = ~_out_T_1661; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_805 = _out_rofireMux_T_260 & out_backSel_136; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_806 = _out_rofireMux_T_805 & _out_T_1689; // @[RegisterRouter.scala:87:24]
assign out_roready_1_161 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_162 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_163 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_164 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_165 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_166 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_167 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
assign out_roready_1_168 = _out_rofireMux_T_806; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_807 = ~_out_T_1689; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_809 = _out_rofireMux_T_260 & out_backSel_137; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_810 = _out_rofireMux_T_809 & _out_T_1653; // @[RegisterRouter.scala:87:24]
assign out_roready_1_40 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_41 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_42 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_43 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_44 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_45 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_46 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
assign out_roready_1_47 = _out_rofireMux_T_810; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_811 = ~_out_T_1653; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_813 = _out_rofireMux_T_260 & out_backSel_138; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_814 = _out_rofireMux_T_813 & _out_T_1685; // @[RegisterRouter.scala:87:24]
assign out_roready_1_155 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_156 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_157 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
assign out_roready_1_158 = _out_rofireMux_T_814; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_815 = ~_out_T_1685; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_817 = _out_rofireMux_T_260 & out_backSel_139; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_818 = _out_rofireMux_T_817; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_821 = _out_rofireMux_T_260 & out_backSel_140; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_822 = _out_rofireMux_T_821; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_825 = _out_rofireMux_T_260 & out_backSel_141; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_826 = _out_rofireMux_T_825; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_829 = _out_rofireMux_T_260 & out_backSel_142; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_830 = _out_rofireMux_T_829; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_833 = _out_rofireMux_T_260 & out_backSel_143; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_834 = _out_rofireMux_T_833; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_837 = _out_rofireMux_T_260 & out_backSel_144; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_838 = _out_rofireMux_T_837; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_841 = _out_rofireMux_T_260 & out_backSel_145; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_842 = _out_rofireMux_T_841; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_845 = _out_rofireMux_T_260 & out_backSel_146; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_846 = _out_rofireMux_T_845; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_849 = _out_rofireMux_T_260 & out_backSel_147; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_850 = _out_rofireMux_T_849; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_853 = _out_rofireMux_T_260 & out_backSel_148; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_854 = _out_rofireMux_T_853; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_857 = _out_rofireMux_T_260 & out_backSel_149; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_858 = _out_rofireMux_T_857; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_861 = _out_rofireMux_T_260 & out_backSel_150; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_862 = _out_rofireMux_T_861; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_865 = _out_rofireMux_T_260 & out_backSel_151; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_866 = _out_rofireMux_T_865; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_869 = _out_rofireMux_T_260 & out_backSel_152; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_870 = _out_rofireMux_T_869; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_873 = _out_rofireMux_T_260 & out_backSel_153; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_874 = _out_rofireMux_T_873; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_877 = _out_rofireMux_T_260 & out_backSel_154; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_878 = _out_rofireMux_T_877; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_881 = _out_rofireMux_T_260 & out_backSel_155; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_882 = _out_rofireMux_T_881; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_885 = _out_rofireMux_T_260 & out_backSel_156; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_886 = _out_rofireMux_T_885; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_889 = _out_rofireMux_T_260 & out_backSel_157; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_890 = _out_rofireMux_T_889; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_893 = _out_rofireMux_T_260 & out_backSel_158; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_894 = _out_rofireMux_T_893; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_897 = _out_rofireMux_T_260 & out_backSel_159; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_898 = _out_rofireMux_T_897; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_901 = _out_rofireMux_T_260 & out_backSel_160; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_902 = _out_rofireMux_T_901; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_905 = _out_rofireMux_T_260 & out_backSel_161; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_906 = _out_rofireMux_T_905; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_909 = _out_rofireMux_T_260 & out_backSel_162; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_910 = _out_rofireMux_T_909; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_913 = _out_rofireMux_T_260 & out_backSel_163; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_914 = _out_rofireMux_T_913; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_917 = _out_rofireMux_T_260 & out_backSel_164; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_918 = _out_rofireMux_T_917; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_921 = _out_rofireMux_T_260 & out_backSel_165; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_922 = _out_rofireMux_T_921; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_925 = _out_rofireMux_T_260 & out_backSel_166; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_926 = _out_rofireMux_T_925; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_929 = _out_rofireMux_T_260 & out_backSel_167; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_930 = _out_rofireMux_T_929; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_933 = _out_rofireMux_T_260 & out_backSel_168; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_934 = _out_rofireMux_T_933; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_937 = _out_rofireMux_T_260 & out_backSel_169; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_938 = _out_rofireMux_T_937; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_941 = _out_rofireMux_T_260 & out_backSel_170; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_942 = _out_rofireMux_T_941; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_945 = _out_rofireMux_T_260 & out_backSel_171; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_946 = _out_rofireMux_T_945; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_949 = _out_rofireMux_T_260 & out_backSel_172; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_950 = _out_rofireMux_T_949; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_953 = _out_rofireMux_T_260 & out_backSel_173; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_954 = _out_rofireMux_T_953; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_957 = _out_rofireMux_T_260 & out_backSel_174; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_958 = _out_rofireMux_T_957; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_961 = _out_rofireMux_T_260 & out_backSel_175; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_962 = _out_rofireMux_T_961; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_965 = _out_rofireMux_T_260 & out_backSel_176; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_966 = _out_rofireMux_T_965; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_969 = _out_rofireMux_T_260 & out_backSel_177; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_970 = _out_rofireMux_T_969; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_973 = _out_rofireMux_T_260 & out_backSel_178; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_974 = _out_rofireMux_T_973; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_977 = _out_rofireMux_T_260 & out_backSel_179; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_978 = _out_rofireMux_T_977; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_981 = _out_rofireMux_T_260 & out_backSel_180; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_982 = _out_rofireMux_T_981; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_985 = _out_rofireMux_T_260 & out_backSel_181; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_986 = _out_rofireMux_T_985; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_989 = _out_rofireMux_T_260 & out_backSel_182; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_990 = _out_rofireMux_T_989; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_993 = _out_rofireMux_T_260 & out_backSel_183; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_994 = _out_rofireMux_T_993; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_997 = _out_rofireMux_T_260 & out_backSel_184; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_998 = _out_rofireMux_T_997; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1001 = _out_rofireMux_T_260 & out_backSel_185; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1002 = _out_rofireMux_T_1001; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1005 = _out_rofireMux_T_260 & out_backSel_186; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1006 = _out_rofireMux_T_1005; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1009 = _out_rofireMux_T_260 & out_backSel_187; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1010 = _out_rofireMux_T_1009; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1013 = _out_rofireMux_T_260 & out_backSel_188; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1014 = _out_rofireMux_T_1013; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1017 = _out_rofireMux_T_260 & out_backSel_189; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1018 = _out_rofireMux_T_1017; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1021 = _out_rofireMux_T_260 & out_backSel_190; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1022 = _out_rofireMux_T_1021; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1025 = _out_rofireMux_T_260 & out_backSel_191; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1026 = _out_rofireMux_T_1025; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1029 = _out_rofireMux_T_260 & out_backSel_192; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1030 = _out_rofireMux_T_1029; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1033 = _out_rofireMux_T_260 & out_backSel_193; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1034 = _out_rofireMux_T_1033; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1037 = _out_rofireMux_T_260 & out_backSel_194; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1038 = _out_rofireMux_T_1037; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1041 = _out_rofireMux_T_260 & out_backSel_195; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1042 = _out_rofireMux_T_1041; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1045 = _out_rofireMux_T_260 & out_backSel_196; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1046 = _out_rofireMux_T_1045; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1049 = _out_rofireMux_T_260 & out_backSel_197; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1050 = _out_rofireMux_T_1049; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1053 = _out_rofireMux_T_260 & out_backSel_198; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1054 = _out_rofireMux_T_1053; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1057 = _out_rofireMux_T_260 & out_backSel_199; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1058 = _out_rofireMux_T_1057; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1061 = _out_rofireMux_T_260 & out_backSel_200; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1062 = _out_rofireMux_T_1061; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1065 = _out_rofireMux_T_260 & out_backSel_201; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1066 = _out_rofireMux_T_1065; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1069 = _out_rofireMux_T_260 & out_backSel_202; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1070 = _out_rofireMux_T_1069; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1073 = _out_rofireMux_T_260 & out_backSel_203; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1074 = _out_rofireMux_T_1073; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1077 = _out_rofireMux_T_260 & out_backSel_204; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1078 = _out_rofireMux_T_1077; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1081 = _out_rofireMux_T_260 & out_backSel_205; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1082 = _out_rofireMux_T_1081; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1085 = _out_rofireMux_T_260 & out_backSel_206; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1086 = _out_rofireMux_T_1085; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1089 = _out_rofireMux_T_260 & out_backSel_207; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1090 = _out_rofireMux_T_1089; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1093 = _out_rofireMux_T_260 & out_backSel_208; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1094 = _out_rofireMux_T_1093; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1097 = _out_rofireMux_T_260 & out_backSel_209; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1098 = _out_rofireMux_T_1097; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1101 = _out_rofireMux_T_260 & out_backSel_210; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1102 = _out_rofireMux_T_1101; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1105 = _out_rofireMux_T_260 & out_backSel_211; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1106 = _out_rofireMux_T_1105; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1109 = _out_rofireMux_T_260 & out_backSel_212; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1110 = _out_rofireMux_T_1109; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1113 = _out_rofireMux_T_260 & out_backSel_213; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1114 = _out_rofireMux_T_1113; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1117 = _out_rofireMux_T_260 & out_backSel_214; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1118 = _out_rofireMux_T_1117; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1121 = _out_rofireMux_T_260 & out_backSel_215; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1122 = _out_rofireMux_T_1121; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1125 = _out_rofireMux_T_260 & out_backSel_216; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1126 = _out_rofireMux_T_1125; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1129 = _out_rofireMux_T_260 & out_backSel_217; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1130 = _out_rofireMux_T_1129; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1133 = _out_rofireMux_T_260 & out_backSel_218; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1134 = _out_rofireMux_T_1133; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1137 = _out_rofireMux_T_260 & out_backSel_219; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1138 = _out_rofireMux_T_1137; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1141 = _out_rofireMux_T_260 & out_backSel_220; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1142 = _out_rofireMux_T_1141; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1145 = _out_rofireMux_T_260 & out_backSel_221; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1146 = _out_rofireMux_T_1145; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1149 = _out_rofireMux_T_260 & out_backSel_222; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1150 = _out_rofireMux_T_1149; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1153 = _out_rofireMux_T_260 & out_backSel_223; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1154 = _out_rofireMux_T_1153; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1157 = _out_rofireMux_T_260 & out_backSel_224; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1158 = _out_rofireMux_T_1157; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1161 = _out_rofireMux_T_260 & out_backSel_225; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1162 = _out_rofireMux_T_1161; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1165 = _out_rofireMux_T_260 & out_backSel_226; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1166 = _out_rofireMux_T_1165; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1169 = _out_rofireMux_T_260 & out_backSel_227; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1170 = _out_rofireMux_T_1169; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1173 = _out_rofireMux_T_260 & out_backSel_228; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1174 = _out_rofireMux_T_1173; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1177 = _out_rofireMux_T_260 & out_backSel_229; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1178 = _out_rofireMux_T_1177; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1181 = _out_rofireMux_T_260 & out_backSel_230; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1182 = _out_rofireMux_T_1181; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1185 = _out_rofireMux_T_260 & out_backSel_231; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1186 = _out_rofireMux_T_1185; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1189 = _out_rofireMux_T_260 & out_backSel_232; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1190 = _out_rofireMux_T_1189; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1193 = _out_rofireMux_T_260 & out_backSel_233; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1194 = _out_rofireMux_T_1193; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1197 = _out_rofireMux_T_260 & out_backSel_234; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1198 = _out_rofireMux_T_1197; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1201 = _out_rofireMux_T_260 & out_backSel_235; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1202 = _out_rofireMux_T_1201; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1205 = _out_rofireMux_T_260 & out_backSel_236; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1206 = _out_rofireMux_T_1205; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1209 = _out_rofireMux_T_260 & out_backSel_237; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1210 = _out_rofireMux_T_1209; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1213 = _out_rofireMux_T_260 & out_backSel_238; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1214 = _out_rofireMux_T_1213; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1217 = _out_rofireMux_T_260 & out_backSel_239; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1218 = _out_rofireMux_T_1217; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1221 = _out_rofireMux_T_260 & out_backSel_240; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1222 = _out_rofireMux_T_1221; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1225 = _out_rofireMux_T_260 & out_backSel_241; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1226 = _out_rofireMux_T_1225; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1229 = _out_rofireMux_T_260 & out_backSel_242; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1230 = _out_rofireMux_T_1229; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1233 = _out_rofireMux_T_260 & out_backSel_243; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1234 = _out_rofireMux_T_1233; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1237 = _out_rofireMux_T_260 & out_backSel_244; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1238 = _out_rofireMux_T_1237; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1241 = _out_rofireMux_T_260 & out_backSel_245; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1242 = _out_rofireMux_T_1241; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1245 = _out_rofireMux_T_260 & out_backSel_246; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1246 = _out_rofireMux_T_1245; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1249 = _out_rofireMux_T_260 & out_backSel_247; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1250 = _out_rofireMux_T_1249; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1253 = _out_rofireMux_T_260 & out_backSel_248; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1254 = _out_rofireMux_T_1253; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1257 = _out_rofireMux_T_260 & out_backSel_249; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1258 = _out_rofireMux_T_1257; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1261 = _out_rofireMux_T_260 & out_backSel_250; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1262 = _out_rofireMux_T_1261; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1265 = _out_rofireMux_T_260 & out_backSel_251; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1266 = _out_rofireMux_T_1265; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1269 = _out_rofireMux_T_260 & out_backSel_252; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1270 = _out_rofireMux_T_1269; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1273 = _out_rofireMux_T_260 & out_backSel_253; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1274 = _out_rofireMux_T_1273; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1277 = _out_rofireMux_T_260 & out_backSel_254; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1278 = _out_rofireMux_T_1277; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1281 = _out_rofireMux_T_260 & out_backSel_255; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1282 = _out_rofireMux_T_1281; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_261 = ~out_front_1_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_262 = _out_wofireMux_T_260 & _out_wofireMux_T_261; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_263 = _out_wofireMux_T_262 & out_backSel_0_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_264 = _out_wofireMux_T_263 & _out_T_1687; // @[RegisterRouter.scala:87:24]
assign out_woready_1_159 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
assign out_woready_1_160 = _out_wofireMux_T_264; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_265 = ~_out_T_1687; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_267 = _out_wofireMux_T_262 & out_backSel_1_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_268 = _out_wofireMux_T_267 & _out_T_1673; // @[RegisterRouter.scala:87:24]
assign out_woready_1_120 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
assign out_woready_1_121 = _out_wofireMux_T_268; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_269 = ~_out_T_1673; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_271 = _out_wofireMux_T_262 & out_backSel_2_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_272 = _out_wofireMux_T_271; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_275 = _out_wofireMux_T_262 & out_backSel_3_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_276 = _out_wofireMux_T_275; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_279 = _out_wofireMux_T_262 & out_backSel_4_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_280 = _out_wofireMux_T_279; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_283 = _out_wofireMux_T_262 & out_backSel_5_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_284 = _out_wofireMux_T_283; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_287 = _out_wofireMux_T_262 & out_backSel_6_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_288 = _out_wofireMux_T_287; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_291 = _out_wofireMux_T_262 & out_backSel_7_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_292 = _out_wofireMux_T_291; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_295 = _out_wofireMux_T_262 & out_backSel_8_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_296 = _out_wofireMux_T_295; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_299 = _out_wofireMux_T_262 & out_backSel_9_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_300 = _out_wofireMux_T_299; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_303 = _out_wofireMux_T_262 & out_backSel_10_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_304 = _out_wofireMux_T_303; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_307 = _out_wofireMux_T_262 & out_backSel_11_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_308 = _out_wofireMux_T_307; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_311 = _out_wofireMux_T_262 & out_backSel_12_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_312 = _out_wofireMux_T_311; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_315 = _out_wofireMux_T_262 & out_backSel_13_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_316 = _out_wofireMux_T_315; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_319 = _out_wofireMux_T_262 & out_backSel_14_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_320 = _out_wofireMux_T_319; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_323 = _out_wofireMux_T_262 & out_backSel_15_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_324 = _out_wofireMux_T_323; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_327 = _out_wofireMux_T_262 & out_backSel_16_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_328 = _out_wofireMux_T_327; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_331 = _out_wofireMux_T_262 & out_backSel_17_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_332 = _out_wofireMux_T_331; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_335 = _out_wofireMux_T_262 & out_backSel_18_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_336 = _out_wofireMux_T_335; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_339 = _out_wofireMux_T_262 & out_backSel_19_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_340 = _out_wofireMux_T_339; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_343 = _out_wofireMux_T_262 & out_backSel_20_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_344 = _out_wofireMux_T_343; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_347 = _out_wofireMux_T_262 & out_backSel_21_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_348 = _out_wofireMux_T_347; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_351 = _out_wofireMux_T_262 & out_backSel_22_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_352 = _out_wofireMux_T_351; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_355 = _out_wofireMux_T_262 & out_backSel_23_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_356 = _out_wofireMux_T_355; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_359 = _out_wofireMux_T_262 & out_backSel_24_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_360 = _out_wofireMux_T_359; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_363 = _out_wofireMux_T_262 & out_backSel_25_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_364 = _out_wofireMux_T_363; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_367 = _out_wofireMux_T_262 & out_backSel_26_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_368 = _out_wofireMux_T_367; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_371 = _out_wofireMux_T_262 & out_backSel_27_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_372 = _out_wofireMux_T_371; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_375 = _out_wofireMux_T_262 & out_backSel_28_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_376 = _out_wofireMux_T_375; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_379 = _out_wofireMux_T_262 & out_backSel_29_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_380 = _out_wofireMux_T_379; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_383 = _out_wofireMux_T_262 & out_backSel_30_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_384 = _out_wofireMux_T_383; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_387 = _out_wofireMux_T_262 & out_backSel_31_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_388 = _out_wofireMux_T_387; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_391 = _out_wofireMux_T_262 & out_backSel_32_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_392 = _out_wofireMux_T_391 & _out_T_1675; // @[RegisterRouter.scala:87:24]
assign out_woready_1_122 = _out_wofireMux_T_392; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_393 = ~_out_T_1675; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_395 = _out_wofireMux_T_262 & out_backSel_33_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_396 = _out_wofireMux_T_395; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_399 = _out_wofireMux_T_262 & out_backSel_34_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_400 = _out_wofireMux_T_399; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_403 = _out_wofireMux_T_262 & out_backSel_35_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_404 = _out_wofireMux_T_403; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_407 = _out_wofireMux_T_262 & out_backSel_36_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_408 = _out_wofireMux_T_407; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_411 = _out_wofireMux_T_262 & out_backSel_37_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_412 = _out_wofireMux_T_411; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_415 = _out_wofireMux_T_262 & out_backSel_38_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_416 = _out_wofireMux_T_415; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_419 = _out_wofireMux_T_262 & out_backSel_39_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_420 = _out_wofireMux_T_419 & _out_T_1691; // @[RegisterRouter.scala:87:24]
assign out_woready_1_169 = _out_wofireMux_T_420; // @[RegisterRouter.scala:87:24]
assign out_woready_1_170 = _out_wofireMux_T_420; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_421 = ~_out_T_1691; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_423 = _out_wofireMux_T_262 & out_backSel_40_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_424 = _out_wofireMux_T_423 & _out_T_1663; // @[RegisterRouter.scala:87:24]
assign out_woready_1_80 = _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_woready_1_81 = _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_woready_1_82 = _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_woready_1_83 = _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_woready_1_84 = _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_woready_1_85 = _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_woready_1_86 = _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
assign out_woready_1_87 = _out_wofireMux_T_424; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_425 = ~_out_T_1663; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_427 = _out_wofireMux_T_262 & out_backSel_41_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_428 = _out_wofireMux_T_427 & _out_T_1683; // @[RegisterRouter.scala:87:24]
assign out_woready_1_147 = _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_woready_1_148 = _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_woready_1_149 = _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_woready_1_150 = _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_woready_1_151 = _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_woready_1_152 = _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_woready_1_153 = _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
assign out_woready_1_154 = _out_wofireMux_T_428; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_429 = ~_out_T_1683; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_431 = _out_wofireMux_T_262 & out_backSel_42_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_432 = _out_wofireMux_T_431 & _out_T_1651; // @[RegisterRouter.scala:87:24]
assign out_woready_1_32 = _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_woready_1_33 = _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_woready_1_34 = _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_woready_1_35 = _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_woready_1_36 = _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_woready_1_37 = _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_woready_1_38 = _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
assign out_woready_1_39 = _out_wofireMux_T_432; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_433 = ~_out_T_1651; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_435 = _out_wofireMux_T_262 & out_backSel_43_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_436 = _out_wofireMux_T_435 & _out_T_1667; // @[RegisterRouter.scala:87:24]
assign out_woready_1_96 = _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_woready_1_97 = _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_woready_1_98 = _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_woready_1_99 = _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_woready_1_100 = _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_woready_1_101 = _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_woready_1_102 = _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
assign out_woready_1_103 = _out_wofireMux_T_436; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_437 = ~_out_T_1667; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_439 = _out_wofireMux_T_262 & out_backSel_44_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_440 = _out_wofireMux_T_439 & _out_T_1693; // @[RegisterRouter.scala:87:24]
assign out_woready_1_171 = _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_woready_1_172 = _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_woready_1_173 = _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_woready_1_174 = _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_woready_1_175 = _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_woready_1_176 = _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_woready_1_177 = _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
assign out_woready_1_178 = _out_wofireMux_T_440; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_441 = ~_out_T_1693; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_443 = _out_wofireMux_T_262 & out_backSel_45_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_444 = _out_wofireMux_T_443 & _out_T_1677; // @[RegisterRouter.scala:87:24]
assign out_woready_1_123 = _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_woready_1_124 = _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_woready_1_125 = _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_woready_1_126 = _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_woready_1_127 = _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_woready_1_128 = _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_woready_1_129 = _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
assign out_woready_1_130 = _out_wofireMux_T_444; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_445 = ~_out_T_1677; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_447 = _out_wofireMux_T_262 & out_backSel_46_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_448 = _out_wofireMux_T_447 & _out_T_1647; // @[RegisterRouter.scala:87:24]
assign out_woready_1_16 = _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_woready_1_17 = _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_woready_1_18 = _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_woready_1_19 = _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_woready_1_20 = _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_woready_1_21 = _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_woready_1_22 = _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
assign out_woready_1_23 = _out_wofireMux_T_448; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_449 = ~_out_T_1647; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_451 = _out_wofireMux_T_262 & out_backSel_47_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_452 = _out_wofireMux_T_451 & _out_T_1669; // @[RegisterRouter.scala:87:24]
assign out_woready_1_104 = _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_woready_1_105 = _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_woready_1_106 = _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_woready_1_107 = _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_woready_1_108 = _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_woready_1_109 = _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_woready_1_110 = _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
assign out_woready_1_111 = _out_wofireMux_T_452; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_453 = ~_out_T_1669; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_455 = _out_wofireMux_T_262 & out_backSel_48_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_456 = _out_wofireMux_T_455 & _out_T_1659; // @[RegisterRouter.scala:87:24]
assign out_woready_1_64 = _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_woready_1_65 = _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_woready_1_66 = _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_woready_1_67 = _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_woready_1_68 = _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_woready_1_69 = _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_woready_1_70 = _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
assign out_woready_1_71 = _out_wofireMux_T_456; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_457 = ~_out_T_1659; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_459 = _out_wofireMux_T_262 & out_backSel_49_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_460 = _out_wofireMux_T_459 & _out_T_1657; // @[RegisterRouter.scala:87:24]
assign out_woready_1_56 = _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_woready_1_57 = _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_woready_1_58 = _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_woready_1_59 = _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_woready_1_60 = _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_woready_1_61 = _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_woready_1_62 = _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
assign out_woready_1_63 = _out_wofireMux_T_460; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_461 = ~_out_T_1657; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_463 = _out_wofireMux_T_262 & out_backSel_50_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_464 = _out_wofireMux_T_463 & _out_T_1697; // @[RegisterRouter.scala:87:24]
assign out_woready_1_187 = _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_woready_1_188 = _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_woready_1_189 = _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_woready_1_190 = _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_woready_1_191 = _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_woready_1_192 = _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_woready_1_193 = _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
assign out_woready_1_194 = _out_wofireMux_T_464; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_465 = ~_out_T_1697; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_467 = _out_wofireMux_T_262 & out_backSel_51_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_468 = _out_wofireMux_T_467 & _out_T_1643; // @[RegisterRouter.scala:87:24]
assign out_woready_1_0 = _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_woready_1_1 = _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_woready_1_2 = _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_woready_1_3 = _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_woready_1_4 = _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_woready_1_5 = _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_woready_1_6 = _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
assign out_woready_1_7 = _out_wofireMux_T_468; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_469 = ~_out_T_1643; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_471 = _out_wofireMux_T_262 & out_backSel_52_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_472 = _out_wofireMux_T_471; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_475 = _out_wofireMux_T_262 & out_backSel_53_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_476 = _out_wofireMux_T_475; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_479 = _out_wofireMux_T_262 & out_backSel_54_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_480 = _out_wofireMux_T_479; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_483 = _out_wofireMux_T_262 & out_backSel_55_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_484 = _out_wofireMux_T_483; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_487 = _out_wofireMux_T_262 & out_backSel_56_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_488 = _out_wofireMux_T_487; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_491 = _out_wofireMux_T_262 & out_backSel_57_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_492 = _out_wofireMux_T_491; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_495 = _out_wofireMux_T_262 & out_backSel_58_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_496 = _out_wofireMux_T_495; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_499 = _out_wofireMux_T_262 & out_backSel_59_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_500 = _out_wofireMux_T_499; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_503 = _out_wofireMux_T_262 & out_backSel_60_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_504 = _out_wofireMux_T_503; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_507 = _out_wofireMux_T_262 & out_backSel_61_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_508 = _out_wofireMux_T_507; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_511 = _out_wofireMux_T_262 & out_backSel_62_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_512 = _out_wofireMux_T_511; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_515 = _out_wofireMux_T_262 & out_backSel_63_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_516 = _out_wofireMux_T_515; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_519 = _out_wofireMux_T_262 & out_backSel_64; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_520 = _out_wofireMux_T_519 & _out_T_1681; // @[RegisterRouter.scala:87:24]
assign out_woready_1_139 = _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_woready_1_140 = _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_woready_1_141 = _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_woready_1_142 = _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_woready_1_143 = _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_woready_1_144 = _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_woready_1_145 = _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
assign out_woready_1_146 = _out_wofireMux_T_520; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_521 = ~_out_T_1681; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_523 = _out_wofireMux_T_262 & out_backSel_65; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_524 = _out_wofireMux_T_523; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_527 = _out_wofireMux_T_262 & out_backSel_66; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_528 = _out_wofireMux_T_527; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_531 = _out_wofireMux_T_262 & out_backSel_67; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_532 = _out_wofireMux_T_531; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_535 = _out_wofireMux_T_262 & out_backSel_68; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_536 = _out_wofireMux_T_535; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_539 = _out_wofireMux_T_262 & out_backSel_69; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_540 = _out_wofireMux_T_539; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_543 = _out_wofireMux_T_262 & out_backSel_70; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_544 = _out_wofireMux_T_543; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_547 = _out_wofireMux_T_262 & out_backSel_71; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_548 = _out_wofireMux_T_547; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_551 = _out_wofireMux_T_262 & out_backSel_72; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_552 = _out_wofireMux_T_551; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_555 = _out_wofireMux_T_262 & out_backSel_73; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_556 = _out_wofireMux_T_555; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_559 = _out_wofireMux_T_262 & out_backSel_74; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_560 = _out_wofireMux_T_559; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_563 = _out_wofireMux_T_262 & out_backSel_75; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_564 = _out_wofireMux_T_563; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_567 = _out_wofireMux_T_262 & out_backSel_76; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_568 = _out_wofireMux_T_567; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_571 = _out_wofireMux_T_262 & out_backSel_77; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_572 = _out_wofireMux_T_571; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_575 = _out_wofireMux_T_262 & out_backSel_78; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_576 = _out_wofireMux_T_575; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_579 = _out_wofireMux_T_262 & out_backSel_79; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_580 = _out_wofireMux_T_579; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_583 = _out_wofireMux_T_262 & out_backSel_80; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_584 = _out_wofireMux_T_583; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_587 = _out_wofireMux_T_262 & out_backSel_81; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_588 = _out_wofireMux_T_587; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_591 = _out_wofireMux_T_262 & out_backSel_82; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_592 = _out_wofireMux_T_591; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_595 = _out_wofireMux_T_262 & out_backSel_83; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_596 = _out_wofireMux_T_595; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_599 = _out_wofireMux_T_262 & out_backSel_84; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_600 = _out_wofireMux_T_599; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_603 = _out_wofireMux_T_262 & out_backSel_85; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_604 = _out_wofireMux_T_603; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_607 = _out_wofireMux_T_262 & out_backSel_86; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_608 = _out_wofireMux_T_607; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_611 = _out_wofireMux_T_262 & out_backSel_87; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_612 = _out_wofireMux_T_611; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_615 = _out_wofireMux_T_262 & out_backSel_88; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_616 = _out_wofireMux_T_615; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_619 = _out_wofireMux_T_262 & out_backSel_89; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_620 = _out_wofireMux_T_619; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_623 = _out_wofireMux_T_262 & out_backSel_90; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_624 = _out_wofireMux_T_623; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_627 = _out_wofireMux_T_262 & out_backSel_91; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_628 = _out_wofireMux_T_627; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_631 = _out_wofireMux_T_262 & out_backSel_92; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_632 = _out_wofireMux_T_631; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_635 = _out_wofireMux_T_262 & out_backSel_93; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_636 = _out_wofireMux_T_635; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_639 = _out_wofireMux_T_262 & out_backSel_94; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_640 = _out_wofireMux_T_639; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_643 = _out_wofireMux_T_262 & out_backSel_95; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_644 = _out_wofireMux_T_643; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_647 = _out_wofireMux_T_262 & out_backSel_96; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_648 = _out_wofireMux_T_647; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_651 = _out_wofireMux_T_262 & out_backSel_97; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_652 = _out_wofireMux_T_651; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_655 = _out_wofireMux_T_262 & out_backSel_98; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_656 = _out_wofireMux_T_655; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_659 = _out_wofireMux_T_262 & out_backSel_99; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_660 = _out_wofireMux_T_659; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_663 = _out_wofireMux_T_262 & out_backSel_100; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_664 = _out_wofireMux_T_663; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_667 = _out_wofireMux_T_262 & out_backSel_101; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_668 = _out_wofireMux_T_667; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_671 = _out_wofireMux_T_262 & out_backSel_102; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_672 = _out_wofireMux_T_671; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_675 = _out_wofireMux_T_262 & out_backSel_103; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_676 = _out_wofireMux_T_675; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_679 = _out_wofireMux_T_262 & out_backSel_104; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_680 = _out_wofireMux_T_679; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_683 = _out_wofireMux_T_262 & out_backSel_105; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_684 = _out_wofireMux_T_683; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_687 = _out_wofireMux_T_262 & out_backSel_106; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_688 = _out_wofireMux_T_687; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_691 = _out_wofireMux_T_262 & out_backSel_107; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_692 = _out_wofireMux_T_691; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_695 = _out_wofireMux_T_262 & out_backSel_108; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_696 = _out_wofireMux_T_695; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_699 = _out_wofireMux_T_262 & out_backSel_109; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_700 = _out_wofireMux_T_699; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_703 = _out_wofireMux_T_262 & out_backSel_110; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_704 = _out_wofireMux_T_703; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_707 = _out_wofireMux_T_262 & out_backSel_111; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_708 = _out_wofireMux_T_707; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_711 = _out_wofireMux_T_262 & out_backSel_112; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_712 = _out_wofireMux_T_711; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_715 = _out_wofireMux_T_262 & out_backSel_113; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_716 = _out_wofireMux_T_715; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_719 = _out_wofireMux_T_262 & out_backSel_114; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_720 = _out_wofireMux_T_719; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_723 = _out_wofireMux_T_262 & out_backSel_115; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_724 = _out_wofireMux_T_723; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_727 = _out_wofireMux_T_262 & out_backSel_116; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_728 = _out_wofireMux_T_727; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_731 = _out_wofireMux_T_262 & out_backSel_117; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_732 = _out_wofireMux_T_731; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_735 = _out_wofireMux_T_262 & out_backSel_118; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_736 = _out_wofireMux_T_735; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_739 = _out_wofireMux_T_262 & out_backSel_119; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_740 = _out_wofireMux_T_739; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_743 = _out_wofireMux_T_262 & out_backSel_120; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_744 = _out_wofireMux_T_743; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_747 = _out_wofireMux_T_262 & out_backSel_121; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_748 = _out_wofireMux_T_747; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_751 = _out_wofireMux_T_262 & out_backSel_122; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_752 = _out_wofireMux_T_751; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_755 = _out_wofireMux_T_262 & out_backSel_123; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_756 = _out_wofireMux_T_755; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_759 = _out_wofireMux_T_262 & out_backSel_124; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_760 = _out_wofireMux_T_759; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_763 = _out_wofireMux_T_262 & out_backSel_125; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_764 = _out_wofireMux_T_763; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_767 = _out_wofireMux_T_262 & out_backSel_126; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_768 = _out_wofireMux_T_767; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_771 = _out_wofireMux_T_262 & out_backSel_127; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_772 = _out_wofireMux_T_771; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_775 = _out_wofireMux_T_262 & out_backSel_128; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_776 = _out_wofireMux_T_775 & _out_T_1679; // @[RegisterRouter.scala:87:24]
assign out_woready_1_131 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_132 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_133 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_134 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_135 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_136 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_137 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
assign out_woready_1_138 = _out_wofireMux_T_776; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_777 = ~_out_T_1679; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_779 = _out_wofireMux_T_262 & out_backSel_129; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_780 = _out_wofireMux_T_779 & _out_T_1645; // @[RegisterRouter.scala:87:24]
assign out_woready_1_8 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_9 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_10 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_11 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_12 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_13 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_14 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
assign out_woready_1_15 = _out_wofireMux_T_780; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_781 = ~_out_T_1645; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_783 = _out_wofireMux_T_262 & out_backSel_130; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_784 = _out_wofireMux_T_783 & _out_T_1695; // @[RegisterRouter.scala:87:24]
assign out_woready_1_179 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_180 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_181 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_182 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_183 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_184 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_185 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
assign out_woready_1_186 = _out_wofireMux_T_784; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_785 = ~_out_T_1695; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_787 = _out_wofireMux_T_262 & out_backSel_131; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_788 = _out_wofireMux_T_787 & _out_T_1655; // @[RegisterRouter.scala:87:24]
assign out_woready_1_48 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_49 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_50 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_51 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_52 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_53 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_54 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
assign out_woready_1_55 = _out_wofireMux_T_788; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_789 = ~_out_T_1655; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_791 = _out_wofireMux_T_262 & out_backSel_132; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_792 = _out_wofireMux_T_791 & _out_T_1671; // @[RegisterRouter.scala:87:24]
assign out_woready_1_112 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_113 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_114 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_115 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_116 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_117 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_118 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
assign out_woready_1_119 = _out_wofireMux_T_792; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_793 = ~_out_T_1671; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_795 = _out_wofireMux_T_262 & out_backSel_133; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_796 = _out_wofireMux_T_795 & _out_T_1649; // @[RegisterRouter.scala:87:24]
assign out_woready_1_24 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_25 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_26 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_27 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_28 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_29 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_30 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
assign out_woready_1_31 = _out_wofireMux_T_796; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_797 = ~_out_T_1649; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_799 = _out_wofireMux_T_262 & out_backSel_134; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_800 = _out_wofireMux_T_799 & _out_T_1665; // @[RegisterRouter.scala:87:24]
assign out_woready_1_88 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_89 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_90 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_91 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_92 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_93 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_94 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
assign out_woready_1_95 = _out_wofireMux_T_800; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_801 = ~_out_T_1665; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_803 = _out_wofireMux_T_262 & out_backSel_135; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_804 = _out_wofireMux_T_803 & _out_T_1661; // @[RegisterRouter.scala:87:24]
assign out_woready_1_72 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_73 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_74 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_75 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_76 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_77 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_78 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
assign out_woready_1_79 = _out_wofireMux_T_804; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_805 = ~_out_T_1661; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_807 = _out_wofireMux_T_262 & out_backSel_136; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_808 = _out_wofireMux_T_807 & _out_T_1689; // @[RegisterRouter.scala:87:24]
assign out_woready_1_161 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_162 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_163 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_164 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_165 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_166 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_167 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
assign out_woready_1_168 = _out_wofireMux_T_808; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_809 = ~_out_T_1689; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_811 = _out_wofireMux_T_262 & out_backSel_137; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_812 = _out_wofireMux_T_811 & _out_T_1653; // @[RegisterRouter.scala:87:24]
assign out_woready_1_40 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_41 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_42 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_43 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_44 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_45 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_46 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
assign out_woready_1_47 = _out_wofireMux_T_812; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_813 = ~_out_T_1653; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_815 = _out_wofireMux_T_262 & out_backSel_138; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_816 = _out_wofireMux_T_815 & _out_T_1685; // @[RegisterRouter.scala:87:24]
assign out_woready_1_155 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_156 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_157 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
assign out_woready_1_158 = _out_wofireMux_T_816; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_817 = ~_out_T_1685; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_819 = _out_wofireMux_T_262 & out_backSel_139; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_820 = _out_wofireMux_T_819; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_823 = _out_wofireMux_T_262 & out_backSel_140; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_824 = _out_wofireMux_T_823; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_827 = _out_wofireMux_T_262 & out_backSel_141; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_828 = _out_wofireMux_T_827; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_831 = _out_wofireMux_T_262 & out_backSel_142; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_832 = _out_wofireMux_T_831; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_835 = _out_wofireMux_T_262 & out_backSel_143; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_836 = _out_wofireMux_T_835; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_839 = _out_wofireMux_T_262 & out_backSel_144; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_840 = _out_wofireMux_T_839; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_843 = _out_wofireMux_T_262 & out_backSel_145; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_844 = _out_wofireMux_T_843; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_847 = _out_wofireMux_T_262 & out_backSel_146; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_848 = _out_wofireMux_T_847; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_851 = _out_wofireMux_T_262 & out_backSel_147; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_852 = _out_wofireMux_T_851; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_855 = _out_wofireMux_T_262 & out_backSel_148; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_856 = _out_wofireMux_T_855; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_859 = _out_wofireMux_T_262 & out_backSel_149; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_860 = _out_wofireMux_T_859; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_863 = _out_wofireMux_T_262 & out_backSel_150; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_864 = _out_wofireMux_T_863; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_867 = _out_wofireMux_T_262 & out_backSel_151; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_868 = _out_wofireMux_T_867; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_871 = _out_wofireMux_T_262 & out_backSel_152; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_872 = _out_wofireMux_T_871; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_875 = _out_wofireMux_T_262 & out_backSel_153; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_876 = _out_wofireMux_T_875; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_879 = _out_wofireMux_T_262 & out_backSel_154; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_880 = _out_wofireMux_T_879; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_883 = _out_wofireMux_T_262 & out_backSel_155; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_884 = _out_wofireMux_T_883; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_887 = _out_wofireMux_T_262 & out_backSel_156; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_888 = _out_wofireMux_T_887; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_891 = _out_wofireMux_T_262 & out_backSel_157; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_892 = _out_wofireMux_T_891; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_895 = _out_wofireMux_T_262 & out_backSel_158; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_896 = _out_wofireMux_T_895; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_899 = _out_wofireMux_T_262 & out_backSel_159; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_900 = _out_wofireMux_T_899; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_903 = _out_wofireMux_T_262 & out_backSel_160; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_904 = _out_wofireMux_T_903; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_907 = _out_wofireMux_T_262 & out_backSel_161; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_908 = _out_wofireMux_T_907; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_911 = _out_wofireMux_T_262 & out_backSel_162; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_912 = _out_wofireMux_T_911; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_915 = _out_wofireMux_T_262 & out_backSel_163; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_916 = _out_wofireMux_T_915; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_919 = _out_wofireMux_T_262 & out_backSel_164; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_920 = _out_wofireMux_T_919; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_923 = _out_wofireMux_T_262 & out_backSel_165; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_924 = _out_wofireMux_T_923; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_927 = _out_wofireMux_T_262 & out_backSel_166; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_928 = _out_wofireMux_T_927; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_931 = _out_wofireMux_T_262 & out_backSel_167; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_932 = _out_wofireMux_T_931; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_935 = _out_wofireMux_T_262 & out_backSel_168; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_936 = _out_wofireMux_T_935; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_939 = _out_wofireMux_T_262 & out_backSel_169; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_940 = _out_wofireMux_T_939; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_943 = _out_wofireMux_T_262 & out_backSel_170; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_944 = _out_wofireMux_T_943; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_947 = _out_wofireMux_T_262 & out_backSel_171; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_948 = _out_wofireMux_T_947; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_951 = _out_wofireMux_T_262 & out_backSel_172; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_952 = _out_wofireMux_T_951; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_955 = _out_wofireMux_T_262 & out_backSel_173; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_956 = _out_wofireMux_T_955; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_959 = _out_wofireMux_T_262 & out_backSel_174; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_960 = _out_wofireMux_T_959; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_963 = _out_wofireMux_T_262 & out_backSel_175; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_964 = _out_wofireMux_T_963; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_967 = _out_wofireMux_T_262 & out_backSel_176; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_968 = _out_wofireMux_T_967; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_971 = _out_wofireMux_T_262 & out_backSel_177; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_972 = _out_wofireMux_T_971; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_975 = _out_wofireMux_T_262 & out_backSel_178; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_976 = _out_wofireMux_T_975; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_979 = _out_wofireMux_T_262 & out_backSel_179; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_980 = _out_wofireMux_T_979; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_983 = _out_wofireMux_T_262 & out_backSel_180; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_984 = _out_wofireMux_T_983; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_987 = _out_wofireMux_T_262 & out_backSel_181; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_988 = _out_wofireMux_T_987; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_991 = _out_wofireMux_T_262 & out_backSel_182; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_992 = _out_wofireMux_T_991; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_995 = _out_wofireMux_T_262 & out_backSel_183; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_996 = _out_wofireMux_T_995; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_999 = _out_wofireMux_T_262 & out_backSel_184; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1000 = _out_wofireMux_T_999; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1003 = _out_wofireMux_T_262 & out_backSel_185; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1004 = _out_wofireMux_T_1003; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1007 = _out_wofireMux_T_262 & out_backSel_186; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1008 = _out_wofireMux_T_1007; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1011 = _out_wofireMux_T_262 & out_backSel_187; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1012 = _out_wofireMux_T_1011; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1015 = _out_wofireMux_T_262 & out_backSel_188; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1016 = _out_wofireMux_T_1015; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1019 = _out_wofireMux_T_262 & out_backSel_189; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1020 = _out_wofireMux_T_1019; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1023 = _out_wofireMux_T_262 & out_backSel_190; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1024 = _out_wofireMux_T_1023; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1027 = _out_wofireMux_T_262 & out_backSel_191; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1028 = _out_wofireMux_T_1027; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1031 = _out_wofireMux_T_262 & out_backSel_192; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1032 = _out_wofireMux_T_1031; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1035 = _out_wofireMux_T_262 & out_backSel_193; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1036 = _out_wofireMux_T_1035; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1039 = _out_wofireMux_T_262 & out_backSel_194; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1040 = _out_wofireMux_T_1039; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1043 = _out_wofireMux_T_262 & out_backSel_195; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1044 = _out_wofireMux_T_1043; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1047 = _out_wofireMux_T_262 & out_backSel_196; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1048 = _out_wofireMux_T_1047; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1051 = _out_wofireMux_T_262 & out_backSel_197; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1052 = _out_wofireMux_T_1051; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1055 = _out_wofireMux_T_262 & out_backSel_198; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1056 = _out_wofireMux_T_1055; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1059 = _out_wofireMux_T_262 & out_backSel_199; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1060 = _out_wofireMux_T_1059; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1063 = _out_wofireMux_T_262 & out_backSel_200; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1064 = _out_wofireMux_T_1063; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1067 = _out_wofireMux_T_262 & out_backSel_201; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1068 = _out_wofireMux_T_1067; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1071 = _out_wofireMux_T_262 & out_backSel_202; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1072 = _out_wofireMux_T_1071; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1075 = _out_wofireMux_T_262 & out_backSel_203; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1076 = _out_wofireMux_T_1075; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1079 = _out_wofireMux_T_262 & out_backSel_204; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1080 = _out_wofireMux_T_1079; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1083 = _out_wofireMux_T_262 & out_backSel_205; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1084 = _out_wofireMux_T_1083; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1087 = _out_wofireMux_T_262 & out_backSel_206; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1088 = _out_wofireMux_T_1087; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1091 = _out_wofireMux_T_262 & out_backSel_207; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1092 = _out_wofireMux_T_1091; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1095 = _out_wofireMux_T_262 & out_backSel_208; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1096 = _out_wofireMux_T_1095; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1099 = _out_wofireMux_T_262 & out_backSel_209; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1100 = _out_wofireMux_T_1099; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1103 = _out_wofireMux_T_262 & out_backSel_210; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1104 = _out_wofireMux_T_1103; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1107 = _out_wofireMux_T_262 & out_backSel_211; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1108 = _out_wofireMux_T_1107; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1111 = _out_wofireMux_T_262 & out_backSel_212; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1112 = _out_wofireMux_T_1111; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1115 = _out_wofireMux_T_262 & out_backSel_213; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1116 = _out_wofireMux_T_1115; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1119 = _out_wofireMux_T_262 & out_backSel_214; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1120 = _out_wofireMux_T_1119; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1123 = _out_wofireMux_T_262 & out_backSel_215; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1124 = _out_wofireMux_T_1123; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1127 = _out_wofireMux_T_262 & out_backSel_216; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1128 = _out_wofireMux_T_1127; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1131 = _out_wofireMux_T_262 & out_backSel_217; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1132 = _out_wofireMux_T_1131; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1135 = _out_wofireMux_T_262 & out_backSel_218; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1136 = _out_wofireMux_T_1135; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1139 = _out_wofireMux_T_262 & out_backSel_219; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1140 = _out_wofireMux_T_1139; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1143 = _out_wofireMux_T_262 & out_backSel_220; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1144 = _out_wofireMux_T_1143; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1147 = _out_wofireMux_T_262 & out_backSel_221; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1148 = _out_wofireMux_T_1147; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1151 = _out_wofireMux_T_262 & out_backSel_222; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1152 = _out_wofireMux_T_1151; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1155 = _out_wofireMux_T_262 & out_backSel_223; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1156 = _out_wofireMux_T_1155; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1159 = _out_wofireMux_T_262 & out_backSel_224; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1160 = _out_wofireMux_T_1159; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1163 = _out_wofireMux_T_262 & out_backSel_225; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1164 = _out_wofireMux_T_1163; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1167 = _out_wofireMux_T_262 & out_backSel_226; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1168 = _out_wofireMux_T_1167; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1171 = _out_wofireMux_T_262 & out_backSel_227; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1172 = _out_wofireMux_T_1171; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1175 = _out_wofireMux_T_262 & out_backSel_228; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1176 = _out_wofireMux_T_1175; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1179 = _out_wofireMux_T_262 & out_backSel_229; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1180 = _out_wofireMux_T_1179; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1183 = _out_wofireMux_T_262 & out_backSel_230; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1184 = _out_wofireMux_T_1183; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1187 = _out_wofireMux_T_262 & out_backSel_231; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1188 = _out_wofireMux_T_1187; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1191 = _out_wofireMux_T_262 & out_backSel_232; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1192 = _out_wofireMux_T_1191; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1195 = _out_wofireMux_T_262 & out_backSel_233; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1196 = _out_wofireMux_T_1195; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1199 = _out_wofireMux_T_262 & out_backSel_234; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1200 = _out_wofireMux_T_1199; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1203 = _out_wofireMux_T_262 & out_backSel_235; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1204 = _out_wofireMux_T_1203; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1207 = _out_wofireMux_T_262 & out_backSel_236; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1208 = _out_wofireMux_T_1207; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1211 = _out_wofireMux_T_262 & out_backSel_237; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1212 = _out_wofireMux_T_1211; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1215 = _out_wofireMux_T_262 & out_backSel_238; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1216 = _out_wofireMux_T_1215; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1219 = _out_wofireMux_T_262 & out_backSel_239; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1220 = _out_wofireMux_T_1219; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1223 = _out_wofireMux_T_262 & out_backSel_240; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1224 = _out_wofireMux_T_1223; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1227 = _out_wofireMux_T_262 & out_backSel_241; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1228 = _out_wofireMux_T_1227; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1231 = _out_wofireMux_T_262 & out_backSel_242; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1232 = _out_wofireMux_T_1231; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1235 = _out_wofireMux_T_262 & out_backSel_243; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1236 = _out_wofireMux_T_1235; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1239 = _out_wofireMux_T_262 & out_backSel_244; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1240 = _out_wofireMux_T_1239; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1243 = _out_wofireMux_T_262 & out_backSel_245; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1244 = _out_wofireMux_T_1243; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1247 = _out_wofireMux_T_262 & out_backSel_246; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1248 = _out_wofireMux_T_1247; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1251 = _out_wofireMux_T_262 & out_backSel_247; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1252 = _out_wofireMux_T_1251; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1255 = _out_wofireMux_T_262 & out_backSel_248; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1256 = _out_wofireMux_T_1255; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1259 = _out_wofireMux_T_262 & out_backSel_249; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1260 = _out_wofireMux_T_1259; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1263 = _out_wofireMux_T_262 & out_backSel_250; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1264 = _out_wofireMux_T_1263; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1267 = _out_wofireMux_T_262 & out_backSel_251; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1268 = _out_wofireMux_T_1267; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1271 = _out_wofireMux_T_262 & out_backSel_252; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1272 = _out_wofireMux_T_1271; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1275 = _out_wofireMux_T_262 & out_backSel_253; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1276 = _out_wofireMux_T_1275; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1279 = _out_wofireMux_T_262 & out_backSel_254; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1280 = _out_wofireMux_T_1279; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1283 = _out_wofireMux_T_262 & out_backSel_255; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1284 = _out_wofireMux_T_1283; // @[RegisterRouter.scala:87:24]
assign in_1_ready = _out_in_ready_T_1; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_1_valid = _out_front_valid_T_1; // @[RegisterRouter.scala:87:24]
assign out_front_1_ready = _out_front_ready_T_1; // @[RegisterRouter.scala:87:24]
assign out_1_valid = _out_out_valid_T_1; // @[RegisterRouter.scala:87:24]
wire out_out_bits_data_out; // @[MuxLiteral.scala:52:28]
wire _GEN_39 = out_oindex_1 == 8'h0; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_5; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_5 = _GEN_39; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_33; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_33 = _GEN_39; // @[MuxLiteral.scala:54:22]
wire _GEN_40 = out_oindex_1 == 8'h1; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_6; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_6 = _GEN_40; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_34; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_34 = _GEN_40; // @[MuxLiteral.scala:54:22]
wire _GEN_41 = out_oindex_1 == 8'h20; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_7; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_7 = _GEN_41; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_35; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_35 = _GEN_41; // @[MuxLiteral.scala:54:22]
wire _GEN_42 = out_oindex_1 == 8'h27; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_8; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_8 = _GEN_42; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_36; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_36 = _GEN_42; // @[MuxLiteral.scala:54:22]
wire _GEN_43 = out_oindex_1 == 8'h28; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_9; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_9 = _GEN_43; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_37; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_37 = _GEN_43; // @[MuxLiteral.scala:54:22]
wire _GEN_44 = out_oindex_1 == 8'h29; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_10; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_10 = _GEN_44; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_38; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_38 = _GEN_44; // @[MuxLiteral.scala:54:22]
wire _GEN_45 = out_oindex_1 == 8'h2A; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_11; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_11 = _GEN_45; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_39; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_39 = _GEN_45; // @[MuxLiteral.scala:54:22]
wire _GEN_46 = out_oindex_1 == 8'h2B; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_12; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_12 = _GEN_46; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_40; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_40 = _GEN_46; // @[MuxLiteral.scala:54:22]
wire _GEN_47 = out_oindex_1 == 8'h2C; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_13; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_13 = _GEN_47; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_41; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_41 = _GEN_47; // @[MuxLiteral.scala:54:22]
wire _GEN_48 = out_oindex_1 == 8'h2D; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_14; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_14 = _GEN_48; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_42; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_42 = _GEN_48; // @[MuxLiteral.scala:54:22]
wire _GEN_49 = out_oindex_1 == 8'h2E; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_15; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_15 = _GEN_49; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_43; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_43 = _GEN_49; // @[MuxLiteral.scala:54:22]
wire _GEN_50 = out_oindex_1 == 8'h2F; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_16; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_16 = _GEN_50; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_44; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_44 = _GEN_50; // @[MuxLiteral.scala:54:22]
wire _GEN_51 = out_oindex_1 == 8'h30; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_17; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_17 = _GEN_51; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_45; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_45 = _GEN_51; // @[MuxLiteral.scala:54:22]
wire _GEN_52 = out_oindex_1 == 8'h31; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_18; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_18 = _GEN_52; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_46; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_46 = _GEN_52; // @[MuxLiteral.scala:54:22]
wire _GEN_53 = out_oindex_1 == 8'h32; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_19; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_19 = _GEN_53; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_47; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_47 = _GEN_53; // @[MuxLiteral.scala:54:22]
wire _GEN_54 = out_oindex_1 == 8'h33; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_20; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_20 = _GEN_54; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_48; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_48 = _GEN_54; // @[MuxLiteral.scala:54:22]
wire _GEN_55 = out_oindex_1 == 8'h40; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_21; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_21 = _GEN_55; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_49; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_49 = _GEN_55; // @[MuxLiteral.scala:54:22]
wire _GEN_56 = out_oindex_1 == 8'h80; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_22; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_22 = _GEN_56; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_50; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_50 = _GEN_56; // @[MuxLiteral.scala:54:22]
wire _GEN_57 = out_oindex_1 == 8'h81; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_23; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_23 = _GEN_57; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_51; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_51 = _GEN_57; // @[MuxLiteral.scala:54:22]
wire _GEN_58 = out_oindex_1 == 8'h82; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_24; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_24 = _GEN_58; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_52; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_52 = _GEN_58; // @[MuxLiteral.scala:54:22]
wire _GEN_59 = out_oindex_1 == 8'h83; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_25; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_25 = _GEN_59; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_53; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_53 = _GEN_59; // @[MuxLiteral.scala:54:22]
wire _GEN_60 = out_oindex_1 == 8'h84; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_26; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_26 = _GEN_60; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_54; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_54 = _GEN_60; // @[MuxLiteral.scala:54:22]
wire _GEN_61 = out_oindex_1 == 8'h85; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_27; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_27 = _GEN_61; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_55; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_55 = _GEN_61; // @[MuxLiteral.scala:54:22]
wire _GEN_62 = out_oindex_1 == 8'h86; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_28; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_28 = _GEN_62; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_56; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_56 = _GEN_62; // @[MuxLiteral.scala:54:22]
wire _GEN_63 = out_oindex_1 == 8'h87; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_29; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_29 = _GEN_63; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_57; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_57 = _GEN_63; // @[MuxLiteral.scala:54:22]
wire _GEN_64 = out_oindex_1 == 8'h88; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_30; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_30 = _GEN_64; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_58; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_58 = _GEN_64; // @[MuxLiteral.scala:54:22]
wire _GEN_65 = out_oindex_1 == 8'h89; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_31; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_31 = _GEN_65; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_59; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_59 = _GEN_65; // @[MuxLiteral.scala:54:22]
wire _GEN_66 = out_oindex_1 == 8'h8A; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_32; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_32 = _GEN_66; // @[MuxLiteral.scala:54:22]
wire _out_out_bits_data_T_60; // @[MuxLiteral.scala:54:22]
assign _out_out_bits_data_T_60 = _GEN_66; // @[MuxLiteral.scala:54:22]
assign out_out_bits_data_out = _out_out_bits_data_T_5 ? _out_T_1687 : _out_out_bits_data_T_6 ? _out_T_1673 : _out_out_bits_data_T_7 ? _out_T_1675 : _out_out_bits_data_T_8 ? _out_T_1691 : _out_out_bits_data_T_9 ? _out_T_1663 : _out_out_bits_data_T_10 ? _out_T_1683 : _out_out_bits_data_T_11 ? _out_T_1651 : _out_out_bits_data_T_12 ? _out_T_1667 : _out_out_bits_data_T_13 ? _out_T_1693 : _out_out_bits_data_T_14 ? _out_T_1677 : _out_out_bits_data_T_15 ? _out_T_1647 : _out_out_bits_data_T_16 ? _out_T_1669 : _out_out_bits_data_T_17 ? _out_T_1659 : _out_out_bits_data_T_18 ? _out_T_1657 : _out_out_bits_data_T_19 ? _out_T_1697 : _out_out_bits_data_T_20 ? _out_T_1643 : _out_out_bits_data_T_21 ? _out_T_1681 : _out_out_bits_data_T_22 ? _out_T_1679 : _out_out_bits_data_T_23 ? _out_T_1645 : _out_out_bits_data_T_24 ? _out_T_1695 : _out_out_bits_data_T_25 ? _out_T_1655 : _out_out_bits_data_T_26 ? _out_T_1671 : _out_out_bits_data_T_27 ? _out_T_1649 : _out_out_bits_data_T_28 ? _out_T_1665 : _out_out_bits_data_T_29 ? _out_T_1661 : _out_out_bits_data_T_30 ? _out_T_1689 : _out_out_bits_data_T_31 ? _out_T_1653 : ~_out_out_bits_data_T_32 | _out_T_1685; // @[MuxLiteral.scala:52:28, :54:{22,28}]
wire [63:0] out_out_bits_data_out_1; // @[MuxLiteral.scala:52:28]
assign out_out_bits_data_out_1 = _out_out_bits_data_T_33 | _out_out_bits_data_T_34 ? 64'h0 : _out_out_bits_data_T_35 ? 64'h380006F : _out_out_bits_data_T_36 ? _out_T_3396 : _out_out_bits_data_T_37 ? _out_T_2585 : _out_out_bits_data_T_38 ? _out_T_3252 : _out_out_bits_data_T_39 ? _out_T_2105 : _out_out_bits_data_T_40 ? _out_T_2745 : _out_out_bits_data_T_41 ? _out_T_3484 : _out_out_bits_data_T_42 ? _out_T_3020 : _out_out_bits_data_T_43 ? _out_T_1945 : _out_out_bits_data_T_44 ? _out_T_2833 : _out_out_bits_data_T_45 ? _out_T_2425 : _out_out_bits_data_T_46 ? _out_T_2337 : _out_out_bits_data_T_47 ? _out_T_3644 : _out_out_bits_data_T_48 ? _out_T_1785 : _out_out_bits_data_T_49 ? _out_T_3164 : _out_out_bits_data_T_50 ? 64'h380006F00C0006F : _out_out_bits_data_T_51 ? 64'hFF0000F0440006F : _out_out_bits_data_T_52 ? 64'hF14024737B241073 : _out_out_bits_data_T_53 ? 64'h4004440310802023 : _out_out_bits_data_T_54 ? 64'hFE0408E300347413 : _out_out_bits_data_T_55 ? 64'h4086300147413 : _out_out_bits_data_T_56 ? 64'h100022237B202473 : _out_out_bits_data_T_57 ? 64'hF140247330000067 : _out_out_bits_data_T_58 ? 64'h7B20247310802423 : _out_out_bits_data_T_59 ? 64'h100026237B200073 : {32'h0, _out_out_bits_data_T_60 ? 32'h100073 : 32'h0}; // @[MuxLiteral.scala:52:28, :54:{22,28}]
assign _out_out_bits_data_T_61 = out_out_bits_data_out ? out_out_bits_data_out_1 : 64'h0; // @[MuxLiteral.scala:52:28]
assign out_1_bits_data = _out_out_bits_data_T_61; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
reg [1:0] ctrlStateReg; // @[Debug.scala:1732:27]
wire [7:0] _hartHalted_T = haltedBitRegs >> selectedHartReg; // @[Debug.scala:861:31, :901:30, :1734:37]
wire hartHalted = _hartHalted_T[0]; // @[Debug.scala:1734:37]
wire [1:0] ctrlStateNxt; // @[Debug.scala:1735:32]
assign _abstractCommandBusy_T = |ctrlStateReg; // @[Debug.scala:1732:27, :1740:42]
assign abstractCommandBusy = _abstractCommandBusy_T; // @[Debug.scala:1220:39, :1740:42]
assign _ABSTRACTCSWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44]
assign ABSTRACTCSWrEnLegal = _ABSTRACTCSWrEnLegal_T; // @[Debug.scala:1190:39, :1742:44]
assign _COMMANDWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1743:44]
assign COMMANDWrEnLegal = _COMMANDWrEnLegal_T; // @[Debug.scala:1282:39, :1743:44]
assign _ABSTRACTAUTOWrEnLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1744:44]
assign ABSTRACTAUTOWrEnLegal = _ABSTRACTAUTOWrEnLegal_T; // @[Debug.scala:1243:41, :1744:44]
assign _dmiAbstractDataAccessLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1745:50]
assign dmiAbstractDataAccessLegal = _dmiAbstractDataAccessLegal_T; // @[Debug.scala:892:46, :1745:50]
assign _dmiProgramBufferAccessLegal_T = ~(|ctrlStateReg); // @[Debug.scala:1732:27, :1740:42, :1742:44, :1746:50]
assign dmiProgramBufferAccessLegal = _dmiProgramBufferAccessLegal_T; // @[Debug.scala:888:47, :1746:50]
wire _errorBusy_T = ~ABSTRACTCSWrEnLegal; // @[Debug.scala:1190:39, :1748:45]
wire _errorBusy_T_1 = ABSTRACTCSWrEnMaybe & _errorBusy_T; // @[Debug.scala:1188:39, :1748:{42,45}]
wire _errorBusy_T_2 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45]
wire _errorBusy_T_3 = autoexecdataWrEnMaybe & _errorBusy_T_2; // @[Debug.scala:1240:41, :1749:{42,45}]
wire _errorBusy_T_4 = _errorBusy_T_1 | _errorBusy_T_3; // @[Debug.scala:1748:{42,74}, :1749:42]
wire _errorBusy_T_5 = ~ABSTRACTAUTOWrEnLegal; // @[Debug.scala:1243:41, :1749:45, :1750:47]
wire _errorBusy_T_6 = autoexecprogbufWrEnMaybe & _errorBusy_T_5; // @[Debug.scala:1241:44, :1750:{44,47}]
wire _errorBusy_T_7 = _errorBusy_T_4 | _errorBusy_T_6; // @[Debug.scala:1748:74, :1749:74, :1750:44]
wire _errorBusy_T_8 = ~COMMANDWrEnLegal; // @[Debug.scala:1282:39, :1751:45]
wire _errorBusy_T_9 = COMMANDWrEnMaybe & _errorBusy_T_8; // @[Debug.scala:1281:39, :1751:{42,45}]
wire _errorBusy_T_10 = _errorBusy_T_7 | _errorBusy_T_9; // @[Debug.scala:1749:74, :1750:74, :1751:42]
wire _errorBusy_T_11 = ~dmiAbstractDataAccessLegal; // @[Debug.scala:892:46, :1752:45]
wire _errorBusy_T_12 = dmiAbstractDataAccess & _errorBusy_T_11; // @[Debug.scala:1263:68, :1752:{42,45}]
wire _errorBusy_T_13 = _errorBusy_T_10 | _errorBusy_T_12; // @[Debug.scala:1750:74, :1751:74, :1752:42]
wire _errorBusy_T_14 = ~dmiProgramBufferAccessLegal; // @[Debug.scala:888:47, :1753:45]
wire _errorBusy_T_15 = dmiProgramBufferAccess & _errorBusy_T_14; // @[Debug.scala:1264:69, :1753:{42,45}]
assign _errorBusy_T_16 = _errorBusy_T_13 | _errorBusy_T_15; // @[Debug.scala:1751:74, :1752:74, :1753:42]
assign errorBusy = _errorBusy_T_16; // @[Debug.scala:1195:36, :1752:74]
wire commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala:1280:39, :1756:60]
wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0; // @[Debug.scala:1277:25, :1757:58]
wire _commandWrIsUnsupported_T = ~commandWrIsAccessRegister; // @[Debug.scala:1756:60, :1759:49]
wire commandWrIsUnsupported = COMMANDWrEn & _commandWrIsUnsupported_T; // @[Debug.scala:1285:40, :1759:{46,49}]
wire commandRegIsUnsupported; // @[Debug.scala:1761:43]
wire commandRegBadHaltResume; // @[Debug.scala:1762:43]
wire _accessRegIsLegalSize_T = accessRegisterCommandReg_size == 3'h2; // @[Debug.scala:1533:44, :1765:63]
wire _accessRegIsLegalSize_T_1 = accessRegisterCommandReg_size == 3'h3; // @[Debug.scala:1533:44, :1765:106]
wire accessRegIsLegalSize = _accessRegIsLegalSize_T | _accessRegIsLegalSize_T_1; // @[Debug.scala:1765:{63,72,106}]
wire _accessRegIsGPR_T = |(accessRegisterCommandReg_regno[15:12]); // @[Debug.scala:1533:44, :1766:58]
wire _accessRegIsGPR_T_1 = accessRegisterCommandReg_regno < 16'h1020; // @[Debug.scala:1533:44, :1766:104]
wire _accessRegIsGPR_T_2 = _accessRegIsGPR_T & _accessRegIsGPR_T_1; // @[Debug.scala:1766:{58,70,104}]
wire accessRegIsGPR = _accessRegIsGPR_T_2 & accessRegIsLegalSize; // @[Debug.scala:1765:72, :1766:{70,117}]
wire _T_695 = ~accessRegisterCommandReg_transfer | accessRegIsGPR; // @[Debug.scala:1533:44, :1766:117, :1776:{19,54}]
assign commandRegIsUnsupported = ~commandRegIsAccessRegister | ~_T_695; // @[Debug.scala:1757:58, :1761:43, :1773:39, :1774:115, :1775:33, :1776:{54,73}, :1777:33]
wire _commandRegBadHaltResume_T = ~hartHalted; // @[Debug.scala:1734:37, :1778:36]
assign commandRegBadHaltResume = commandRegIsAccessRegister & _T_695 & _commandRegBadHaltResume_T; // @[Debug.scala:1757:58, :1762:43, :1773:39, :1774:115, :1776:{54,73}, :1778:{33,36}]
wire _wrAccessRegisterCommand_T = COMMANDWrEn & commandWrIsAccessRegister; // @[Debug.scala:1285:40, :1756:60, :1782:48]
wire _GEN_67 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala:1183:34, :1782:103]
wire _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:103]
assign _wrAccessRegisterCommand_T_1 = _GEN_67; // @[Debug.scala:1782:103]
wire _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:103]
assign _regAccessRegisterCommand_T_1 = _GEN_67; // @[Debug.scala:1782:103, :1783:103]
wire wrAccessRegisterCommand = _wrAccessRegisterCommand_T & _wrAccessRegisterCommand_T_1; // @[Debug.scala:1782:{48,78,103}]
wire _regAccessRegisterCommand_T = autoexec & commandRegIsAccessRegister; // @[Debug.scala:1272:48, :1757:58, :1783:48]
wire regAccessRegisterCommand = _regAccessRegisterCommand_T & _regAccessRegisterCommand_T_1; // @[Debug.scala:1783:{48,78,103}]
wire _T_697 = wrAccessRegisterCommand | regAccessRegisterCommand; // @[Debug.scala:1782:78, :1783:78, :1790:37]
wire _T_699 = ctrlStateReg == 2'h1; // @[Debug.scala:1732:27, :1797:30]
assign errorUnsupported = (|ctrlStateReg) ? _T_699 & commandRegIsUnsupported : ~_T_697 & (commandWrIsUnsupported | autoexec & commandRegIsUnsupported); // @[Debug.scala:1197:36, :1272:48, :1732:27, :1740:42, :1759:46, :1761:43, :1789:47, :1790:{37,66}, :1792:43, :1793:26, :1794:{28,56}, :1797:{30,59}, :1804:38]
assign errorHaltResume = (|ctrlStateReg) & _T_699 & ~commandRegIsUnsupported & commandRegBadHaltResume; // @[Debug.scala:1198:36, :1732:27, :1740:42, :1761:43, :1762:43, :1789:47, :1797:{30,59}, :1804:38, :1807:43]
wire _GEN_68 = commandRegIsUnsupported | commandRegBadHaltResume; // @[Debug.scala:1761:43, :1762:43, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33]
assign goAbstract = (|ctrlStateReg) & _T_699 & ~_GEN_68; // @[Debug.scala:1495:32, :1732:27, :1740:42, :1789:47, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33]
wire _T_700 = ctrlStateReg == 2'h2; // @[Debug.scala:1732:27, :1818:30]
wire _GEN_69 = ~(|ctrlStateReg) | _T_699; // @[Debug.scala:1196:36, :1732:27, :1740:42, :1742:44, :1789:47, :1797:{30,59}, :1818:51]
assign errorException = ~_GEN_69 & _T_700 & hartExceptionWrEn; // @[Debug.scala:881:36, :1196:36, :1789:47, :1797:59, :1818:{30,51}, :1826:31]
assign goCustom = ~(_GEN_69 | _T_700) & (&ctrlStateReg); // @[Debug.scala:1196:36, :1496:32, :1732:27, :1789:47, :1797:59, :1818:{30,51}, :1831:{30,53}]
assign ctrlStateNxt = (|ctrlStateReg) ? (_T_699 ? {~_GEN_68, 1'h0} : _T_700 & (hartExceptionWrEn | ~goReg & hartHaltedWrEn & hartHaltedId == {7'h0, selectedHartReg}) ? 2'h0 : ctrlStateReg) : _T_697 ? 2'h1 : ctrlStateReg; // @[Debug.scala:875:36, :876:36, :881:36, :901:30, :1494:27, :1732:27, :1735:32, :1740:42, :1789:47, :1790:{37,66}, :1791:22, :1797:{30,59}, :1804:38, :1806:22, :1807:43, :1809:22, :1811:33, :1818:{30,51}, :1823:{18,30,48,95,116}, :1824:22, :1826:31, :1828:24, :1831:53] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_157( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_90( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_a_ready = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_valid = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _a_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _a_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire a_first_done = 1'h0; // @[Edges.scala:233:22]
wire _a_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire _a_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire _d_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_opdata = 1'h0; // @[Edges.scala:106:36]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _d_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire d_first_done = 1'h0; // @[Edges.scala:233:22]
wire _d_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire _d_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire _a_first_T_1 = 1'h0; // @[Decoupled.scala:51:35]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire _a_first_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire a_first_done_1 = 1'h0; // @[Edges.scala:233:22]
wire _a_first_count_T_1 = 1'h0; // @[Edges.scala:234:27]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _a_first_counter_T_1 = 1'h0; // @[Edges.scala:236:21]
wire _d_first_T_1 = 1'h0; // @[Decoupled.scala:51:35]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:106:36]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire _d_first_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire d_first_done_1 = 1'h0; // @[Edges.scala:233:22]
wire _d_first_count_T_1 = 1'h0; // @[Edges.scala:234:27]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _d_first_counter_T_1 = 1'h0; // @[Edges.scala:236:21]
wire d_release_ack = 1'h0; // @[Monitor.scala:673:46]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire _d_first_T_2 = 1'h0; // @[Decoupled.scala:51:35]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_opdata_2 = 1'h0; // @[Edges.scala:106:36]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire _d_first_last_T_4 = 1'h0; // @[Edges.scala:232:25]
wire d_first_done_2 = 1'h0; // @[Edges.scala:233:22]
wire _d_first_count_T_2 = 1'h0; // @[Edges.scala:234:27]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _d_first_counter_T_2 = 1'h0; // @[Edges.scala:236:21]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire a_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire a_first = 1'h1; // @[Edges.scala:231:25]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire d_first = 1'h1; // @[Edges.scala:231:25]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire a_first_counter1_1 = 1'h1; // @[Edges.scala:230:28]
wire a_first_1 = 1'h1; // @[Edges.scala:231:25]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire d_first_counter1_1 = 1'h1; // @[Edges.scala:230:28]
wire d_first_1 = 1'h1; // @[Edges.scala:231:25]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_counter1_2 = 1'h1; // @[Edges.scala:230:28]
wire d_first_2 = 1'h1; // @[Edges.scala:231:25]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] _a_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _d_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _a_first_counter1_T_1 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _d_first_counter1_T_1 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _d_first_counter1_T_2 = 2'h3; // @[Edges.scala:230:28]
wire [10:0] io_in_d_bits_source = 11'h0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = 11'h0; // @[Parameters.scala:52:29]
wire [10:0] source_ok_uncommonBits_1 = 11'h0; // @[Parameters.scala:52:56]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_d_bits_opcode = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] _d_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] _d_first_beats1_decode_T_5 = 3'h0; // @[package.scala:243:46]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] a_sizes_set_interm = 3'h0; // @[Monitor.scala:648:38]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] _d_first_beats1_decode_T_8 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [4159:0] _inflight_opcodes_T_1 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:706:62]
wire [4159:0] _inflight_sizes_T_1 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:707:56]
wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62]
wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58]
wire [1039:0] _inflight_T_1 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:705:38]
wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [4159:0] a_opcodes_set = 4160'h0; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set = 4160'h0; // @[Monitor.scala:632:31]
wire [4159:0] d_opcodes_clr = 4160'h0; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr = 4160'h0; // @[Monitor.scala:670:31]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF; // @[Monitor.scala:680:76]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF; // @[Monitor.scala:681:74]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF; // @[Monitor.scala:790:76]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF; // @[Monitor.scala:791:74]
wire [13:0] _a_opcode_lookup_T = 14'h0; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T = 14'h0; // @[Monitor.scala:641:65]
wire [13:0] _d_opcodes_clr_T_4 = 14'h0; // @[Monitor.scala:680:101]
wire [13:0] _d_sizes_clr_T_4 = 14'h0; // @[Monitor.scala:681:99]
wire [13:0] _c_opcode_lookup_T = 14'h0; // @[Monitor.scala:749:69]
wire [13:0] _c_size_lookup_T = 14'h0; // @[Monitor.scala:750:67]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [13:0] _d_opcodes_clr_T_10 = 14'h0; // @[Monitor.scala:790:101]
wire [13:0] _d_sizes_clr_T_10 = 14'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1039:0] a_set = 1040'h0; // @[Monitor.scala:626:34]
wire [1039:0] d_clr = 1040'h0; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready = 1040'h0; // @[Monitor.scala:665:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34]
wire [2047:0] _d_clr_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1 = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1 = 2048'h1; // @[OneHot.scala:58:35]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] a_opcodes_set_interm = 4'h0; // @[Monitor.scala:646:40]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2:0] _d_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [2:0] _d_first_beats1_decode_T_4 = 3'h7; // @[package.scala:243:76]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [2:0] _d_first_beats1_decode_T_7 = 3'h7; // @[package.scala:243:76]
wire [5:0] _d_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3 = 6'h7; // @[package.scala:243:71]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6 = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire _same_cycle_resp_T = io_in_a_valid_0; // @[Monitor.scala:36:7, :684:44]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
wire [1039:0] _inflight_T = inflight; // @[Monitor.scala:614:27, :705:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes; // @[Monitor.scala:616:35, :706:43]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire [4159:0] _inflight_sizes_T = inflight_sizes; // @[Monitor.scala:618:33, :707:39]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [2047:0] _GEN_0 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_0; // @[OneHot.scala:58:35]
assign a_set_wo_ready = io_in_a_valid_0 ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
wire [13:0] _GEN_1 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_1; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_1; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = 16387'h0 << _a_opcodes_set_T; // @[Monitor.scala:659:{54,79}]
wire [16385:0] _a_sizes_set_T_1 = 16386'h0 << _a_sizes_set_T; // @[Monitor.scala:660:{52,77}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T_2 = _inflight_T; // @[Monitor.scala:705:{27,36}]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T; // @[Monitor.scala:706:{43,60}]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T; // @[Monitor.scala:707:{39,54}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_168( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_304 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module AsyncResetRegVec_w5_i0_4( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input [4:0] io_d, // @[AsyncResetReg.scala:59:14]
output [4:0] io_q // @[AsyncResetReg.scala:59:14]
);
wire [4:0] io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire [4:0] io_q_0; // @[AsyncResetReg.scala:56:7]
reg [4:0] reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 5'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w4_d3_i0_35( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_321 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_322 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_323 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_324 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_82( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_release_ack = 1'h0; // @[Monitor.scala:673:46]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [4159:0] _inflight_opcodes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62]
wire [4159:0] _inflight_sizes_T_4 = 4160'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58]
wire [1039:0] _inflight_T_4 = 1040'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [4159:0] d_opcodes_clr_1 = 4160'h0; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1 = 4160'h0; // @[Monitor.scala:777:34]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [1039:0] d_clr_1 = 1040'h0; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1 = 1040'h0; // @[Monitor.scala:775:34]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_659; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_592 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_4 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35]
assign d_clr = _T_605 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_14( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52]
wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35]
wire [279:0] c_sizes_set = 280'h0; // @[Monitor.scala:741:34]
wire [139:0] c_opcodes_set = 140'h0; // @[Monitor.scala:740:34]
wire [34:0] c_set = 35'h0; // @[Monitor.scala:738:34]
wire [34:0] c_set_wo_ready = 35'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_35 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_41 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_47 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_53 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_36 = _source_ok_T_35 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = _source_ok_T_53 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = io_in_d_bits_source_0 == 6'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire _source_ok_T_60 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1524 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1524; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1524; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1597 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1597; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1597; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1597; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [34:0] inflight; // @[Monitor.scala:614:27]
reg [139:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [279:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [34:0] a_set; // @[Monitor.scala:626:34]
wire [34:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [139:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [279:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [139:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [139:0] _a_opcode_lookup_T_6 = {136'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [139:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[139:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [279:0] _a_size_lookup_T_6 = {272'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [279:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[279:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire _T_1450 = _T_1524 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1450 ? _a_set_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1450 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1450 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1450 ? _a_opcodes_set_T_1[139:0] : 140'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1450 ? _a_sizes_set_T_1[279:0] : 280'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [34:0] d_clr; // @[Monitor.scala:664:34]
wire [34:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [139:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [279:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1496 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1496 & ~d_release_ack ? _d_clr_wo_ready_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire _T_1465 = _T_1597 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1465 ? _d_clr_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1465 ? _d_opcodes_clr_T_5[139:0] : 140'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1465 ? _d_sizes_clr_T_5[279:0] : 280'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [34:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [34:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [34:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [139:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [139:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [139:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [279:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [279:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [34:0] inflight_1; // @[Monitor.scala:726:35]
wire [34:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [139:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [139:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [279:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [279:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [139:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [139:0] _c_opcode_lookup_T_6 = {136'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [139:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[139:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [279:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [279:0] _c_size_lookup_T_6 = {272'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [279:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[279:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [34:0] d_clr_1; // @[Monitor.scala:774:34]
wire [34:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [139:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [279:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1568 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1568 & d_release_ack_1 ? _d_clr_wo_ready_T_1[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire _T_1550 = _T_1597 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1550 ? _d_clr_T_1[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1550 ? _d_opcodes_clr_T_11[139:0] : 140'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1550 ? _d_sizes_clr_T_11[279:0] : 280'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113]
wire [34:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [34:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [139:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [139:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [279:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [279:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module MulAddRecFNToRaw_preMul_e8_s24_29( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
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